CN1684242A - Method for producing semiconductor device - Google Patents
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- CN1684242A CN1684242A CN200510064979.XA CN200510064979A CN1684242A CN 1684242 A CN1684242 A CN 1684242A CN 200510064979 A CN200510064979 A CN 200510064979A CN 1684242 A CN1684242 A CN 1684242A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 76
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 62
- 238000007254 oxidation reaction Methods 0.000 claims description 62
- 238000000034 method Methods 0.000 claims description 38
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 20
- 239000007789 gas Substances 0.000 claims description 13
- 229910052786 argon Inorganic materials 0.000 claims description 10
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052754 neon Inorganic materials 0.000 claims description 4
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims description 4
- 150000003376 silicon Chemical class 0.000 claims description 4
- 229910052756 noble gas Inorganic materials 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 49
- 238000007514 turning Methods 0.000 description 32
- 229910052757 nitrogen Inorganic materials 0.000 description 25
- 238000005516 engineering process Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 102000004316 Oxidoreductases Human genes 0.000 description 1
- 108090000854 Oxidoreductases Proteins 0.000 description 1
- 238000003723 Smelting Methods 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000002829 nitrogen Chemical class 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28238—Making the insulator with sacrificial oxide
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
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Abstract
A method for producing a semiconductor device includes the steps of forming a trench for device isolation on a silicon substrate; and annealing the silicon substrate in an atmosphere containing a noble gas at any step after the growth of a buried oxide film until the growth of a gate polysilicon.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, and relate in particular to, under the condition that device property is worsened, make the method for semiconductor device by improving the reliability of the gate oxidation films of boundary between channel separating zone and active area.
Background technology
In recent years, the demand to the semiconductor device of more extensive, more speed increases day by day.In order to satisfy this demand, used the method for STI (shallow trench isolation from) as isolating device.In STI, dielectric film is buried in the groove to realize isolation.Therefore, this method is compared with LOCOS (local oxidation of silicon) and is not produced beak effect, and is suitable for obtaining high integrated level.
Yet, in STI, be that boundary between the groove forms cubic STI turning in the promptly main silicon face of active area and isolated area.As a result, gate oxidation films has thin part around the corner, and electric field concentrates on corner thus.Therefore these turnings make the reliability of gate oxidation films and the deterioration that the generation of transistorized performance is not expected.
In correlation technique, make the inner wall oxide and the nitrogenize of sti trench groove, to form the inwall nitrogen oxidation film, this inwall nitrogen oxidation film is left in order to avoid expose the STI turning.This nitrogen oxidation film has suppressed the formation and the electric field of the thin part of gate insulating film to be concentrated, to improve the reliability of gate insulating film.
For example, in open (JP-A) No.2001-135720 of Japanese Unexamined Patent Application, 64-33935,4-103173 and 10-41241 above-mentioned relevant technology is disclosed.
Yet in above-mentioned correlation technique, the nitrogen that comprises in the nitrogen oxidation film plays the effect of positive charge, and silicon interface has been produced adverse influence.In addition, though the inwall of groove by the nitrogen oxidation, the formation of gate oxidation films also has been subjected to inhibition, therefore, this film has thin part.Therefore, correlation technique undesirably makes the reliability of gate oxidation films and the deterioration that the generation of transistorized performance is not expected, because gate oxidation films has thin part and electric field is concentrated.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of semiconductor device of high reliability, its thickness at gate oxidation films does not have can improve under the situation of localized variation the reliability of gate oxidation films.
The invention provides a kind of manufacture method of semiconductor device.This method may further comprise the steps: form groove and be used for device isolation on silicon substrate; And the arbitrary step during the gate polysilicon growth behind the growth buried oxidation film, in comprising the atmosphere of rare gas, silicon substrate is annealed, so that STI turning rounding.
In the manufacture method of semiconductor device according to the invention, rare gas is preferably argon gas, neon or helium.
In the manufacture method of semiconductor device according to the invention, preferably carried out this annealing ten minutes to five hours at 1,000 ℃ to 1,200 ℃.
In the manufacture method of semiconductor device according to the invention, preferably this silicon substrate is carried out annealing in process not exposing under the situation that silicon substrate and silicon substrate be coated with dielectric film.
In the manufacture method of semiconductor device according to the invention, preferably before injecting, raceway groove anneals immediately.
In the manufacture method of semiconductor device according to the invention, preferably before the growth gate polysilicon, anneal immediately.
In the manufacture method of semiconductor device according to the invention, preferably before CMP, anneal immediately.
In the manufacture method of semiconductor device according to the invention, preferably before removing the pad oxide-film, anneal immediately.
In the manufacture method of semiconductor device according to the invention, can be after the growth buried oxidation film in the technology during the growth gate polysilicon, be increased in the annealing steps in high temperature, the rare gas atmosphere, with the STI turning of boundary between sphering isolated area and the active area.And annealing steps can not introduced nitrogen to the influence on oxide-film and the silicon interface in rare gas atmosphere, and therefore stable fixing electric charge and interface level be provided.Therefore, under the condition that does not have localized variation on the thickness, by making the turning rounding, eliminating the influence of nitrogen on the silicon interface and the gate oxidation films that forms high reliability, this method can be made the semiconductor device of high reliability.
Description of drawings
Fig. 1 is the flow chart that illustrates according to the technology of first embodiment;
Fig. 2 A to 2E is the profile according to the semiconductor device of first embodiment;
Fig. 3 A to 3D shows the shape at turning;
Fig. 4 is the graph of a relation that illustrates between annealing steps and the turning radius of curvature;
Fig. 5 is the graph of a relation that illustrates between annealing time and the turning radius of curvature;
Fig. 6 is the figure that CV curvature is shown;
Fig. 7 illustrates the graph of a relation between the annealing conditions and capacitance in the reversing mode;
Fig. 8 is the graph of a relation that illustrates between annealing conditions and the Qbd;
Fig. 9 is the figure that the Vg-Id characteristic is shown; And
Figure 10 is the graph of a relation that illustrates between annealing conditions and the threshold value.
Embodiment
The manufacture method of semiconductor device according to the invention is described referring now to each figure.
At first, on the first type surface of silicon substrate 1, form thick pad oxide-film 2 and the thick nitride film 3 of 140nm of 9nm, shown in the step S1 and S2 and Fig. 2 A of Fig. 1.Then by photoetching etching nitride film 3 and pad oxide-film 2, and etched silicon substrate 1 is to form groove 4, shown in the step S3 and Fig. 2 A of Fig. 1.The inwall of oxidation groove 4 is to form the thick inner wall oxide film 5 of 20nm.Fill up groove 4 with buried oxidation film 6 then, shown in the step S4 and S5 and Fig. 2 B of Fig. 1.
By chemico-mechanical polishing (CMP) polishing buried oxidation film 6,, shown in the step S6 of Fig. 1, and form smooth surface thus until exposing nitride film 3.Remove nitride film 3 and pad oxide-film 2 then to expose active area, shown in the step S7 and Fig. 2 C of Fig. 1.Etching took place when removing nitride film 3 and pad oxide-film 2.As a result, the top of inner wall oxide film 5 is etched, to expose the part inwall of the groove 4 on silicon substrate 1.The STI turning refers to the border between the first type surface of the inwall of groove 4 and silicon substrate 1.This moment, the STI turning was cubic.Expose silicon substrate 1 in STI corner, and form groove between isolated area and active area, this groove is denoted as indenture (divot) 9 in Fig. 2 C.
Form the thick sacrificial oxidation film 7 of 10nm, shown in the step S8 and Fig. 2 D of Fig. 1.This oxide-film 7 in cubic STI corner than thin on first type surface.Inject with after regulating transistorized threshold value at ion, remove sacrificial oxidation film 7, shown in the step S9 and S10 of Fig. 1.Etching has appearred crossing when removing sacrificial oxidation film 7.As a result, expose silicon substrate 1 once more in STI corner, the STI turning is still cubic.
Form gate oxidation films 8, shown in the step S11 and Fig. 2 E of Fig. 1.Gate oxidation films 8 has thin part on cubic STI turning, and electric field concentrates on the turning thus.The gate polysilicon film is grown on gate oxidation films 8, and carry out remaining transistor fabrication, shown in the step S12 of Fig. 1.
In the above-mentioned key step S1 to S12 of the normality transistor fabrication of being undertaken by STI, in order to improve the reliability of gate oxidation films 8, the inventor has imagined the method for revising the STI corner shape by annealing.Add annealing in process 1,2 and 3 to this technology, as annealing steps SA1 to SA3, shown in Fig. 1 right side.Check to the rounding at STI turning between isolated area and the active area with about the relation of annealing atmosphere.The inspection data that the result is obtained are shown among Fig. 3 A to 10.
Fig. 3 A to 4 shows and does not add annealing steps, adds annealing steps SA2 and add the comparative result of the situation of annealing steps SA3 in formation gate oxidation films 8 backs after adding annealing steps SA1 behind the growth buried oxidation film 6, forming sacrificial oxidation film 7.In blanket of nitrogen, carried out annealing steps SA1 to SA3 one hour at 1,000 ℃.According to this result, the annealing steps SA1 behind growth buried oxidation film 6 compares the radius of curvature that has increased about 0.5nm with the radius of curvature that does not have annealing steps, and promptly radius of curvature surpasses 2nm.Annealing steps SA2 after forming sacrificial oxidation film 7 increases the radius of curvature of about 1.5nm, and promptly radius of curvature is 3.5nm.Annealing steps SA3 after forming gate oxidation films 8 increases the radius of curvature of about 7nm, and promptly radius of curvature is 9nm.
Fig. 3 A to 3D shows the observed result of these shapes.Fig. 3 A shows the shape that does not have annealing steps.Fig. 3 B shows the shape of utilizing annealing steps SA1 behind growth buried oxidation film 6.Fig. 3 C shows the shape of utilizing annealing steps SA2 after forming sacrificial oxidation film 7.Fig. 3 D shows the shape of utilizing annealing steps SA3 after forming gate oxidation films 8.According to the order of Fig. 3 A to 3D, the shape at STI turning is better, and is promptly round.Therefore, being used to make the best annealing steps of turning rounding is annealing steps SA3 after forming gate oxidation films 8.The secondth, the annealing steps SA2 after forming sacrificial oxidation film 7, and the 3rd be annealing steps SA1 behind growth buried oxidation film 6.
After forming transistor, observed the shape that is shown among Fig. 3 A to 3D.According in the check result at step place separately, by making STI turning rounding forming arbitrary oxide-film after annealing.After the annealing, remove oxide-film exposing silicon substrate 1, and on substrate 1, form another oxide-film.The turning of rounding becomes square once more by oxidation then.If forming gate oxidation films 8 backs, then film 8 is left at last and not and removes, so that make the turning keep circular to turning annealing.If forming sacrificial oxidation film 7 backs to turning annealing, then the STI turning of rounding becomes not too round by gate oxidation after removing sacrificial oxidation film 7.If forming buried oxidation film 6 backs to turning annealing, then the STI turning of rounding becomes still not too round by two oxidation steps that are used to form sacrificial oxidation film 7 and gate oxidation films 8.The gate oxidation films 8 that is formed on the STI turning of rounding has than there not being the higher reliability of annealing steps.
When Fig. 5 shows and forms sacrificial oxidation film 7 backs carry out annealing steps SA2 in blanket of nitrogen about the result of annealing temperature and time relationship.These results show a small amount of that has obtained the turning radius of curvature 1,100 ℃ of annealing to be increased, and has obtained the bigger increase of radius of curvature and the time is had bigger dependence 1,150 ℃ of annealing.Therefore preferably under higher temperature, anneal the longer time.
Fig. 7 shows when annealing the relation about annealing conditions and gate oxidation condition after forming sacrificial oxidation film 7.Measure and the capacitance Cinv between grid and the substrate 1 in reversing mode relatively by the CV method.In the method, on the two ends that voltage are applied to grid and substrate 1, according to accumulation, exhaust with reversing mode in capacitance estimate the quality at gate oxidation films 8 and its interface, as shown in Figure 6.
With reference to figure 7, the capacitance in the reversing mode has shown under blanket of nitrogen, has not changed behind 1,100 ℃ of annealing one hour and smelting furnace wet oxidation, and annealing and with having reduced behind atomic group or the salt acid oxidase under blanket of nitrogen.Then the capacitance minimizing is bigger also to experience the longer time under higher temperature.On the other hand, show not minimizing of capacitance after 1,100 ℃ of annealing was also used the atomic group gate oxidation in a hour or three hours under argon atmospher.
These results be likely owing under blanket of nitrogen with high annealing during nitrogen invade or intrude in the active area and cause in the oxide-film on groove 4 inwalls.Even remove the sacrificial oxidation film 7 in the active area and form gate oxidation films 8 again, the influence of the nitrogen of the capacitance in the reversing mode by being retained in the silicon interface place reduces, in the inner wall oxide film 5 of this silicon interface boundary in active area and between isolated area and the active area.Therefore on the other hand, for being that annealing this reaction can not occur in the argon gas at rare gas, and the capacitance in the reversing mode is not affected and do not demonstrate minimizing.
And the annealing after forming sacrificial oxidation film 7 under the condition that changes is to determine above result.Fig. 8 shows the Qbd (breakdown charge) of gate oxidation films 8.Fig. 9 shows transistorized Vg-Id characteristic.Figure 10 shows transistorized threshold value.In Fig. 8, the 50%Qbd value after 1,100 ℃ or 1,150 ℃ of annealing and increasing after one hour 1,100 ℃ of annealing under the argon atmospher, but reduces after one hour 1,100 ℃ of annealing two hours with 1,150 ℃ of annealing under blanket of nitrogen under argon atmospher.By the influence at sphering turning, under blanket of nitrogen, can form the oxide-film of uniform thickness in one hour 1,100 ℃ of annealing, increasing Qbd, and since the adverse effect of nitrogen under blanket of nitrogen, annealed two hours or reduced Qbd 1,150 ℃ of annealing.
According to transistorized Vg-Id characteristic among Fig. 9, under blanket of nitrogen, after one hour, knot and cut-off leakage current occur and flow 1,100 ℃ of annealing.On the other hand, similar 1,100 ℃ or result after 1,150 ℃ of annealing under argon atmospher to the result who does not have annealing, and knot does not appear.Figure 10 shows 10
-8The threshold value that A leakage current place is measured.In Figure 10, annealing has caused the threshold value of a large amount of declines under blanket of nitrogen.
Above data can be summarized as follows.Annealing can make the turning rounding under nitrogen or argon atmospher.Can increase annealing steps in the technology during the growth gate polysilicon behind the growth buried oxidation film.This silicon substrate is carried out annealing in process not exposing under the situation that silicon substrate and silicon substrate be coated with dielectric film, described dielectric film for example is oxide-film and nitride film.Preferably inject, the growth gate polysilicon, carry out this annealing steps immediately before removing pad oxide-film or CMP at raceway groove.
In addition, long-time with high annealing in blanket of nitrogen, can oxide-film be worsened, and in argon atmospher, can not cause for a long time worsening at high annealing.Therefore, in order to make STI turning rounding fully, argon atmospher allowed in the higher temperature annealing long period.Similarly, because neon and helium is the rare gas of 0 family in the periodic table and is chemically inert, so neon and helium are effective.
And annealing temperature is the range changing from 1,000 ℃ to 1,200 ℃ preferably, more preferably 1,100 ℃ to 1,150 ℃, and the preferred range changing from ten minutes to five hours of annealing time.
In the manufacture method of semiconductor device, as mentioned above, in order to make the STI turning rounding of boundary between isolated area and the active area, the annealing steps in high temperature, rare gas atmosphere can be added to the growth buried oxidation film after until the growth gate polysilicon technology in.And the annealing steps in rare gas atmosphere can not introduced the influence of the nitrogen on oxide-film and the silicon interface, and therefore stable fixing electric charge and interface level be provided.Therefore, when thickness did not have localized variation, by making the turning rounding, eliminating the influence of nitrogen on the silicon interface and the gate oxidation films that forms high reliability, this method can be made the semiconductor device of high reliability.
Though described the present invention with reference to the accompanying drawings particularly, the present invention is not limited to the above embodiments.Certainly, allow various modifications within the scope of the invention.
Claims (8)
1. the manufacture method of a semiconductor device comprises the steps:
On silicon substrate, form groove and be used for device isolation; And
After the growth buried oxidation film,, in comprising the atmosphere of rare gas, silicon substrate is annealed until arbitrary step of growth gate polysilicon.
2. according to the manufacture method of the semiconductor device of claim 1, wherein:
This rare gas is to be selected from least a in the group that is made of argon gas, neon and helium.
3. according to the manufacture method of the semiconductor device of claim 1, wherein:
Carried out this annealing ten minutes to five hours at 1,000 ℃ to 1,200 ℃.
4. according to the manufacture method of the semiconductor device of claim 1, wherein:
This silicon substrate is carried out annealing in process not exposing under the situation that silicon substrate and silicon substrate be coated with dielectric film.
5. according to the manufacture method of the semiconductor device of claim 1, wherein:
Before injecting, raceway groove carries out this annealing immediately.
6. according to the manufacture method of the semiconductor device of claim 1, wherein:
Before the growth gate polysilicon, carry out this annealing immediately.
7. according to the manufacture method of the semiconductor device of claim 1, wherein:
Before CMP, carry out this annealing immediately.
8. according to the manufacture method of the semiconductor device of claim 1, wherein:
Before removing the pad oxide-film, carry out this annealing immediately.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004117798 | 2004-04-13 | ||
| JP2004117798A JP4577680B2 (en) | 2004-04-13 | 2004-04-13 | Manufacturing method of semiconductor device |
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| CN1684242A true CN1684242A (en) | 2005-10-19 |
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| JP (1) | JP4577680B2 (en) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102446762A (en) * | 2010-10-13 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide silicon (MOS) transistor and production method thereof |
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| US7432148B2 (en) * | 2005-08-31 | 2008-10-07 | Micron Technology, Inc. | Shallow trench isolation by atomic-level silicon reconstruction |
| US8125037B2 (en) * | 2008-08-12 | 2012-02-28 | International Business Machines Corporation | Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage |
| US7838353B2 (en) * | 2008-08-12 | 2010-11-23 | International Business Machines Corporation | Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method |
| CN102332400B (en) * | 2011-07-28 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor device |
| US9945048B2 (en) * | 2012-06-15 | 2018-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method |
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| DE69211329T2 (en) * | 1992-03-27 | 1996-11-28 | Ibm | Method for producing pseudo-planar thin-film PFET devices and structure produced thereby |
| JP4420986B2 (en) * | 1995-11-21 | 2010-02-24 | 株式会社東芝 | Shallow trench isolated semiconductor substrate and method of manufacturing the same |
| JPH1079421A (en) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | Manufacturing method of semiconductor integrated circuit device |
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| JP3575408B2 (en) * | 2000-08-15 | 2004-10-13 | セイコーエプソン株式会社 | Method of manufacturing semiconductor device having trench element isolation region |
| US6455382B1 (en) * | 2001-05-03 | 2002-09-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-step method for forming sacrificial silicon oxide layer |
| JP3597495B2 (en) * | 2001-08-31 | 2004-12-08 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| JP4123961B2 (en) * | 2002-03-26 | 2008-07-23 | 富士電機デバイステクノロジー株式会社 | Manufacturing method of semiconductor device |
| US6713335B2 (en) * | 2002-08-22 | 2004-03-30 | Chartered Semiconductor Manufacturing Ltd. | Method of self-aligning a damascene gate structure to isolation regions |
| US7091105B2 (en) * | 2002-10-28 | 2006-08-15 | Hynix Semiconductor Inc. | Method of forming isolation films in semiconductor devices |
| EP1602125B1 (en) * | 2003-03-07 | 2019-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shallow trench isolation process |
| JP2004273971A (en) * | 2003-03-12 | 2004-09-30 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| KR100505068B1 (en) * | 2003-07-05 | 2005-07-29 | 삼성전자주식회사 | method of forming gate oxide layer in semiconductor device and method of gate electrode of the same |
| US7018873B2 (en) * | 2003-08-13 | 2006-03-28 | International Business Machines Corporation | Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate |
| JP4550453B2 (en) * | 2004-03-23 | 2010-09-22 | 株式会社東芝 | Process management system and process management method |
-
2004
- 2004-04-13 JP JP2004117798A patent/JP4577680B2/en not_active Expired - Fee Related
-
2005
- 2005-04-12 US US11/103,613 patent/US20050227452A1/en not_active Abandoned
- 2005-04-13 CN CN200510064979.XA patent/CN1684242A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446762A (en) * | 2010-10-13 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide silicon (MOS) transistor and production method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US20050227452A1 (en) | 2005-10-13 |
| JP2005303044A (en) | 2005-10-27 |
| JP4577680B2 (en) | 2010-11-10 |
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