CN1684242A - Method for producing semiconductor device - Google Patents

Method for producing semiconductor device Download PDF

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Publication number
CN1684242A
CN1684242A CN 200510064979 CN200510064979A CN1684242A CN 1684242 A CN1684242 A CN 1684242A CN 200510064979 CN200510064979 CN 200510064979 CN 200510064979 A CN200510064979 A CN 200510064979A CN 1684242 A CN1684242 A CN 1684242A
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China
Prior art keywords
annealing
oxide film
semiconductor device
method
manufacturing
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CN 200510064979
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Chinese (zh)
Inventor
大桥拓夫
诹访刚
久保田大志
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尔必达存储器株式会社
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Priority to JP2004117798A priority Critical patent/JP4577680B2/en
Application filed by 尔必达存储器株式会社 filed Critical 尔必达存储器株式会社
Publication of CN1684242A publication Critical patent/CN1684242A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28238Making the insulator with sacrificial oxide

Abstract

一种半导体器件的制造方法,包括如下步骤:在硅衬底上形成沟槽用于器件隔离;以及在从生长掩埋氧化膜之后直至生长栅多晶硅的期间的任一步骤中,在包含稀有气体的气氛中对硅衬底进行退火。 A method for manufacturing a semiconductor device, comprising the steps of: forming a trench on a silicon substrate for device isolation; and during either step after the buried oxide film grown up from the growth of the gate polysilicon, comprising a rare gas atmosphere for annealing the silicon substrate.

Description

半导体器件的制造方法 A method of manufacturing a semiconductor device

技术领域 FIELD

本发明涉及半导体器件的制造方法,且尤其涉及通过提高在沟槽隔离区和有源区之间边界处的栅氧化膜的可靠性,在不使器件特性恶化的条件下制造半导体器件的方法。 The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method by increasing the gate oxide film at the boundary between the active region and the trench isolation regions reliability of manufacturing a semiconductor device without deteriorating the device characteristics of conditions.

背景技术 Background technique

近年来,对更大规模、更高速度的半导体器件的需求已日益增加。 In recent years, on a larger scale, the demand for higher-speed semiconductor devices has been increasing. 为了满足该需求,已使用STI(浅沟槽隔离)作为隔离器件的方法。 To meet this demand, it has been used STI (Shallow Trench Isolation) method as a separator device. 在STI中,将绝缘膜掩埋在沟槽中以实现隔离。 In the STI, the insulating film is buried in the trench to achieve isolation. 因此,该方法和LOCOS(硅的局部氧化)相比没有产生鸟嘴效应,且适合于获得高的集成度。 Thus, the method and LOCOS (local oxidation of silicon) is not generated compared to bird's beak effect, and is suitable for obtaining a high degree of integration.

然而,在STI中,在有源区即主硅表面和隔离区即沟槽之间的边界处形成四方STI拐角。 However, in the STI, i.e., formed in four corners of the main STI silicon surface and the boundary between the isolation region trench region that is active. 结果,栅氧化膜在拐角处具有薄的部分,且由此电场集中在拐角处。 As a result, gate oxide film having a thin portion at the corner, and thus the electric field concentration at the corner. 因此这些拐角使栅氧化膜的可靠性和晶体管的性能发生不期望的恶化。 It is not desired that the deterioration of the corners of the gate oxide film and the reliability performance of these transistors to occur.

在相关技术中,使STI沟槽的内壁氧化和氮化,以形成内壁氮氧化膜,该内壁氮氧化膜被留下以免暴露出STI拐角。 In the related art, the inner wall of the oxidation and nitridation STI trenches, to form an oxynitride film inner wall, the inner wall of the oxynitride film is left so as not to expose the STI corners. 该氮氧化膜抑制了栅绝缘膜的薄部分的形成和电场集中,以提高栅绝缘膜的可靠性。 The oxynitride film inhibits the formation of an electric field and a thin portion of the gate insulating film of the concentration to improve the reliability of the gate insulating film.

例如,在日本未审专利申请公开(JP-A)No.2001-135720、64-33935、4-103173和10-41241中公开了上述相关的技术。 For example, in Japanese Unexamined Patent Application Publication (JP-A) No.2001-135720,64-33935,4-103173 and 10-41241 disclose related art described above.

然而,在上述相关技术中,氮氧化膜中包含的氮起到正电荷的作用,对硅界面产生了不利的影响。 However, in the related art, the nitrogen contained in the oxynitride film acts as a positive charge, the silicon interface adversely affected. 另外,即使沟槽的内壁被氮氧化,栅氧化膜的形成也受到了抑制,因此,该膜具有薄的部分。 Further, even if the wall of the trench is oxynitride, forming a gate oxide film is also suppressed, and therefore, the film has a thin portion. 因此,相关技术不希望地使栅氧化膜的可靠性和晶体管的性能发生不期望的恶化,因为栅氧化膜具有薄的部分且电场集中。 Thus, the related art undesirably performance and reliability of gate oxide film transistor undesirable deterioration occurs, since the gate oxide film having a thin portion and the electric field concentration.

发明内容 SUMMARY

因此,本发明的目的在于提供一种高可靠性的半导体器件的制造方法,其在栅氧化膜的厚度没有局部变化的情况下能够提高栅氧化膜的可靠性。 Accordingly, an object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device, it is possible to improve the reliability of the gate oxide film at a thickness of the gate oxide film is not locally varying circumstances.

本发明提供了一种半导体器件的制造方法。 The present invention provides a method of manufacturing a semiconductor device. 该方法包括以下步骤:在硅衬底上形成沟槽用于器件隔离;以及在从生长掩埋氧化膜后直至栅多晶硅生长的期间的任一步骤中,在包含稀有气体的气氛中对硅衬底进行退火,以使得STI拐角圆形化。 The method comprises the steps of: forming a trench on a silicon substrate for device isolation; and during any step after the buried oxide film grown up from the gate polysilicon grown in an atmosphere containing a rare gas in the silicon substrate annealing, so that the STI corners rounded.

在根据本发明的半导体器件的制造方法中,稀有气体优选为氩气、氖气或氦气。 In the semiconductor device manufacturing method according to the present invention, the noble gas is preferably argon, helium or neon.

在根据本发明的半导体器件的制造方法中,优选在1,000℃至1,200℃进行该退火十分钟至五小时。 In the method of manufacturing a semiconductor device according to the present invention, preferably 1,000 deg.] C to 1,200 deg.] C in the annealing according ten to five minutes.

在根据本发明的半导体器件的制造方法中,优选的是在没有暴露出硅衬底并且硅衬底覆盖有绝缘膜的情况下对该硅衬底进行退火处理。 In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the silicon substrate is annealed without exposing the silicon substrate and the silicon substrate is covered with an insulating film according to the.

在根据本发明的半导体器件的制造方法中,优选在沟道注入之前立即进行退火。 In the method of manufacturing a semiconductor device according to the present invention, annealing is preferably performed immediately before injection channel.

在根据本发明的半导体器件的制造方法中,优选在生长栅多晶硅之前立即进行退火。 In the semiconductor device manufacturing method according to the present invention, annealing is preferably performed immediately prior to the growth of gate polysilicon.

在根据本发明的半导体器件的制造方法中,优选在CMP之前立即进行退火。 In the method of manufacturing a semiconductor device according to the present invention, annealing is preferably performed immediately before the CMP.

在根据本发明的半导体器件的制造方法中,优选在移除垫氧化膜之前立即进行退火。 In the semiconductor device manufacturing method according to the present invention, annealing is preferably performed immediately prior to removing the pad oxide film.

在根据本发明的半导体器件的制造方法中,可在生长掩埋氧化膜之后直至生长栅多晶硅的期间的工艺中,增加在高温、稀有气体气氛中的退火步骤,以圆化隔离区和有源区之间边界处的STI拐角。 In the semiconductor device manufacturing method according to the present invention, the gate may be grown after the growth until the buried oxide film during the process of polycrystalline silicon, an annealing step at a high temperature increases, the rare gas atmosphere, rounded to the isolation region and the active region at the corner boundary between the STI. 而且,在稀有气体气氛中退火步骤不会引入氮对氧化膜和硅界面上的影响,且因此提供了稳定的固定的电荷和界面水平。 Further, in a rare gas atmosphere in the annealing step does not introduce the effects of nitrogen on the silicon oxide film and the interface, thus providing a stable and fixed charges and interface levels. 因此,在厚度上没有局部变化的条件下,通过使拐角圆形化、消除硅界面上氮的影响以及形成高可靠性的栅氧化膜,该方法可以制造高可靠性的半导体器件。 Thus, under no local variation in thickness, by rounded corners to eliminate the effects of nitrogen on the silicon interface and the formation of a highly reliable gate oxide film, the method may manufacturing a highly reliable semiconductor device.

附图说明 BRIEF DESCRIPTION

图1是示出根据第一实施例的工艺的流程图;图2A至2E是根据第一实施例的半导体器件的剖面图;图3A至3D示出了拐角的形状;图4是示出退火步骤和拐角曲率半径之间的关系图;图5是示出退火时间和拐角曲率半径之间的关系图;图6是示出CV曲率的图;图7是示出反转模式中退火条件和电容量之间的关系图;图8是示出退火条件和Qbd之间的关系图;图9是示出Vg-Id特性的图;以及图10是示出退火条件和阈值之间的关系图。 FIG 1 is a flowchart illustrating a process of the first embodiment; FIGS. 2A to 2E is a sectional view of the semiconductor device of the first embodiment; FIGS. 3A to 3D show a shape of the corner; FIG. 4 is a diagram illustrating the annealing and the relationship between the curvature radius of corner step; FIG. 5 is a diagram showing a relationship between annealing time and the curvature radius of corner; FIG. 6 is a diagram illustrating curvature CV; Figure 7 is a diagram illustrating the inversion mode and the annealing conditions the relation between the capacity; FIG. 8 is a diagram illustrating the relationship between the Qbd and the annealing conditions; FIG. 9 is a graph illustrating Vg-Id characteristics of Figure 1; and FIG. 10 is a diagram illustrating the relationship between the annealing conditions and thresholds .

具体实施方式 Detailed ways

现在将参考各图描述根据本发明的半导体器件的制造方法。 Now be described with reference to the drawings a method for manufacturing a semiconductor device according to the present invention.

首先,在硅衬底1的主表面上形成9nm厚的垫氧化膜2和140nm厚的氮化膜3,如图1的步骤S1和S2及图2A所示。 First, a pad oxide film 2 and a thickness of 9nm 140nm thick nitride film on the main surface 3 of the silicon substrate 1, as shown in step 1, and S1 and S2 shown in FIG. 2A. 然后通过光刻蚀刻氮化膜3和垫氧化膜2,并蚀刻硅衬底1以形成沟槽4,如图1的步骤S3和图2A所示。 Then the nitride film 3 is etched by photolithography and the pad oxide film 2 and silicon substrate 1 is etched to form the trench 4, the step S3 of FIG. 1 and FIG. 2A. 氧化沟槽4的内壁以形成20nm厚的内壁氧化膜5。 Oxidizing an inner wall of the trench 4 to form a 20nm-thick oxide film 5 of the inner wall. 然后用掩埋氧化膜6填满沟槽4,如图1的步骤S4和S5及图2B所示。 6 is then filled in the grooves 4 with a buried oxide film, as shown in steps S4 and S5. 1 and 2B.

通过化学机械抛光(CMP)抛光掩埋氧化膜6,直至露出氮化膜3,如图1的步骤S6所示,且由此形成平坦的表面。 By chemical mechanical polishing (CMP) polishing the buried oxide film 6, until the nitride film 3 is exposed, as shown in step S6 in FIG. 1, and thereby form a flat surface. 然后移除氮化膜3和垫氧化膜2以暴露出有源区,如图1的步骤S7和图2C所示。 The nitride film 3 is then removed and the pad oxide film 2 to expose the active region, a step S7 of FIG. 2C and FIG. 在移除氮化膜3和垫氧化膜2时发生过蚀刻。 Overetching occurs upon removal of the nitride film 3 and the pad oxide film 2. 结果,内壁氧化膜5的顶部被蚀刻,以暴露出在硅衬底1上的沟槽4的部分内壁。 As a result, the top of the inner wall oxide film 5 is etched to expose part of the inner wall of the silicon substrate 1 on the trench 4. STI拐角指的是在沟槽4的内壁和硅衬底1的主表面之间的边界。 STI comers means that the boundary between the main surface of the silicon substrate and the inner wall of the trench 4 1. 此时STI拐角是四方的。 At this STI corner of the Quartet. 在STI拐角处暴露出硅衬底1,且在隔离区和有源区之间形成凹槽,该凹槽在图2C中被标示为凹痕(divot)9。 STI is exposed at the corners of the silicon substrate 1, and a groove is formed between the isolation region and the active region, the groove is denoted as dimples (divot) 9 in FIG. 2C.

形成10nm厚的牺牲氧化膜7,如图1的步骤S8和图2D所示。 10nm thick sacrificial oxide film 7 is formed, the step S8 of FIG. 1 and FIG. 2D. 该氧化膜7在四方STI拐角处比在主表面上薄。 The thin oxide film 7 on the main surface than in the four corners of the STI. 在离子注入以调节晶体管的阈值之后,移除牺牲氧化膜7,如图1的步骤S9和S10所示。 In the ion implantation to adjust the threshold value of the transistor after removing the sacrificial oxide film 7, as shown in steps S9 and S10 shown in FIG. 1. 在移除牺牲氧化膜7时出现了过蚀刻。 Overetching occurred upon removal of the sacrificial oxide film 7. 结果,在STI拐角处再次暴露出硅衬底1,STI拐角仍是四方的。 As a result, the STI corners of the silicon substrate 1 is exposed again, the STI comers remain square.

形成栅氧化膜8,如图1的步骤S11和图2E所示。 Forming a gate oxide film 8, step S11 in FIG. 1 and FIG. 2E. 栅氧化膜8在四方STI拐角上具有薄的部分,且由此电场集中在拐角上。 A thin gate oxide film 8 having a square portion on the STI comers, and thereby an electric field concentration at the corner. 使栅多晶硅膜在栅氧化膜8上生长,并进行其余的晶体管制造工艺,如图1的步骤S12所示。 The gate polysilicon film is grown on the gate oxide film 8, and the rest of the transistor fabrication process, as shown in step S12 of FIG 1.

在通过STI进行的常态晶体管制造工艺的上述主要步骤S1至S12中,为了提高栅氧化膜8的可靠性,本发明人设想了通过退火修改STI拐角形状的方法。 In the main steps of the manufacturing process carried out by the normal STI transistor Sl to S12, the order to improve the reliability of the gate oxide film 8, the present invention contemplates a method for modifying the shape of the STI comers by annealing. 将退火处理1、2和3添加到该工艺,作为退火步骤SA1至SA3,如图1右侧所示。 2 and 3 the annealing treatment is added to the process, as the steps SA1 to SA3, annealing, as shown in Figure 1 on the right side. 对隔离区和有源区之间STI拐角的圆形化和关于退火气氛的关系进行检查。 Circular relationship between the annealing atmosphere and the corner between the STI isolation region and the active region to be checked. 将结果得到的检查数据示于图3A至10中。 The inspection data obtained results are shown in Figures 3A to 10.

图3A至4示出了没有添加退火步骤、在生长掩埋氧化膜6后添加退火步骤SA1、在形成牺牲氧化膜7后添加退火步骤SA2以及在形成栅氧化膜8后添加退火步骤SA3的情况的比较结果。 3A to 4 illustrate without adding an annealing step to add an annealing step SA1 after the growth of the buried oxide film 6, forming the sacrificial oxide film is added after 7 annealing step SA2, and in the case of adding an annealing step after 8 forming a gate oxide film SA3 is Comparing results. 在氮气氛中、在1,000℃进行退火步骤SA1至SA3一小时。 , An annealing step SA1 to SA3 1,000 deg.] C for one hour in a nitrogen atmosphere. 根据该结果,在生长掩埋氧化膜6后的退火步骤SA1与没有退火步骤的曲率半径相比增加了约0.5nm的曲率半径,即曲率半径超过2nm。 From this result, the step of annealing after growth of the buried oxide film 6 with a radius of curvature SA1 annealing step is not increased compared to the radius of curvature of about 0.5nm, i.e., the radius of curvature of more than 2nm. 在形成牺牲氧化膜7后的退火步骤SA2增加约1.5nm的曲率半径,即曲率半径为3.5nm。 After the sacrificial oxide film 7 is formed annealing step SA2 increase of about 1.5nm radius of curvature, i.e. a curvature radius of 3.5nm. 在形成栅氧化膜8后的退火步骤SA3增加约7nm的曲率半径,即曲率半径为9nm。 In the gate oxide film 8 is formed after the annealing step SA3 increase the radius of curvature of about 7nm, i.e., radius of curvature of 9nm.

图3A至3D示出了这些形状的观察结果。 3A to 3D illustrate observation results of these shapes. 图3A示出了没有退火步骤的形状。 Figure 3A shows the shape without annealing step. 图3B示出了在生长掩埋氧化膜6后利用退火步骤SA1的形状。 FIG 3B shows the shape of the growth of the buried oxide film after an annealing step 6 of SA1. 图3C示出了在形成牺牲氧化膜7后利用退火步骤SA2的形状。 FIG 3C shows the shape after forming a sacrificial oxide film 7 of an annealing step SA2. 图3D示出了在形成栅氧化膜8后利用退火步骤SA3的形状。 Figure 3D shows the shape after forming the gate oxide film 8 in an annealing step SA3. 按照图3A至3D的顺序,STI拐角的形状更好,即更圆。 3A to 3D in the order, the shape of the STI comers better, i.e. more rounded. 因此,用于使拐角圆形化的最好退火步骤是在形成栅氧化膜8后的退火步骤SA3。 Thus, for rounding the corners is preferably formed in the annealing step is an annealing step SA3 8 after the gate oxide film. 第二是在形成牺牲氧化膜7后的退火步骤SA2,且第三是在生长掩埋氧化膜6后的退火步骤SA1。 7 is a second annealing step after the sacrificial oxide film is formed SA2, and the third burying growth in the annealing step SA1 after the oxide film 6.

在形成晶体管后观察到了示于图3A至3D中的形状。 After forming a transistor was observed in the shape shown in FIG. 3A to 3D. 根据在各自步骤处的检查结果,通过在形成任一氧化膜后退火使STI拐角圆形化。 The check result at each step, by annealing after formation of an oxide film so that any of the STI comers rounded. 退火后,移除氧化膜以暴露出硅衬底1,并在衬底1上形成另一氧化膜。 After annealing, the oxide film is removed to expose the silicon substrate 1, and another oxide film is formed on the substrate 1. 然后圆形化的拐角通过氧化再次变为四方形。 Then rounded corner square changed again by oxidation. 如果在形成栅氧化膜8后对拐角退火,则将膜8留到最后而不移除,以便使拐角保持圆形。 If the corner annealed after forming the gate oxide film 8, the membrane 8 will remain without removing the end, so that the corner remains circular. 如果在形成牺牲氧化膜7后对拐角退火,则圆形化的STI拐角在移除牺牲氧化膜7后通过栅氧化而变得不太圆。 If the sacrificial oxide film is formed after seven pairs of corner annealing, the rounded corners of the STI after removing the sacrificial oxide film 7 is unlikely to become circular by a gate oxide. 如果在形成掩埋氧化膜6后对拐角退火,则圆形化的STI拐角通过用于形成牺牲氧化膜7和栅氧化膜8的两个氧化步骤而变得还是不太圆。 Becomes less round or sacrificial oxide film 7 and gate oxide film two oxidation step 8 if the buried oxide film is formed after six pairs of annealed corner, of the rounded corners formed by a STI. 形成在圆形化的STI拐角上的栅氧化膜8具有比没有退火步骤更高的可靠性。 A gate oxide film is formed on the STI rounded corner 8 with a higher reliability than without the annealing step.

图5示出了形成牺牲氧化膜7后在氮气氛中进行退火步骤SA2时关于退火温度和时间关系的结果。 Figure 5 illustrates the formation of a sacrificial oxide film results for the relationship between annealing temperature and time of the annealing step SA2 in a nitrogen atmosphere after 7. 这些结果示出了在1,100℃退火获得了拐角曲率半径的小量增加,而在1,150℃退火获得了曲率半径较大增加且对时间具有更大的依赖性。 These results show that annealing at 1,100 deg.] C to obtain a small increase in the radius of curvature of a corner, in annealed 1,150 deg.] C to obtain a larger radius of curvature and has a greater increase in dependence on time. 因此优选在更高的温度下进行退火更长的时间。 Annealing is preferably carried out in a longer time at higher temperatures.

图7示出了在形成牺牲氧化膜7后进行退火时关于退火条件和栅氧化条件的关系。 Figure 7 shows a time annealing after forming the sacrificial oxide film 7 on the relationship between the annealing conditions and the conditions of gate oxide. 通过CV法测量和比较在反转模式中栅极和衬底1之间的电容量Cinv。 CV method by measuring and comparing the capacitance between a Cinv inversion mode in the gate and the substrate. 在该方法中,通过将电压施加到栅极与衬底1的两端上,根据累积、耗尽和反转模式中的电容量来估算栅氧化膜8和其界面的质量,如图6所示。 In this method, by applying a voltage to both ends of the gate and the substrate 1, to estimate the quality of the gate oxide film 8 and the capacitance of the interface according to the accumulation, depletion and inversion mode, FIG. 6 shows.

参考图7,反转模式中的电容量显示了在氮气氛下、在1,100℃退火一小时和熔炉湿法氧化后没有改变,且在氮气氛下退火和用原子团或盐酸氧化后减少了。 Referring to Figure 7, the capacitance of the inversion mode is displayed under a nitrogen atmosphere, no change after one hour and 1,100 deg.] C annealing furnace wet oxidation, and post-annealing, and with a hydrochloric acid oxidation radicals or reduced under a nitrogen atmosphere. 在较高的温度下并经历更长时间则电容量减少更大。 At higher temperatures and longer experience the greater reduction in capacity. 另一方面,示出了在氩气氛下在1,100℃退火一小时或三小时并用原子团栅氧化后电容量没有减少。 On the other hand, it shows a one hour anneal 1,100 deg.] C or three hours has not been reduced by the capacitance of the gate oxide radicals under argon atmosphere.

这些结果很可能是由于在氮气氛下以高温退火期间氮侵入或入侵到有源区中和沟槽4内壁上的氧化膜中而引起的。 These results are likely to be due to the invasion of nitrogen during high temperature annealing under a nitrogen atmosphere or intrusion into the oxide film on the active region 4 and the inner wall of the trench caused. 即使移除有源区中的牺牲氧化膜7并且重新形成栅氧化膜8,反转模式中的电容量通过保留在硅界面处的氮的影响而减少,该硅界面位于有源区中以及隔离区和有源区之间边界处的内壁氧化膜5中。 Even if the sacrificial oxide film is removed in the active region 7 and the gate oxide film 8 is formed again, the capacitance of the inversion mode is reduced by the influence of nitrogen remains in the silicon at the interface, the silicon interface of the active region and an isolation an inner wall oxide film at the boundary between the region and the active region 5. 另一方面,对于在稀有气体即氩气中退火不会出现这种反应,且反转模式中的电容量没有受到影响且因此没有显示出减少。 On the other hand, i.e., annealing for such a reaction does not occur in the rare gas argon, and the capacitance of the inversion mode is not affected and thus does not exhibit reduced.

而且,在变化的条件下进行形成牺牲氧化膜7后的退火,以确定以上结果。 Further, for forming a sacrificial oxide film 7 after annealing under varying conditions to determine the above results. 图8示出了栅氧化膜8的Qbd(击穿电荷)。 FIG 8 shows the Qbd (charge to breakdown) of the gate oxide film 8. 图9示出了晶体管的Vg-Id特性。 Figure 9 shows a Vg-Id characteristics of the transistor. 图10示出了晶体管的阈值。 FIG. 10 shows a threshold value of the transistor. 在图8中,50%Qbd值在氩气氛下在1,100℃或1,150℃退火后和在氩气氛下在1,100℃退火一小时后增加,但在氮气氛下在1,100℃退火两小时和在1,150℃退火一小时后减少。 In FIG. 8, 50% Qbd value under an argon atmosphere and after 1,100 ℃ annealed one hour increase after annealing at 1,100 deg.] C or 1,150 deg.] C under an argon atmosphere, in a nitrogen atmosphere at 1,100 deg.] C annealing two hours and at 1,150 deg.] C after one hour annealing reduction. 通过圆化拐角的影响,在氮气氛下在1,100℃退火一小时能够形成均匀厚度的氧化膜,以增加Qbd,而由于氮的不利影响在氮气氛下退火两小时或在1,150℃退火减少了Qbd。 By influencing rounded corners, under a nitrogen atmosphere can be formed oxide film having a uniform thickness of 1,100 deg.] C annealing for one hour to increase the Qbd, and because the adverse effects of nitrogen in the nitrogen atmosphere annealed two hours or reduce Qbd annealing at 1,150 deg.] C .

根据图9中晶体管的Vg-Id特性,在氮气氛下在1,100℃退火一小时后,出现纽结且截止漏电流流动。 The Vg-Id characteristics of the transistor in FIG. 9, under a nitrogen atmosphere at 1,100 deg.] C after annealing for one hour and kink occurs off leak current flows. 另一方面,在氩气氛下在1,100℃或在1,150℃退火后的结果与没有退火的结果相似,且没有出现纽结。 On the other hand, under an argon atmosphere at 1,100 deg.] C or similar results after annealing results without annealing and 1,150 deg.] C, and does not appear in the kink. 图10示出了在10-8A漏电流处测量的阈值。 FIG. 10 shows a threshold leakage current measured at the 10-8A. 在图10中,在氮气氛下退火引起了大量下降的阈值。 In FIG 10, annealed in a nitrogen atmosphere to cause a large drop threshold.

以上数据可概括如下。 The above data may be summarized as follows. 退火可以在氮或氩气氛下使拐角圆形化。 Annealing allows the corner under a nitrogen or argon atmosphere rounded. 可在生长掩埋氧化膜后直至生长栅多晶硅期间的工艺中增加退火步骤。 It can grow until the polysilicon gate process during the annealing step to increase the buried oxide film after growth. 在没有暴露出硅衬底并且硅衬底覆盖有绝缘膜的情况下对该硅衬底进行退火处理,所述绝缘膜例如是氧化膜和氮化膜。 The silicon substrate is annealed without exposing the silicon substrate and the silicon substrate is covered with an insulating film, the insulating film such as an oxide film and a nitride film. 优选在沟道注入、生长栅多晶硅、移除垫氧化膜或CMP之前立即进行该退火步骤。 Preferably the channel implantation, the gate polysilicon growth, the annealing step immediately prior to removing the pad oxide film or CMP.

另外,在氮气氛中以高温退火长时间,会由于氮的不利影响而使氧化膜恶化,而在氩气氛中在高温退火长时间不会导致恶化。 Further, in a nitrogen atmosphere at a high temperature annealing for a long time, due to the adverse effects of nitrogen oxide film is deteriorated, and in an argon atmosphere for a long time does not cause deterioration of high-temperature annealing. 因此,为了使STI拐角充分地圆形化,氩气氛允许在较高温度退火较长时间。 Accordingly, in order that the STI corners sufficiently rounded, argon annealing at a higher temperature to allow a longer time. 相似地,由于氖和氦是周期表中0族的稀有气体且是化学惰性的,所以氖和氦是有效的。 Similarly, since neon and helium is a rare gas in group 0 of the periodic table and is chemically inert, it is effective neon and helium.

而且,退火温度优选从1,000℃到1,200℃范围变动,更优选1,100℃到1,150℃,且退火时间优选从十分钟到五小时范围变动。 Further, the annealing temperature preferably ranges from 1,000 to 1,200 deg.] C change deg.] C, more preferably 1,100 deg.] C to 1,150 deg.] C, and the annealing time is preferably from ten minutes to five variations hours.

在半导体器件的制造方法中,如上所述,为了使隔离区和有源区之间边界处的STI拐角圆形化,可将在高温、稀有气体气氛中的退火步骤添加到生长掩埋氧化膜后直至生长栅多晶硅的工艺中。 In the semiconductor device manufacturing method, as described above, in order to make corners at the boundary between the STI isolation region and an active region of a circular, may be added to the buried oxide film is grown at a high temperature, a rare gas atmosphere in the annealing step until the gate polysilicon growth process. 而且,在稀有气体气氛中的退火步骤不会引入氧化膜和硅界面上的氮的影响,且因此提供了稳定的固定的电荷和界面水平。 Further, the annealing step in a rare gas atmosphere does not introduce the effects of nitrogen on the silicon oxide film and the interface, thus providing a stable and fixed charges and interface levels. 因此,在厚度没有局部变化时,通过使拐角圆形化、消除硅界面上氮的影响以及形成高可靠性的栅氧化膜,该方法可以制造高可靠性的半导体器件。 Thus, there is no local variation in thickness, by rounded corners to eliminate the effects of nitrogen on the silicon interface and the formation of a highly reliable gate oxide film, the method may manufacturing a highly reliable semiconductor device.

虽然参考附图以上已具体地描述了本发明,但本发明并不限于上述的实施例。 While the foregoing has been with reference to the drawings the present invention is specifically described, but the present invention is not limited to the embodiments. 当然,在本发明的范围内容许各种修改。 Of course, within the scope of the present invention SUMMARY many various modifications.

Claims (8)

1.一种半导体器件的制造方法,包括如下步骤:在硅衬底上形成沟槽用于器件隔离;以及在生长掩埋氧化膜之后直至生长栅多晶硅的任一步骤,在包含稀有气体的气氛中对硅衬底进行退火。 A method of manufacturing a semiconductor device, comprising the steps of: forming a trench on a silicon substrate for device isolation; and growing the gate until any step after the growth of the buried polycrystalline silicon oxide film in an atmosphere containing a rare gas annealing the silicon substrate.
2.根据权利要求1的半导体器件的制造方法,其中:该稀有气体是选自由氩气、氖气和氦气构成的组中的至少一种。 The method of manufacturing a semiconductor device as claimed in claim 1, wherein: the noble gas is selected from the group consisting of argon, neon and at least one of the group consisting of helium in.
3.根据权利要求1的半导体器件的制造方法,其中:在1,000℃至1,200℃进行该退火十分钟至五小时。 3, wherein the method of manufacturing a semiconductor device as claimed in claim 1: The annealing performed ten to five minutes at 1,000 deg.] C to 1,200 ℃.
4.根据权利要求1的半导体器件的制造方法,其中:在没有暴露出硅衬底并且硅衬底覆盖有绝缘膜的情况下对该硅衬底进行退火处理。 The method of manufacturing a semiconductor device as claimed in claim 1, wherein: the silicon substrate is annealed without exposing the silicon substrate and the silicon substrate is covered with an insulating film.
5.根据权利要求1的半导体器件的制造方法,其中:在沟道注入之前立即进行该退火。 The method of manufacturing a semiconductor device according to claim 1, wherein: the annealing is performed immediately prior to the injection channel.
6.根据权利要求1的半导体器件的制造方法,其中:在生长栅多晶硅之前立即进行该退火。 The method of manufacturing a semiconductor device as claimed in claim 1, wherein: the annealing is performed immediately prior to the growth of gate polysilicon.
7.根据权利要求1的半导体器件的制造方法,其中:在CMP之前立即进行该退火。 7. A method of manufacturing a semiconductor device according to claim 1, wherein: the annealing is performed immediately prior to CMP.
8.根据权利要求1的半导体器件的制造方法,其中:在移除垫氧化膜之前立即进行该退火。 The method of manufacturing a semiconductor device as claimed in claim 1, wherein: the annealing is performed immediately prior to removing the pad oxide film.
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