JP2004273971A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004273971A
JP2004273971A JP2003066111A JP2003066111A JP2004273971A JP 2004273971 A JP2004273971 A JP 2004273971A JP 2003066111 A JP2003066111 A JP 2003066111A JP 2003066111 A JP2003066111 A JP 2003066111A JP 2004273971 A JP2004273971 A JP 2004273971A
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Japan
Prior art keywords
trench
semiconductor device
layer
forming
insulating layer
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JP2003066111A
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Japanese (ja)
Inventor
Kaori Akamatsu
Hiroyuki Kaimoto
Masashi Tsutsui
博之 海本
将史 筒井
かおり 赤松
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Priority to JP2003066111A priority Critical patent/JP2004273971A/en
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Abstract

A semiconductor device having a high driving force and a small variation in characteristics by reducing stress, and a method for manufacturing the same are provided.
In a method for manufacturing a semiconductor device according to the present invention, after an oxide film for a gate insulating film is formed on a semiconductor substrate, a heat treatment is performed in a non-oxidizing atmosphere at a temperature higher than the formation temperature of the oxide film. Is performed to form the gate electrode 12. Thereby, stress generated in the step of forming the oxide film 11 for the gate insulating film and the like can be reduced.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a gate-insulated semiconductor device having an STI (Shallow Trench Isolation) and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, studies have been made on stresses generated in a semiconductor layer in a semiconductor device manufacturing process. For example, Non-Patent Document 1 reports that stress generated in a semiconductor layer during the manufacture of a MISFET affects the driving force of the MISFET.
[0003]
Further, in the manufacturing process of a semiconductor device having an STI, a large stress is generated when the STI is formed. According to Non-Patent Document 2, it is reported that this stress is one of the causes of variations in transistor characteristics and impairs the accuracy of layout design.
[0004]
Furthermore, generation of stress is also reported in the salicide forming process and the interlayer insulating film forming process. In recent years, various measures have been taken to reduce these stresses.
[0005]
FIG. 13 is a sectional view showing a structure of trench element isolation in a conventional semiconductor device. In the trench element isolation shown in FIG. 13, a thermal oxide film 102 formed by removing a part of the semiconductor substrate 101 to cover the side wall of the trench 105, and a first buried layer provided inside the thermal oxide film 102 An oxide film 103 and a second buried oxide film 104 filling the inside of the first buried oxide film 103 are provided. In this structure, since a cavity is formed between the first buried oxide films 103 in the trenches 105 during a high-temperature heat treatment after the formation of the first buried oxide film 103, stress generated in the semiconductor substrate 101 is reduced.
[0006]
[Patent Document 1]
JP 2001-135718 A
[0007]
[Non-patent document 1]
A. Hamada, et al. , "A New Aspect of Mechanical Stress Effects in Scaled MOS Devices," IEEE Trans. Electron Devices, Vol. 38 pp. 895-900, 1991.
[Non-patent document 2]
G. FIG. Scot, et al. , "NMOS Drive CuRnt Reduction Caused by Transistor Layout and Trench Isolation Induced Stress," IEDM Tech. Dig, pp. 827-830, 1999.
[0008]
[Problems to be solved by the invention]
However, in the manufacture of the conventional MISFET, various measures have been taken to reduce the generated stress, but not all the causes of the stress have been clarified, and sufficient improvement has not been made. .
[0009]
In particular, in recent years, with the miniaturization of MISFETs, it has become necessary to more accurately control the thickness of the gate insulating film, and thus oxidation has been performed at lower temperatures. Since the viscosity of the gate insulating film formed at a low temperature is high, the stress given to the semiconductor layer and the like by the gate insulating film increases. As described above, the stress generated at the time of forming the gate insulating film is also in a state that cannot be ignored.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a high driving force and a small variation in characteristics by taking measures to reduce stress, and a method of manufacturing the same.
[0011]
[Means for Solving the Problems]
According to the first method for manufacturing a semiconductor device of the present invention, a step (a) of forming an oxide film for a gate insulating film by thermally oxidizing a surface portion of a semiconductor layer; and the step (a) in a non-oxidizing atmosphere. The method includes a step (b) of performing a heat treatment at a temperature higher than the temperature in the step (a), and a step (c) of forming a gate electrode on the oxide film after the step (b).
[0012]
Thus, stress applied to the semiconductor layer can be reduced, so that a semiconductor device with high driving force can be formed. Further, variation in transistor characteristics can be reduced, so that layout design can be performed more accurately.
[0013]
In the step (b), it is preferable that the heat treatment is performed at a temperature that reduces stress applied to the semiconductor layer.
[0014]
In the step (b), the stress can be reduced more effectively by performing the heat treatment at a temperature of 900 ° C. or more and 1150 ° C. or less.
[0015]
In the step (b), by performing the heat treatment in a rare gas atmosphere or a nitrogen atmosphere, the heat treatment can be performed without a reaction between the gas in the atmosphere and the semiconductor layer or the like.
[0016]
Before the step (a), a step (d) of forming a trench by removing a part of the semiconductor layer, and a step (e) of forming a trench element isolation by filling the trench with an insulating layer. , The stress generated in the step of forming the trench element isolation can also be reduced by the heat treatment.
[0017]
In the step (e), the stress acting on the semiconductor layer can be reduced, for example, when an oxide film for a gate insulating film is formed by forming the trench element isolation having a hole therein.
[0018]
In the step (e), a first insulating layer and a second insulating layer having a different coefficient of thermal expansion from the first insulating layer are formed as the insulating layer, and then the temperature is lowered to thereby form the trench element. By forming a layer having a lower elastic modulus than at least one of the first insulating layer and the second insulating layer as a part of separation, for example, when forming an oxide film for a gate insulating film, Stress acting on the semiconductor layer can be reduced.
[0019]
After the step (d) and before the step (e), the method further includes a step (f) of implanting ions of a heavy ion species into a region of the semiconductor layer located under the trench. Since a defect can be generated in a region of the semiconductor layer located below the trench, stress can be absorbed by the defect.
[0020]
According to the second method for manufacturing a semiconductor device of the present invention, the step (a) of forming an oxygen-containing region by supplying oxygen to the surface portion of the semiconductor layer, and the step of performing heat treatment to form at least the oxygen-containing region The method includes a step (b) of forming an oxide film for a gate insulating film from a part and a step (c) of forming a gate electrode on the oxide film.
[0021]
According to a third method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device in which an element is provided in an element formation region of a semiconductor layer, a portion of the semiconductor layer surrounding a side of the element formation region is provided. The method includes a step (a) of forming a trench by removing the trench, and a step (b) of forming a trench element isolation having a hole therein by filling the trench with an insulating film.
[0022]
Accordingly, when an oxide film for a gate insulating film is formed, stress acting on the semiconductor layer can be reduced, so that a semiconductor device with high driving force can be formed. Since variations in transistor characteristics can be reduced, layout design can be performed more accurately.
[0023]
According to a fourth method of manufacturing a semiconductor device of the present invention, a step (a) of forming a trench by removing a portion of the semiconductor layer surrounding a side of the element formation region, and covering a surface of the trench Forming a first insulating layer and a second insulating layer that covers the first insulating layer and has a different coefficient of thermal expansion from that of the first insulating layer, and then lowers the temperature to reduce the temperature of the first insulating layer; Forming a trench element isolation having a layer having a lower elastic modulus than at least one of the second insulating layer.
[0024]
Accordingly, when an oxide film for a gate insulating film is formed, stress acting on the semiconductor layer can be reduced, so that a semiconductor device with high driving force can be formed. Since variations in transistor characteristics can be reduced, layout design can be performed more accurately.
[0025]
In a fifth method of manufacturing a semiconductor device according to the present invention, a step (a) of forming a trench by removing a portion of the semiconductor layer surrounding a side of the element formation region; A step (b) of implanting ions of heavy ion species into a region located below the trench; and a step (c) of forming a trench element isolation by filling the trench with an insulating layer.
[0026]
Accordingly, a defect can be caused in a region of the semiconductor layer located below the trench, and thus the stress can be absorbed by the defect. Accordingly, a semiconductor device with high driving force can be formed, and variation in characteristics of the transistor can be reduced. Therefore, layout design can be performed more accurately.
[0027]
A first semiconductor device according to the present invention is a trench element comprising a semiconductor layer having an element formation region, and an insulating layer provided around a side of the element formation region in the semiconductor layer and having a hole therein. And an element provided in the element formation region of the semiconductor layer.
[0028]
Accordingly, when an oxide film for a gate insulating film is formed, stress acting on the semiconductor layer can be reduced, so that driving force can be increased. Since variations in transistor characteristics can be reduced, layout design can be performed more accurately.
[0029]
A second semiconductor device of the present invention is provided so as to surround a semiconductor layer having an element formation region and a side of the element formation region in the semiconductor layer, and includes a first insulation layer, the first insulation layer, A trench element isolation having a second insulating layer having a different coefficient of thermal expansion, a layer having a lower elastic modulus than at least one of the first insulating layer and the second insulating layer; Provided element.
[0030]
Accordingly, when an oxide film for a gate insulating film is formed, stress acting on the semiconductor layer can be reduced, so that driving force can be increased. Since variations in transistor characteristics can be reduced, layout design can be performed more accurately.
[0031]
According to a third semiconductor device of the present invention, there is provided a semiconductor device having an element formation region, a trench element isolation including an insulating layer provided on a side of the element formation region in the semiconductor layer, A gate insulating film covering a part of the element forming region, a gate electrode provided on the gate insulating film, and a gate electrode provided on the part of the element forming region of the semiconductor layer, the gate insulating film being spaced apart from each other; And a source / drain region, and a heavy ion species having a conductivity type different from that of the source / drain region, which is provided in a region of the semiconductor layer located below the trench element isolation, is generated by ion implantation. A layer having a defect.
[0032]
Accordingly, since a layer including a defect is provided in a region of the semiconductor layer located below the trench, stress can be absorbed by the defect. As a result, driving power can be increased and variations in transistor characteristics can be reduced, so that layout design can be performed more accurately.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a method of reducing stress by performing heat treatment after forming a gate insulating film using an n-MISFET as an example will be described with reference to FIGS. 1A to 2E. 1A to 1E and 2A to 2E are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to the first embodiment.
[0034]
First, in the step shown in FIG. 1A, the steps up to the step of forming the trench 5 are performed. Specifically, the protective film 2 is formed by oxidizing the surface of the semiconductor substrate (semiconductor layer) 1. Subsequently, a nitride film 3 is formed by depositing a semiconductor nitride on the protective film 2 by a chemical vapor deposition (CVD) method. A mask 4 having an opening in the element isolation region Ri is formed on the nitride film 3 by photolithography. Then, by performing anisotropic etching using the mask 4, a trench 5 is formed that penetrates through the nitride film 3 and the protective film 2 and is removed to a depth of 0.3 μm of the semiconductor substrate 1.
[0035]
Next, in a step shown in FIG. 1B, after removing the mask 4, a surface oxide film 6 is formed on the surface of the semiconductor substrate 1 exposed in the trench 5 by a thermal oxidation method. Subsequently, an insulating layer 7 filling the trench 5 is formed on the substrate by a high-density plasma CVD method or the like.
[0036]
Next, in the step shown in FIG. 1C, the upper part of the insulating layer 7 is planarized by a CMP method or the like. The flattening of the insulating layer 7 is performed until the upper surface of the nitride film 3 is exposed. After that, by removing the nitride film 3, a trench element isolation 8 composed of the surface oxide film 6 and the insulating layer 7 is formed. Here, the surface oxide film 6 may not be provided.
[0037]
Next, in the step shown in FIG. 1D, a dose of 3 × 10 3 is implanted from above the protective film 2 into the element formation region Rr of the semiconductor substrate 1 at an implantation energy of 20 KeV. 12 / Cm 2 A threshold voltage control layer 10 having a depth of 0.15 μm is formed by ion-implanting boron (B) of a degree.
[0038]
Next, in a step shown in FIG. 1E, the protective film 2 is removed by wet etching.
[0039]
Next, in a step shown in FIG. 2A, oxidation is performed at a temperature of 800 ° C. for about 5 minutes to form an oxide film for a gate insulating film made of a silicon oxide film having a thickness of 2 nm on the semiconductor substrate 1. 11 is formed. At this time, the lower the temperature at which the oxide film 11 is formed, the stronger the stress applied from the oxide film 11 to the upper surface of the semiconductor substrate 1.
[0040]
Next, in the step shown in FIG. 2B, a stress generated in the semiconductor substrate 1 is reduced by performing a heat treatment at a temperature of 950 ° C. for about 30 minutes in an argon (Ar) atmosphere.
[0041]
Note that by performing this heat treatment at a temperature higher than the temperature at which the oxide film 11 for the gate insulating film is formed, the effect of reducing stress can be obtained. However, in order to more effectively reduce the stress, it is preferable to perform the treatment at a temperature of 900 ° C. or more and 1150 ° C. or less. The required heat treatment time becomes shorter as the heat treatment temperature becomes higher. For example, it is preferable to perform the heat treatment at 900 ° C. for 30 minutes or more, and it is preferable to perform the heat treatment at 950 ° C. for 25 minutes or more.
[0042]
The heat treatment is performed in a non-oxidizing atmosphere. In particular, in the case of a rare gas atmosphere such as argon (Ar), heat treatment can be performed without a reaction between the gas in the atmosphere and the semiconductor layer or the like. However, the atmosphere for the heat treatment may be a nitrogen atmosphere.
[0043]
Next, in a step shown in FIG. 2C, a gate electrode 12 made of polysilicon and having a gate length of 0.13 μm and a thickness of 0.2 μm is formed on the oxide film 11 for the gate insulating film.
[0044]
Next, in a step shown in FIG. 2D, a source region 13 and a drain region 14 are formed by performing ion implantation using the gate electrode 12 as a mask by a known LSI manufacturing method.
[0045]
Next, in a step shown in FIG. 2E, an interlayer insulating film 15 covering the gate electrode 12 is deposited on the semiconductor substrate 1. Then, a wiring step of forming a contact 16 and the like penetrating through the interlayer insulating film 15 and reaching the source region 13 and the drain region 14 is performed. Through the above steps, the semiconductor device of the present embodiment is formed.
[0046]
Hereinafter, the stress generated in the manufacturing method of the present embodiment will be described. In the present embodiment, in the step shown in FIG. 1B, when the inside of the trench 5 is thermally oxidized to form the surface oxide film 6, or the inside of the trench 5 is filled with the insulating layer 7 and planarized by the CMP method or the like. When performing, stress acts in the semiconductor substrate 1. It is considered that this stress increases and decreases in various steps after the trench element isolation 8 is formed. In particular, when the oxide film 11 for the gate insulating film is formed by thermal oxidation in the step shown in FIG.
[0047]
In the manufacturing method according to the present embodiment, by performing heat treatment after forming the oxide film 11 for the gate insulating film, the stress caused by the formation of the oxide film 11 and the stress caused by the formation of the trench isolation 8 are reduced. And a semiconductor device with high driving force can be obtained. Thus, variations in transistor characteristics can be reduced, so that layout design can be performed more accurately.
[0048]
Note that it is particularly preferable that the heat treatment be performed after the oxide film 11 is formed and before the gate electrode 12 is formed. In this case, the stress generated during the formation of oxide film 11 can be effectively reduced. After the oxide film 11 is formed, the substrate may be cooled and then heated to a heat treatment temperature, or may be heated to a heat treatment temperature without cooling. Further, the substrate may be taken in and out of the furnace. Further, it is preferable that the condition of the heat treatment is such that the impurity in the threshold voltage control layer 10 is not diffused and the impurity profile is not largely changed.
[0049]
(Second embodiment)
Hereinafter, a method for forming a gate insulating film by performing heat treatment after supplying oxygen to a surface portion of a semiconductor substrate in advance for the purpose of reducing stress will be described with reference to FIGS. I will explain it. 3A to 3D and 4A to 4D are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to the second embodiment.
[0050]
First, up to the step of forming the trench 35 in the step shown in FIG. Specifically, the protective film 32 is formed by oxidizing the surface of the semiconductor substrate (semiconductor layer) 31. Subsequently, a nitride film 33 is formed by depositing a semiconductor nitride on the protective film 32 by a chemical vapor deposition (CVD) method. A mask 34 having an opening in the element isolation region Ri is formed on the nitride film 33 by photolithography. Then, by performing anisotropic etching using the mask 34, a trench 35 is formed which penetrates the nitride film 33 and the protective film 32 and is formed by removing the semiconductor substrate 31 to a depth of 0.3 μm.
[0051]
Next, in a step shown in FIG. 3B, after removing the mask 34, a surface oxide film 36 is formed on the surface of the semiconductor substrate 31 exposed in the trench 35 by a thermal oxidation method. Subsequently, an insulating layer 37 filling the trench 35 is formed on the substrate by a high-density plasma CVD method or the like.
[0052]
Next, in a step shown in FIG. 3C, the insulating layer 37 is planarized by a CMP method or the like. The planarization of the insulating layer 37 is performed until the upper surface of the nitride film 33 is exposed. Thereafter, by removing the nitride film 33, a trench element isolation 38 composed of the surface oxide film 36 and the insulating layer 37 is formed. Here, the surface oxide film 36 may not be provided.
[0053]
Next, in a step shown in FIG. 3D, a portion of the semiconductor substrate 31 located above the protective film 32 and located in the element formation region Rr is implanted with an implantation energy of 20 KeV and a dose of 3 × 10 3. 12 / Cm 2 A threshold voltage control layer 40 having a depth of 0.15 μm is formed by ion-implanting boron (B) of a degree.
[0054]
Next, in the step shown in FIG. 4A, the protective film 32 is removed by wet etching.
[0055]
Next, in the step shown in FIG. 4B, a region of the semiconductor substrate 31 located at a depth of up to 2 nm is implanted with an implantation energy of 0.2 KeV and a dose of 1 × 10 4. Fifteen / Cm 2 Is implanted to form an oxygen-containing region 41a. Here, the ion implantation of oxygen is preferably performed at an implantation energy in the range of 0.1 KeV to 0.5 KeV. In this case, oxygen can be implanted to a desired depth in the semiconductor substrate 31.
[0056]
Next, in a step shown in FIG. 4C, a heat treatment is performed at a temperature of 750 ° C. for about 1 minute to form an oxide film 41 for a gate insulating film having a thickness of 2 nm on the semiconductor substrate 31. . By performing the heat treatment at a temperature of 750 to 900 ° C., the oxide film 41 for the gate insulating film having low viscosity can be formed in a short time.
[0057]
Next, in the step shown in FIG. 4D, a gate electrode 42 having a gate length of 0.13 μm and a thickness of 0.2 μm is formed on the oxide film 41. After that, a semiconductor device is formed through the same method as in the first embodiment.
[0058]
Conventionally, in a process of forming an oxide film for a gate insulating film by thermal oxidation, stress applied to a semiconductor substrate has been significantly increased. On the other hand, in the present embodiment, an oxide film of a low-viscosity gate insulating film can be formed by performing a heat treatment after supplying oxygen to the upper portion of the semiconductor substrate 31 in advance. Thereby, the stress that acts on the semiconductor device becomes smaller than that of the conventional semiconductor device, so that a semiconductor device having a high driving force can be obtained. From the above, variation in transistor characteristics can be reduced, so that layout design can be performed more accurately.
[0059]
Note that, in the above description, a method of ion-implanting oxygen has been described, but oxygen may be supplied to the upper portion of the semiconductor substrate 31 in a radical state. The heat treatment temperature in this case is the same as in the case of ion implantation. This method can also form a low-viscosity gate insulating film.
[0060]
(Third embodiment)
In the following, in addition to the method of the first embodiment, a method of further reducing the stress by providing a hole inside the trench element isolation will be described with reference to FIGS. 5A to 6D. I do. FIGS. 5A to 5E and 6A to 6D are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to the third embodiment.
[0061]
First, in the step shown in FIG. 5A, the steps up to the step of forming the trench 55 are performed. Specifically, the protective film 52 is formed by oxidizing the surface of the semiconductor substrate (semiconductor layer) 51. Subsequently, a nitride film 53 is formed by depositing a semiconductor nitride on the protective film 52 by a chemical vapor deposition (CVD) method. Subsequently, a mask 54 having an opening in the element isolation region Ri is formed on the nitride film 53 by photolithography. Then, by performing anisotropic etching using the mask 54, a shallow trench 55 is formed through the nitride film 53 and the protective film 52, which is formed by removing the semiconductor substrate 51 to a depth of 0.3 μm.
[0062]
Next, in the step shown in FIG. 5B, the mask 54 is removed.
[0063]
Next, in a step shown in FIG. 5C, an insulating layer 57a made of an HTO (High Temperature Oxide) film is deposited on the substrate by a CVD method. At this time, a hole 56 is formed in the trench 55. Here, since the HTO film has poor coverage, the deposition rate of the HTO film is lower in the lower portion of the trench 55 than in the upper portion. Therefore, the upper portion of the trench 55 is covered with the HTO film in a state where the hole 56 remains in the lower portion of the trench 55. Note that an oxide film formed by a normal pressure CVD method may be used instead of the HTO film.
[0064]
Next, in a step shown in FIG. 5D, the insulating layer 57a is planarized by a CMP method or the like until the upper surface of the nitride film 53 is exposed. Thereafter, by removing the nitride film 53, a trench isolation 57 having a hole 56 is formed.
[0065]
Next, in the step shown in FIG. 5E, a portion of the semiconductor film 51 located on the element formation region Rr from above the protective film 52 is implanted with an implantation energy of 20 KeV and a dose of 3 × 10 3. 12 / Cm 2 A threshold voltage control layer 58 having a depth of 0.15 μm is formed by ion-implanting about boron (B).
[0066]
Next, in a step shown in FIG. 6A, the protective film 52 is removed.
[0067]
Next, in a step shown in FIG. 6B, oxidation is performed at a temperature of 800 ° C. for about 5 minutes to form an oxide film for a gate insulating film made of a silicon oxide film having a thickness of 2 nm on the semiconductor substrate 51. 59 are formed. At this time, the semiconductor substrate 51 receives a compressive stress, but the compressive stress is relaxed because the holes 56 exist in the trench element isolation 57.
[0068]
Next, in the step shown in FIG. 6C, by performing a heat treatment at a temperature of 950 ° C. for about 30 minutes in an argon atmosphere, the stress generated in the semiconductor substrate 51 is further reduced. This heat treatment is performed under the same conditions as in the first embodiment.
[0069]
Next, in a step shown in FIG. 6D, a gate electrode 60 made of polysilicon and having a gate length of 0.13 μm and a thickness of 0.2 μm is formed on the oxide film 59. Thereafter, the semiconductor device is formed through the same steps as in the first embodiment.
[0070]
Next, the structure of the semiconductor device of the present embodiment will be described with reference to FIG. FIG. 7 is a cross-sectional view illustrating a structure of a CMOS semiconductor device according to the third embodiment.
[0071]
As shown in FIG. 7, the semiconductor device according to the present embodiment is provided by removing a semiconductor substrate (semiconductor layer) 51 and a portion of the semiconductor substrate 51 located in the element isolation region Ri. And a MISFET 61 (element) provided in a portion of the semiconductor substrate 51 located in the element formation region Rr. Here, the MISFET 61 includes an oxide film 59 for a gate insulating film provided on the semiconductor substrate 51, a gate electrode 60 provided on the oxide film 59, and a lateral side of the gate electrode 60 in the semiconductor substrate 51. And a source / drain region 62 provided in the region located at the position (1).
[0072]
In this embodiment, since the oxide film 59 for the gate insulating film is formed after the trench isolation 57 having the holes 56 is formed, the stress applied to the semiconductor substrate 51 during the formation of the oxide film 59 for the gate insulating film is reduced. can do. Furthermore, by performing the same heat treatment as that of the first embodiment after forming the oxide film 59, the stress acting in the semiconductor substrate 51 can be reduced. Thus, a semiconductor device with high driving force can be obtained. From the above, the characteristics of the transistor can be reduced, so that the layout can be designed more accurately.
[0073]
Here, a modified example of the present embodiment will be described with reference to FIG. FIG. 8 is a cross-sectional view illustrating a modification of the semiconductor device according to the fourth embodiment. In the semiconductor device shown in FIG. 8, the trench element isolation 63 is located inside the surface insulating film 64 made of silicon nitride (SiN), ozone BPSG (Boron-Phospho Silicate Glass) or HTO, and the surface insulating film 64. An insulating layer 65 made of a material having a high thermal expansion coefficient such as ozone NSG (Non doped Silicate Glass), and a low elastic region 66 having an elastic modulus lower than at least one of the surface insulating film 64 and the insulating layer 65. Have been. When this structure is formed, the inner surface of the trench 55 is covered with a surface insulating film 64, and after the insulating layer 65 is formed on the surface insulating film 64, the temperature is lowered. This cooling causes the insulating layer 65 having a high thermal expansion coefficient to contract, so that a low elasticity region having a lower elastic modulus than at least one of the surface insulating layer 64 and the insulating layer 65 is generated. Here, when the volume of the insulating layer 65 is reduced, holes (not shown) may be generated in a part of the trench element isolation 63. Since the trench element isolation 63 has such a structure, stress generated when the gate insulating film is formed can be reduced.
[0074]
(Fourth embodiment)
In the following, in addition to the method of the first embodiment, a method of reducing stress by providing a layer containing a defect in a region of the semiconductor substrate located under the trench element isolation will be described with reference to FIG. This will be described with reference to FIG. FIGS. 9A to 9E and 10A to 10C are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to the fourth embodiment.
[0075]
First, in the step shown in FIG. 9A, the steps up to the step of forming the trench 75 are performed. Specifically, the protective film 72 is formed by oxidizing the surface of the semiconductor substrate (semiconductor layer) 71. Subsequently, a nitride film 73 is formed by depositing a semiconductor nitride on the protective film 72 by a chemical vapor deposition (CVD) method. A mask 74 having an opening in the element isolation region Ri is formed on the nitride film 73 by photolithography. Then, by performing anisotropic etching using the mask 74, a shallow trench 75 is formed through the nitride film 73 and the protective film 72 by removing the semiconductor substrate 71 to a depth of 0.3 μm.
[0076]
Next, in the step shown in FIG. 9B, a dose of 1 × 10 Fifteen / Cm 2 About silicon is ion-implanted. As a result, a defect is generated in a region of the semiconductor substrate 71 whose depth from the bottom surface of the trench 75 is 0.2 μm, and a defect-containing region 76 is formed. Here, silicon ion implantation is performed at 1 × 10 Fifteen ~ 5 × 10 Fifteen / Cm 2 It is preferable to carry out in the range of. Here, a defect may be generated by implanting a heavy ion species such as indium (In) or antimony (Sb) instead of silicon as the implanted ions. Here, as the heavy ion species, an ion species having a relatively larger mass number than boron or arsenic is used.
[0077]
Next, in the step shown in FIG. 9C, after removing the mask 74, an insulating layer (not shown) for filling the trench 75 is deposited on the substrate by high-density plasma CVD or the like. Then, the upper portion of the insulating layer is performed by a CMP method or the like until the upper surface of the nitride film 73 is exposed. After that, by removing the nitride film 73, a trench element isolation 77 filling the trench 75 is formed.
[0078]
Next, in a step shown in FIG. 9D, a dose of 3 × 10 3 is implanted from above the protective film 72 to a portion of the semiconductor substrate 71 which is located in the element formation region Rr at an implantation energy of 20 KeV. 12 / Cm 2 A threshold voltage control layer 78 having a depth of 0.15 μm is formed by ion-implanting about boron (B).
[0079]
Next, in the step shown in FIG. 9E, the protective film 72 is removed by wet etching.
[0080]
Next, in the step shown in FIG. 10A, oxidation is performed at a temperature of 800 ° C. for about 5 minutes to form an oxide film for a gate insulating film made of a silicon oxide film having a thickness of 2 nm on the semiconductor substrate 71. Form 79. At this time, the semiconductor substrate 71 receives stress, but the stress is reduced because the region of the semiconductor substrate 71 located below the trench element isolation 77 is the defect-containing region 76.
[0081]
Next, in the step shown in FIG. 10B, by performing a heat treatment at a temperature of 950 ° C. for about 30 minutes in an argon atmosphere, the stress generated in the semiconductor substrate 71 is further reduced. This heat treatment is performed under the same conditions as in the first embodiment.
[0082]
Next, in a step shown in FIG. 10C, a gate electrode 80 made of polysilicon and having a gate length of 0.13 μm and a thickness of 0.2 μm is formed on the semiconductor substrate 71. Thereafter, the semiconductor device is formed through the same steps as in the first embodiment.
[0083]
Next, the structure of the semiconductor device of the present embodiment will be described with reference to FIG. FIG. 11 is a cross-sectional view illustrating the structure of the semiconductor device according to the fourth embodiment.
[0084]
As shown in FIG. 11, the semiconductor device of the present embodiment includes a semiconductor substrate (semiconductor layer) 71, a trench element isolation 77 provided by removing a portion of the semiconductor substrate 71 located in the element isolation region Ri, A defect-containing region 76 containing Si having a conductivity type different from that of the source / drain region 82 and provided in a region of the semiconductor substrate 71 below the trench element isolation 77, and an element formation region Rr of the semiconductor substrate 71. And a MISFET 81 (element) provided at a portion where the MISFET is located. Here, the MISFET 81 includes an oxide film 79 for a gate insulating film provided on the semiconductor substrate 71, a gate electrode 80 provided on the oxide film 79, and a lateral side of the gate electrode 80 of the semiconductor substrate 71. And a source / drain region 82 provided in a region located at the position (1). Further, defects are generated in the defect-containing region 76 by ion implantation of heavy ion species such as Si, In, or Sb.
[0085]
In the present embodiment, since the oxide film 79 for the gate insulating film is formed after the formation of the defect-containing region 76, the stress applied to the semiconductor substrate 71 when the oxide film 79 for the gate insulating film is formed can be reduced. Further, by performing the same heat treatment as in the first embodiment after forming the oxide film 79 for the gate insulating film, the stress acting in the semiconductor substrate 71 can be reduced. Thus, a semiconductor device with high driving force can be obtained. From the above, variation in transistor characteristics can be reduced, so that layout design can be performed more accurately.
[0086]
If the depth of the defect-containing region 76 is too large, the stress is not easily reduced when the oxide film 79 for the gate insulating film is formed. On the other hand, if the depth is too shallow, the distance between the defect-containing region 76 and the source / drain region becomes shorter, so that the defect may become a leak path and deteriorate the characteristics of the transistor. For these reasons, the impurity-containing region 76 is preferably provided at a depth of 0.1 to 0.3 μm from the bottom surface of the trench 75.
[0087]
Here, a modified example of the present embodiment will be described with reference to FIG. FIG. 12 is a cross-sectional view showing a modification of the step of forming the defect-containing region 76 in the manufacturing steps according to the fourth embodiment. As shown in FIG. 12, silicon may be implanted after a sidewall 95 made of HTO is formed on the side surface of the trench 94. According to this method, the defect containing region 96 and the source / drain region (not shown) can be separated by a longer distance.
[0088]
(Other embodiments)
In the present invention, in the step of ion implantation for forming the threshold voltage control layer in the first to fourth embodiments, even when a well layer, a channel stop layer, a punch-through stop layer, and the like are simultaneously formed, The effect of reducing stress can be obtained. A channel stop layer is a layer provided to stop a channel region from extending to another region during operation of a semiconductor device. This is a layer for stopping the extension to prevent the occurrence of punch-through.
[0089]
In the above embodiment, the threshold voltage control layer is formed after forming the trench element isolation. However, in the present invention, the effect of reducing the stress can be obtained even if the trench element isolation is formed after the formation of the threshold voltage control layer.
[0090]
In the above embodiment, a bulk Si substrate is used as the semiconductor substrate. However, in the first and second embodiments of the present invention, an SOI substrate may be used. Even when an SOI substrate is used, effects similar to the above effects can be obtained.
[0091]
【The invention's effect】
According to the present invention, since the stress acting on the semiconductor substrate 1 can be reduced, a semiconductor device having a high driving force can be obtained. Thus, variations in transistor characteristics can be reduced, so that layout design can be performed more accurately.
[Brief description of the drawings]
FIGS. 1A to 1E are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to a first embodiment.
FIGS. 2A to 2E are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to the first embodiment.
FIGS. 3A to 3D are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to a second embodiment.
FIGS. 4A to 4D are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to a second embodiment.
FIGS. 5A to 5E are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to a third embodiment.
FIGS. 6A to 6D are cross-sectional views illustrating a method of manufacturing a CMOS semiconductor device according to a third embodiment.
FIG. 7 is a cross-sectional view illustrating a structure of a CMOS semiconductor device according to a third embodiment.
FIG. 8 is a cross-sectional view illustrating a modification of the semiconductor device according to the fourth embodiment.
FIGS. 9A to 9E are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to a fourth embodiment.
FIGS. 10A to 10C are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to a fourth embodiment.
FIG. 11 is a cross-sectional view illustrating a structure of a semiconductor device according to a fourth embodiment.
FIG. 12 is a cross-sectional view showing a modification of the step of forming a defect-containing region in the manufacturing steps according to the fourth embodiment.
FIG. 13 is a cross-sectional view showing a trench element isolation structure in a conventional semiconductor device.
[Explanation of symbols]
1 Semiconductor substrate (semiconductor layer)
2 Protective film
3 nitride film
4 Mask
5 Trench
6 Surface oxide film
7 Insulation layer
8 Trench element isolation
10 Threshold voltage control layer
11 Oxide film
12 Gate electrode
13 Source area
14 Drain region
15 Interlayer insulation film
16 contacts
31 Semiconductor substrate (semiconductor layer)
32 Protective film
33 nitride film
34 Mask
35 Trench
36 Surface oxide film
37 Insulation layer
38 Trench element isolation
40 threshold voltage control layer
41a Oxygen-containing region
41 Oxide film
42 Gate electrode
51 Semiconductor substrate (semiconductor layer)
52 Protective film
53 nitride film
54 Mask
55 trench
56 voids
57a insulating layer
57 Trench element isolation
58 Threshold voltage control layer
59 oxide film
60 Gate electrode
61 MISFET (element)
62 Source / drain regions
63 Trench element isolation
64 Surface insulating film
65 Insulation layer
66 Low elasticity area
71 Semiconductor substrate (semiconductor layer)
72 Protective film
73 nitride film
74 mask
75 Trench
76 Defect-containing area
77 Trench element isolation
78 Threshold voltage control layer
79 Oxide film
80 Gate electrode
81 MISFET (element)
82 Source / drain region
94 trench
95 Sidewall
96 Defect-containing area

Claims (15)

  1. (A) forming an oxide film for a gate insulating film by thermally oxidizing a surface portion of the semiconductor layer;
    (B) performing a heat treatment at a temperature higher than the temperature in the step (a) in a non-oxidizing atmosphere;
    A method (c) of forming a gate electrode on the oxide film after the step (b).
  2. The method for manufacturing a semiconductor device according to claim 1,
    In the step (b), the heat treatment is performed at a temperature that reduces stress applied to the semiconductor layer.
  3. The method for manufacturing a semiconductor device according to claim 1, wherein
    The method of manufacturing a semiconductor device, wherein in the step (b), the heat treatment is performed at a temperature of 900 ° C. or more and 1150 ° C. or less.
  4. The method of manufacturing a semiconductor device according to claim 1,
    In the step (b), a method for manufacturing a semiconductor device, wherein the heat treatment is performed in a rare gas atmosphere or a nitrogen atmosphere.
  5. The method of manufacturing a semiconductor device according to claim 1,
    A step (d) of forming a trench by removing a part of the semiconductor layer before the step (a);
    Forming a trench element isolation by filling the trench with an insulating layer (e).
  6. The method for manufacturing a semiconductor device according to claim 5,
    In the step (e), a method of manufacturing a semiconductor device, wherein the trench element isolation having a hole therein is formed.
  7. The method for manufacturing a semiconductor device according to claim 6,
    In the step (e), a first insulating layer and a second insulating layer having a different coefficient of thermal expansion from the first insulating layer are formed as the insulating layer, and then the temperature is lowered to thereby form the trench element. A method for manufacturing a semiconductor device, comprising forming a layer having a lower elastic modulus than at least one of the first insulating layer and the second insulating layer as a part of separation.
  8. The method of manufacturing a semiconductor device according to claim 5,
    After the step (d) and before the step (e), the method further includes a step (f) of implanting ions of heavy ion species into a region of the semiconductor layer located under the trench. Manufacturing method of a semiconductor device.
  9. (A) forming an oxygen-containing region by supplying oxygen to the surface of the semiconductor layer;
    (B) forming an oxide film for a gate insulating film from at least a part of the oxygen-containing region by performing a heat treatment;
    And (c) forming a gate electrode on the oxide film.
  10. In a method for manufacturing a semiconductor device in which an element is provided in an element formation region of a semiconductor layer,
    (A) forming a trench by removing a portion of the semiconductor layer surrounding a side of the element formation region;
    Forming a trench element isolation having voids therein by filling the trench with an insulating film (b).
  11. In a method for manufacturing a semiconductor device in which an element is provided in an element formation region of a semiconductor layer,
    (A) forming a trench by removing a portion of the semiconductor layer surrounding a side of the element formation region;
    By lowering the temperature after forming a first insulating layer covering the surface of the trench and a second insulating layer covering the first insulating layer and having a different coefficient of thermal expansion from the first insulating layer, Forming a trench element isolation having a layer having a lower elastic modulus than at least one of the first insulating layer and the second insulating layer (b). .
  12. In a method for manufacturing a semiconductor device in which an element is provided in an element formation region of a semiconductor layer,
    (A) forming a trench by removing a portion of the semiconductor layer surrounding a side of the element formation region;
    (B) ion-implanting heavy ion species into a region of the semiconductor layer located under the trench;
    Forming a trench element isolation by filling the trench with an insulating layer (c).
  13. A semiconductor layer having an element formation region;
    A trench element isolation provided around the element formation region of the semiconductor layer and formed of an insulating layer having holes therein;
    A device provided in the element formation region of the semiconductor layer.
  14. A semiconductor layer having an element formation region;
    A first insulating layer, a second insulating layer having a coefficient of thermal expansion different from that of the first insulating layer, the first insulating layer being provided so as to surround a side of the element formation region in the semiconductor layer; A trench isolation having a layer exhibiting a lower elastic modulus than at least one of the second insulating layers;
    And a device provided in the device formation region.
  15. A semiconductor layer having an element formation region;
    Trench element isolation made of an insulating layer provided to surround the element forming region of the semiconductor layer,
    A gate insulating film that covers a part of the element formation region in the semiconductor layer;
    A gate electrode provided on the gate insulating film;
    Source / drain regions provided apart from each other in a part of the element formation region in the semiconductor layer;
    A semiconductor layer provided in a region of the semiconductor layer located under the trench element isolation and having a defect caused by ion implantation of a heavy ion species having a conductivity type different from that of the source / drain region. apparatus.
JP2003066111A 2003-03-12 2003-03-12 Semiconductor device and its manufacturing method Withdrawn JP2004273971A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303044A (en) * 2004-04-13 2005-10-27 Elpida Memory Inc Manufacturing method of semiconductor device
JP2006294675A (en) * 2005-04-06 2006-10-26 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2010219429A (en) * 2009-03-18 2010-09-30 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303044A (en) * 2004-04-13 2005-10-27 Elpida Memory Inc Manufacturing method of semiconductor device
JP4577680B2 (en) * 2004-04-13 2010-11-10 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
JP2006294675A (en) * 2005-04-06 2006-10-26 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2010219429A (en) * 2009-03-18 2010-09-30 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device

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