CN1669145A - Schottky barrier CMOS device and method - Google Patents
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- CN1669145A CN1669145A CN 03816343 CN03816343A CN1669145A CN 1669145 A CN1669145 A CN 1669145A CN 03816343 CN03816343 CN 03816343 CN 03816343 A CN03816343 A CN 03816343A CN 1669145 A CN1669145 A CN 1669145A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/095—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.
Description
Quoting alternately of related application
The application is No. 09/465357, the U.S. Patent application that applies on December 16th, 1999, now be No. 09/777536, the U.S. Patent application that applies for February 6 calendar year 2001 of dividing an application of No. 6303479, United States Patent (USP), now the part for No. 10/236685, the U.S. Patent application that applies on September 6th, 2002 of the continuation of No. 6495882, United States Patent (USP) continues.The application applies on January 15th, 2003, requires to continue for No. 60/351114, the U.S. Provisional Patent Application that applies on January 23rd, 2002 and the part of U.S. Patent application 10/342590 of priority that applies for No. 60/319098, the U.S. Patent application on January 25th, 2002.The application also is that the part that applies for No. 10/215447, the U.S. Patent application that applies on August 9th, 2002 that the part of No. 09/928163, No. 09/928124, the U.S. Patent application in August 10 calendar year 2001 and U.S. Patent application continues simultaneously continues.Each above-mentioned application all is combined in herein in full by application.
The application requires the priority for No. 60/445711, the U.S. Provisional Patent Application that applies on February 7th, 2003.The application requires the priority for No. 60/381162, the U.S. Provisional Patent Application that applies on May 16th, 2002.The application requires the priority for No. 60/381238, the U.S. Provisional Patent Application that applies on May 16th, 2002.The application requires the priority for No. 60/381659, the U.S. Provisional Patent Application that applies on May 16th, 2002.The application requires the priority for No. 60/381240, the U.S. Provisional Patent Application that applies on May 16th, 2002.The application requires the priority for No. 60/381237, the U.S. Provisional Patent Application that applies on May 16th, 2002.The application requires the priority for No. 60/381321, the U.S. Provisional Patent Application that applies on May 16th, 2002.The application requires the priority for No. 60/381239, the U.S. Provisional Patent Application that applies on May 16th, 2002.The application requires the priority for No. 60/381236, the U.S. Provisional Patent Application that applies on May 16th, 2002.The application requires the priority for No. 60/381320, the U.S. Provisional Patent Application that applies on May 16th, 2002.Each above-mentioned application all is combined in herein in full by application.
Technical field
The present invention relates generally to the field of semiconductor system and manufacturing process.More particularly, the present invention relates to have semiconductor integrated circuit (IC) and the manufacturing process thereof of Schottky barrier mos field effect transistor (MOSFET), this Schottky barrier mos field effect transistor (MOSFET) comprises Schottky barrier P type MOSFET (PMOS), Schottky barrier N type MOSFET (NMOS) and Schottky barrier complementary MOS FET (CMOS).
Background technology
Since transistor invention in 1940, shown huge superiority at semiconductor and microelectronic.Today, the semiconductor technology of dominating is the metal-oxide semiconductor (MOS) of CMOS-complementation.Current CMOS technology can reach the cost-benefit manufacturing that has of on the silicon chip of an about 10mm size integrated integrated circuit that surpasses 100,000,000 elements.1,000,000,000 transistorized IC also commercial product will occur within several years.Obtain bigger function and performance demands for each IC with lower cost and driven several trend.
At first, the driving transistors number that requires to function rises.Secondly, the size of transistor itself reduces to reach bigger integrated level and to the more important thing is and improve its performance.With regard to relating to performance, the key parameter of MOSFET is the length of raceway groove.Channel length (L) is the distance that charge carrier is getted over device, and the reducing of this length simultaneously must bring higher current drives, dead resistance through reducing and electric capacity and through improved high frequency performance.Common quality factor are products of power and time of delay, to this recapitulative cube (1/L that is expressed as the channel length inverse that measures of transistor performance
3).This explanation IC manufacturer must use up its manufacturing capacity and reduce a kind of so huge incentive action of this channel length.
For digital application, the behavior of MOS transistor seems switch.When " conducting ", they are by relatively large electric current, and when " ending ", they are characterized by a certain amount of leakage current.The common CMOS inverter circuit that is made of NMOS that is connected in series and PMOS device only just consumes appreciable power during the short transition of switching.Otherwise, static power consumption, perhaps the power that is consumed in the phase of leaving standstill by cmos circuit only is the function of MOSFET leakage current, for great majority are used, the power consumption of this static power consumption appreciable impact entire circuit.
When channel length reduced, drive current increased, and as mentioned above, this helps the raising of circuit performance.But leakage current has also increased.Transistorized leakage current has increased static power consumption, can influence the transmission of binary message between active operational stage under opposite extreme situations.Therefore the designer of device has sufficient reason to keep the low-leakage current of MOSFET when channel length reduces.
The leakage current of MOS transistor leaks the dopant profiles of leaking the two poles of the earth side direction and vertical direction in the also well-designed source, zone (channel region) between the two poles of the earth by the source of the impurity (doping) of controlled amounts being introduced device traditionally and is controlled.Though these measures are to the potential barrier that reduces MOS transistor inside thereby to reduce leakage current effective, also can reduce drive current and increase parasitic capacitance, this also be reduce that channel length means must improved importance.In addition, also depend on the doping of how introducing raceway groove and leak the two poles of the earth through well-designed source in manufacturing process just, manufacturing cost can be affected significantly.
Another factor that influences manufacturing cost is the technology income.This income is functional device and whole ratio of device count on the substrate of manufacturing.The technology income is the function of whole processing steps fully.For example, if the average yield of each processing step be 99.5% and whole processing steps of CMOS technology have 50 the step, then the technology income is about 90%.The manufacturing cost of CMOS technology is the function of technology income fully, improves with the reduction of technology income.Characterize the manufacturing complexity of CMOS technology and therefore and the simple criterion of the cost that comes is whole masks number, each masks all comprises a series of gluings, the mask alignment, and photolithographic exposure, etch step is cleaned and is measured.In CMOS technology, reduce the masks number and directly reduced manufacturing cost by reducing whole processing steps and additional additional income.For existing traditional MOS transistor design and the manufacturing process of technology and CMOS, at drive current, leakage current, parasitic capacitance and resistance and the choice aspect of making between complexity and the manufacturing cost have only limited several schemes.
The present invention provides a kind of new relation between the requirement of these antagonism, and has proposed to become circuit be beyond one's reach possibility on the performance of traditional (impurity) MOS technology with the CMOS basis set for the MOS device.Metal leaks use on the two poles of the earth to reducing parasitic capacitance in the source, reduce the device property aspect the static change variation that reduces to take place of channel length (especially with) and all provide improvement to reducing manufacturing cost and complexity aspect in device property.
The doping section
The generation of the cmos device that has earlier depends on the uneven channel doping section of the even vertical direction of MOS transistor side direction with the leakage current between the Controlling Source drain electrode.See Yuan Taur, " The IncredibleShrinking Transistor ", IEEE SPECTRUM, page 25-29 (July 1999 for www.Spectrum.Ieee.org, ISSN 0018-9235).Fig. 1 has illustrated the conventional MOS device (100) of the long raceway groove of a demonstration, this device comprises the source (101) of doping, the leakage (102) of mixing, conventional MOS type grid structures (103) and the uniform channel doping section of side direction in substrate (104) that helps the leakage current between Controlling Source leakage the two poles of the earth.Device is by an oxidation (105) electricity isolation mutually.It is very common that such channel doping section is reduced in the device of about 200 nanometers (nm) in channel length.
But when the channel length of device was reduced to the 100nm scope, document pointed out that it all is heterogeneous that the doping section of raceway groove requires in side direction and vertical direction.With reference to figure 2, the short channel MOS device (200) of demonstration has some elements similar with long channel device (100).This structure comprise custom doped source (201) and leak (202) and conventional grid structure (203) (corresponding to its width of channel length L＜～100nm).This structure also comprises and source (207) leak that (206) trap mixes that the shallow doping of leaking (209) utmost point together with the source (208) of using is extended and the channel doping (204) of the leakage current of conventional Controlling Source between leaking.All there are identical doping polarity (N type or P type) and the doping polarity opposite with (207) with trap doping element (206) with raceway groove (204) in source-drain electrode (201) and (202) and extension separately (208) thereof and (209) (whole four electrodes constituted well-designed source/leakage doping section).Also have, an oxidation (205) is with device electricity isolation mutually.
Conventional cmos circuit
With reference to figure 3, the P type MOSFET device 301 that be connected in series and the N type MOSFET device 302 of typical C MOS inverter circuit 300 on the lightly doped P type epitaxial semiconductor layer 331 on the heavily doped Semiconductor substrate 330, making.Source 304,306 and leakage 303,305 contact and comprise impure source 304,306 and drain electrode 303,305 shallow doped source 316,318 and leakage 315,317 extensions, and trap doping 345,346 and raceway groove and substrate mix 347,348.The drain contact 303,305 of two devices 301,302 is connected to each other, and the source 304 of P type device 301 is connected to V
Dd307, the source 306 of N type device 302 is connected to the low power supply V that is generally ground connection
DdThe grid 309,310 of 308, two devices 301,302 have common tie point V
g311.PMOS device 301 and nmos device 302 are isolated by the N trap injection region 321 of field oxidation 320 and PMOS device, and N trap injection region 321 is connected to V by heavily doped N type ohmic contact point 340
Dd307.
The output voltage V of public leakage tie point
oDepend on grid V
g311 input voltage.Work as V
g311 is that height (is generally V
Dd307) time, N type device 302 " conducting " and P type device 301 " ending ".That is to say the channel region of N type device 302 313 conductions and the channel region 314 of P type device 301 is non-conductive.The result is output voltage V
o312 change to the voltage in the source 306 of N type, or V
Ss308.Work as V
g311 (are generally V for low
SsOpposite situation takes place in the time of 308).Now N type device 302 " ending " and P type device 301 " conducting ", output voltage changes to the voltage in the source 304 of P type, or V
Dd307.Put it briefly high (low) input voltage V
g311 produce low (height) output voltage V
o312, anti-phase function is provided effectively.An exemplary feature of this kind typical C MOS inverter circuit is that suitable electric current is only at input voltage V
g311 flow from high to low or between transfer period from low to high.Otherwise when leaving standstill, reigning static power consumption source is a leakage current.
Schottky barrier CMOS
In No. 5760449, United States Patent (USP), Welch discloses a kind of have the N raceway groove that is connected in series and the Schottky barrier transistor device system of P channel mosfet D, in this system, the source knot of N type and P type device, it or not drain junction, electricity is connected to each other, and this Schottky barrier transistor device system forms the Schottky barrier source and drain areas of N type and P type device with middle energy gap chromium silicide.Middle energy gap silicide such as chromium silicide is characterized by Fermi level, and this Fermi level is near the mid-gap that is about 0.56eV of silicon.Welch is called " the single device that is equivalent to CMOS " with circuit as a result, because this cmos device is manufactured on the Semiconductor substrate of single doping type and with two transistorized source and drain areas of identical metal silicide formation.The cmos device of the routine of together using with the N type of the opposite types of complementation and P transistor npn npn is compared, and two transistors of this device are identical.In addition, Welch points out that this device shows the phase-veversal switch characteristic of positive feedback.Source voltage when device switches (not resembling conventional CMOS inverter is drain voltage) changes, thereby has improved the potential difference of grid to the source, thereby makes device " conducting " " positive feedback " or extraly, finishes until switching.Welch points out that middle energy gap chromium silicide has caused the computation performance of two MOSFET device symmetries, makes the inverse technique of CMOS type depend on bias condition.But middle energy gap silicide also causes the high leakage current between unacceptable low drive current and the source leakage.In addition, Welch does not narrate the performance with the negative circuit of Effect of Short-channel MOSFET device, the leakage current of the doping problem of yet not handling raceway groove or substrate when improving each MOSFET device cut-off state.
Put it briefly, prior art does not disclose or points out Schottky barrier, source metal leakage CMOS device or Schottky barrier, the manufacturing process of source metal leakage CMOS device.
Device isolation
In order to make integrated circuit, be independent of other device work in order in circuit, to make each device, each transistor device must be isolated mutually.Best device separation has high density, reasonably process complexity, high yield and acceptable ghost effect.Device isolation is divided into Semiconductor substrate in the zone of two types.First zone has the semiconductor surface of exposure and is represented as makes transistorized active region thereon.Second zone comprises " oxidation " of sheltering Semiconductor substrate and being represented as the territory, place of not making device thereon.
Have much such as local silicon oxidation (LOCOS) and shallow trench isolation technology from the device isolation of (STI).Optimize though LOCOS and STI are advanced CMOS technology, they all are subjected to several whole challenges.Some examples to the challenge of LOCOS are included in the stress of the silicon substrate that brings out in the oxidation technology, and leukorrhea nitride effect and existence are called as the phenomenon of beak.Though the flexibility that these challenges all exist solution, these schemes to increase the complexity of manufacturing process or limited technology for great majority.
Silicide is got rid of mask process
Silicide is arranged at the surface of whole Semiconductor substrate usually.The introducing of silicide brings injurious effects for the circuit of some application, such as (having reduced the integrality of signal for active C MOS pel array (having increased the dark current and the opacity of photodiode) or analog circuit, aggravated circuit stress, influenced the skew of threshold voltage and the leakage current of knot).Developed silicide and get rid of mask process in prior art, optionally the masked portion Semiconductor substrate prevents to form silicide in masked zone.Example referring to No. 5883010, No. 6160282, United States Patent (USP) and United States Patent (USP), in No. 6160282 patents, Merrill discloses a kind of silicide and has got rid of mask process to improve the performance of active C MOS pel array, in No. 5883010 patents, a kind of isolation oxidation mask process that provides silicide to get rid of is provided Merrill.
Silicide is got rid of mask process and is generally included a silicide eliminating of deposit oxidation mask layer; the deposit photoresist; form the figure of photoresist; the etching silicide is got rid of the oxidation mask layer and the zone that is covered by photoresist and oxide is protected avoid forming silicide and the zone that will form silicide is exposed; the stripping photolithography glue-line; on by silicide eliminating oxidation mask figure exposed silicon surface, optionally form metal silicide layer, and remove silicide and get rid of the oxidation mask layer.This silicide is got rid of mask technique and is not used to make Schottky barrier CMOS device and circuit.
Therefore, there are needs technically for Schottky barrier CMOS device and manufacturing process thereof.Also further exist for the needs that have through the low-cost manufacturing process of the short channel cmos device of improved performance and simplification thereof.
Summary of the invention
Put it briefly, in various embodiments, the cmos device that is disclosed comprises the Schottky barrier nmos device that optionally has P type channel dopant and optionally has the Schottky barrier PMOS device of N type channel dopant.Channel dopant and/or trap inject and can or cannot electrically contact with the ohmic contact point.Device can be separated by the field oxidation, optionally the recessed indistinctively Semiconductor substrate of the window of oxide layer.
Another aspect of the present invention is the manufacturing process of cmos device.The oxidation layer window of simple non-re-entrant is provided as an oxidation.Raceway groove and/or trap inject further to be introduced to isolate N type and P type active region.The grid of nmos device is formed on N type active region, and the grid of PMOS device is formed on P type active region, and grid has the sidewall of thin electric insulation isolates.Silicide is got rid of mask and is used to prevent that forming silicide at P type active region exposes N type active region simultaneously.When this gets rid of mask layer with wet-chemical chamber formation figure, get rid of the etch rate of the etch rate of mask layer greater than the isolation of nmos device sidewall.Form Schottky or class Schottky contacts by the Semiconductor substrate reaction that makes a thin metal layer and in zone, expose at least adjacent to the nmos device grid.Similarly, silicide eliminating mask is used to prevent that forming silicide at N type active region exposes P type active region simultaneously.When this gets rid of mask layer with wet-chemical chamber formation figure, get rid of the etch rate of the etch rate of mask layer greater than the isolation of PMOS device side wall.Form Schottky or class Schottky contacts by the Semiconductor substrate reaction that makes a thin metal layer and in zone, expose at least adjacent to the PMOS device grids.
When disclosing various embodiments, the present invention show in addition and other embodiment of narrating illustrative embodiment of the present invention by hereinafter detailed narration for for the skilled personnel in present technique field, also will being conspicuous.As will be recognized, the present invention can both make amendment aspect tangible at each and not deviate from the spirit and scope of the present invention.Therefore, accompanying drawing and detailed descriptionthe all will be considered to explanation rather than the restriction to its performance.
Description of drawings
Fig. 1 has shown the long channel doping source/leakage device of prior art;
Fig. 2 has shown the short channel doped source/leakage device of prior art, has trap injection and source/leakage and extends;
Fig. 3 has shown the short channel doped source/leakage CMOS inverter circuit of prior art;
Fig. 4 has shown the definition of channel length and channel region;
Fig. 5 has shown cmos device according to an embodiment of the invention;
Fig. 6 has shown the example embodiment of the technology that application P type device active region of the present invention territory is injected;
Fig. 7 has shown the example embodiment of the technology that application N type device active region of the present invention territory is injected;
Fig. 8 has shown that application of the present invention is formed for the example embodiment of technology of the LOCOS field oxidation of device isolation;
Fig. 9 has shown the example embodiment of the technology of the silicon thin film that has formed figure on the application of thin gate oxidation of the present invention;
Figure 10 has shown that application of the present invention forms thin oxidized sidewalls and is exposed to grid, the example embodiment of the technology of the silicon in source and the drain region;
Figure 11 has shown the silicidation anneal of application silicide eliminating mask of the present invention and metal deposit and N type device, and the example embodiment of using the technology of removing unannealed metal;
Figure 12 has shown the silicidation anneal of application silicide eliminating mask of the present invention and metal deposit and P type device, and the example embodiment of using the technology of removing unannealed metal;
Figure 13 has shown the example embodiment of the resultative construction of technology of the present invention;
Figure 14 has shown the example embodiment according to the Schottky barrier CMOS inverter circuit of principle of the present invention, and this Schottky barrier CMOS inverter circuit has PMOS and the nmos device that the simple trap that approaches an oxidation and do not electrically contact by the ohmic contact point injects that have that is connected in series; With
Figure 15 has shown the example embodiment of the Schottky barrier CMOS inverter circuit layout of the PMOS that is connected in series according to having of principle of the present invention and nmos device
Embodiment
Fig. 5 has shown the example embodiment by two last complementary MOS FET structure 500 examples of the present invention.This embodiment comprises the Schottky N channel device and the Schottky P-channel device that has platinum silicide 505 that have the silication erbium 504 that is used for source/drain region.503 layers of channel doping that can be used separately as N raceway groove and P-channel device of indium 502 and arsenic.Grid is made by phosphorus that is used for N type device 506 and P type device 507 and the in-situ doped polysilicon membrane of boron respectively.The field oxidation 501 that device is worked together by mixing in conjunction with raceway groove and substrate is disconnected from each other, and the mutual electricity that reaches between the device is isolated.The interface that Schottky (or class Schottky) barrier 512,513,522,523 is present between corresponding metal source/leakage 504,505 and the silicon substrate 509 is brought into play intrinsic trap or dizzy effect of injecting, and do not bring parasitic capacitance into when being played a role.
In whole discussion of presents, utilized following definitions:
The ohmic contact point
The ohmic contact point is electrically contacting for the low-resistivity of Semiconductor substrate.For example, doping ohmic contact point comprises N type heavily doped region that contacts with N type dope semiconductor substrates and the P type heavily doped region that contacts with P type dope semiconductor substrates.In addition, for example comprise the platinum silicide that silication erbium that the Semiconductor substrate of mixing with the N type contact contacts with Semiconductor substrate with the doping of P type for the metal ohmic contact point of Semiconductor substrate.Contacting that these metal silicides and its Semiconductor substrate type are separately carried out is that the ohmic contact point is because it is for the low Schottky barrier height of electric charge carrier and the low contact resistance that therefore obtains.
Trap injects
Breech lock is the problem of cmos circuit uniqueness, owing to existing ambipolar NPN horizontal PNP transistor to cause this problem.This undesirable parasitical bipolar transistor can have the effect of amplifier, owing to making power supply short circuit ground connection make circuit malfunction.In order to address this problem, conventional CMOS layout generally includes the N type that is respectively applied for P type and N type MOSFET device and the trap of P type injects.N type and P type trap inject the V that is connected to power supply respectively by the ohmic contact point
DdAnd ground connection.As an example and with reference to figure 3, N trap 321 mix with the impurity of Semiconductor substrate 330 opposite polarities, doping content is approximately greater than order of magnitude of epitaxial substrate layer 331 doping contents usually.N trap 321 has and raceway groove and the substrate 347 identical polarity of mixing.The manufacturing step of trap depends on requirement that breech lock is eliminated and such as other factors of integrated level and independent threshold voltage-regulation.A heavily doped N type ohmic contact point 340 is set directly contacts and be connected to power supply V with N trap 321
Dd, substrate 330 is connected to V simultaneously
Ss, be generally ground connection.
Channel length
With reference to figure 4, channel length (L) the 401st, charge carrier in Semiconductor substrate 415 from source electrode 402 to the drain electrode 403 distances of getting over.For source metal/drain MOSFET device, this distance is by the distance definition of facing the interface 405 of source electrode 402 under the gate insulator 406 from source electrode 402 in the face of the interface 404 of drain electrode 403 to drain electrode 403.
Channel region, channel doping and substrate mix
With reference to figure 4, the electric current of active region delivery zone is commonly called channel region in the semiconductor device.For the doped source and drain MOSFET device of routine, the channel region in the Semiconductor substrate 415 is positioned at the place of very close gate insulator, and does not substantially vertically extend into downwards in the Semiconductor substrate 415.But for other MOSFET device technologies such as the Schottky barrier source drain MOSFET, a considerable amount of electric currents can flow in the zone below gate insulator 406 is basic.For purpose of the present invention, the channel region in the Semiconductor substrate 415 extends vertically up to depth d below source electrode 402 and drain electrode 403
1On the 407 and feather edge 421 of the feather edge 420 of source electrode 402 and drain electrode 403 border 416 of roughly aliging.
Channel doping is the doping that provides in the channel region of Semiconductor substrate 415, is generally used for improving from the source electrode 402 of MOSFET device and the purpose of the electric leakage performance of drain electrode 403.It is and the doping that provides of bottom interface 420,421 belows of source electrode 402 and drain electrode 403 that substrate mixes at the end 416 of channel region in Semiconductor substrate.
Understand the very important of difference that channel doping and substrate mix.With reference to figure 4, two injections of mixing have been shown among the figure.First mixes to inject and is set to depth d
2The exposed region of 430 first mask layer also has laterally even vertical uneven concentration profile.Second doping is injected and is set to depth d
3Second mask layer exposed region and have laterally evenly vertical uneven concentration profile.In this example, the first doping injection and second is mixed to inject and is had different concentration and different vertical inhomogeneous sections.The device of MOS as a result that Fig. 4 describes has the laterally even vertical uneven doping content section of channel region, and the substrate doping section below channel region has laterally and vertical all uneven doping content section.
Semiconductor on the insulator (SOI) substrate
The SOI substrate be included in have an appointment 100 nanometers (nm) to 400nm thickness such as silicon dioxide (SiO
2) the insulating material of burying underground on the 20nm that has an appointment to the semi-conducting material such as silicon of 100nm thickness, this SOI substrate is formed on the Semiconductor substrate.
Be not limited to MOSFET
The present invention is particularly suitable for the MOSFET semiconductor device, but the application of the principles of the present invention is not limited to this specific application.Other semiconductor device also can be used principle of the present invention.Like this, though this specification is narrated with the term of " MOSFET " device, this term should be interpreted as to comprise that being used to regulate electric current has conducting channel, has any device of two or more electrical pickofves widely.
Be not limited to CMOS
The present invention is particularly suitable for using and making of CMOS integrated circuit, but the application of the principles of the present invention is not limited to this specific application.Comprise complementary or non-complementary NMOS and/or transistorized other circuit of PMOS also can be used principle of the present invention.Like this, though this specification is narrated with the term of " CMOS " device, this term should be interpreted as to comprise any device that is made of interconnected NMOS and/or PMOS transistor widely.
Channel length is unrestricted
The present invention is particularly suitable for making the occasion of short channel length MOSFET, especially is suitable for the scope of channel length＜100nm.But principle of the present invention is not limited to be applied in short channel length devices.Principle of the present invention advantageously is suitable for the channel length of virtually any size.
It is unrestricted to mix
Whole discussion of this paper all will be the example that utilizes the various doping techniques of relevant MOSFET device manufacturing to provide.These doping have only illustrated specific embodiments of the invention, and should not be construed as is restriction to the scope of the principle of the invention.
But notice that the present invention especially expects for from by arsenic, phosphorus, antimony, boron, indium, and/or the application of foreign atom in the scope of the principle of the invention of selecting in the set formed of gallium.
Circuit types is unrestricted
The present technique field skilled personnel will readily appreciate that, the invention is not restricted to such as comprising inverter, NAND gate, NOR gate, composite gate, the Digital Logical Circuits of multiplexer, and the specific CMOS of easy memory that lose or non-volatile uses or the scope of circuit types.And, the present invention also be not limited to numeral and or the CMOS of simulation use.These and the every other circuit types of using NMOS and/or the transistorized combination of PMOS are all among the scope of principle of the present invention.
The source of being not limited to/leakage
Whole discussion of this paper will be that " source " that the relevant MOSFET device of reference is made is connected the example that provides with " leakage " all.The personnel skilled in the present technique field will recognize, in any MOSFET configuration that provides, can exchange and do not lose its generality around the various terms of these contacts, therefore, " source " contact can contact exchange with " leakages " and not deviate from scope of the present invention.In addition, the personnel skilled in the present technique field will recognize, leak and connect though a lot of the preferred embodiments of the present invention can be used for the manufacturing source, and the situation in the reality that do not require that Here it is.In order to obtain advantageous conditions, the side in connecting is leaked in the source of the device that provides under backgrounds such as IC, and both sides can use principle of the present invention or need not.
Like this, term " source " and " leakage " should be understood to include various vicissitudinous " leakage " and " source ", and " source or leakage " and " source and leakage ".
Metal is unrestricted
The example that whole discussion of this paper all provide the metal that is the manufacturing of the relevant MOSFET device of reference.The present invention does not think that the relevant metal of using what type can influence principle of the present invention aspect any restriction is arranged.Like this, such as titanium, the metal that cobalt etc. are usually used on the transistor rank obtains the use expected especially, but also comprises numerous rarer metals and other alloy.Use any specific metal or alloy without any effects limit the present invention.The personnel skilled in the present technique field will recognize, can use the interconnected material of any conduction and not lose generality in implementing principle of the present invention.
But note, the present invention expect especially use in the scope of principle of the present invention by platinum silicide, palladium silicide, silication iridium, and/or source/drain electrode of forming of any silicide in the set formed of rare earth silicide.Be also noted that in another embodiment, the source/leakage of silicide can constitute with the composite bed of metal silicide, under these circumstances, can use other demonstration silicides such as titanium silicide or tungsten silicide.
Schottky is unrestricted
Whole discussion of this paper all will be " Schottky " barrier and the similar example that provides that contacts made from reference to relevant IC.The present invention does not think that the relevant schottky interface of using what type can influence principle of the present invention aspect any restriction is arranged.Like this, the present invention expects the knot of those types of producing with any type of electric conducting material especially.
In addition, though traditional schottky junction suddenlys change, the present invention expects especially, in some cases, can utilize a boundary layer between the Schottky barrier metal of silicon substrate and reality.Like this, useful in the embodiment of this invention " class Schottky " knot and the equivalent thereof of the special expection of the present invention.In addition, boundary layer can comprise having conduction, and is semiconductive, and/or the material of the performance of class insulation.
Lithographic technique is unrestricted
Whole discussion of this paper all will be to be used to remove oxide layer, the example that the lithographic technique of silicon and/or metal provides with reference in the various IC manufacturing process.The present invention does not limit and reaches the result who illustrates and the type of the lithographic technique that uses in typical technological process.These technology are well-known technically.
Isolation technology is unrestricted
Whole discussion of this paper all will be to isolate the example that isolation technology that each NMOS and PMOS transistor utilize provides with reference to various for electricity.The present invention does not limit and reaches the result who illustrates and the type of the isolation technology that uses in typical technological process.Such as LOCOS, technically well-known of the isolation technology of STI and non-re-entrant oxidation window.
Trap injects unrestricted
Whole discussion of this paper are all injected the example that provides with the trap that is the relevant IC manufacturing process of reference.Usually, conventional trap inject by ohmic contact point be electrically connected to respectively PMOS and nmos pass transistor such as V
DdPower supply with ground connection.The present invention does not limit and is electrically connected to the type that trap injects, and can maybe cannot be electrically connected to such as V by the ohmic contact point thereby trap is injected
DdOr the power supply of ground connection.Any trap of narration injects and all is characterized as being " being electrically connected to the ohmic contact point " or " non-electric-connecting to the ohmic contact point " in this discussion.Phrase " is electrically connected to the ohmic contact point ", and expression is connected to such as V by the ohmic contact point
DdOr the power supply of ground connection.
The doping section is unrestricted
Whole discussion of this paper all will be the examples that provides with reference to the doping section in the Semiconductor substrate of in the channel region and channel region below.The present invention does not limit can be in order to the channel doping that influences principle of the present invention and the type of substrate doping section.The present technique field skilled personnel will easily understand, and can for example comprise and laterally injecting with vertical all uneven channel/substrate with a lot of doping sections; Laterally all even vertical uneven channel/substrate is injected; Laterally with vertical all channel/substrate injections uniformly.These of such doping section and any combination and any other channel/substrate doping section are all in the scope of principle of the present invention.
It is unrestricted to get rid of mask process
Whole discussion of this paper all will be to get rid of the example that mask process provides with reference to the silicide that is used for optionally forming in the zone of Semiconductor substrate silicide.The present invention does not limit the eliminating mask process and is used for metal silicide metal-semiconductor compound in addition.The present technique field skilled personnel will easily understand, and can use a lot of metal-semiconductor compounds that form Schottky or class Schottky contacts, and these metal-semiconductor compounds are all in the scope of principle of the present invention.
Substrate is unrestricted
Whole discussion of this paper all will be with reference to Schottky barrier CMOS device form thereon the example that provides of Semiconductor substrate.The present invention is not restricted to Semiconductor substrate any concrete type.The present technique field skilled personnel will easily understand, and a lot of Semiconductor substrate can be used for Schottky barrier CMOS, comprise silicon, the silicon on strained silicon and the insulator.Adaptable these backing materials are all in the scope of principle of the present invention.
Process/method
Fig. 6-13 has shown an exemplary process of manufacturing source metal/leakage CMOS device.Though this technology is exemplary for principle widely of the present invention, it is for understanding the effect that basic conception of the present invention has guidance the skilled personnel in present technique field.The technological process of this demonstration can be described below:
With reference to figure 6, technology starts from heavily doped silicon substrate 602 and lightly doped epitaxial loayer 601, and this epitaxial loayer has the effect of mutual electric isolated transistor, and growth is thin shelters oxidation 604 (about 200 ) as injecting mask.In another embodiment, silicon substrate 601 is carried out stress.Cause additional improvement on power supply and the speed ability with the use of the strained silicon substrate 601 of Schottky barrier MOSFET combination of devices, as the explanation in No. 10/342590, the U.S. Patent application that awaits the reply jointly that applies on January 15th, 2003.In another embodiment, substrate is SOI.One of formation stopped graph layer 605 after oxidation 604 was sheltered in growth, and the active region 606 of PMOS device is exposed, and dopant arsenic 607 is injected by ion and is injected into the predetermined depth d 1 608 of silicon (about 1000 ) by sheltering oxidation.
With reference to figure 7, stop that graph layer 605 is stripped from, wafer is formed figure once more, and the active region 701 of N type device is exposed.The dopant indium 702 that is used for N type device active region territory 701 is injected by ion and is injected into the predetermined depth d 2 703 of silicon (for example 1000 ) by sheltering oxidation 604.
With reference to figure 8, by isolate the active region of P type and N type device such as the isolation technology of local silicon oxidation (LOCOS).For example, in hydrofluoric acid, remove and shelter oxidation 604, the thin liner oxidation 801 (for example about 150 ) of growth one deck.Deposit one deck Si on wafer then
3N
4802 (about 3000 ).Wafer is oxidized then to limit oxide in field with photoetching technique.Usually, oxide in field 803 has the thickness of 2500 and the Semiconductor substrate 601 of the recessed extension of quilt part.Release liner oxidation 801 and nitride film 802 then.In another example embodiment, device active region territory 606,701 is isolated by simple oxidation technology, as apply for explain in No. 60/381162, the U.S. Provisional Patent Application on May 16th, 2002.For example, shelter oxidation 604 and in hydrofluoric acid, remove, the isolation oxidation of about 100 thickness of growing then.Be formed with the figure of source region 606,701 and oxide in field 803 then by the photoetching technique of standard.The degree of depth that importantly should understand the field oxidation 803 recessed Semiconductor substrate 601 of this simple oxidation technology generation is lower than source-and-drain junction 1102 basically, 1103,1202, (annotation of translation: this is the free translation of understanding according to the translator to 1203 the degree of depth, be " the not recessed Semiconductor substrate 601 of an oxidation is lower than source-and-drain junction 1102 substantially; the degree of depth that 1103,1202,1203 degree of depth are such " as literal translation).
With reference to figure 9, growth thin oxide gate 901 (for example about 10-40 ).In another embodiment, the material with high-k (" high K ") is used as insulating barrier 901.The example of hafnium is those materials that its dielectric constant is higher than silicon dioxide, comprises for example such as TiO
2The material of metal oxide.The high K gate insulation layer that is used in combination with the Schottky barrier device causes in the additional improvement aspect the drive current, as the explanation in U.S. Patent application 10/215447 series number that applies on August 9th, 2002.
In one embodiment, the polysilicon layer of about 2000 thickness of deposit.Use photoetching technique (first mask) and shelter the PMOS active region, the polysilicon in the NMOS active region that exposes is mixed phosphorus by heavy doping N type dopant such as injecting with ion.Then, use photoetching technique (second mask) to shelter the NMOS active region once more, the polysilicon in the PMOS active region that exposes is mixed boron by heavy doping P type dopant such as injecting with ion.Substrate is annealed, and the dopant that is injected into channel region and grid is activated by electricity and distribution again.With photoetching technique (the 3rd mask) with for the silicon etching formation N type 902 of silicon dioxide high selectivity and the gate patterns of P type 903, shown in the processing step 900 of Fig. 9.
In another embodiment, grid forms with the two in-situ doped polycrystalline technology of two masks, as No. 60/381240, the U.S. Provisional Patent Application that applies on May 16th, 2002 explains.In this example embodiment, deposit has the in-situ doped N-type polysilicon layer of about 500 thickness.Shelter the NMOS active region with photoetching technique (first mask), the PMOS active region of exposure is by partial etching.Use then for second etching of following gate oxidation 901 high selectivities and remove the polysilicon that the N type in the remaining PMOS active region mixes.Then, deposit has the in-situ doped P type polysilicon layer of about 1500 thickness.With photoetching technique (second mask) with for the silicon etching formation N type 902 of silicon dioxide high selectivity and the gate patterns of P type 903, shown in the processing step 900 of Fig. 9.The thickness of the polysilicon gate 902 of result's in-situ doped N type device is greater than the polysilicon gate 903 of P type device.Substrate is annealed by selectivity so that the dopant of N type 902 and P type 903 grids all evenly distributes.
With reference to Figure 10, the thin oxidation (about 100 ) of heat growth on silicon gate and horizontal surface 1002 and sidewall 1003 then.With the oxide layer on the anisotropic etching removal horizontal surface 1002 (therefore exposing silicon 1004), be retained in the sidewall oxidation 1001 on the vertical surface simultaneously then.Form thin sidewalls isolation oxidation 1001 with such method.Shown in the processing step 1000 of Figure 10.In another example embodiment, thin sidewalls isolated insulation body 1001 can comprise oxidation-nitride layer or nitride layer.Oxidation-nitride layer is the material that comprises oxygen and nitrogen.
With reference to Figure 11, following step comprises the source-drain electrode that forms metal silicide.In one embodiment, wafer forms figure with suitable masking layer 1110 by photoetching technique, and the P type active region of N type device 1101 is exposed.In an example embodiment, masking layer 1110 is that silicide is got rid of mask oxide layer.Depositing silicide is got rid of mask oxide layer.Deposit photoresist then; then form the figure of photoresist; method etching silicide by application examples such as buffer oxide etching is got rid of mask oxide layer 1110 and stripping photoresist, so N type active region is avoided forming silicide by the covering of silicide eliminating mask oxide layer thereby be protected.Importantly use the wet etching of high selectivity, make sidewall isolation oxidation 1001 unaffected substantially for the oxidation mask etching.Such as the wet etching of buffer oxide etching should be preferably can be used for providing the oxide of speed etching institute deposit of the etch rate of the exemplary materials that grid lateral wall insulation thing isolates substantially greater than etching heat growth side wall oxide or other.The grid side wall insulator of conventional device is thicker than the grid side wall insulator of Schottky barrier MOS device greatly.This is damaged conventional MOS sidewall less in the wet chemical etch process, the integrated step of the silicide eliminating mask of the CMOS technology that use is conventional is more simple.
Deposit is used for the proper metal (for example erbium) of N type device suicide, and a metal level (about 200 ) is provided on all surfaces of wafer.This wafer is the official hour of annealing under the temperature of regulation (for example annealing 30 minutes under 450 ℃) then, like this, chemical reaction all takes place in all places that directly contact at metal and silicon, and at source electrode 1102, drain electrode 1103 and grid 1104 are converted into metal silicide with metal.Importantly, the isolation 1001 of the sidewall of institute's exposed portions etching is comprehensively protected grid in the annealing that silicide forms.Use wet chemical etch (for example for erbium HNO then
3Or H
2SO
4) remove unreacted metal, stay the not metal silicide of contact simultaneously, as shown in the processing step 1100 of Figure 11.
In another embodiment, deposit is used for the proper metal (for example erbium, about 150 ) of N type device suicide, and then second proper metal of deposit (for example titanium, about 50 ) causes a metal level with two kinds of metal levels.This wafer is the official hour of annealing under the temperature of regulation (for example annealing 30 minutes under 450 ℃) then, like this, chemical reaction all takes place in all places that directly contact at metal and silicon, and at source electrode 1102, drain electrode 1103 and grid 1104 all are converted into metal silicide with first and second metals.Importantly, the isolation 1001 of the sidewall of institute's exposed portions etching is comprehensively protected grid in the annealing that silicide forms.Use wet chemical etch (Sulfuric Peroxide) to remove unreacted metal then, stay the not metal silicide of contact simultaneously.
Importantly select second metal (for example titanium) in order to keep initial deposited metal order.For example, in previous exemplary technology, the basal surface of silication erbium contacts with Semiconductor substrate, and the top surface of silication erbium contacts with titanium silicide.Second silicide provides stronger etching to stop to later metallization process step to provide through improved manufacturing capacity by providing, reduce the clean resistivity of source-drain electrode, and more stable in the oxidation environment of room temperature, as apply for explain in U.S. Provisional Patent Application 60/381238 series number on May 16th, 2002.
Because compare with the conventional high relatively underlayer temperature (for example greater than 1000 ℃) of doped source and drain manufacture process requirement, the source-drain silicide manufacturing step requires much lower underlayer temperature (for example less than 700 ℃), other non-standard materials in the silicon base CMOS, such as high-k dielectrics, metal gate or strained silicon etc. can more easily be integrated in the CMOS manufacturing process of the present invention.As apply for explain in No. 60/381320, the U.S. Provisional Patent Application on May 16th, 2002.
With reference to Figure 12, wafer forms figure with suitable masking layer by photoetching technique once more, exposes the N type active region of P type device 1201.In an example embodiment, masking layer is that silicide is got rid of mask oxide layer.Depositing silicide is got rid of the mask oxidation.Follow the deposit photoresist; form the figure of photoresist then; get rid of mask oxide layer with for example buffer oxide etching etching silicide, stripping photoresist avoids forming silicide thereby make P type active region and N type device 1101 be covered to be protected by the oxidation of silicide eliminating mask.Importantly use the wet etching of high selectivity, make the sidewall isolation oxidation 1001 of P type device 1201 unaffected substantially for the oxidation mask etching.Such as the wet etching of buffer oxide etching should be preferably can be used for providing the oxide of speed etching institute deposit of the etch rate of the exemplary materials that grid lateral wall insulation thing isolates substantially greater than etching heat growth side wall oxide or other.
Deposit is used for the proper metal (for example platinum) of P type device suicide, and a metal level (about 200 ) is provided on all surfaces of wafer.This wafer is the official hour of annealing under the temperature of regulation (for example annealing 45 minutes under 400 ℃) then, like this, chemical reaction all takes place in all places that directly contact at metal and silicon, and in drain electrode 1202, source electrode 1203 and grid 1204 are converted into metal silicide with metal.Importantly, the isolation 1001 of the sidewall of institute's exposed portions etching is comprehensively protected grid in the annealing that silicide forms.Use wet chemical etch (for example for the platinum chloroazotic acid) to remove unreacted metal then, stay the not metal silicide of contact simultaneously, as shown in the processing step 1200 of Figure 12.The example embodiment that comprises the dual silicide eliminating mask process that is used for Schottky barrier CMOS with reference to the technology of processing step 1100 (as shown in figure 11) and processing step 1200 (as shown in figure 12) narration.
Dual silicide can be provided by another example embodiment with a silicide eliminating mask.For example, deposit is used for the proper metal of N type device, provides silicide to get rid of mask layer with photoetching technique then, thereby exposes the N type active region of P type device.Deposit is used for second proper metal of P type device.This wafer official hour of annealing under the temperature of regulation then, like this, chemical reaction all takes place in all places that directly contact at first metal and silicon, at source electrode 1102, drain 1103 and grid 1104 metal is converted into metal silicide.In addition, in annealing process, second metal is by first metal diffusing, thereby at source electrode 1202, drain electrode 1203 and grid 1204 form metal silicide.
Shown in the processing step 1300 of Figure 13 explanation, Schottky barrier NMOS1101 and PMOS1201 are electrically contacted comprehensively and easily.In order to form CMOS inverter circuit 1300 as shown in figure 13, add conductor wire and connect grid 902 and 903 to form the input V of cmos circuit 1300
g1301, connect drain electrode 1103 and 1202 to form the output V of cmos circuit 1300
o1302.Also add conductor wire so that nmos source 1102 is connected to V
Ss1303, pmos source 1202 is connected to power supply V
Dd1304.
Put it briefly, the Schottky barrier CMOS manufacturing process of this demonstration needs whole 8 masking steps:
Cover the pattern number mask functions
1 PMOS arsenic injects
2 NMOS indiums inject
3 is active
4 NMOS phosphorus inject
5 PMOS boron inject
6 grid
7 Platinum Silicides are got rid of
8 erbium silicides are got rid of
With a step in 8 masks of the two in-situ doped polycrystalline technologies formation grids replacements of dual masks.The skilled personnel in present technique field will be appreciated that above-mentioned technology only is to realize a kind of method of source metal/source/drain Schottky device, also exists a lot of modification and alternative.
Device/system
Figure 13 has shown the profile (1300) as an example embodiment of the present invention of being demonstrated by two last complementary MOS FET structures.This embodiment comprises a nmos device 1101 of making as source/ drain region 1102,1103 with the silication erbium and the PMOS device of making as source/ drain region 1202,1203 with platinum silicide 1201.Along the corresponding metal source/ leakage 1102,1103,1202,1203 and Schottky (or the class Schottky) barrier (1312 that exists of the interface of silicon substrate 601,1313,1322,1323) intrinsic trap of performance or dizzy effect of injecting and when playing a role additional parasitic capacitance not.It has also eliminated the needs that the source/leakage for shallow injection is extended simultaneously, because source metal/leakage itself just has the natural performance of shallow and high conduction.It has also further been eliminated by the ohmic contact point for PMOS and nmos device respectively and has electrically contacted to power supply V
DdThe needs that inject with the trap on ground.Therefore by cancellation simultaneously dizzy/trap injects, the source is leaked to extend to inject and inject by the trap that the ohmic contact point electrically contacts and has been realized obviously reducing the complexity made.These also are the major advantages that surpasses the MOS device of conventional structure.
The metal suicide source/drain extension can be used for NMOS and PMOS source and drain areas (1102,1103,1202,1203) with the performance of further reinforcement Schottky barrier CMOS device, as apply for explain in the U.S. Provisional Patent Application 60/381321 on May 16th, 2002.
Because the precipitous performance of Schottky barrier on atomic scale and the quantity of coordinating very much and repeating thereof, in fact two sources of the variation that exists on the conventional distinctive statistics of MOS device are eliminated.The statistical property at random that the impurity that injects by ion in conventional device is introduced is in the position of implanted dopant and quantitatively all produce obvious variation.All there is this problem for dizzy/trap and source/leakage impurity.Consequently such as channel length (L), the change at random of some in the device parameters of drive current and leakage current.These variations make circuit design more difficult, do not descend and have also caused the problem of manufacturing cost owing to meet output that the IC of specification causes.Owing to the littler effective volume of silicon in each device reduces channel length, therefore the smooth-going mean effort of departing from of statistics variations is reduced, it is more serious that this problem just becomes.
(substitute the doped source/leakage of routine) because source metal/leakages and have for the nature of silicon substrate 601, coordinate very much with atomic scale on precipitous Schottky barrier (1312,1313,1322,1323), the position and the quantity of barrier are independent of channel length, and because this barrier has served as the role that dizzy/trap injects (make these injection unnecessary) in fact, source/leakages and dizzy/trap injection period owing to the statistics variations of the random file generation of atom is eliminated substantially.When channel length reduced, this conclusion still kept correctly even is more correct.
Another advantage of source metal/leakage MOS structure is unconditionally to have eliminated parasitic ambipolar gain.The ambipolar gain of this parasitism is that source/leakage and area are used the direct result of opposite doping type and can be caused breech lock and other ill-effects., eliminated this ambipolar gain when thereby source-drain electrode is made of when providing for the contact of the Schottky barrier of Semiconductor substrate metal.This makes source metal/drain structure (inter alia) especially desirable for high radiation environment.In addition, not having parasitic ambipolar gain also further to eliminate by the ohmic contact point for PMOS and nmos device respectively electrically contacts to power supply V
DdNeeds with the trap on ground injects cause reducing processing step, reduce cost and improve the result of output.Because Schottky barrier CMOS is not subjected to the influence of parasitic ambipolar effect, so its field at power MOSFET device also can find application, as disclosing in No. 60/381237, the above-mentioned U.S. Provisional Patent Application that applies on May 16th, 2002.
Make grid 902,903 with boron-doping and the polysilicon membrane of mixing phosphorus respectively for P type device and N type device.In this example, use boron and phosphorus because of its big solid solubility (comparing with indium) with arsenic.
Grid width can be less than 100nm (corresponding to channel length L), because the advantage that its structure that is in Schottky barrier surpasses conventional structure becomes more significantly under the situation.These advantages comprise owing to not needing trap to inject simplifies technology, and has reduced the influence for output in the product of finishing, and has reduced electric capacity and statistics variations.
Device is disconnected from each other by the insulating barrier of the oxide layer 803 (being called an oxidation) of growing such as heat, and this insulating barrier mixes with raceway groove and substrate and combines work so that device is isolated mutually.This oxidation 803 can be provided by the technology such as the routine of LOCOS, produces the recessed field oxidation 803 of part, or by providing such as simple thin better simply device isolation technology non-re-entrant or shallow oxidation.In this occasion, shallow the oxidation that is called as the oxidation window sometimes do not extend into substrate to the degree of depth that is lower than source-and-drain junction substantially.The application of shallow oxidation window has caused other processing step, lower cost and the output of Geng Gao through reducing.
With reference to Figure 14, an oxidation 1403 is not simple thin oxidations of recessed epitaxial semiconductor substrate 601 substantially.In this example embodiment, the optional trap that does not electrically contact ohmic contact point injects 1405,1406 and can be used to isolate respectively PMOS and nmos device.Be important to note that the trap that does not need to be electrically connected to ohmic contact point for the PMOS in the inverter circuit or nmos device injects.If inject, the step that extra arsenic injects will be set in the processing step 600 that Fig. 6 shows cause an arsenic trap 1405, and the step that extra indium injects will be set in the processing step 700 that Fig. 7 shows cause an indium trap 1406 with optional trap.Trap injects 1405,1406 not to be needed to electrically contact to the ohmic contact point.
Figure 15 has shown the vertical view of a preferred embodiment of the present invention, makes demonstration by Schottky barrier CMOS inverter circuit and typical operation thereof and bias condition.The source 1501 of PMOS device 1502 is connected to positive source V
Dd1503, and the source 1504 of nmos device 1505 is connected to V
Ss, be generally ground.Grid contact point 1507 and 1508 shared public inputs are electrically connected V
g1509, miss contact 1510 and 1511 shared public outputs electrical connection V
o1512.When isolating with simple thin oxide device, PMOS device 1502 and nmos device 1505 have optional trap to inject 1520,1521.Trap injects 1520,1521 and is not electrically connected to the ohmic contact point.By the bias condition group of this demonstration, the output voltage V that these two devices 1502 are connected with 1505 public leakage
o1512 depend on the input voltage V on the grid
g1509.Work as V
g1509 is that height (is generally V
Dd1503) time, then N type device 1505 " conducting " and P type device 1502 " ending ".It is the channel region conduction of N type the device 1505 and channel region of P type device 1502 is non-conductive.The result is output voltage V
o1512 change to low value V
Ss1506.Work as V
g1509 (are generally V for low
Ss1506) time, opposite situation takes place.Now N type device 1505 " ending " and P type device 1502 " conducting ", output voltage V
oChange to the voltage in P type source, or change to V
Ss, anti-phase function is provided effectively.The Schottky barrier CMOS circuit can be worked under the temperature through reducing further adding high power and speed ability, as apply for explain in No. 60/388659, the U.S. Provisional Patent Application on May 16th, 2002.
The present technique field skilled personnel be understood that, above-mentioned CMOS inverter circuit only is to use a complementary Schottky barrier PMOS and a demonstration methods of nmos pass transistor, in integrated circuit, also there is the modification of a lot of combination PMOS and/or nmos pass transistor, but do not deviate from the spirit and scope of the present invention.
Though narration above comprises a lot of details, this should not be understood that the restriction to scope of the present invention, and understands the demonstration to a preferred embodiment of the present invention.The skilled personnel in present technique field will recognize can also many other variations.The metal that many candidates for example, can be arranged as source/leakage.It is also very favourable for a thin oxide layer is inserted between this metal and the silicon substrate.Silicon substrate itself also can be by any amount of other semiconductors or alternative such as the substrate type of SOI.In addition, the line of demarcation between each level or the element can be forever with other materials or interface means classification or insert to improve performance.This invention is intended to cover comprise that this paper discloses or by reference and the cmos device of any variation feature that discloses in the material of combination, and cover comprise that this paper discloses or by reference and the CMOS manufacturing process of the manufacturing technology of any change that discloses in the material of combination.
Though the present invention narrates by the reference preferred embodiment, the personnel skilled in the present technique field will recognize, can make a lot of variations in the form and details and not deviate from the spirit and scope of the present invention.
Claims (26)
1. the cmos device on the Semiconductor substrate comprises:
At least one has the Schottky barrier nmos device of P type channel doping;
At least one has the Schottky barrier PMOS device of N type channel doping; With
Not P type that electrically contacts by the ohmic contact point and at least a doping in the N type channel doping.
2. the cmos device on the Semiconductor substrate comprises:
At least one Schottky barrier nmos device, this Schottky barrier nmos device are positioned at least one Schottky barrier NMOS active region;
At least one Schottky barrier PMOS device, this Schottky barrier PMOS device is positioned at least one Schottky barrier PMOS active region;
At least one trap at least one zone of Schottky barrier NMOS active region that does not electrically contact by the ohmic contact point and Schottky barrier PMOS active region injects.
3. the cmos device on the Semiconductor substrate comprises:
At least one Schottky barrier nmos device;
At least one Schottky barrier PMOS device; With
The device that is used for electrical isolation device is in the not recessed Semiconductor substrate of this device.
4. the cmos device on the Semiconductor substrate comprises:
At least one has the Schottky barrier NMOS active region of at least one Schottky barrier nmos device;
At least one has the Schottky barrier PMOS active region of at least one Schottky barrier PMOS device;
At least one comprises an electric insulation layer in the recessed Semiconductor substrate for Schottky NMOS active region and Schottky barrier PMOS active region provide the territory, place of isolation, this territory, place.
5. a method of making cmos device on Semiconductor substrate comprises the following steps:
At least one Schottky barrier NMOS active region is provided;
At least one Schottky barrier PMOS active region is provided;
In at least some zones of at least one Schottky barrier NMOS active region, form the metal of the first kind, prevent from other zones of Semiconductor substrate, to form the metal of this first kind simultaneously;
In at least some zones of at least one Schottky barrier PMOS active region, form the metal of second type, prevent from other zones of Semiconductor substrate, to form the metal of this second type simultaneously.
6. one kind is removed the method that mask process is made cmos device with double on Semiconductor substrate, comprises the following steps:
At least one Schottky barrier NMOS active region is provided, and this zone comprises a zone of the Semiconductor substrate of at least one grid and exposure;
At least one Schottky barrier PMOS active region is provided, and this zone comprises a zone of the Semiconductor substrate of at least one grid and exposure;
Be provided for preventing forming first kind metal in the zone of Semiconductor substrate of the exposure in Schottky barrier PMOS active region, expose simultaneously and therefore allow to form first of first kind metal in the zone of Semiconductor substrate of the exposure in Schottky barrier NMOS active region and get rid of mask layer;
Be provided for preventing forming second types of metals in the zone of Semiconductor substrate of the exposure in Schottky barrier NMOS active region, expose simultaneously and therefore allow to form second of second types of metals in the zone of Semiconductor substrate of the exposure in Schottky barrier PMOS active region and get rid of mask layer.
7. method as claimed in claim 6 is characterized in that, wherein the grid in Schottky barrier NMOS and the PMOS active region has the isolation of electric insulation sidewall, and this method further comprises the following steps:
Be formed for the figure that first of Schottky barrier PMOS active region is got rid of mask layer with first etching of getting rid of the mask layer etch rate that has greater than sidewall isolated etching speed, thereby expose the Semiconductor substrate in the Schottky barrier NMOS active region, this Schottky barrier NMOS active region has at least some zones of the Semiconductor substrate of the exposure that is close to the grid that exposes;
Provide Schottky or class Schottky contacts by a kind of metal level is provided so that it reacts with the Semiconductor substrate that exposes in the semiconductor substrate region of the exposure of part Schottky barrier NMOS active region, sidewall is isolated between gate lateral wall and this metal level and provides continuous barrier to chemical reaction;
Be formed for the figure that second of Schottky barrier NMOS active region is got rid of mask layer with second etching of getting rid of the mask layer etch rate that has greater than sidewall isolated etching speed, thereby expose the Semiconductor substrate in the Schottky barrier PMOS active region, this Schottky barrier PMOS active region has at least some zones of the Semiconductor substrate of the exposure that is close to the grid that exposes;
Provide Schottky or class Schottky contacts by a kind of schottky metal layer is provided so that it reacts with the Semiconductor substrate that exposes in the semiconductor substrate region of the exposure of part Schottky barrier PMOS active region, sidewall is isolated between gate lateral wall and this metal level and provides continuous barrier to chemical reaction.
8. one kind is removed the method that mask process is made cmos device with double on Semiconductor substrate, comprises the following steps:
Provide at least one grid at least one Schottky barrier N type active region of Semiconductor substrate, this grid has the electric insulation sidewall isolates;
Provide at least one grid at least one Schottky barrier P type active region of Semiconductor substrate, this grid has the electric insulation sidewall isolates;
Be provided for first of Schottky barrier P type active region and get rid of mask layer, this eliminating mask layer etching formation figure that has greater than the eliminating mask layer etch rate of sidewall isolated etching speed, thereby at least some parts of the Semiconductor substrate in the exposure Schottky barrier N type active region;
The thin metal layer that reacts by the Semiconductor substrate that provides and expose in Schottky barrier N type active region provides Schottky or class Schottky contacts, and the sidewall of exposure is isolated between grid and this thin metal layer and provides continuous barrier to chemical reaction;
Be provided for second of Schottky barrier N type active region and get rid of mask layer, this eliminating mask layer etching formation figure that has greater than the eliminating mask layer etch rate of sidewall isolated etching speed, thereby at least some parts of the Semiconductor substrate in the exposure Schottky barrier P type active region; With
The Schottky contacts material that reacts by the Semiconductor substrate that provides and expose in Schottky barrier P type active region provides Schottky or class Schottky contacts, and the sidewall of exposure is isolated between grid and this Schottky contacts material and provides continuous barrier to chemical reaction.
9. method as claimed in claim 8 is characterized in that, wherein the source-drain electrode of Schottky barrier P type active region is used by platinum silicide, and the member in the set that palladium silicide and silication iridium are formed forms.
10. method as claimed in claim 8 is characterized in that, wherein the source-drain electrode of Schottky barrier N type active region uses the member in the set of being made up of the rare earth silicide to form.
11. method as claimed in claim 8 is characterized in that, wherein in the source-drain electrode of Schottky barrier P type active region at least a at least and source-drain electrode between the raceway groove adjacent areas in and Semiconductor substrate form Schottky or class Schottky contacts.
12. method as claimed in claim 8 is characterized in that, wherein in the source-drain electrode of Schottky barrier N type active region at least a at least and source-drain electrode between the raceway groove adjacent areas in and Semiconductor substrate form Schottky or class Schottky contacts.
13. method as claimed in claim 8 is characterized in that, wherein whole interfaces between at least a and Semiconductor substrate in the source-drain electrode of Schottky barrier P type active region and Semiconductor substrate form Schottky contacts or class schottky area.
14. method as claimed in claim 8 is characterized in that, wherein whole interfaces between at least a and Semiconductor substrate in the source-drain electrode of Schottky barrier N type active region and Semiconductor substrate form Schottky contacts or class schottky area.
15. method as claimed in claim 8 is characterized in that, wherein provides grid after all channel doping technology is finished.
16. method as claimed in claim 8 is characterized in that, wherein channel dopant is introduced into Semiconductor substrate and is used for Schottky barrier P type and Schottky barrier N type active region.
17. method as claimed in claim 8 is characterized in that wherein channel dopant is introduced into Semiconductor substrate, the concentration of dopant that makes Schottky barrier P type and Schottky barrier N type active region is laterally keeping constant substantially in the vertical direction significant change.
18. method as claimed in claim 8 is characterized in that, wherein channel dopant is from by arsenic, phosphorus, and antimony, boron is selected in the set that indium and gallium are formed.
19. method as claimed in claim 8 is characterized in that, wherein the source-drain electrode of Schottky barrier P type and Schottky barrier N type active region is configured to make channel length to be less than or equal to 100nm.
20. method as claimed in claim 8 is characterized in that, wherein grid provides through the following steps:
The gate insulator that is included in the electric insulation layer on the Semiconductor substrate is provided;
Deposit conductive film on insulating barrier;
The figure that forms conductive film by etching is to form grid; With
Isolate by at least one sidewall of grid, providing at least one thin dielectric layer to form the electric insulation sidewall.
21. method as claimed in claim 20 is characterized in that, wherein gate insulator has the dielectric constant greater than 4.0.
22. method as claimed in claim 20 is characterized in that, wherein gate insulator uses the member in the set of being made up of metal oxide to form.
23. method as claimed in claim 8 is characterized in that wherein Semiconductor substrate is carried out stress.
24. method as claimed in claim 8, it is characterized in that, wherein Schottky in the Semiconductor substrate of the Schottky barrier N type active region of Bao Luing or class Schottky contacts provide by first thin metal layer that contacts with the Semiconductor substrate that exposes and second thin metal layer that contacts with first thin metal layer are provided, and wherein first and second thin metal layers react by the Semiconductor substrate of thermal annealing and exposure.
25. method as claimed in claim 24 is characterized in that, wherein second thin metal layer forms with titanium.
26. the cmos device with Schottky barrier source-drain electrode comprises:
At least one Schottky barrier nmos device;
At least one Schottky barrier PMOS device, this NMOS and PMOS device are electrically connected.
Applications Claiming Priority (26)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US38124002P | 2002-05-16 | 2002-05-16 | |
| US38116202P | 2002-05-16 | 2002-05-16 | |
| US38123802P | 2002-05-16 | 2002-05-16 | |
| US38123702P | 2002-05-16 | 2002-05-16 | |
| US38123902P | 2002-05-16 | 2002-05-16 | |
| US38132002P | 2002-05-16 | 2002-05-16 | |
| US38123602P | 2002-05-16 | 2002-05-16 | |
| US38132102P | 2002-05-16 | 2002-05-16 | |
| US38865902P | 2002-05-16 | 2002-05-16 | |
| US60/381,162 | 2002-05-16 | ||
| US60/381,237 | 2002-05-16 | ||
| US60/388,659 | 2002-05-16 | ||
| US60/381,320 | 2002-05-16 | ||
| US60/381,238 | 2002-05-16 | ||
| US60/381,321 | 2002-05-16 | ||
| US60/381,236 | 2002-05-16 | ||
| US60/381,240 | 2002-05-16 | ||
| US60/381,239 | 2002-05-16 | ||
| US10/215,447 US6949787B2 (en) | 2001-08-10 | 2002-08-09 | Transistor having high dielectric constant gate insulating layer and source and drain forming Schottky contact with substrate |
| US10/215,447 | 2002-08-09 | ||
| US10/236,685 US6744103B2 (en) | 1999-12-16 | 2002-09-06 | Short-channel schottky-barrier MOSFET device and manufacturing method |
| US10/236,685 | 2002-09-06 | ||
| US10/342,590 | 2003-01-15 | ||
| US10/342,590 US6784035B2 (en) | 2002-01-23 | 2003-01-15 | Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate |
| US44571103P | 2003-02-07 | 2003-02-07 | |
| US60/445,711 | 2003-02-07 |
Publications (1)
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|---|---|
| CN1669145A true CN1669145A (en) | 2005-09-14 |
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| EP (1) | EP1506579A2 (en) |
| JP (1) | JP2006514424A (en) |
| CN (1) | CN1669145A (en) |
| AU (1) | AU2003239475A1 (en) |
| WO (1) | WO2003098693A2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005371A (en) * | 2009-08-28 | 2011-04-06 | 夏普株式会社 | Method for manufacturing semiconductor device |
| CN101533804B (en) * | 2009-04-02 | 2011-09-14 | 英属维京群岛商节能元件股份有限公司 | A metal oxide semiconductor P-N junction schootky diode structure and the production method thereof |
| CN101510528B (en) * | 2009-04-02 | 2011-09-28 | 英属维京群岛商节能元件股份有限公司 | P-N junction diode structure of metal oxide semiconductor and method for producing the same |
| CN113972220A (en) * | 2021-09-27 | 2022-01-25 | 沈阳工业大学 | High-integration central bidirectional Schottky junction type single-tube inverter and manufacturing method thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5108408B2 (en) * | 2007-07-26 | 2012-12-26 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| CA3031736A1 (en) | 2015-07-29 | 2017-02-02 | Circuit Seed, Llc | Complementary current field-effect transistor devices and amplifiers |
| CN110581175A (en) * | 2019-07-26 | 2019-12-17 | 中国科学院微电子研究所 | PMOS transistor, preparation method of PMOS transistor and electronic equipment |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE8101994L (en) * | 1981-03-27 | 1982-09-28 | Tove Per Arne | ELECTRONIC CIRCUIT WITH SCHOTTKY FIELD TRANSISTOR WITH CONTACT ELEMENT WITH DIFFERENT SCHOTTKY BARRIER HEAD |
| JPS58223362A (en) * | 1982-06-21 | 1983-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| US4513309A (en) * | 1982-11-03 | 1985-04-23 | Westinghouse Electric Corp. | Prevention of latch-up in CMOS integrated circuits using Schottky diodes |
| JPS63168046A (en) * | 1986-12-29 | 1988-07-12 | Nec Corp | Cmos device |
| US5250834A (en) * | 1991-09-19 | 1993-10-05 | International Business Machines Corporation | Silicide interconnection with schottky barrier diode isolation |
| JPH0697109A (en) * | 1992-09-16 | 1994-04-08 | Fujitsu Ltd | Semiconductor device |
| US5665993A (en) * | 1994-09-29 | 1997-09-09 | Texas Instruments Incorporated | Integrated circuit including a FET device and Schottky diode |
| JP3378512B2 (en) * | 1998-10-16 | 2003-02-17 | 株式会社東芝 | Semiconductor device |
| US6303479B1 (en) * | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
-
2003
- 2003-05-16 EP EP03734043A patent/EP1506579A2/en not_active Withdrawn
- 2003-05-16 JP JP2004506087A patent/JP2006514424A/en active Pending
- 2003-05-16 CN CN 03816343 patent/CN1669145A/en active Pending
- 2003-05-16 AU AU2003239475A patent/AU2003239475A1/en not_active Abandoned
- 2003-05-16 WO PCT/US2003/015367 patent/WO2003098693A2/en active Search and Examination
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101533804B (en) * | 2009-04-02 | 2011-09-14 | 英属维京群岛商节能元件股份有限公司 | A metal oxide semiconductor P-N junction schootky diode structure and the production method thereof |
| CN101510528B (en) * | 2009-04-02 | 2011-09-28 | 英属维京群岛商节能元件股份有限公司 | P-N junction diode structure of metal oxide semiconductor and method for producing the same |
| CN102005371A (en) * | 2009-08-28 | 2011-04-06 | 夏普株式会社 | Method for manufacturing semiconductor device |
| CN113972220A (en) * | 2021-09-27 | 2022-01-25 | 沈阳工业大学 | High-integration central bidirectional Schottky junction type single-tube inverter and manufacturing method thereof |
| CN113972220B (en) * | 2021-09-27 | 2024-03-15 | 沈阳工业大学 | High-integration central bidirectional Schottky junction type single-tube inverter and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2003098693A2 (en) | 2003-11-27 |
| JP2006514424A (en) | 2006-04-27 |
| WO2003098693A3 (en) | 2004-10-21 |
| EP1506579A2 (en) | 2005-02-16 |
| AU2003239475A1 (en) | 2003-12-02 |
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