CN1669145A - Schottky barrier CMOS device and method - Google Patents

Schottky barrier CMOS device and method Download PDF

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CN1669145A
CN1669145A CN 03816343 CN03816343A CN1669145A CN 1669145 A CN1669145 A CN 1669145A CN 03816343 CN03816343 CN 03816343 CN 03816343 A CN03816343 A CN 03816343A CN 1669145 A CN1669145 A CN 1669145A
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schottky
barrier
cmos
device
method
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CN 03816343
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J·P·施奈德
J·M·拉森
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斯平内克半导体股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/095Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66643Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact

Abstract

本发明揭示一种CMOS器件及其制造方法。 The present invention discloses a method of manufacturing the CMOS device. 本发明为CMOS器件和CMOS集成电路的范围内的源和/漏接触利用了肖特基壁垒接触,以消除对晕/阱注入,浅源/漏延伸的要求以控制短沟道效应,取消阱注入步骤和复杂的器件隔离步骤。 Within the scope of the present invention is a CMOS device and a CMOS integrated circuit and a source / drain contact using a Schottky barrier contact to eliminate the halo / well implants, shallow source / required to control the short channel effect and drain extension of the well cancellation implantation step and complex device isolation step. 另外,和现有技术相比,本发明消除了和CMOS器件运行相关的寄生双极型增益,减少了制造成本,严格了对器件性能参数的控制以及提供了优越的器件性能。 Further, compared to the prior art, the present invention eliminates the parasitic bipolar and CMOS devices gain related to the operation, reduce manufacturing costs, strict control of the performance parameters of the device and provide superior device performance. 在一个实施例中本发明用硅化物排除掩模工艺形成用于形成CMOS器件的互补PMOS和NMOS器件的双硅化物肖特基壁垒源和/漏的接触。 In one embodiment of the present invention mask process to form the source Schottky Barrier bis silicide complementary PMOS and NMOS devices for forming CMOS devices and / drain silicide contact for exclusion.

Description

肖特基壁垒CMOS器件及其方法 Schottky barrier CMOS device and method

相关申请的交互引用本申请为申请于1999年12月16日的美国专利申请09/465357号,现为美国专利6303479号的分案申请的申请于2001年2月6日的美国专利申请09/777536号,现为美国专利6495882号的继续的申请于2002年9月6日的美国专利申请10/236685号的部分继续。 Interactive REFERENCE TO RELATED APPLICATIONS This application is filed on December 16, 1999 US Patent Application No. 09/465357, now US Patent No. 6,303,479 divisional application is filed on February 6, 2001 US Patent Application 09 / No. 777,536, now continue the application of US Patent No. 6,495,882 US Patent September 6, 2002 application No. 10/236685 part continue. 本申请也是申请于2003年1月15日,要求对于申请于2002年1月23日的美国临时专利申请60/351114号和申请于2002年1月25日的美国专利申请60/319098号的优先权的美国专利申请10/342590的部分继续。 This application is also filed on January 15, 2003, the requirements for application on January 23, 2002 of US Provisional Patent Application No. 60/351114 and No. 60/319098 priority application to US Patent Application No. 2002 of January 25 part of US patent application 10/342590 of the right to continue. 本申请也是同时申请于2001年8月10日的美国专利申请09/928124号和美国专利申请09/928163号的部分继续的申请于2002年8月9日的美国专利申请10/215447号的部分继续。 No. 10/215447 part of this application also apply for 2001 August 10 of US Patent Application No. 09/928124 and US Patent Application No. 09/928163 continue to apply in August 9, 2002 US Patent Application carry on. 每一个上述申请都通过应用而全文结合在本文中。 Each of the above applications are incorporated herein in their entirety by the application.

本申请要求对于申请于2003年2月7日的美国临时专利申请60/445711号的优先权。 This application claims filed on February 7, 2003 of US Provisional Patent Application Serial No. 60/445711. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381162号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381162. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381238号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381238. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381659号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381659. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381240号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381240. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381237号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381237. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381321号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381321. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381239号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381239. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381236号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381236. 本申请要求对于申请于2002年5月16日的美国临时专利申请60/381320号的优先权。 This application claims filed on May 16, 2002 of US Provisional Patent Application Serial No. 60/381320. 每一个上述申请都通过应用而全文结合在本文中。 Each of the above applications are incorporated herein in their entirety by the application.

技术领域 FIELD

本发明一般涉及半导体系统和制造工艺的领域。 The present invention relates generally to the field of semiconductor manufacturing processes and systems. 更具体地说,本发明涉及具有肖特基壁垒金属氧化物半导体场效应晶体管(MOSFET)的半导体集成电路(IC)及其制造工艺,该肖特基壁垒金属氧化物半导体场效应晶体管(MOSFET)包括肖特基壁垒P型MOSFET(PMOS),肖特基壁垒N型MOSFET(NMOS)和肖特基壁垒互补MOSFET(CMOS)。 More particularly, the present invention relates to a semiconductor integrated circuit having a Schottky barrier metal oxide semiconductor field effect transistor (MOSFET) (IC) for its manufacturing process, the Schottky barrier metal oxide semiconductor field effect transistor (MOSFET) comprising a P-type Schottky barrier MOSFET (PMOS), N-type Schottky barrier MOSFET (NMOS) and complementary Schottky barrier MOSFET (CMOS).

背景技术 Background technique

自从1940年晶体管发明以来,在半导体和微电子领域表现出巨大的优越性。 Since the invention of the transistor in 1940, he showed great superiority in the semiconductor and microelectronics. 今天,取得支配地位的半导体技术是CMOS-互补的金属氧化物半导体。 Today, semiconductor technology has achieved a dominant position is CMOS- complementary metal oxide semiconductor. 当前的CMOS技术能达到在一个约10mm尺寸的硅片上集成超过1亿元件的集成电路的具有成本效益的制造。 Current CMOS technology to achieve cost-effective manufacturing integrated over $ 100 million member integrated circuit on a silicon wafer of a size of about 10mm. 10亿晶体管的IC也将在几年之内出现商业产品。 One billion transistors IC will also appear in commercial products within a few years. 对于每个IC以更低的成本获得更大的功能和性能的要求驱动了几种趋势。 For each IC requires greater functionality and performance at lower cost driven several trends.

首先,对功能的要求驱动晶体管数上升。 First, to increase the number of transistors required driving function. 其次,晶体管本身的尺寸减小以达到更大的集成度以及更重要的是改进其性能。 Second, the size of the transistor itself is reduced to achieve a greater degree of integration, and more importantly, to improve its performance. 就涉及性能而言,MOSFET的关键参数是沟道的长度。 It involves in terms of performance, the key parameter is the length of the channel MOSFET. 沟道长度(L)是载流子渡越器件的距离,该长度的减小同时必然带来更高的电流驱动,经减小的寄生电阻和电容以及经改进的高频性能。 The channel length (L) is a carrier transit distance of the device, while reducing the length inevitably lead to higher current drive, via parasitic resistance and capacitance and improved high frequency performance is reduced. 普通的品质因数是功率和延迟时间的乘积,对晶体管性能的这种概括性的量度被表述为沟道长度倒数的立方(1/L3)。 Common quality factor is the product of power and delay time, a measure of this general transistor performance is expressed as the reciprocal of the cube of the channel length (1 / L3). 这说明IC制造商必须尽其制造能力减小该沟道长度这样一种巨大的激励作用。 This shows that the manufacturer must do their IC manufacturing capacity of the channel length to reduce a great incentive.

对于数字应用,MOS晶体管的行为好象开关。 For digital applications, MOS transistor switch if the behavior. 在“导通”时,它们通过相对较大的电流,在“截止”时,它们由一定量的漏电流表征。 When "on", through which a relatively large current, when "off", the drain current thereof is characterized by a certain amount. 由串联连接的NMOS和PMOS器件构成的普通的CMOS反相器电路仅在切换的短暂过渡期间才消耗可感知的功率。 Conventional CMOS inverter circuit NMOS and PMOS devices connected in series was composed of only the power consumption can be perceived during the transition in a short switching. 反之,静态功率消耗,或者由CMOS电路在静置期消耗的功率仅仅是MOSFET漏电流的函数,对于大多数应用而言,该静态功率消耗显著影响整个电路的功率消耗。 On the contrary, the static power consumed by a CMOS circuit or a power consumption of only left MOSFET drain current as a function, for most applications, the static power consumption significantly impact the power consumption of the entire circuit.

当沟道长度减小时,驱动电流增加,如上所述,这有利于电路性能的提高。 When the channel length is reduced, driving current increases, as described above, which will help improve circuit performance. 但是漏电流也增加了。 However, the leakage current increases. 晶体管的漏电流增加了静态功率消耗,在极端的情况下能影响有源运算期间二进制信息的传输。 Transistor leakage current increases static power consumption, can affect the transmission of binary information during active operation in extreme cases. 因此器件的设计人员有充分的理由在沟道长度减小时保持MOSFET的低漏电流。 Thus the designer of the device there is good reason to maintain a low leakage current when the MOSFET channel length decreases.

MOS晶体管的漏电流传统上通过将受控数量的杂质(掺杂)引入器件的源漏两极之间的区域(沟道区域)并精心设计源漏两极侧向和垂直方向的掺杂分布而受到控制。 Region (channel region) between the source and drain poles on the drain current of the device is introduced by the conventional MOS transistor controlled amount of impurities (dopant) and the source-drain poles designed lateral and vertical doping profile and by control. 虽然这些措施对减小MOS晶体管内部的势垒因而减小漏电流有效,但也会降低驱动电流和增加寄生电容,这也是减小沟道长度意味着必须改进的重要方面。 While these measures reduce the internal barrier MOS transistor thus reducing the leakage current effectively, but also reduces the parasitic capacitance and increasing the drive current, which is meant to reduce the need to improve the channel length of the important aspects. 另外,也正是取决于在制造工艺中怎样引入沟道和经精心设计的源漏两极的掺杂,制造成本可显著地受到影响。 Further, depending on how it is introduced into the source-drain channel and a well-designed bipolar doping in the manufacturing process, the manufacturing cost can be significantly affected.

另一个影响制造成本的因素是工艺收益。 Another factor affecting the cost of manufacturing is the process of return. 该收益是所制造的衬底上功能性器件和全部器件数之比。 The benefit is more than the total number of functional devices and the devices fabricated on the substrate. 工艺收益完全是全部工艺步骤的函数。 The process proceeds entirely a function of all process steps. 例如,如果每个工艺步骤的平均收益为99.5%而CMOS工艺的全部工艺步骤有50步,则工艺收益约为90%。 For example, if the average revenue per process step was 99.5% and the entire process step of the CMOS process step 50, the process proceeds about 90%. CMOS工艺的制造成本完全是工艺收益的函数,随工艺收益的降低而提高。 Cost CMOS manufacturing process is entirely a function of process benefits, with lower income and improve the process. 表征CMOS技术的制造复杂度以及因此而来的成本的简单的衡量标准是全部的掩模步骤数,每一个掩模步骤都包含一系列涂胶,掩模套准,光刻曝光,刻蚀步骤,清洗和测量。 Characterization of CMOS technology and manufacturing complexity from simple and therefore cost metrics of all, the number of masking steps, each coating contains a series of masking step, the mask register, lithographic exposure, etching step , cleaning and measurement. 在CMOS工艺中减少掩模步骤数通过减少全部工艺步骤以及附加增加收益而直接减少了制造成本。 Reducing the number of mask steps in a CMOS process by reducing all of the additional processing steps and increase profits directly reduce the manufacturing cost. 对于现有的传统的MOS晶体管设计和技术以及CMOS的制造工艺,在驱动电流,漏电流,寄生电容和电阻以及制造复杂度和制造成本之间的取舍方面只有有限的几个方案。 For existing conventional MOS transistor, and design and manufacturing process of CMOS technology, in terms of trade-offs between the driving current, leakage current, parasitic capacitance and resistance and manufacturing complexity and manufacturing costs only a limited number of programs.

本发明在这些对抗的要求之间提供了一种新的关系,并提出了对于MOS器件和CMOS基集成电路用传统的(掺杂杂质)MOS技术无法达到的性能上的可能性。 The present invention provides a confrontation between these requirements, a new relationship, and raised the possibility of MOS devices and for CMOS integrated circuits on a conventional group (dopants) MOS technology can not achieve the performance. 金属在源漏两极上的使用对减小寄生电容,在器件特性中减小静态变化(尤其是随沟道长度的减小发生的变化)方面的器件特性以及对减少制造成本和复杂度方面都提供了改进。 Use on the source drain metal bipolar device characteristics (in particular with decreasing channel length change occurs) as well as all aspects of reducing the manufacturing cost and complexity of the parasitic capacitance is reduced to reduce the static variation in the device characteristics It provides improved.

掺杂剖面先有的CMOS器件的产生依赖于MOS晶体管侧向均匀垂直方向不均匀的沟道掺杂剖面以控制源漏极之间的漏电流。 First generate some doping profile is dependent on the CMOS device MOS transistor nonuniform lateral direction perpendicular to a uniform doping profile in the channel to control the leakage current between the source and drain. 见Yuan Taur,“The IncredibleShrinking Transistor”,IEEE SPECTRUM,page 25-29(www.Spectrum.Ieee.org,ISSN 0018-9235,July 1999)。 See Yuan Taur, "The IncredibleShrinking Transistor", IEEE SPECTRUM, page 25-29 (www.Spectrum.Ieee.org, ISSN 0018-9235, July 1999). 图1说明了一个示范的长沟道常规MOS器件(100),该器件包括掺杂的源(101),掺杂的漏(102),常规的MOS型栅结构(103)以及有助于控制源漏两极之间的漏电流的在衬底中侧向均匀的沟道掺杂剖面(104)。 1 illustrates an exemplary conventional long-channel MOS device (100), the device comprising a doped source (101), doped drain (102), the conventional MOS type gate structure (103) and help control source-drain leakage current in the substrate between the two poles laterally uniform doping profile of the channel (104). 器件通过场氧化(105)互相电隔离。 Means electrically isolated from each other by a field oxide (105). 这样的沟道掺杂剖面在沟道长度降至约200纳米(nm)的器件中是很普通的。 Such a channel doping profile in the channel length down to about 200 nanometers (nm) of the device is very common.

但是,当器件的沟道长度被减小到100nm范围时,文献指出,沟道的掺杂剖面要求在侧向和垂直方向都是非均匀的。 However, when the channel length of the device is reduced to 100nm range, the literature indicates that the channel doping profile is required in the lateral and vertical directions are non-uniform. 参考图2,示范的短沟道MOS器件(200)具有和长沟道器件(100)相似的一些元件。 Referring to FIG 2, an exemplary short-channel MOS device (200) and having a long channel devices (100) of some elements similar. 该结构包括常规掺杂的源(201)和漏(202)以及常规的栅结构(203)(相应于沟道长度L其宽度<~100nm)。 The conventional structure includes a doped source (201) and drain (202) and a conventional gate structure (203) (which corresponds to the width of the channel length L <~ 100nm). 该结构还包括和源(207)漏(206)阱掺杂连同使用的源(208)漏(209)极的浅掺杂延伸以及常规的控制源漏之间的漏电流的沟道掺杂(204)。 The structure further comprises a source (207) a drain (206), together with well dopant source (208) a drain (209) using a shallow doping extending poles and leakage current between the source and drain of the conventional control channel doping ( 204). 源漏极(201)和(202)及其各自的延伸(208)和(209)(全部四个电极的组合构成了精心设计的源/漏掺杂剖面)都有相同的掺杂极性(N型或P型)以及和沟道(204)和阱掺杂元件(206)和(207)相反的掺杂极性。 Source and drain (201) and (202) and their respective extension (208) and (209) (combination of all four electrodes form the source designed / drain doping profile) has the same doping polarity ( N-type or P-type) and the channel well (204) and well doping element (206) and (207) opposite doping polarity. 还有,场氧化(205)将器件互相电隔离。 Further, the field oxide (205) are electrically isolated from the device.

常规的CMOS电路参考图3,典型的CMOS反相器电路300为在重掺杂的半导体衬底330上的轻掺杂的P型外延半导体层331上制造的串联连接的P型MOSFET器件301和N型MOSFET器件302。 P-type MOSFET device 3, a typical CMOS inverter circuit 300 on the semiconductor substrate 330 on the heavily doped P-type lightly doped semiconductor epitaxial layer 331 is fabricated with reference to a conventional CMOS circuits 301 are connected in series, and FIG. N-type MOSFET device 302. 源304,306和漏303,305接触包括掺杂的源极304,306和漏极303,305浅掺杂源316,318和漏315,317延伸,阱掺杂345,346以及沟道和衬底掺杂347,348。 304, 306, 303, 305 source and drain contacts and the drain electrode 304, 306 303, 305 comprise doped source and drain lightly doped source extension 315, 317, 316, 318, 345, 346 and the channel doping and well lining background doping 347, 348. 两个器件301,302的漏接触303,305互相连接,P型器件301的源304连接到Vdd307,N型器件302的源306连接到通常为接地的低电源Vdd308,两个器件301,302的栅309,310具有共同的连接点Vg311。 Drain contacts 301, 302 of the two devices 303, 305 connected to each other, P-type device 301 is connected to the source 304 Vdd307, N-type device 302 is typically connected to a source 306 of low power ground Vdd308, two devices 301, 302 gate 309, 310 have a common connection point Vg311. PMOS器件301和NMOS器件302由场氧化320和PMOS器件的N阱注入区321隔离,N阱注入区321通过重掺杂的N型欧姆接触点340连接到Vdd307。 PMOS device 301 and NMOS device 302 321 N well implant are separated by a field oxide region 320 and PMOS devices, N well implant region 321 heavily doped N-type ohmic contact point 340 is connected to Vdd307.

公共漏连接点的输出电压Vo取决于栅Vg311的输入电压。 The common drain connection point of the output voltage Vo depends on the input voltage of the gate Vg311. 当Vg311为高(通常为Vdd307)时,N型器件302“导通”而P型器件301“截止”。 When Vg311 is high (typically Vdd307), N-type device 302 "on" and the P-type device 301 "off." 也就是说,N型器件302的沟道区域313导电而P型器件301的沟道区域314不导电。 That is, N-type channel region 313 of the device 302 and the P-type conductivity channel region 314 device 301 is non-conductive. 结果是,输出电压Vo312变到N型的源306的电压,或Vss308。 As a result, the output voltage Vo312 is changed to N-type voltage source 306, or Vss308. 当Vg311为低(通常为Vss308)时发生相反的情况。 The opposite occurs when Vg311 is low (typically Vss308). 现在N型器件302“截止”而P型器件301“导通”,输出电压变到P型的源304的电压,或Vdd307。 N-type device 302 is now "off" the P-type device 301 "on", the output voltage of the variable voltage source 304 of the P-type, or Vdd307. 概括地说,高(低)输入电压Vg311产生低(高)输出电压Vo312,有效地提供了反相的功能。 In summary, high (low) generates a low input voltage Vg311 (high) output voltage Vo312, effectively providing an inverted function. 该种典型的CMOS反相器电路的一个示范特性是适当的电流仅在输入电压Vg311从高到低或从低到高的切换期间流动。 The typical characteristics of an exemplary CMOS inverter circuit is appropriate only when the input current or voltage Vg311 Low flow during switching from low to high. 反之,当静置时,起支配作用的静态功率消耗源为漏电流。 Conversely, when left to stand, the predominant source of static power consumption of the leakage current.

肖特基壁垒CMOS在美国专利5760449号中,Welch公开了一种具有串联连接的N沟道和P沟道MOSFETD的肖特基壁垒晶体管器件系统,该系统中,N型和P型器件的源结,不是漏结,电互相连接,该肖特基壁垒晶体管器件系统用中间能隙硅化铬形成N型和P型器件的肖特基壁垒源漏区域。 CMOS Schottky barriers in U.S. Patent No. 5760449, Welch discloses a Schottky barrier transistor device system having serially connected N-channel and P-channel MOSFETD of the system, the source of the N-type and P-type devices junction, junction leakage is not electrically connected to each other, the Schottky barrier transistor device systems midgap chromium silicide forming N-type and P-type devices Schottky barrier source and drain regions. 诸如硅化铬的中间能隙硅化物由费米能级表征,该费米能级接近硅的约为0.56eV的中间带隙。 Intermediate, such as about 0.56eV bandgap intermediate chromium silicide is a silicide characterized by a Fermi energy level, the Fermi level near the silicon band gap. Welch将结果电路称为“相当于CMOS的单器件”,因为该CMOS器件制造在单掺杂类型的半导体衬底上并用完全相同的金属硅化物形成两个晶体管的源漏区域。 The results of the circuit Welch referred to as "equivalent to a single CMOS devices", because the CMOS device fabricated on a single doping type of the semiconductor substrate and forming source and drain regions of the two transistors of the same metal with a silicide. 和互补的相反类型的N型和P型晶体管在一起使用的常规的CMOS器件相比,该器件的两个晶体管完全相同。 Compared with the conventional CMOS device and a complementary N-type and the opposite type of P-type transistor used together, two identical transistors of the device. 另外,Welch指出,该器件表现出正反馈的反相开关特性。 Further, Welch noted that the switching inverter device exhibits characteristics of a positive feedback. 在器件切换时源电压(不象常规的CMOS反相器是漏电压)发生变化,从而提高了栅到源的电位差,从而“正反馈”地或额外地使器件“导通”,直至切换完成。 When the device is switched voltage source (unlike a conventional CMOS inverter is the drain voltage) is changed, thereby increasing the difference in potential of the gate to the source, so that "positive feedback" or additionally, the device "on" until the switching carry out. Welch指出,中间能隙硅化铬导致了两个MOSFET器件对称的运算特性,使CMOS类型的反相技术取决于偏置条件。 Welch noted midgap chromium silicide leads calculation characteristic symmetrical two MOSFET devices, of the CMOS inverter techniques depend on the type of bias conditions. 但是,中间能隙硅化物也导致不可接受的低驱动电流和源漏之间的高漏电流。 However, the mid-gap also result in a silicide of a high leakage current between the low current drive source and drain unacceptable. 另外,Welch没有叙述用短沟道MOSFET器件的反相电路的性能,也没有处理沟道或衬底的掺杂问题以改进各个MOSFET器件截止状态时的漏电流。 Further, no description Welch inverter circuit performance short-channel MOSFET device, do not address the problem of the channel or the doping of the substrate in order to improve the leakage current when an off state of the respective MOSFET device.

概括地说,先有技术没有揭示或指出肖特基壁垒,金属源漏CMOS器件或肖特基壁垒,金属源漏CMOS器件的制造工艺。 In summary, the prior art does not disclose or indicate a Schottky barrier, metal source and drain CMOS device, or a Schottky barrier, metal source and drain of the CMOS device fabrication process.

器件隔离为了制造集成电路,为了在电路中使每个器件独立于其他器件工作,各个晶体管器件必须互相隔离。 In order to manufacture an integrated circuit device isolation, manipulation for each device in the circuit device operating independently of the other, each transistor device must be isolated from each other. 最佳的器件隔离技术具有高密度,合理的工艺复杂度,高收益以及可接受的寄生效应。 Best device isolation technology with high density and reasonable process complexity, high yield and acceptable parasitics. 器件隔离将半导体衬底分成两个类型的区域。 The device isolation semiconductor substrate into two types of regions. 第一个区域具有暴露的半导体表面并被表示为在其上制造晶体管的有源区域。 A first semiconductor region having a surface exposed active region is represented as transistors fabricated thereon. 第二个区域包括掩蔽半导体衬底并被表示为在其上不制造器件的场区域的“场氧化”。 The second region includes a semiconductor substrate and a masking region is not represented as a field of manufacturing a device on which the "field oxide."

有很多诸如本地硅氧化(LOCOS)和浅沟槽隔离(STI)的器件隔离的技术。 There are many such as a local oxidation of silicon (LOCOS) and a shallow trench isolation (STI) device isolation technique. 虽然LOCOS和STI都为先进的CMOS技术进行了优化,但它们都受到几个整体挑战。 Although the LOCOS and STI are optimized for advanced CMOS technology, but overall they have been a few challenges. 一些对LOCOS的挑战的实例包括在氧化工艺中诱发的硅衬底的应力,白带氮化物效应以及存在被称为鸟嘴的现象。 Some examples include challenge LOCOS silicon substrate in an oxidation process induced stress, and the presence of vaginal nitride effect is called bird's beak phenomenon. 虽然对于大多数这些挑战都存在解决方案,但这些方案增加了制造工艺的复杂度或限制了工艺的灵活性。 While most of these challenges are present for solutions, but these solutions increases the complexity of the manufacturing process or limits the flexibility of the process.

硅化物排除掩模工艺硅化物通常设置于整个半导体衬底的表面。 Silicide silicide exclusion mask process is generally provided on the entire surface of the semiconductor substrate. 硅化物的引入对于某些应用的电路带来有害的影响,诸如对于有源CMOS像素阵列(增加了光电二极管的暗电流和不透明性)或模拟电路(降低了信号的完整性,加剧了电路应力,影响了阈值电压的偏移和结的漏电流)。 Introducing silicide detrimental effect on the circuit of certain applications, such as for CMOS active pixel array (increased dark current of the photodiode and opacity) or analog circuitry (reduce signal integrity, increased stress circuit Effects of the threshold voltage shift and the junction leakage current). 在先有技术中发展了硅化物排除掩模工艺,选择性地掩蔽部分半导体衬底,防止在被掩蔽区域形成硅化物。 Developed in the prior art silicide exclusion mask process, is selectively masking portions of the semiconductor substrate, prevent the formation of silicide is masked area. 参看美国专利6160282号和美国专利5883010号的实例,在6160282号专利中,Merrill公开了一种硅化物排除掩模工艺以改进有源CMOS像素阵列的性能,在5883010号专利中,Merrill公开了一种提供硅化物排除的隔离氧化掩模工艺。 See example U.S. Patent No. 6,160,282 and U.S. Patent No. 5,883,010, Patent No. 6,160,282 in, Merrill discloses a silicide exclusion mask process is performed to improve the performance of an active CMOS pixel array, in Patent No. 5,883,010, discloses a Merrill method of providing isolation oxide silicide exclusion mask process.

硅化物排除掩模工艺通常包括淀积一个硅化物排除氧化掩模层,淀积光刻胶,形成光刻胶的图形,刻蚀硅化物排除氧化掩模层而使由光刻胶和氧化物覆盖的区域受到保护免于形成硅化物并使将形成硅化物的区域得以暴露,剥离光刻胶层,在由硅化物排除氧化掩模图形暴露的硅表面上选择性地形成金属硅化物层,以及去除硅化物排除氧化掩模层。 Silicide exclusion mask process generally involves depositing a silicide exclusion mask oxide layer, depositing a photoresist to form a photoresist pattern, etching the silicide exclusion oxide mask layer is a photoresist and the oxide the area covered is protected from the formation of silicide and silicide formation region is exposed, stripping the photoresist layer, selectively forming a metal silicide layer on the oxide silicide exclusion mask pattern exposed silicon surfaces, and removing the silicide exclusion mask oxide layer. 该硅化物排除掩模技术没有被用于制造肖特基壁垒CMOS器件和电路。 The silicide exclusion mask techniques have not been used for manufacturing a Schottky barrier CMOS devices and circuits.

因此,在技术上存在对于肖特基壁垒CMOS器件及其制造工艺的需要。 Accordingly, there is a need for a Schottky barrier CMOS device fabrication process and technically. 还进一步存在对于带有经改进的性能的短沟道CMOS器件及其简化的低成本制造工艺的需要。 Further need exists for a short-channel CMOS device with improved performance and simplified low-cost manufacturing process.

发明内容 SUMMARY

概括地说,在各种实施例中,所揭示的CMOS器件包括选择性地具有P型沟道掺杂剂的肖特基壁垒NMOS器件和选择性地具有N型沟道掺杂剂的肖特基壁垒PMOS器件。 Broadly speaking, in various embodiments, the disclosed device includes a CMOS having selectively a P-type channel dopant SCHOTT Schottky barrier NMOS device and optionally having N-channel dopant yl barrier PMOS device. 沟道掺杂剂和/或阱注入可以或不可以和欧姆接触点进行电接触。 Channel dopant and / or injection wells may or may not ohmic contact and the electrical contact points. 器件可由场氧化分离,选择性地氧化层的窗口不显著地凹入半导体衬底。 Separation means may be a field oxide, a window is selectively oxidized layer does not significantly recessed semiconductor substrate.

本发明的另一个方面是CMOS器件的制造工艺。 Another aspect of the present invention is a manufacturing process of a CMOS device. 简单的非凹入的氧化层窗口被提供作为场氧化。 Simple non-recessed oxide layer is provided as a field oxide window. 沟道和/或阱注入被进一步引入以隔离N型和P型有源区域。 Channel and / or injection wells are further introduced to isolate the P-type and N-type active region. NMOS器件的栅极形成在N型有源区域,PMOS器件的栅极形成在P型有源区域,栅极具有薄的电绝缘的侧壁隔离。 Gate of the NMOS device is formed in the N-type active region, the gate of PMOS device formed in a P-type active region, the gate sidewall spacer having a thin electrically insulating. 硅化物排除掩模被用于防止在P型有源区域形成硅化物同时暴露N型有源区域。 Silicide exclusion mask is used to prevent the formation of silicide on the P-type active region while exposing the N-type active region. 当该排除掩模层用湿化学刻蚀形成图形时,排除掩模层的刻蚀速率大于NMOS器件侧壁隔离的刻蚀速率。 When the negative mask pattern layer is formed by wet chemical etching, negative etch rate greater than the etching rate of the mask layer sidewall spacer of the NMOS device. 通过使一个薄金属层和至少在相邻于NMOS器件栅极的区域中暴露的半导体衬底反应而形成肖特基或类肖特基接触。 A thin metal layer by the semiconductor substrate and exposed at least in the reaction region adjacent to the gate of the NMOS device is formed in a Schottky or Schottky-like contacts. 相似地,硅化物排除掩模被用于防止在N型有源区域形成硅化物同时暴露P型有源区域。 Similarly, the silicide exclusion mask is used to prevent the formation of the silicide P-type active region while exposing the N-type active region. 当该排除掩模层用湿化学刻蚀形成图形时,排除掩模层的刻蚀速率大于PMOS器件侧壁隔离的刻蚀速率。 When the negative mask pattern layer is formed by wet chemical etching, negative etch rate greater than the etching rate of the mask layer sidewall spacer of the PMOS device. 通过使一个薄金属层和至少在相邻于PMOS器件栅极的区域中暴露的半导体衬底反应而形成肖特基或类肖特基接触。 A thin metal layer by the semiconductor substrate and exposed at least in the reaction region adjacent to the gate of the PMOS device is formed in a Schottky or Schottky-like contacts.

在揭示多种实施例的同时,本发明还有显示和叙述本发明的说明性实施例的其他实施例通过下文详尽的叙述对于在本技术领域熟练的人员而言也将是显而易见的。 While the various embodiments disclosed, the present invention also has other embodiments shown and described illustrative embodiments of the present invention by the detailed description below for those skilled in the art in this art will also be apparent. 如将认识到的那样,本发明在各个明显的方面都能进行修改而不背离本发明的精神和范围。 As will be appreciated, the invention can be modified in various obvious respects, all without departing from the spirit and scope of the invention. 因此,附图和详尽叙述都将被认为是对其性能的说明而不是限制。 Accordingly, the drawings and detailed description are to be regarded as the performance of its description and not of limitation.

附图说明 BRIEF DESCRIPTION

图1显示了先有技术的长沟道掺杂源/漏器件;图2显示了先有技术的短沟道掺杂源/漏器件,带有阱注入和源/漏延伸;图3显示了先有技术的短沟道掺杂源/漏CMOS反相器电路;图4显示了沟道长度和沟道区域的定义;图5显示了根据本发明的一个实施例的CMOS器件;图6显示了本发明的应用P型器件有源区域注入的工艺的示范实施例;图7显示了本发明的应用N型器件有源区域注入的工艺的示范实施例;图8显示了本发明的应用形成用于器件隔离的LOCOS场氧化的工艺的示范实施例;图9显示了本发明的应用薄栅氧化上已形成图形的硅薄膜的工艺的示范实施例;图10显示了本发明的应用形成薄氧化侧壁以及暴露在栅,源和漏区域中的硅的工艺的示范实施例;图11显示了本发明的应用硅化物排除掩模和金属淀积以及N型器件的硅化退火,以及应用去除未退火金属的工艺的示 Figure 1 shows a prior art long channel doped source / drain device; FIG. 2 shows a prior art short channel doped source / drain device, with the injection well and the source / drain extension; FIG. 3 shows the prior art short channel doped source / drain CMOS inverter circuit; FIG. 4 shows the definition of the channel length and the channel region; FIG. 5 shows a CMOS device in accordance with one embodiment of the present invention; Figure 6 shows process exemplary application P-type active device region of the present invention implanted embodiment; FIG. 7 shows an exemplary process of the present invention using N-type active device region implanted embodiment; FIG. 8 shows an application of the present invention is formed Figure 9 shows an exemplary embodiment of the process a silicon thin film pattern formed on the thin gate oxide applications of embodiments of the present invention;; exemplary embodiment of the LOCOS field oxidation process is used for device isolation Figure 10 shows the application of the present invention is to form a thin oxidizing the sidewall and the process model is exposed to the gate, source and drain regions in the silicon of the embodiment; FIG. 11 shows the application of the present invention, the silicide exclusion mask and metal deposition and suicide annealing N-type device, and the application is removed unannealed metal process shown 实施例;图12显示了本发明的应用硅化物排除掩模和金属淀积以及P型器件的硅化退火,以及应用去除未退火金属的工艺的示范实施例;图13显示了本发明的工艺的结果结构的示范实施例;图14显示了根据本发明的原理的肖特基壁垒CMOS反相器电路的示范实施例,该肖特基壁垒CMOS反相器电路具有串联连接的带有简单的薄场氧化和不通过欧姆接触点电接触的阱注入的PMOS和NMOS器件;和图15显示了根据本发明的原理的具有串联连接的PMOS和NMOS器件的肖特基壁垒CMOS反相器电路布局的示范实施例具体实施方式图5显示了本发明的由两个最后的互补MOSFET结构500示例的示范实施例。 Example embodiment; FIG. 12 shows the application of the present invention, the silicide exclusion embodiment of masks and metal deposition and suicide P-type annealing device, and the application of the process of removing unannealed metal exemplary embodiment; FIG. 13 shows the process of the present invention results exemplary configuration of the embodiment; FIG. 14 shows an exemplary CMOS inverter circuit barrier Schottky principles of the present embodiment of the invention, the Schottky barrier having a simple CMOS inverter circuit connected in series with a thin injection wells and field oxide PMOS and NMOS devices are not in contact with the electrical contact points by the ohmic; and Figure 15 shows a Schottky having PMOS and NMOS devices connected in series barriers CMOS inverter circuit layout according to the principles of the present invention DETAILED DESCRIPTION Example embodiments exemplary embodiment of FIG. 5 shows an exemplary embodiment of the MOSFET 500 is complementary to the last two exemplary embodiments of the structure of the present invention. 该实施例包括一个带有用于源/漏区域的硅化铒504的肖特基N沟道器件和一个带有硅化铂505的肖特基P沟道器件。 This embodiment erbium silicide embodiment comprises a drain region having a source / Schottky N-channel device 504 and a P channel device with a Schottky platinum silicide 505. 铟502和砷503层可被分别用作N沟道和P沟道器件的沟道掺杂。 502 503 layer of indium and arsenic, respectively, may be used as the N channel and P-channel devices doping. 栅极分别由用于N型器件506和P型器件507的磷和硼原位掺杂的多晶硅薄膜制作。 Gates of phosphorus and boron in situ for N-type device 506 and a P-type device 507 doped polysilicon thin film production. 器件通过结合沟道以及衬底掺杂一起工作的场氧化501互相分离,达到器件之间的互相电隔离。 Working device with a doped substrate by combining field oxide 501 and a channel separated from each other, from each other to achieve electrical isolation between devices. 肖特基(或类肖特基)壁垒512,513,522,523存在于相应的金属源/漏504,505和硅衬底509之间的界面,发挥固有阱或晕注入的作用,并且在发挥作用时不带入寄生电容。 Schottky (or Schottky-like) barriers 512,513,522,523 metal present in the corresponding source / drain interface between the silicon substrate 504, 505 and 509, the inherent role of the well or halo implant, and not brought into play when the parasitic capacitance.

在本文件的全部讨论中利用了下述定义:欧姆接触点欧姆接触点是对于半导体衬底的低电阻率的电接触。 Using the following definitions are all discussed in the present document: the ohmic contact point ohmic contact point for a low-resistivity semiconductor substrate in electrical contact. 例如,掺杂欧姆接触点包括和N型掺杂半导体衬底接触的N型重掺杂区域与和P型掺杂半导体衬底接触的P型重掺杂区域。 For example, the ohmic contact points include doped N-type dopant and the N-type semiconductor substrate in contact with the heavily doped region and a P-type doped semiconductor substrate in contact with the P-type heavily doped region. 另外,例如对于半导体衬底的金属欧姆接触点包括和N型掺杂的半导体衬底接触的硅化铒与和P型掺杂的半导体衬底接触的硅化铂。 Further, for example, platinum silicide ohmic metal contact point of the semiconductor substrate comprises a doped semiconductor and an N-type substrate contact erbium silicide contact with the semiconductor substrate and the P-type doped. 这些金属硅化物和其各自的半导体衬底类型进行的接触是欧姆接触点是因为其对于电荷载流子的低肖特基壁垒高度以及因此而得到的低接触电阻。 These metal silicide and contact the respective types of the semiconductor substrate ohmic contact point because of its lower height of the Schottky barrier for the charge carriers and thus low contact resistance is obtained.

阱注入闩锁是CMOS电路独特的问题,由于存在横向的双极型NPN个PNP晶体管而引起这个问题。 Well implant of the latch circuit is a CMOS unique problems due to the presence of a lateral bipolar NPN and PNP transistors cause this problem. 该不希望的寄生双极型晶体管可有放大器的作用,由于使电源短路接地而使电路失效。 The undesired parasitic bipolar transistor amplifier may have a role, since the power supply circuit fails shorted to ground. 为了解决这个问题,常规的CMOS布局通常包括分别用于P型和N型MOSFET器件的N型和P型的阱注入。 To solve this problem, the conventional layout of a CMOS well implants generally comprise respectively a P-type and N-type of P-type and N-type MOSFET devices. N型和P型阱注入分别通过欧姆接触点连接到电源的Vdd和接地。 P-type and N-type well implant and the ground are connected to the power supply Vdd through the ohmic contacts. 作为实例而参考图3,N阱321掺以和半导体衬底330相反极性的杂质,通常掺杂浓度大约大于外延衬底层331掺杂浓度一个数量级。 As an example and with reference to Figure 3, N-well 321 and the semiconductor substrate 330 doped with an impurity of opposite polarity, generally greater than about doping concentration 331 the doping concentration of the epitaxial substrate layer an order of magnitude. N阱321有和沟道和衬底掺杂347相同的极性。 Channel and N-well 321 and has the same polarity as the substrate 347 doping. 阱的制造步骤取决于对闩锁消除的要求以及诸如集成度和独立阈值电压调节的其他因素。 Well it depends on the requirements of the manufacturing steps and the elimination of the latch, and other factors such as the degree of integration independent of the threshold voltage regulation. 设置一个重掺杂的N型欧姆接触点340和N阱321直接接触并连接到电源Vdd,同时衬底330连接到Vss,通常为接地。 Provided a heavily doped N-type ohmic contact 340 and contact points 321 direct the N-well and connected to the power supply Vdd, while the substrate 330 is connected to Vss, typically ground.

沟道长度参考图4,沟道长度(L)401是载流子在半导体衬底415中从源极402到漏极403渡越的距离。 Referring to Figure 4 the channel length, the channel length (L) 401 is a carrier in the semiconductor substrate 415 from the source 402 to drain 403 from the transit. 对于金属源/漏MOSFET器件,该距离由栅绝缘体406的正下方从源极402面对漏极403的界面404到漏极403面对源极402的界面405的距离定义。 The metal source / drain of the MOSFET device, by a distance just below the gate insulator 406 from the source 402 facing the drain electrode 403 to the drain 403 of the interface 404 face the source electrode 402 from the definition of the interface 405.

沟道区域,沟道掺杂和衬底掺杂参考图4,半导体器件中有源区域的电流运载区域通常被称为沟道区域。 A channel region, the channel doping and the doping of the substrate 4, the current carrying region of the active region of the semiconductor device is generally called a channel region. 对于常规的掺杂源漏MOSFET器件,半导体衬底415中的沟道区域位于非常靠近栅绝缘体的地方,并且不基本垂直地向下延伸进半导体衬底415中。 For conventional MOSFET device doped source and drain, a channel region of the semiconductor substrate 415 is located much closer to the gate insulator, and do not extend substantially vertically downwardly into the semiconductor substrate 415. 但是对于诸如肖特基壁垒源漏MOSFET的其他MOSFET器件技术,相当数量的电流可以在栅绝缘体406基本下方的区域中流动。 However, other techniques such as a Schottky barrier MOSFET devices the source and drain of the MOSFET, a considerable amount of current can flow substantially in the region 406 under the gate insulator. 对于本发明的目的,半导体衬底415中的沟道区域在源极402和漏极403的下方垂直延伸到深度d1407上和源极402的底边缘420和漏极403的底边缘421大致对齐的边界416。 For the purposes of the present invention, the channel region 415 of the semiconductor substrate 402 in a vertical pole 403 source and drain electrodes extend to a depth below the bottom edge and d1407 source 402 and drain 420 is substantially aligned with bottom edge 403 421 boundary 416.

沟道掺杂是在半导体衬底415的沟道区域中提供的掺杂,通常用于改进来自MOSFET器件的源极402和漏极403的漏电性能的目的。 Channel doping is provided in the channel region of the semiconductor substrate 415 is doped, typically for purposes of improving the source electrode 402 and drain 403 of the drain from the performance of MOSFET devices. 衬底掺杂是在半导体衬底中沟道区域的底416下方以及源极402和漏极403的底界面420,421下方提供的掺杂。 The substrate is doped in the semiconductor substrate below the bottom of the channel region 416 and source 402 and drain 420, 421 below the bottom of the interface 403 to provide doping.

理解沟道掺杂和衬底掺杂的差别的很重要的。 Channel doping and substrate doping understanding of the difference is very important. 参考图4,图中显示了两个掺杂注入。 Referring to Figure 4, there is shown a two doping implantation. 第一个掺杂注入设置到深度d2430的第一掩模层的暴露区域并具有横向均匀垂直不均匀的浓度剖面。 Setting a first dopant implant to a depth d2430 exposed region of the first mask layer having a uniform lateral cross-section perpendicular to an uneven concentration. 第二掺杂注入设置到深度d3的第二掩模层的暴露区域并具有横向均匀垂直不均匀的浓度剖面。 Setting a second dopant implant to a depth d3 of the second mask layer and the exposed region has a uniform transverse cross section perpendicular to nonuniform density. 在该实例中,第一掺杂注入和第二掺杂注入具有不同的浓度和不同的垂直不均匀剖面。 In this example, a first implanted dopant implantation and the second doped with different concentrations and different vertical non-uniform cross-section. 图4描述的结果MOS器件具有沟道区域的横向均匀垂直不均匀的掺杂浓度剖面,而在沟道区域下方的衬底掺杂剖面有横向和垂直都不均匀的掺杂浓度剖面。 Lateral MOS device described in FIG. 4 results in a channel region having a uniform cross section perpendicular to the uneven doping concentration, and a channel region in the substrate below the lateral and vertical doping profile with a doping concentration profile is streaky.

绝缘体上的半导体(SOI)衬底SOI衬底包括在有约100纳米(nm)到400nm厚度的诸如二氧化硅(SiO2)的埋设的绝缘材料上的有约20nm到100nm厚度的诸如硅的半导体材料,该SOI衬底形成在半导体衬底上。 A semiconductor (SOI) substrate on insulator SOI substrate comprising a semiconductor 20nm to 100nm thickness, such as silicon at about 100 nanometers (nm) to about 400nm on a thickness such as silicon dioxide (SiO2) embedded in an insulating material material, the SOI substrate is formed on the semiconductor substrate.

不限于MOSFET本发明特别适合用于MOSFET半导体器件,但本发明原理的应用不限于该特定的应用。 The present invention is not limited to the MOSFET MOSFET semiconductor device is particularly suitable for, but the application of the principles of the present invention is not limited to this particular application. 其他半导体器件也可以应用本发明的原理。 Other principles of the present invention, the semiconductor device may also be used. 这样,虽然本说明书用“MOSFET”器件的术语进行叙述,该术语应该被广泛地理解为包括用于调节电流具有导电沟道,具有两个或更多电接触点的任何器件。 Thus, while the present specification, the term "MOSFET" devices will be described, this term should be broadly construed to comprise means for adjusting a current having a conducting channel, any device having two or more electrical contacts.

不限于CMOS本发明特别适合于CMOS集成电路的使用和制造,但本发明原理的应用不限于该特定的应用。 The present invention is not limited to CMOS, and particularly suitable for use in manufacturing a CMOS integrated circuit, but the application of the principles of the present invention is not limited to this particular application. 包括互补的或非互补的NMOS和/或PMOS晶体管的其他电路也可以应用本发明的原理。 It includes complementary and non-complementary NMOS / PMOS transistors or other circuitry of the principles of the present invention may also be applied. 这样,虽然本说明书用“CMOS”器件的术语进行叙述,该术语应该被广泛地理解为包括由互相连接的NMOS和/或PMOS晶体管构成的任何器件。 Thus, although the present specification will be described by the term "CMOS" devices, this term should be broadly understood to include any device consisting of NMOS and / or PMOS transistors connected to each other.

沟道长度无限制本发明特别适合用于制造短沟道长度MOSFET的场合,尤其适合用于沟道长度<100nm的范围。 The channel length is not limited to the case of the present invention is particularly suitable for producing short channel length of the MOSFET, the channel length is particularly suitable for the range <100nm in. 但是本发明的原理不限于应用在短沟道长度器件。 The principles of the present invention is not limited to use in a short channel length devices. 本发明的原理有利地适合用于任何尺寸的沟道长度。 The principles of the present invention is advantageously suitable for any size channel length.

掺杂无限制本文的全部讨论都将是利用有关MOSFET器件制造的各种掺杂技术提供的实例。 Examples of doping technique provides unlimited all discussions herein will be related to the use of various doping MOSFET device fabrication. 这些掺杂仅说明了本发明的具体实施例,不应理解为是对本发明原理的范围的限制。 These dopant only illustrate specific embodiments of the present invention and should not be construed as limiting the scope of the principles of the present invention.

但注意,本发明尤其预期对于从由砷,磷,锑,硼,铟,和/或镓组成的集合中选择的杂质原子在本发明原理的范围中的应用。 It is noted that the present invention is in particular intended application for the impurity atoms selected from the group arsenic, phosphorus, antimony, boron, indium and / or gallium in the scope of the principles of the present invention.

电路类型无限制本技术领域熟练的人员将容易地认识到,本发明不限于诸如包括反相器,与非门,或非门,复合门,多路复用器的数字逻辑电路,以及易失的或非易失的存储器的特定的CMOS应用或电路类型的范围。 Unlimited circuit type person skilled in the art will readily appreciate that the present invention is not limited to such as including an inverter, a NAND gate, NOR gate, composite doors, digital logic multiplexer, and a volatile CMOS application specific range or type of circuits or nonvolatile memory. 而且,本发明也不限于数字和或模拟的CMOS应用。 Further, the present invention is not limited to digital or analog and CMOS applications. 应用NMOS和/或PMOS晶体管的组合的这些以及所有其他的电路类型都在本发明的原理的范围之中。 These and all other types of circuit applications in combination NMOS and / or PMOS transistors are in the scope of the principles of the present invention.

不限于源/漏本文的全部讨论都将是参考有关MOSFET器件制造的“源”和“漏”连接提供的实例。 Is not limited to the source / drain all of the discussion herein will be made with reference to the relevant MOSFET device "source" and "drain" are connected to the examples provided. 在本技术领域熟练的人员将认识到,在任何给出的MOSFET构型中,围绕这些接触的各种术语可以进行交换而不失却其普遍性,因此,“源”接触可以和“漏”接触互换而不背离本发明的范围。 Skilled in the art will recognize that in any given MOSFET configuration, the contact around these various terms can be exchanged without lose its universality, therefore, a "source" and the contact may "leak" into contact interchanged without departing from the scope of the invention. 另外,在本技术领域熟练的人员将认识到,虽然很多本发明的优选实施例可以用于制造源漏连接,但是并不要求这就是实际中的情况。 Further, the skilled person in the art will recognize that, although many preferred embodiments of the present invention may be used to manufacture source and drain connections, but this is not required in actual. 为了获得有利的条件,在IC等背景下给出的器件的源漏连接中的一方,双方都可以应用本发明的原理或都不用。 In order to obtain favorable conditions, one of the source and drain connected to the device at a given IC or the like background, both the principles of the present invention may be applied, or not at all.

这样,术语“源”和“漏”应该被理解为包括各种有变化的“漏”和“源”,以及“源或漏”和“源和漏”。 Thus, the term "source" and "drain" should be understood to include various changes in the "drain" and "source" and "source or drain" and "source and drain."

金属无限制本文的全部讨论都将是参考有关MOSFET器件制造的金属提供的实例。 All discussion herein unlimited metals are examples of metals will provide a reference about the MOSFET device fabrication. 本发明不认为有关应用什么类型的金属可影响本发明的原理方面有任何限制。 The present invention does not think about what type of metal can affect the application of the principle aspects of the present invention there is any restriction. 这样,诸如钛,钴等在晶体管级别上通常应用的金属特别得到预期的使用,但也包括众多更加稀有的金属及其他的合金。 Thus, the metal at the transistor level usually applied, such as titanium, cobalt, obtained in particular intended use, but also include many more other rare metals and alloys. 没有任何因素限制本发明使用任何特定的金属或合金。 There is nothing to limit the present invention to any particular metal or alloy. 在本技术领域熟练的人员将认识到,可以使用任何导电的互相连接的材料而不失却在实施本发明的原理中的普遍性。 Skilled in the art will recognize, may be used any electrically conductive material connected to each other not lose generality embodiment of the principles of the present invention.

但是注意,本发明特别预期使用在本发明的原理的范围中的由硅化铂,硅化钯,硅化铱,和/或稀土硅化物组成的集合中的任何硅化物形成的源/漏极。 Note, however, the present invention is particularly contemplated to use the source / drain collection scope of the principles of the present invention by a platinum silicide, palladium silicide, iridium, and / or rare earth silicide of any of silicide formation. 还要注意,在另一个实施例中,硅化物的源/漏可以用金属硅化物的复合层构成,在这样的情况下,可以使用诸如硅化钛或硅化钨的其他示范硅化物。 Note also that in another embodiment, the source / drain silicide composite layer may be constituted by a metal silicide, in this case, it may be used, such as other exemplary silicide, titanium silicide or tungsten silicide.

肖特基无限制本文的全部讨论都将是参考有关IC制造的“肖特基”壁垒和相似接触提供的实例。 Schottky all discussions herein will be unrestricted example of a "Schottky" barriers and similar references provided about the contact IC manufacturing. 本发明不认为有关应用什么类型的肖特基界面可影响本发明的原理方面有任何限制。 The present invention does not think about what type of application Schottky interface can affect the principles of the invention aspect of any restrictions. 这样,本发明特别预期用任何形式的导电材料产生的那些类型的结。 Thus, the present invention especially those of the type of junction conductive materials in any form for the anticipated.

另外,虽然传统的肖特基结是突变的,但本发明特别预期,在一些情况中,可以在硅衬底和实际的肖特基壁垒金属之间利用一个界面层。 Further, while traditional Schottky junction is abrupt, the present invention is particularly contemplated, in some cases, may utilize a barrier interface layer between the metal substrate and the actual Schottky silicon. 这样,本发明特别预期在实施本发明中有用的“类肖特基”结及其等效物。 Thus, the present invention is particularly useful in the contemplated embodiment of the present invention, the "Schottky-like" junctions and their equivalents. 另外,界面层可以包括具有导电的,半导电的,和/或类绝缘的性能的材料。 Further, the interface layer may comprise a conductive, semiconductive, and / or performance-based insulating material.

刻蚀技术无限制本文的全部讨论都将是参考各种IC制造工艺中用于去除氧化层,硅和/或金属的刻蚀技术提供的实例。 Etching unlimited all discussions herein will be with reference to examples oxide layer, silicon and / or metal etching techniques to provide a variety of processes for removal of IC manufacturing. 本发明不限制达到在典型的工艺流程中说明的结果而使用的刻蚀技术的类型。 The present invention is not limited to achieve the results described in the exemplary process flow and the type of etching technique used. 这些技术在技术上是众所周知的。 These techniques are well known in the art.

隔离技术无限制本文的全部讨论都将是参考各种为电隔离各个NMOS和PMOS晶体管而利用的隔离技术提供的实例。 Isolation techniques all discussions herein will be unrestricted with reference to various examples electrically isolate each NMOS and PMOS transistors utilize isolation techniques provided. 本发明不限制达到在典型的工艺流程中说明的结果而使用的隔离技术的类型。 The present invention is not limited in the exemplary process flow to achieve the results described in the type of isolation technology used. 诸如LOCOS,STI以及非凹入氧化窗口的隔离技术在技术上的众所周知的。 Such as LOCOS, STI and non-recessed oxide isolation window is well known in the art.

阱注入无限制本文的全部讨论都将是参考有关IC制造工艺的阱注入提供的实例。 Well implant unrestricted all discussions herein will be with reference to the related IC fabrication process well implant the examples provided. 通常,常规的阱注入通过欧姆接触点分别电连接到PMOS和NMOS晶体管的诸如Vdd和接地的电源。 Typically, a conventional power source such as a well implant Vdd and ground connections to the NMOS and PMOS transistors respectively through the ohmic contact points. 本发明不限制电连接到阱注入的类型,从而使阱注入可以或不可以通过欧姆接触点电连接到诸如Vdd或接地的电源。 The present invention is not limited to a type well implants are electrically connected, so that the injection wells may or may not be connected to a power source such as Vdd or ground via an ohmic electrical contact points. 在本讨论中叙述的任何阱注入都被表征为“电连接到欧姆接触点”或“非电连接到欧姆接触点”。 Any of the well implant is described in the present discussion are characterized as "ohmic contacts electrically connected to the point" or "non-ohmic electrically connected to the contact point." 短语“电连接到欧姆接触点”表示通过欧姆接触点连接到诸如Vdd或接地的电源。 The phrase "electrically connected to the ohmic contact point" indicates the power supply connected to Vdd or ground, such as through the ohmic contacts.

掺杂剖面无限制本文的全部讨论都将是参考沟道区域中和沟道区域下方的半导体衬底中的掺杂剖面提供的实例。 Unlimited doping profile all discussions herein will be with reference to examples provided in the channel region and doping profile of the semiconductor substrate under the channel region. 本发明不限制可以用以影响本发明的原理的沟道掺杂和衬底掺杂剖面的类型。 It does not limit the present invention may be used to affect the principles of the present invention, channel doping type and doping profile of the substrate. 本技术领域熟练的人员将容易地理解,可以用很多掺杂剖面,包括例如横向和垂直都不均匀的沟道/衬底注入;横向均匀和垂直不均匀的沟道/衬底注入;横向和垂直都均匀的沟道/衬底注入。 A person skilled in the art will readily appreciate that many doping profile may be used, including, for example, both lateral and vertical non-uniform channel / substrate injection; uniform lateral and vertical non-uniform channel / substrate injection; horizontal and uniformly vertical channel / substrate injection. 这样的掺杂剖面的这些和任何组合以及任何其他沟道/衬底掺杂剖面都在本发明的原理的范围内。 Such doping are within the scope of the principles of the present invention, these and any section, and any other combination of channel / doping profile in the substrate.

排除掩模工艺无限制本文的全部讨论都将是参考用于在半导体衬底的区域中选择性地形成硅化物的硅化物排除掩模工艺提供的实例。 Unlimited exclusion mask process all discussions herein, reference will be used for selectively forming the silicide region in the semiconductor substrate in the silicide exclusion mask process examples provided. 本发明不限制排除掩模工艺用于金属硅化物以外的金属-半导体化合物。 The present invention is not limited exclusion mask process for a metal silicide than the metal - semiconductor compound. 本技术领域熟练的人员将容易地理解,可以用很多形成肖特基或类肖特基接触的金属-半导体化合物,这些金属-半导体化合物都在本发明的原理的范围中。 A person skilled in the art will readily appreciate, may form a Schottky contact or Schottky-like in many metal - semiconductor compound, the metal - semiconductor compounds are scope of the principles of the present invention.

衬底无限制本文的全部讨论都将是参考肖特基壁垒CMOS器件在其上形成的的半导体衬底提供的实例。 All discussion herein, the substrate will be unrestricted with reference to Examples Schottky barrier CMOS device formed on a semiconductor substrate is provided on its. 本发明不将半导体衬底限制到任何具体的类型。 The present invention is not limited to the semiconductor substrate to any particular type. 本技术领域熟练的人员将容易地理解,很多半导体衬底可以用于肖特基壁垒CMOS,包括硅,应变硅以及绝缘体上的硅。 Person skilled in the art will readily appreciate that many semiconductor substrates may be used for the Schottky barrier CMOS, including silicon, strained silicon, and silicon on insulator. 可以应用的这些衬底材料都在本发明的原理的范围中。 These substrate materials can be applied in the scope of the principles of the present invention.

工艺/方法图6-13显示了制造金属源/漏CMOS器件的一个示范工艺。 Process / method of FIG. 6-13 show an exemplary process for producing a metal source / drain of the CMOS device. 虽然该工艺对于本发明的广泛的原理是示范性的,但其对于在本技术领域熟练的人员理解本发明的基本概念具有指导的作用。 While the process for the broad principle of the invention is exemplary, but for the person skilled in the art to understand the basic concept of the present invention has a guiding effect. 该示范的工艺流程可叙述如下: The exemplary process may be described as follows:

参考图6,工艺开始于重掺杂的硅衬底602和轻掺杂的外延层601,该外延层具有互相电隔离晶体管的作用,生长薄掩蔽氧化604(约200)用作注入掩模。 Referring to FIG 6, the process begins with a heavily doped silicon substrate 602 and the lightly doped epitaxial layer 601, the epitaxial layer is electrically isolated from each other has an effect transistors, growing a thin screen oxide 604 (about 200 Å) as an implantation mask . 在另一个实施例中,硅衬底601被加以应力。 Embodiment, the silicon substrate 601 is to be stress another embodiment. 和肖特基壁垒MOSFET器件组合的应变硅衬底601的使用导致电源和速度性能上的附加的改进,如在申请于2003年1月15日的共同待批的美国专利申请10/342590号中的解释。 And a strained silicon substrate 601 Schottky barrier MOSFET device combinations result in additional improvements in speed and power performance, as described in co-pending application on January 15, 2003 U.S. Patent Application No. 10/342590 explanation of. 在另一个实施例中,衬底是SOI。 In another embodiment, the substrate is a SOI. 生长掩蔽氧化604以后形成一个阻挡图形层605,使PMOS器件的有源区域606暴露,掺杂剂砷607由离子注入通过掩蔽氧化注入到硅中预先确定的深度d1 608(约1000)。 After the screen oxide 604 growth of the active region 606 is formed a resist pattern layer 605 of the PMOS device is exposed, by a dopant ion implantation 607 arsenic implanted to a depth d1 608 (about 1000 Å) by a predetermined silicon oxide masking.

参考图7,阻挡图形层605被剥离,晶片被再次形成图形,使N型器件的有源区域701暴露。 Referring to Figure 7, the barrier layer pattern 605 is peeled off, the wafer is again patterned, the N-type active device region 701 is exposed. 用于N型器件有源区域701的掺杂剂铟702由离子注入通过掩蔽氧化604注入到硅中预先确定的深度d2 703(例如1000)。 702 indium dopant for N-type active device region 701 is implanted into the silicon by the ion-implanted in a predetermined depth d2 703 (e.g. 1000 Å) by masking oxide 604.

参考图8,通过诸如本地硅氧化(LOCOS)的隔离工艺隔离P型和N型器件的有源区域。 Active area, such as by local oxidation of silicon (LOCOS) isolation process isolation P-type and N-type device with reference to FIG. 例如,在氢氟酸中去除掩蔽氧化604,生长一层薄衬垫氧化801(例如约150)。 For example, the masking oxide is removed in hydrofluoric acid 604, growing a thin layer of pad oxide 801 (e.g., about 150 Å). 然后在晶片上淀积一层Si3N4802(约3000)。 And then depositing a layer Si3N4802 (about 3000 ANGSTROM) on the wafer. 用光刻技术限定场氧化区域然后晶片被氧化。 Photolithography defines a field oxide region and the wafer is oxidized. 通常,场氧化区域803有2500的厚度并被部分凹入外延的半导体衬底601。 Typically, the thickness of field oxide region 803 and has a concave portion 2500 epitaxial semiconductor substrate 601. 然后剥离衬垫氧化801和氮化物薄膜802。 Then the release pad oxide 801 and nitride film 802. 在另一个示范实施例中,器件有源区域606,701由简单的氧化工艺隔离,如申请于2002年5月16日的美国临时专利申请60/381162号中解释的一样。 Another exemplary embodiment as explained in Example No. 60/381162, the device active regions 606, 701, isolated by a simple oxidation process, such as in applications on May 16, 2002 U.S. Provisional Patent Application. 例如,掩蔽氧化604在氢氟酸中去除,然后生长约100厚度的隔离氧化。 For example, masking oxide 604 is removed in hydrofluoric acid, then grown isolation oxide thickness of about 100. 然后通过标准的光刻技术形成有源区域606,701和场氧化区域803的图形。 Active regions 606, 701, then the graphics and the field oxide region 803 formed by standard photolithographic techniques. 重要的是应理解该简单的氧化工艺产生的场氧化803凹入半导体衬底601的深度基本上低于源漏结1102,1103,1202,1203的深度(译注:此句是根据译者的理解意译,如直译为“场氧化不凹入半导体衬底601基本低于源漏结1102,1103,1202,1203深度那样的深度”)。 Depth is important to understanding this simple oxidation process produces recessed field oxide 803 of the semiconductor substrate 601 is substantially lower than the source-drain junction depth 1102,1103,1202,1203 (Annotation: The sentence is understood translator translation as literally translated as "recessed field oxide semiconductor substrate 601 is not substantially lower than the source-drain junction depth as the depth 1102,1103,1202,1203").

参考图9,生长薄栅氧化901(例如约10-40)。 Referring to FIG 9, growing a thin gate oxide 901 (e.g., about 10-40). 在另一个实施例中,具有高介电常数(“高K”)的材料被用作绝缘层901。 In another embodiment, the material having a high dielectric constant ( "high K") is used as the insulating layer 901. 高K材料的实例是其介电常数高于二氧化硅的那些材料,包括例如诸如TiO2的金属氧化物的材料。 Examples of high K materials are those materials having a dielectric constant higher than silicon dioxide, for example, a material comprising a metal oxide such as TiO2. 和肖特基壁垒器件结合使用的高K栅绝缘层导致在驱动电流方面的附加的改进,如在申请于2002年8月9日的美国专利申请10/215447系列号中的解释一样。 Schottky barrier devices and the use in conjunction with high-K gate insulating layer results in an additional improvement in terms of the driving current, as explained Application No. 10/215447 filed on in the series on August 9, 2002 U.S. patent.

在一个实施例中,淀积一个约2000厚度的多晶硅层。 In one embodiment, a polysilicon layer is deposited to a thickness of about 2000. 应用光刻技术(第一掩模)掩蔽PMOS有源区域,暴露出的NMOS有源区域中的多晶硅被重掺杂N型掺杂剂,诸如用离子注入掺入磷。 Lithography (first mask) masking the PMOS active region, the active region exposed in the NMOS polysilicon is heavily doped N-type dopant, such as phosphorus incorporated by ion implantation. 然后,再次用光刻技术(第二掩模)掩蔽NMOS有源区域,暴露出的PMOS有源区域中的多晶硅被重掺杂P型掺杂剂,诸如用离子注入掺入硼。 Then, again masked photolithography (second mask) the NMOS active region, the PMOS active region exposed polysilicon is heavily doped P-type dopant, such as boron by ion implantation incorporated. 衬底进行退火,使注入到沟道区域和栅极的掺杂剂被电激活和再分布。 Annealing the substrate, implanted into the channel region and the gate electrode is electrically activated and dopant redistribution. 用光刻技术(第三掩模)和对于二氧化硅高度选择性的硅刻蚀形成N型902和P型903的栅极图形,如图9的工艺步骤900所示。 FIG photolithography (third mask) high selectivity to silicon dioxide and silicon etching to form the P-type and N-type gate electrode 902 of the pattern 903, the process step 900 of FIG. 9.

在另一个实施例中,栅极用两个掩模的双原位掺杂的多晶工艺形成,如申请于2002年5月16日的美国临时专利申请60/381240号所解释的一样。 Embodiment, the gate mask with two double-situ doped polycrystalline process for forming, as filed on May 16, 2002, U.S. Provisional Patent Application No. 60/381240 as explained in another embodiment. 在该示范实施例中,淀积具有约500厚度的原位掺杂N型多晶硅层。 In the exemplary embodiment, in situ deposition of a thickness of about 500 doped N-type polysilicon layer. 用光刻技术(第一掩模)掩蔽NMOS有源区域,暴露的PMOS有源区域被部分刻蚀。 (First masking) NMOS active region masked by photolithography, the exposed PMOS active region is partially etched. 然后用对于下面的栅氧化901高度选择性的第二刻蚀去除余留的PMOS有源区域中的N型掺杂的多晶硅。 Then highly selective to the underlying gate oxide 901 of a second PMOS active region is removed by etching the remaining N-type doped polysilicon. 接着,淀积具有约1500厚度的原位掺杂的P型多晶硅层。 Next, in situ deposition has a thickness of about 1500 doped P-type polysilicon layer. 用光刻技术(第二掩模)和对于二氧化硅高度选择性的硅刻蚀形成N型902和P型903的栅极图形,如图9的工艺步骤900所示。 Photolithography (second mask) 902 and the N-type and P-type gate pattern 903 of silicon to silicon dioxide highly selective etching process step 900 as shown in FIG. 9. 结果的原位掺杂的N型器件的多晶硅栅902的厚度大于P型器件的多晶硅栅903。 The thickness of the polysilicon gate results situ doped N-type device 902 is larger than the P-type polysilicon gate devices 903. 衬底被选择性退火以使N型902和P型903栅极的掺杂剂都均匀分布。 The substrate is annealed to selectively N-type gate electrode 902 and a P-type dopant 903 are uniformly distributed.

参考图10,然后在硅栅极和水平表面1002和侧壁1003上热生长薄氧化(约100)。 Referring to FIG 10, on the silicon gate and the horizontal surface 1002 and sidewalls 1003 and a thin oxide thermally grown (about 100Å). 然后用各向异性刻蚀去除水平表面1002上的氧化层(因此而暴露硅1004),同时保留在垂直表面上的侧壁氧化1001。 Then removing the oxide layer on the horizontal surfaces with an anisotropic etching 1002 (and thus expose the silicon 1004), while retaining the sidewall oxide on the vertical surface 1001. 用这样的方法形成薄侧壁隔离氧化1001。 Forming a thin oxide sidewall spacer 1001 in such a way. 如图10的工艺步骤1000所示。 10 is shown in process step 1000 shown in FIG. 在另一个示范实施例中,薄侧壁隔离绝缘体1001可以包括氧化-氮化物层或氮化物层。 In another exemplary embodiment, a thin sidewall spacer insulator 1001 may include oxide - nitride layer or a nitride layer. 氧化-氮化物层是包括氧和氮的材料。 Oxide - nitride layer is a material comprising oxygen and nitrogen.

参考图11,下面的步骤包括形成金属硅化物的源漏极。 Referring to FIG 11, the following steps include forming source and drain metal silicide. 在一个实施例中,晶片用适当的掩蔽层1110通过光刻技术形成图形,使N型器件1101的P型有源区域暴露。 In one embodiment, the wafer layer 1110 is patterned by a photolithographic technique with a suitable mask, the P-type active region 1101 of the N-type exposure device. 在一个示范实施例中,掩蔽层1110是硅化物排除掩模氧化层。 In one exemplary embodiment, the masking layer 1110 is a silicide exclusion mask oxide layer. 淀积硅化物排除掩模氧化层。 Depositing a silicide exclusion mask oxide layer. 然后淀积光刻胶,接着形成光刻胶的图形,通过应用例如缓冲氧化刻蚀的方法刻蚀硅化物排除掩模氧化层1110以及剥离光刻胶,因此N型有源区域被硅化物排除掩模氧化层覆盖,从而受到保护免于形成硅化物。 The photoresist is then deposited, a photoresist pattern is then formed by applying a buffer oxide etch etching method, for example, silicide exclusion mask oxide and stripping the photoresist layer 1110, the N-type active region and therefore the silicide exclusion a mask oxide layer covering, so is protected from formation of a silicide. 重要的是对于氧化掩模刻蚀应用高选择性的湿法刻蚀,使侧壁隔离氧化1001基本不受影响。 Important for the application of high oxidation mask etch selective wet etching, so that sidewall oxide spacer 1001 is substantially unaffected. 诸如缓冲氧化物刻蚀的湿法刻蚀应该最好以基本大于刻蚀热生长侧壁氧化物或其他可用于提供栅侧壁绝缘物隔离的示范材料的刻蚀速率的速率刻蚀所淀积的氧化物。 Buffered oxide etch such as a wet etching should preferably be substantially greater than the etch thermally grown sidewall oxide etch rate or other exemplary materials may be used to provide the gate sidewall spacer insulator etching rate of the deposited oxides. 常规器件的栅侧壁绝缘体大大厚于肖特基壁垒MOS器件的栅侧壁绝缘体。 The gate sidewall insulator conventional device significantly thicker than the Schottky barrier gate sidewall insulator of the MOS device. 这使常规的MOS侧壁在湿法化学刻蚀过程中少受损坏,使用常规的CMOS工艺的硅化物排除掩模的集成步骤更简单易行。 This makes the conventional MOS sidewalls wet chemical etching process less damaged, using a conventional CMOS process integration steps silicide exclusion mask is more simple.

淀积用于N型器件硅化物的适当的金属(例如铒),在晶片的全部表面上提供一个金属层(约200)。 Depositing a suitable metal silicide N type elements (e.g. erbium), a metal layer (about 200 Å) on the entire surface of the wafer. 然后该晶片在规定的温度下退火规定的时间(例如在450℃下退火30分钟),这样,在金属和硅直接接触的所有地方都发生化学反应,在源极1102,漏极1103和栅极1104将金属转化为金属硅化物。 The wafer is then defined at a predetermined temperature annealing times (e.g., at 450 ℃ annealing at 30 minutes), so that all parts of silicon metal and in direct contact with the chemical reactions occur, the source electrode 1102, the drain electrode 1103 and the gate 1104 metal into metal silicide. 重要的是,所暴露的部分刻蚀的侧壁隔离1001在硅化物形成的退火中对栅极进行全面的保护。 Importantly, the exposed sidewall portions of the isolation etching 1001 pairs of gates comprehensive protection of silicide formation anneal. 然后用湿法化学刻蚀(例如对于铒用HNO3或H2SO4)去除未反应的金属,同时留下未接触的金属硅化物,如图11的工艺步骤1100中所示。 Followed by wet chemical etching (for example, doped with HNO3 or H2SO4) removing unreacted metal while leaving the metal silicide is not in contact, as shown in process step 1100 in FIG. 11.

在另一个实施例中,淀积用于N型器件硅化物的适当的金属(例如铒,约150),接着淀积第二个适当的金属(例如钛,约50),导致一个具有两种金属层的金属层。 In another embodiment, suitable for depositing a metal silicide N-type device (e.g., erbium, about 150 Å), is deposited followed by a second suitable metal (e.g. titanium, about 50Å), having a lead metal layers of two metal layers. 然后该晶片在规定的温度下退火规定的时间(例如在450℃下退火30分钟),这样,在金属和硅直接接触的所有地方都发生化学反应,在源极1102,漏极1103和栅极1104将第一和第二金属都转化为金属硅化物。 The wafer is then defined at a predetermined temperature annealing times (e.g., at 450 ℃ annealing at 30 minutes), so that all parts of silicon metal and in direct contact with the chemical reactions occur, the source electrode 1102, the drain electrode 1103 and the gate 1104 the first and second metal is converted into metal silicide. 重要的是,所暴露的部分刻蚀的侧壁隔离1001在硅化物形成的退火中对栅极进行全面的保护。 Importantly, the exposed sidewall portions of the isolation etching 1001 pairs of gates comprehensive protection of silicide formation anneal. 然后用湿法化学刻蚀(Sulfuric Peroxide)去除未反应的金属,同时留下未接触的金属硅化物。 Followed by wet chemical etching (Sulfuric Peroxide) removing unreacted metal while leaving the metal silicide untouched.

重要的是为了保留初始的淀积金属层次序而选择第二金属(例如钛)。 Important in order to preserve the initial deposition of the second metal layer sequence selected metal (e.g., titanium). 例如,在前述示范工艺中,硅化铒的底表面和半导体衬底接触,硅化铒的顶表面和硅化钛接触。 For example, in the foregoing exemplary process, the bottom surface of the semiconductor substrate, and a contact erbium silicide, erbium silicide, and the top surface of titanium silicide contacts. 第二硅化物通过提供对以后的金属化工艺步骤提供更有力的刻蚀阻挡提供经改进的制造能力,减小源漏极的净电阻率,并在室温的氧化环境中更稳定,如申请于2002年5月16日的美国临时专利申请60/381238系列号中解释的一样。 A second silicide blocking by providing a subsequent metallization process to provide more effective etching steps to provide improved manufacturing capabilities, reducing the net resistance of the source and drain, and more stable in an oxidizing environment at room temperature, as filed on May 16, 2002 of US provisional Patent application No. 60/381238 series of the same interpretation.

因为和常规的掺杂源漏制造工艺要求相对高的衬底温度(例如大于1000℃)相比,源漏硅化物制造步骤要求低得多的衬底温度(例如小于700℃),硅基CMOS中的其他非标准材料,诸如高K电介质,金属栅或应变硅等能更容易地集成到本发明的CMOS制造工艺中。 Because the doped source and drain conventional manufacturing process requires a relatively high substrate temperature (e.g., greater than 1000 ℃) compared to the source and drain suicide substrate manufacturing steps require much lower temperatures (e.g. less than 700 deg.] C), a silicon CMOS the other non-standard materials, such as high-K dielectric, metal or strained silicon gate can be more easily integrated into a CMOS fabrication process of the present invention. 如申请于2002年5月16日的美国临时专利申请60/381320号中解释的一样。 If the application is on May 16, 2002 of US Provisional Patent Application No. 60/381320 interpretation of the same.

参考图12,晶片再次用适当的掩蔽层通过光刻技术形成图形,暴露P型器件1201的N型有源区域。 Referring to Figure 12, a wafer pattern is formed again by a photolithographic technique with a suitable masking layer, the exposed N-type active region 1201 of the P-type device. 在一个示范实施例中,掩蔽层是硅化物排除掩模氧化层。 In one exemplary embodiment, the masking layer is a silicide exclusion mask oxide layer. 淀积硅化物排除掩模氧化。 Silicide exclusion mask oxide is deposited. 接着淀积光刻胶,然后形成光刻胶的图形,用例如缓冲氧化物刻蚀刻蚀硅化物排除掩模氧化层,剥离光刻胶,使P型有源区域和N型器件1101被硅化物排除掩模氧化覆盖从而受到保护免于形成硅化物。 Then depositing a photoresist, a photoresist pattern is then formed, for example, a buffered oxide etch etch the silicide exclusion mask oxide layer, stripping the photoresist, the P-type and N-type active region 1101 is a silicide device exclusion mask oxide coating is protected from such silicide formation. 重要的是对于氧化掩模刻蚀应用高选择性的湿法刻蚀,使P型器件1201的侧壁隔离氧化1001基本不受影响。 Important for the application of high oxidation mask etch selective wet etching, the side wall 1201 of the P-type device isolation oxide 1001 is substantially unaffected. 诸如缓冲氧化物刻蚀的湿法刻蚀应该最好以基本大于刻蚀热生长侧壁氧化物或其他可用于提供栅侧壁绝缘物隔离的示范材料的刻蚀速率的速率刻蚀所淀积的氧化物。 Buffered oxide etch such as a wet etching should preferably be substantially greater than the etch thermally grown sidewall oxide etch rate or other exemplary materials may be used to provide the gate sidewall spacer insulator etching rate of the deposited oxides.

淀积用于P型器件硅化物的适当的金属(例如铂),在晶片的全部表面上提供一个金属层(约200)。 Depositing a P-type device suitable metal silicide (e.g., platinum), a metal layer (about 200 Å) on the entire surface of the wafer. 然后该晶片在规定的温度下退火规定的时间(例如在400℃下退火45分钟),这样,在金属和硅直接接触的所有地方都发生化学反应,在漏极1202,源极1203和栅极1204将金属转化为金属硅化物。 The wafer is then defined at a predetermined temperature annealing times (e.g., annealing at 400 ℃ 45 minutes), so that all parts of silicon metal and in direct contact with the chemical reactions occur, the drain 1202, the source electrode 1203 and the gate 1204 metal into metal silicide. 重要的是,所暴露的部分刻蚀的侧壁隔离1001在硅化物形成的退火中对栅极进行全面的保护。 Importantly, the exposed sidewall portions of the isolation etching 1001 pairs of gates comprehensive protection of silicide formation anneal. 然后用湿法化学刻蚀(例如对于铂用王水)去除未反应的金属,同时留下未接触的金属硅化物,如图12的工艺步骤1200中所示。 Followed by wet chemical etching (for example, platinum with aqua regia) removing unreacted metal while leaving the metal silicide is not in contact, as shown in process step 1200 in FIG. 12. 参考工艺步骤1100(如图11所示)和工艺步骤1200(如图12所示)叙述的工艺包括用于肖特基壁垒CMOS的双硅化物排除掩模工艺的示范实施例。 Reference Process step 1100 (FIG. 11) and process step 1200 (FIG. 12) described a process comprising a Schottky barrier CMOS exemplary dual silicide exclusion mask process embodiment.

双硅化物可由只用一个硅化物排除掩模的另一个示范实施例提供。 Double the silicide may be only a silicide exclusion mask provides another exemplary embodiment. 例如,淀积用于N型器件的适当的金属,然后用光刻技术提供硅化物排除掩模层,从而暴露P型器件的N型有源区域。 For example, a suitable metal is deposited N-type device, and then provides the silicide exclusion mask layer by photolithography, thereby exposing the N-type active region of the P type device. 淀积用于P型器件的第二个适当的金属。 Depositing a second metal suitable for the P-type device. 然后该晶片在规定的温度下退火规定的时间,这样,在第一金属和硅直接接触的所有地方都发生化学反应,在源极1102,漏极1103和栅极1104将金属转化为金属硅化物。 The wafer is then defined at a predetermined temperature annealing time, so that all parts of the first metal and silicon are in direct contact with a chemical reaction occurs in the source 1102, drain 1103 and gate 1104 will be converted to a metal silicide metal . 另外,在退火过程中,第二金属通过第一金属扩散,从而在源极1202,漏极1203和栅极1204形成金属硅化物。 In addition, during annealing, the second metal diffusion by the first metal, so that the source 1202, drain 1203 and gate 1204 to form a metal silicide.

如图13说明的工艺步骤1300所示,肖特基壁垒NMOS1101和PMOS1201被全面和方便地进行电接触。 13 illustrates the process steps as shown, and the Schottky barriers NMOS1101 been fully and conveniently PMOS1201 electrical contact 1300. 为了形成如图13所示的CMOS反相器电路1300,添加导电线连接栅极902和903以形成CMOS电路1300的输入Vg1301,连接漏极1103和1202以形成CMOS电路1300的输出Vo1302。 In order to form a CMOS inverter circuit 1300 shown in Figure 13, addition of the conductive wires 902 and 903 connecting the gate to form an input Vg1301 CMOS circuit 1300, and an output connected to the drain 1103 Vo1302 1202 to 1300 form the CMOS circuit. 还添加导电线以将NMOS源极1102连接到Vss1303,将PMOS源极1202连接到电源Vdd1304。 Added to the electrically conductive wire 1102 is connected to the NMOS source Vss1303, the electrode 1202 is connected to the power source of the PMOS Vdd1304.

概括地说,该示范的肖特基壁垒CMOS制造工艺需要全部8个掩蔽步骤:掩模号 掩模功能1 PMOS砷注入2 NMOS铟注入 In summary, the exemplary Schottky barrier CMOS fabrication processes require all eight masking step: a mask function mask No. 1 PMOS indium arsenic implant 2 NMOS injection

3 有源4 NMOS磷注入5 PMOS硼注入6 栅7 铂硅化物排除8 铒硅化物排除用双掩模双原位掺杂多晶工艺形成栅极代替8个掩模步骤中的一个步骤。 3 4 NMOS active phosphorus implanted boron implantation 5 PMOS gate 6 7 8 platinum silicide exclusion erbium doped polycrystalline silicide exclusion mask process by double in situ formation of a double gate 8 in place of a step of masking steps. 本技术领域熟练的人员将理解的是,上述工艺仅是实现金属源/漏肖特基器件的一种方法,还存在很多变型和替代。 A person skilled in the art will understand that the above process is only one way to achieve metal source / drain Schottky devices, there are many variations and alternatives.

器件/系统图13显示了作为由两个最后的互补MOSFET结构示范的本发明的一个示范实施例的剖面图(1300)。 Device / system of FIG. 13 shows a cross section (1300) as a model of the present invention consists of the last two complementary MOSFET structure exemplary embodiment. 该实施例包括一个用硅化铒用作源/漏区域1102,1103制造的NMOS器件1101和用硅化铂用作源/漏区域1202,1203制造的PMOS器件1201。 This embodiment comprises a silicide, erbium is used as a source / drain region of the NMOS devices 1102, 1103 and 1101 manufactured by platinum silicide PMOS devices as the source / drain regions 1202, 1203 1201 manufactured. 沿相应的金属源/漏1102,1103,1202,1203和硅衬底601的界面存在的肖特基(或类肖特基)壁垒(1312,1313,1322,1323)发挥固有阱或晕注入的作用并且在发挥作用时不附加寄生电容。 Along respective metal source / drain and the presence of the silicon substrate 1102,1103,1202,1203 Schottky interface 601 (or Schottky-like) barriers (1312,1313,1322,1323) exhibit an inherent injection well or halo effects and without additional parasitic capacitance during play. 其同时也消除了对于浅注入的源/漏延伸的需要,因为金属源/漏本身就有浅和高导电的自然性能。 It also eliminates the need for shallow implanted source / drain extension, because the metal source / drain and shallow itself highly conductive nature performance. 其分别对于PMOS和NMOS器件还进一步消除了通过欧姆接触点电接触到电源Vdd和地的阱注入的需要。 Respectively PMOS and NMOS devices for further eliminating the need for ohmic contact with the contact point through the electrical power supply Vdd and ground well implants of. 因此通过同时取消晕/阱注入,源漏延伸注入以及通过欧姆接触点电接触的阱注入实现了明显减小制造的复杂度。 Thus canceled by simultaneous Halo / well implants, source and drain extension implants and well implant through the ohmic contact point of the electrical contacts to achieve a significant reduction in manufacturing complexity. 这些也是超过常规结构的MOS器件的主要优点。 These are major advantages over a conventional MOS device structure.

金属硅化物源/漏延伸可用于NMOS和PMOS源漏区域(1102,1103,1202,1203)以进一步加强肖特基壁垒CMOS器件的性能,如申请于2002年5月16日的美国临时专利申请60/381321中解释的一样。 Metal silicide source / drain extension may be used for NMOS and PMOS source and drain regions (1102,1103,1202,1203) to further enhance the performance of the Schottky barrier CMOS devices, such as U.S. Provisional Patent Application filed on May 16, 2002 of 60/381321 in the same interpretation.

由于肖特基壁垒在原子层面上的陡峭的性能及其非常协调和重复的数量,常规的MOS器件特有的统计上存在的变化的两个来源被实际上消除。 Schottky barrier source number two steep performance on an atomic level and well-coordinated and repetitive, the presence of specific statistical variation a conventional MOS device is practically eliminated. 在常规器件中通过离子注入的杂质引入的随机的统计性质在注入杂质的位置和数量上都产生明显的变化。 Random statistical properties introduced by ion implantation of impurities in the conventional device are significant changes in the position and number of implanted impurities. 对于晕/阱和源/漏杂质都存在这个问题。 For Halo / well and the source / drain impurities have this problem. 其结果是诸如沟道长度(L),驱动电流以及漏电流的器件参数中一定数量的随机变化。 As a result, such a channel length (L), randomly varying the drive current and device parameters leakage current of a certain number. 这些变化使电路设计更困难,由于不符合性能规格的IC造成的产量下降也引起了制造成本的问题。 These changes make circuit design more difficult, because the production does not meet the performance specifications of the IC due to decline also caused problems in manufacturing costs. 由于每个器件中硅的更小的有效体积而减小沟道长度,因此使统计变化的偏离平顺的平均作用减小,这个问题就变得更加严重。 The average deviation from smooth action due to the smaller effective volume of each device in the silicon channel length is reduced, so that the statistical variation is reduced, the problem becomes more severe.

由于金属源/漏(替代常规的掺杂源/漏)具有对于硅衬底601的自然的,非常协调的和原子层面上的陡峭的肖特基壁垒(1312,1313,1322,1323),壁垒的位置和数量独立于沟道长度,以及由于该壁垒实质上充当了晕/阱注入的角色(使这些注入不必要),在源/漏和晕/阱注入期间由于原子的随机位移产生的统计变化被基本消除。 Since the metal source / drain (replace conventional doped source / drain) having a steep Schottky barrier (1312,1313,1322,1323) on the silicon substrate 601 for a natural, well-coordinated and the atomic level, the barriers statistics and the number of independent position in the channel length, and since this is essentially acted as barriers halo / well implantation (implantation of these unnecessary), implanted in the source / drain halo and / well during the displacement of atoms due to the random generated change is substantially eliminated. 当沟道长度减小时,这个结论仍保持正确甚至更加正确。 When the channel length is reduced, this conclusion remains correct even more correct.

金属源/漏MOS结构的另一个优点是无条件地消除了寄生的双极型增益。 Another advantage of the metal source / drain of the MOS structure is unconditionally eliminating parasitic bipolar gain. 该寄生的双极型增益是对源/漏和衬底区域使用相反的掺杂类型的直接结果并能导致闩锁和其他有害效应。 The parasitic bipolar gain is a direct result of the opposite doping type to the source / drain regions and the substrate and can cause latch-up and other harmful effects. 当源漏极由金属构成从而提供对于半导体衬底的肖特基壁垒接触时,消除了该双极型增益。 When the source and drain electrodes made of a metal for the Schottky barrier to provide a semiconductor substrate contact, eliminating the bipolar gain. 这使金属源/漏结构(除了别的方面以外)对于高辐射环境尤其理想。 This allows the metal source / drain structure (in addition to other ways), in particular for high radiation environments over. 另外,没有寄生的双极型增益分别对于PMOS和NMOS器件还进一步消除了通过欧姆接触点电接触到电源Vdd和地的阱注入的需要,导致减少工艺步骤,降低成本和提高产量的结果。 Further, no parasitic bipolar gain to the PMOS and NMOS devices respectively further eliminate the need for access to the well through the ohmic contact point of the electrical power supply Vdd and the ground of the injection, resulting in reduced processing steps, reduce costs and improve yield results. 由于肖特基壁垒CMOS不受寄生的双极型作用的影响,因此其在功率MOSFET器件的领域也能找到应用,如上述申请于2002年5月16日的美国临时专利申请60/381237号中揭示的一样。 Due to the role of the bipolar CMOS Schottky barriers are not parasitic, so the application can also be found, such as the above application in the field of power MOSFET devices in US Provisional Patent May 16, 2002 Application No. 60/381237 as revealed.

铟702和砷607分别用作NMOS和PMOS器件的沟道和衬底的掺杂剂。 702 607 indium and arsenic are used as dopant and the substrate channel NMOS and PMOS devices. 由于这些原子穿过硅晶格时相对低的扩散速率(相对于沟道和衬底的另两个可能的候选掺杂剂)因此而使用该两种原子。 Through the silicon lattice due to a relatively low diffusion rate of the atoms (with respect to the other two possible candidate dopants channel and the substrate) so that two kinds of atoms used. 这样在器件的制造中允许有更大的热聚集,因此在完成的产品的性能中降低统计变化。 This allows greater heat accumulated in producing the device, thereby reducing the statistical variations in the performance of the finished product. 重要的是应理解,具有沟道和衬底掺杂剂607,702的区域并不电连接到欧姆接触点。 It is important to be understood that the channel region and the substrate having a dopant 607,702 are not electrically connected to the ohmic contact.

对于P型器件和N型器件分别用掺硼和掺磷的多晶硅薄膜制造栅极902,903。 Producing a polysilicon thin film gate for a P-type and N-type devices are devices using boron-doped and phosphorus-doped 902, 903. 在该实例中,因为其大的固溶度(和砷与铟相比)而使用硼和磷。 In this example, because of its large solid solubility (indium and arsenic as compared with) the use of boron and phosphorus.

栅极宽度可以小于100nm(相应于沟道长度L),因为其处于肖特基壁垒的结构超过常规结构的优点变得更加明显的状况下。 May be less than 100 nm or the width of the gate (corresponding to a channel length L), as it is in Schottky barrier structure advantages over conventional structure becomes more pronounced under condition. 这些优点包括由于不需要阱注入而简化工艺,以及在完成的产品中减小了对于产量的影响,减小了电容以及统计变化。 These advantages include simplified because no well implantation process, and reducing the impact on the yield of the finished product, as well as the capacitance is reduced statistical variation.

器件由诸如热生长的氧化层803(称为场氧化)的绝缘层互相分离,该绝缘层与沟道和衬底掺杂相结合工作以将器件互相隔离。 Insulating layers of the device, such as an oxide layer 803 is thermally grown (referred to as field oxide) separated from each other, the insulating layer and the substrate doping and the channel combining device operates to isolate from each other. 该场氧化803可以由诸如LOCOS的常规的工艺提供,产生部分凹入的场氧化803,或由诸如简单的薄的非凹入的或浅氧化的较简单的器件隔离工艺提供。 The field oxide 803 may be provided by the conventional processes such as LOCOS, producing field oxide recessed portion 803, or by simpler means such as a simple isolation process of a thin non-oxidized or shallow concave. 在这种场合,有时被称为氧化窗口的浅场氧化并不延伸入衬底到基本低于源漏结的深度。 In this case, light is sometimes called oxidation field oxide window does not extend into the substrate substantially less than the depth of the source-drain junction. 浅场氧化窗口的应用导致了另外的经减少的工艺步骤,更低的成本和更高的产量。 Application of shallow window field oxide leads to reduction through additional process steps, lower cost and higher yields.

参考图14,场氧化1403是基本不凹入外延半导体衬底601的简单的薄氧化。 Referring to Figure 14, field oxide 1403 is substantially concave simple thin oxide semiconductor epitaxial substrate 601. 在该示范实施例中,不电接触欧姆接触点的任选的阱注入1405,1406可被用于分别隔离PMOS和NMOS器件。 In the exemplary embodiment, the electrical contact is not ohmic contact point Optionally well implant 1405, 1406 may be used to isolate PMOS and NMOS devices, respectively. 重要的是注意,对于反相器电路中的PMOS或NMOS器件不需要电连接到欧姆接触点的阱注入。 Is important to note that no electrical inverter circuit for the PMOS or NMOS device connected to the ohmic contact point of the injection well. 如果用任选的阱注入,在图6显示的工艺步骤600中将设置额外的砷注入的步骤导致一个砷阱1405,以及在图7显示的工艺步骤700中将设置额外的铟注入的步骤导致一个铟阱1406。 If the optional injection well, the step of providing an additional arsenic implant in process step 600 shown in Figure 6 will result in a 1405 well arsenic, indium and the additional step of providing injection in step 700 in the process shown in FIG 7 leads indium a trap 1406. 阱注入1405,1406不需要电接触到欧姆接触点。 Well implant 1405, 1406, no electrical contact with the ohmic contact.

图15显示了本发明的一个优选实施例的俯视图,由肖特基壁垒CMOS反相器电路及其典型的操作和偏置条件作出示范。 Figure 15 shows a top view of a preferred embodiment of the present invention, CMOS inverter circuit and typical operating conditions and bias Schottky barriers made exemplary. PMOS器件1502的源1501连接到电源正极Vdd1503,而NMOS器件1505的源1504连接到Vss,通常为地。 15011502 source PMOS devices connected to the power cathode Vdd1503, while the NMOS device is connected to the source 15,041,505 Vss, typically ground. 栅接触点1507和1508共用一个公共的输入电连接Vg1509,漏接触点1510和1511共用一个公共的输出电连接Vo1512。 A gate contact 1507 and 1508 share a common input connected Vg1509, drain contact 1510 and 1511 share a common output electrically connected Vo1512. 当用简单的薄氧化器件隔离时,PMOS器件1502和NMOS器件1505有任选的阱注入1520,1521。 When isolated with a simple thin oxide device, PMOS device 1502 and NMOS device 1505 with an optional well implant 1520,1521. 阱注入1520,1521不电连接到欧姆接触点。 1520,1521 well implant is not electrically connected to the ohmic contact. 通过该示范的偏置条件组,该两个器件1502和1505的公共漏连接上的输出电压Vo1512取决于栅上的输入电压Vg1509。 By the exemplary set of bias conditions, the two devices 1502 and 1505 of the common drain connection of the output voltage depends on the input voltage Vg1509 Vo1512 the gate. 当Vg1509为高(通常为Vdd1503)时,则N型器件1505“导通”而P型器件1502“截止”。 When Vg1509 is high (typically Vdd1503), the N-type device 1505 "on" and the P-type device 1502 "off." 即N型器件1505的沟道区域导电而P型器件1502的沟道区域不导电。 I.e., N-type channel region conductive device 1505 and the channel region of the P-type device 1502 is non-conducting. 结果是,输出电压Vo1512变到低值Vss1506。 As a result, the output voltage is changed to a low value Vo1512 Vss1506. 当Vg1509为低(通常为Vss1506)时,发生相反的情况。 When Vg1509 low (typically Vss1506), the opposite occurs. 现在N型器件1505“截止”而P型器件1502“导通”,输出电压Vo改变到P型源的电压,或改变到Vss,有效地提供反相的功能。 N-type device 1505 is now "off" type device 1502 and P "on", the output voltage Vo is changed to the source voltage of the P-type, or changed to Vss, effectively providing an inverted function. 肖特基壁垒CMOS电路可以在经降低的温度下工作以进一步加强功率和速度性能,如申请于2002年5月16日的美国临时专利申请60/388659号中解释的一样。 Schottky barrier CMOS circuit can work to further strengthen the power and speed performance at the decreased temperature, as explained in No. 60/388659 as filed on May 16, 2002 of US Provisional Patent Application.

本技术领域熟练的人员应理解的是,上述CMOS反相器电路仅是应用互补的肖特基壁垒PMOS和NMOS晶体管的一个示范方法,在集成电路中还存在很多组合PMOS和/或NMOS晶体管的变型,但并不背离本发明的精神和范围。 Skilled in the art will appreciate that, in the CMOS inverter circuit is merely one exemplary application of the method is complementary to the Schottky barrier PMOS and NMOS transistors, there are many combinations of PMOS and / or NMOS transistors in the integrated circuit variations, but without departing from the spirit and scope of the invention.

虽然上文的叙述包含很多具体细节,这不应被理解为对本发明的范围的限制,而理解对本发明的一个优选实施例的示范。 While the above description contains many specifics, these should not be construed as limiting the scope of the present invention, the understanding of the exemplary embodiments of a preferred embodiment of the present invention. 本技术领域熟练的人员将认识到还可以有许多其他的变化。 Skilled in the art will recognize that there are many other variations. 例如,可以有许多候选的用作源/漏的金属。 For example, there may be many candidates as the source / drain metal. 对于将一个薄氧化层插入该金属和硅衬底之间也很有利。 It is also advantageous for a thin oxide layer interposed between the metal and the silicon substrate. 硅衬底本身也可以由任何数量的其他半导体或诸如SOI的衬底类型替代。 Silicon substrate itself may be replaced by any number of other types of substrate such as a semiconductor or an SOI. 另外,各层次或元件之间的分界线能永远用其他材料或界面手段分级或插入以改进性能。 Further, the dividing line between the various levels can always elements or materials or other interface means to improve performance rating or insertion. 本发明意欲覆盖包括本文揭示的或通过引用而结合的材料中揭示的任何变动特征的CMOS器件,以及覆盖包括本文揭示的或通过引用而结合的材料中揭示的任何变动的制造技术的CMOS制造工艺。 The present invention is intended to cover any variations features herein disclosed or material incorporated by reference in the disclosed CMOS devices, and to cover manufacturing technology any variation herein disclosed or material incorporated by reference in the disclosed CMOS manufacturing process .

虽然本发明通过参考优选实施例进行了叙述,在本技术领域熟练的人员将认识到,在形式上和细节上可以作出很多变化而不背离本发明的精神和范围。 While the embodiments of the present invention has been described with reference to preferred, the skilled person in the art will recognize that, in form and detail that many changes may be made without departing from the spirit and scope of the invention.

Claims (26)

  1. 1.一种半导体衬底上的CMOS器件,包括:至少一个具有P型沟道掺杂的肖特基壁垒NMOS器件;至少一个具有N型沟道掺杂的肖特基壁垒PMOS器件;和不通过欧姆接触点电接触的P型和N型沟道掺杂中的至少一种掺杂。 A CMOS device on a semiconductor substrate, comprising: at least one dopant having a P-channel Schottky barrier NMOS device; at least one N-type doped channel PMOS devices having Schottky barriers; and not P-type and N-type channel doped ohmic contact point electrical contact via at least one doping.
  2. 2.一种半导体衬底上的CMOS器件,包括:至少一个肖特基壁垒NMOS器件,该肖特基壁垒NMOS器件位于至少一个肖特基壁垒NMOS有源区域内;至少一个肖特基壁垒PMOS器件,该肖特基壁垒PMOS器件位于至少一个肖特基壁垒PMOS有源区域内;在不通过欧姆接触点电接触的肖特基壁垒NMOS有源区域和肖特基壁垒PMOS有源区域的至少一个区域中的至少一个阱注入。 A CMOS device on a semiconductor substrate, comprising: at least one Schottky barrier NMOS device, the Schottky barrier NMOS device is located at least one Schottky barrier NMOS active region; at least one Schottky barrier PMOS device, the Schottky barrier PMOS device located within at least one Schottky barrier PMOS active region; the NMOS active region and the Schottky barrier PMOS active region of the Schottky barrier ohmic contact point no electrical contact through at least a at least one region of a well implant.
  3. 3.一种半导体衬底上的CMOS器件,包括:至少一个肖特基壁垒NMOS器件;至少一个肖特基壁垒PMOS器件;和用于电隔离器件的装置,该装置不凹入半导体衬底中。 A CMOS device on a semiconductor substrate, comprising: at least one Schottky barrier NMOS device; at least one Schottky barrier PMOS device; and means for electrically isolating the device, the device is not recessed in the semiconductor substrate .
  4. 4.一种半导体衬底上的CMOS器件,包括:至少一个具有至少一个肖特基壁垒NMOS器件的肖特基壁垒NMOS有源区域;至少一个具有至少一个肖特基壁垒PMOS器件的肖特基壁垒PMOS有源区域;至少一个为肖特基NMOS有源区域和肖特基壁垒PMOS有源区域提供隔离的场区域,该场区域包括一个不凹入半导体衬底中的电绝缘层。 A CMOS device on a semiconductor substrate, comprising: at least one active region of the at least one Schottky barrier NMOS Schottky barrier NMOS device having; at least one having at least one Schottky barrier PMOS device Schottky barrier PMOS active region; providing at least one field isolation region is a Schottky barrier NMOS active region and the Schottky PMOS active region, the field region comprises an electrically insulating layer is recessed in the semiconductor substrate.
  5. 5.一种在半导体衬底上制造CMOS器件的方法,包括下列步骤:提供至少一个肖特基壁垒NMOS有源区域;提供至少一个肖特基壁垒PMOS有源区域;在至少一个肖特基壁垒NMOS有源区域的至少一些区域中形成第一类型的金属,同时防止在半导体衬底的其他区域中形成该第一类型的金属;在至少一个肖特基壁垒PMOS有源区域的至少一些区域中形成第二类型的金属,同时防止在半导体衬底的其他区域中形成该第二类型的金属。 A method for manufacturing a CMOS device on a semiconductor substrate, comprising the steps of: providing an active region of the NMOS least a Schottky barrier; providing at least one Schottky barrier PMOS active region; at least one Schottky barrier the first type of metal forming at least some of the NMOS region of the active region, while preventing the first type of metal is formed in other regions of the semiconductor substrate; at least some areas of at least one Schottky barrier PMOS active region forming a second type of metal, while preventing the second type of metal is formed in other regions of the semiconductor substrate.
  6. 6.一种在半导体衬底上用双排除掩模工艺制造CMOS器件的方法,包括下列步骤:提供至少一个肖特基壁垒NMOS有源区域,该区域包括至少一个栅极以及暴露的半导体衬底的一个区域;提供至少一个肖特基壁垒PMOS有源区域,该区域包括至少一个栅极以及暴露的半导体衬底的一个区域;提供用于防止在肖特基壁垒PMOS有源区域中的暴露的半导体衬底的区域中形成第一类型金属,同时暴露并且因此而允许在肖特基壁垒NMOS有源区域中的暴露的半导体衬底的区域中形成第一类型金属的第一排除掩模层;提供用于防止在肖特基壁垒NMOS有源区域中的暴露的半导体衬底的区域中形成第二类型金属,同时暴露并且因此而允许在肖特基壁垒PMOS有源区域中的暴露的半导体衬底的区域中形成第二类型金属的第二排除掩模层。 A semiconductor substrate used in the method of double exclusion mask process for manufacturing CMOS devices, comprising the steps of: providing at least one Schottky barrier NMOS active region, the gate electrode and a region including at least the exposed semiconductor substrate a region; providing at least one Schottky barrier PMOS active region, the at least one gate region comprises a region of the semiconductor substrate and exposed; provided for preventing exposure of the Schottky barrier PMOS active region of a semiconductor substrate region of a first type of metal is formed while exposing and thus allows the Schottky barrier NMOS active region exposed region of the semiconductor substrate, forming a first negative type first mask metal layer; providing a second type of metal for preventing the NMOS region of the semiconductor substrate is exposed in the active region of the Schottky barrier is formed while exposing the semiconductor substrate and thereby allowing the exposed Schottky barrier PMOS active region the second type of metal regions formed in the bottom of the second exclusion mask layer.
  7. 7.如权利要求6所述的方法,其特征在于,其中肖特基壁垒NMOS和PMOS有源区域中的栅极具有电绝缘侧壁隔离,该方法进一步包括下列步骤:用具有大于侧壁隔离刻蚀速率的第一排除掩模层刻蚀速率的刻蚀形成用于肖特基壁垒PMOS有源区域的第一排除掩模层的图形,从而暴露肖特基壁垒NMOS有源区域中的半导体衬底,该肖特基壁垒NMOS有源区域具有邻近暴露的栅极的暴露的半导体衬底的至少一些区域;在部分肖特基壁垒NMOS有源区域的暴露的半导体衬底区域中通过提供一种金属层以使其与暴露的半导体衬底发生反应而提供肖特基或类肖特基接触,侧壁隔离在栅极侧壁和该金属层之间向化学反应提供连续的壁垒;用具有大于侧壁隔离刻蚀速率的第二排除掩模层刻蚀速率的刻蚀形成用于肖特基壁垒NMOS有源区域的第二排除掩模层的图形,从而暴露肖特基壁垒PMOS有 7. The method according to claim 6, characterized in that, wherein a Schottky barrier gate NMOS and PMOS active region having an electrically insulating sidewall spacers, the method further comprising the steps of: isolating sidewall having greater than a first negative etch rate of the etch rate of the etching mask layer pattern used to form the Schottky barrier PMOS active region of the first negative mask layer, thereby exposing the Schottky barrier NMOS active region of the semiconductor at least some areas of the substrate, the Schottky barrier NMOS active region having an exposed semiconductor substrate adjacent to the gate electrode is exposed; the exposed region of the semiconductor substrate in a portion of the Schottky barrier NMOS active region by providing a metal layer exposed semiconductor substrate so as to react with and provide Schottky contacts or Schottky-like, side wall isolation barrier to provide a continuous chemical reaction between the metal layer and the gate sidewall; having sidewall spacer etch rate is greater than a second negative etch rate etch mask layer pattern used to form the Schottky barrier NMOS active region of the second negative mask layer, thereby exposing the Schottky barrier PMOS have 区域中的半导体衬底,该肖特基壁垒PMOS有源区域具有邻近暴露的栅极的暴露的半导体衬底的至少一些区域;在部分肖特基壁垒PMOS有源区域的暴露的半导体衬底区域中通过提供一种肖特基金属层以使其与暴露的半导体衬底发生反应而提供肖特基或类肖特基接触,侧壁隔离在栅极侧壁和该金属层之间向化学反应提供连续的壁垒。 A semiconductor substrate region, the Schottky barrier PMOS active region has at least some of the exposed region of the semiconductor substrate adjacent the gate electrode is exposed; the exposed region of the semiconductor substrate in a portion of the Schottky barrier PMOS active region by providing a Schottky metal layer and the semiconductor substrate is exposed so as to react to provide a Schottky or Schottky-like contact sidewall spacer to a chemical reaction between the metal layer and the gate sidewall to provide a continuous barrier.
  8. 8.一种在半导体衬底上用双排除掩模工艺制造CMOS器件的方法,包括下列步骤:在半导体衬底的至少一个肖特基壁垒N型有源区域中提供至少一个栅极,该栅极具有电绝缘侧壁隔离;在半导体衬底的至少一个肖特基壁垒P型有源区域中提供至少一个栅极,该栅极具有电绝缘侧壁隔离;提供用于肖特基壁垒P型有源区域的第一排除掩模层,该排除掩模层用具有大于侧壁隔离刻蚀速率的排除掩模层刻蚀速率的刻蚀形成图形,从而暴露肖特基壁垒N型有源区域中的半导体衬底的至少一些部分;在肖特基壁垒N型有源区域中通过提供和暴露的半导体衬底发生反应的薄金属层提供肖特基或类肖特基接触,暴露的侧壁隔离在栅极和该薄金属层之间向化学反应提供连续的壁垒;提供用于肖特基壁垒N型有源区域的第二排除掩模层,该排除掩模层用具有大于侧壁隔离刻蚀速率 A negative on a semiconductor substrate manufacturing process using a double mask method CMOS device, comprising the steps of: providing at least one gate, the gate Schottky barrier at least a N-type active region of the semiconductor substrate electrode having an electrically insulating sidewall spacers; at least one Schottky barrier in the semiconductor substrate of P-type active region is provided at least one gate, the gate electrode having an electrically insulating sidewall spacers; providing a P-type Schottky barrier the first exclusion mask layers of the active region, the negative mask layer pattern is formed by etching a mask layer having an etching rate greater than the negative of the sidewall spacer etch rate, thereby exposing the N-type active region Schottky barrier at least some portions of the semiconductor substrate; a thin metal layer by providing and reacting the exposed semiconductor substrate in the active region of N-type Schottky or Schottky barrier type provided in Schottky contact, the exposed sidewall providing isolation between the gate and the thin metal layer to a continuous chemical barrier; providing a second masking layer for the Schottky barrier to exclude the N-type active region, the negative mask layer having sidewall spacers of greater than etch rate 排除掩模层刻蚀速率的刻蚀形成图形,从而暴露肖特基壁垒P型有源区域中的半导体衬底的至少一些部分;和在肖特基壁垒P型有源区域中通过提供和暴露的半导体衬底发生反应的肖特基接触材料提供肖特基或类肖特基接触,暴露的侧壁隔离在栅极和该肖特基接触材料之间向化学反应提供连续的壁垒。 Negative etch rate etch mask layer patterned to expose at least some portion of P-type semiconductor substrate of the Schottky barriers of the active region; and by providing a P-type active region and the Schottky barrier is exposed Schottky contact with the semiconductor substrate material react to provide a Schottky or Schottky-like contact with the exposed sidewall spacers and the gate Schottky contact provides a continuous barrier to the chemical reaction between the materials.
  9. 9.如权利要求8所述的方法,其特征在于,其中肖特基壁垒P型有源区域的源漏极用由硅化铂,硅化钯和硅化铱组成的集合中的成员形成。 9. The method according to claim 8, characterized in that, wherein the source region of the active Schottky barrier formed with a P-type drain collection of platinum silicide, palladium silicide, iridium silicide and consisting of a member.
  10. 10.如权利要求8所述的方法,其特征在于,其中肖特基壁垒N型有源区域的源漏极用由稀土硅化物组成的集合中的成员形成。 10. The method according to claim 8, characterized in that, wherein the source of the N-type Schottky barrier of the drain region is formed by active rare earth silicide set of members.
  11. 11.如权利要求8所述的方法,其特征在于,其中肖特基壁垒P型有源区域的源漏极中的至少一种至少在和源漏极之间的沟道相邻的区域中和半导体衬底形成肖特基或类肖特基接触。 Region 11. The method according to claim 8, wherein at least one of the source and drain electrodes and the channel between adjacent source drain of the P-type Schottky barrier active region at least in and the semiconductor substrate forms a Schottky or Schottky-like contacts.
  12. 12.如权利要求8所述的方法,其特征在于,其中肖特基壁垒N型有源区域的源漏极中的至少一种至少在和源漏极之间的沟道相邻的区域中和半导体衬底形成肖特基或类肖特基接触。 Region 12. The method according to claim 8, wherein at least one of the source and drain electrodes and the channel between adjacent source drain of the N-type active region of the Schottky barrier at least in and the semiconductor substrate forms a Schottky or Schottky-like contacts.
  13. 13.如权利要求8所述的方法,其特征在于,其中肖特基壁垒P型有源区域的源漏极中的至少一种和半导体衬底之间的全部界面和半导体衬底形成肖特基接触或类肖特基区域。 13. The method according to claim 8, characterized in that at least all of the interface between the semiconductor substrate and a semiconductor substrate and a Schottky barrier Schottky drain of the P-type wherein the active region in based contact or Schottky-like region.
  14. 14.如权利要求8所述的方法,其特征在于,其中肖特基壁垒N型有源区域的源漏极中的至少一种和半导体衬底之间的全部界面和半导体衬底形成肖特基接触或类肖特基区域。 14. The method according to claim 8, characterized in that at least all of the interface between the semiconductor substrate and a semiconductor substrate and a Schottky barrier Schottky source and drain electrodes wherein the N-type active region in based contact or Schottky-like region.
  15. 15.如权利要求8所述的方法,其特征在于,其中在全部沟道掺杂工艺完成以后提供栅极。 15. The method according to claim 8, characterized in that, all of which provide a gate channel doping process is completed later.
  16. 16.如权利要求8所述的方法,其特征在于,其中沟道掺杂剂被引入半导体衬底用于肖特基壁垒P型和肖特基壁垒N型有源区域。 16. The method according to claim 8, characterized in that, wherein the channel dopant is introduced into the semiconductor substrate for the P-type Schottky barrier Schottky barriers and N-type active region.
  17. 17.如权利要求8所述的方法,其特征在于,其中沟道掺杂剂被引入半导体衬底,使肖特基壁垒P型和肖特基壁垒N型有源区域的掺杂剂浓度在垂直方向明显变化,在横向基本保持常数。 17. The method according to claim 8, characterized in that, wherein the channel dopant is introduced into the semiconductor substrate, so that the P-type Schottky barrier Schottky barriers and the N-type dopant concentration in the active region significant change in the vertical direction, in the lateral direction remains substantially constant.
  18. 18.如权利要求8所述的方法,其特征在于,其中沟道掺杂剂从由砷,磷,锑,硼,铟和镓组成的集合中选择。 18. The method according to claim 8, characterized in that, wherein the channel dopant selected from a group of arsenic, phosphorus, antimony, boron, indium and gallium thereof.
  19. 19.如权利要求8所述的方法,其特征在于,其中肖特基壁垒P型和肖特基壁垒N型有源区域的源漏极被设置成使沟道长度小于或等于100nm。 19. The method according to claim 8, characterized in that, wherein the source and the drain of the P-type Schottky barrier Schottky barrier N-type active region are set so that the channel length is less than or equal to 100nm.
  20. 20.如权利要求8所述的方法,其特征在于,其中栅极通过下列步骤提供:提供包括在半导体衬底上的电绝缘层的栅绝缘体;在绝缘层上淀积导电薄膜;通过刻蚀形成导电薄膜的图形以形成栅极;和通过在栅极的至少一个侧壁上提供至少一个薄绝缘层形成电绝缘侧壁隔离。 20. The method according to claim 8, characterized by the steps of providing the gate wherein: providing a gate insulator comprising an electrically insulating layer on a semiconductor substrate; depositing a conductive film on the insulating layer; etching through the forming a conductive thin film pattern to form the gate electrode; and an upper gate electrode by at least one sidewall insulating layer providing at least one thin electrically insulating sidewall spacer is formed.
  21. 21.如权利要求20所述的方法,其特征在于,其中栅绝缘体具有大于4.0的介电常数。 21. The method according to claim 20, wherein, wherein the gate insulator having a dielectric constant greater than 4.0.
  22. 22.如权利要求20所述的方法,其特征在于,其中栅绝缘体用由金属氧化物组成的集合中的成员形成。 22. The method according to claim 20, wherein, wherein the gate insulator is formed of a metal oxide with a set of members.
  23. 23.如权利要求8所述的方法,其特征在于,其中半导体衬底被加以应力。 23. The method according to claim 8, characterized in that, where a semiconductor substrate is to be stress.
  24. 24.如权利要求8所述的方法,其特征在于,其中暴露的肖特基壁垒N型有源区域的半导体衬底中的肖特基或类肖特基接触通过提供和暴露的半导体衬底接触的第一薄金属层以及和第一薄金属层接触的第二薄金属层而提供,其中第一和第二薄金属层通过热退火和暴露的半导体衬底发生反应。 24. The method according to claim 8, wherein a Schottky barrier semiconductor substrate of N-type active region wherein the exposed Schottky or Schottky-like contacts and the semiconductor substrate is exposed through the provision of the second thin metal layer and a first thin metal layer and a first thin metal layer is provided in contact with the contact, wherein the first and second thin metal layer by thermal annealing reaction and the exposed semiconductor substrate.
  25. 25.如权利要求24所述的方法,其特征在于,其中第二薄金属层用钛形成。 25. The method according to claim 24, wherein, wherein the second thin metal layer is formed of titanium.
  26. 26.一种具有肖特基壁垒源漏极的CMOS器件,包括:至少一个肖特基壁垒NMOS器件;至少一个肖特基壁垒PMOS器件,该NMOS和PMOS器件电连接。 26. A Schottky barrier source and drain of the CMOS device, comprising: at least one Schottky barrier NMOS device; at least one Schottky barrier PMOS device, the NMOS and PMOS devices are electrically connected.
CN 03816343 1999-12-16 2003-05-16 Schottky barrier CMOS device and method CN1669145A (en)

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US38116202 true 2002-05-16 2002-05-16
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US38132102 true 2002-05-16 2002-05-16
US38865902 true 2002-05-16 2002-05-16
US38123802 true 2002-05-16 2002-05-16
US38123702 true 2002-05-16 2002-05-16
US38123902 true 2002-05-16 2002-05-16
US38123602 true 2002-05-16 2002-05-16
US10215447 US6949787B2 (en) 2001-08-10 2002-08-09 Transistor having high dielectric constant gate insulating layer and source and drain forming Schottky contact with substrate
US10236685 US6744103B2 (en) 1999-12-16 2002-09-06 Short-channel schottky-barrier MOSFET device and manufacturing method
US10342590 US6784035B2 (en) 2002-01-23 2003-01-15 Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate
US44571103 true 2003-02-07 2003-02-07

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CN101533804B (en) 2009-04-02 2011-09-14 英属维京群岛商节能元件股份有限公司 A metal oxide semiconductor P-N junction schootky diode structure and the production method thereof
CN101510528B (en) 2009-04-02 2011-09-28 英属维京群岛商节能元件股份有限公司 P-N junction diode structure of metal oxide semiconductor and method for producing the same

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CN101533804B (en) 2009-04-02 2011-09-14 英属维京群岛商节能元件股份有限公司 A metal oxide semiconductor P-N junction schootky diode structure and the production method thereof
CN101510528B (en) 2009-04-02 2011-09-28 英属维京群岛商节能元件股份有限公司 P-N junction diode structure of metal oxide semiconductor and method for producing the same
CN102005371A (en) * 2009-08-28 2011-04-06 夏普株式会社 Method for manufacturing semiconductor device

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