CN1649271A - Low voltage high speed TTL and Not gate circuit and its method for improving operation speed - Google Patents
Low voltage high speed TTL and Not gate circuit and its method for improving operation speed Download PDFInfo
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Abstract
This invention discloses a low voltage high speed TTL, a NOT-gate circuit and a method for increasing operation speed with 1.5V working voltage. The circuit includes a logic stage and an output level, the output level is a Q2 triode inverter. The logic part is composed of multiple-tube Q1, an emitter follower Q3 and a floating bleeder tube Q4, the logic level uses feedback tracing and floating bleeder circuit, characterizing that the emitter input signal of Q1 is sent to Q3 base from Q1 based on base-base coupled way to realize up and down at nearly the same speed for the internal points, Q4 provides low-resistance bleeding channel to speed up Q2 block, Q4 reduces its emit flow to zero quickly to block the channel from Q1 to Q2 and reduce Q1 basic flow to increase Q3 to a large emit flow and speed up conduction of Q2.
Description
Technical field:
The present invention is a kind of bipolar integrated circuit, and specifically a kind of TTL NAND gate circuit belongs to technical field of integrated circuits.
Technical background:
Integrated circuit can be divided into logical integrated circuit and linear integrated circuit two big classes, and the former is called digital integrated circuit again, is used for computer, digital communication, and digital instrument, Digit Control Machine Tool etc., the latter is used for linear amplification.In addition, integrated circuit is divided into bipolar integrated circuit and MOS integrated circuit again.Ambipolar circuit at full speed is good at, and the MOS circuit then is celebrated with low-power consumption, and the two is supplied mutually, and is indispensable.Bipolar integrated circuit has TTL and ECL etc., the TTL circuit is except that being used in small scale integrated circuit and medium scale integrated circuit, also be used in the ambipolar application-specific integrated circuit (ASIC) by ambipolar gate array form, also be used for the ISPLSI of system programmable ISP (IN SYSTEM PROGRAMMABILOTY) high density PLD, the ISPLSI device has thoroughly changed traditional digital circuit design method.Under the support of software, it can be freely within it portion's performance of generating the small-scale IC piece in the various TTL series create the logical circuit that the brand-new scale of the unexistent performance of middle and small scale IC more strengthens.
Prior art and existing problems
Now the integrated level of integrated circuit improves constantly, and increasing product develops to high speed, miniaturization, portable, low-power consumption direction, and supply voltage to 3.3V, even is reduced to lower voltage from 5V.But along with improving constantly of integrated circuit integrated level, current densities increases, and the bipolar transistor size is dwindled, and produces problems such as puncture thus, so supply voltage is also wanted corresponding reduction
[5], Low-Voltage Logic Devices appears thus.In addition, portable electric appts requires to use powered battery, and the device that volume monocell little and high-speed low-power-consumption is powered is just meeting this developing trend, has wide application prospects.So the growth of Low-Voltage Logic Devices surpassed 500% in past 5 years, the world market adds up 5.72 hundred million dollars, has 10 tame suppliers at least in this market of contention.Low-Voltage Logic Devices is as the up-and-coming youngster, and output has accounted for 25% of the global logical device market share.It is predicted, will be in its market share of the five-year near 50% of global logical device.
Conventional TTL NAND gate circuit: routine 74/54 sequence TTL NAND gate circuit illustrated in figures 1 and 2, operating voltage is 5V, by dividing about dotted line, the dotted line left side is that logic level and the right are output stage.T in Fig. 1 and Fig. 2 logic level
1To T
3Coupling be collector-base coupling (abbreviating collection-Ji as is coupled), promptly input signal passes through T
1Collector coupled to T
3Base stage.T among Fig. 1
3Base stage connect an active bleed-off circuit, as shown in Figure 4.T among Fig. 2
2Base stage connect an active bleeder resistance R
4Active bleed-off circuit and bleeder resistance R
4A termination T
2Base stage, other end dead earth.
Because move back saturation time t
sBe the principal element of decision speed, and t
sRelevant with the base with the unnecessary stored charge of collector region, for reducing base and the unnecessary stored charge of collector region, generally between the base stage of triode and collector electrode, connect a Schottky barrier diode SBD, form the anti-saturation triode, thereby Fig. 2 is become Fig. 1 by mode shown in Figure 3.The anti-saturation triode reduces saturation depth, significantly reduces unnecessary stored charge.But can not eliminate unnecessary stored charge fully, so an active bleed-off circuit also to be arranged among Fig. 1 (promptly by T
4, R
3And R
4Form), replace bleeder resistance R among Fig. 2
4, show as Fig. 4.Active bleed-off circuit is a low-resistance moving back between the period of saturation, produces the leakage current of being extracted out by base stage, and acceleration is moved back saturated, makes and moves back saturation time t
sReduce.The method of this raising speed is to realize by the saturation time that moves back that reduces each pipe, up till now for all adopting this conventional method to TTL.Conventional method is the whole mode in local earlier back.At first study single triode, improve the speed of entire circuit by the speed that improves single triode, thus pipe move back the principal element that saturation time becomes the speed-raising obstacle.
Ambipolar circuit is used for a lot of high speed circuits always, and will keep this advantage future for a long time, yet still has some intrinsic problems: bigger saturated memory time and power consumption.TTL's moves back saturation time t in the ambipolar circuit
sBe the principal element of decision speed, the average transfer delay time t of 74/54 serial TTL gate circuit
PdGreater than 1.5ns.Work in 1.5V and t
PdTTL gate circuit less than 1ns is not found as yet.
Summary of the invention:
The method that the present invention seeks to disclose a kind of low-voltage high speed TTL NAND gate circuit and improve the speed of service, operating voltage is 1.5 volts, the speed raising with the TTL gate circuit reaches t
PdLess than 0.4ns, further also can drop to t
Pd=0.2ns, in addition littler.The AND that not only is used for TTL NAND gate circuit and the corresponding open collector NAND gate that bipolar circuit technology makes and is used for being made up of this, the trigger sum counter also is used for the logic element of ambipolar gate array, and is used for ambipolar PLD.
The method of the present invention's a kind of low-voltage high speed TTL NAND gate circuit and the raising speed of service thereof, operating voltage is 1.5 volts, the composition of its circuit comprises logic level and output stage two parts.The input x of logic level part
1, x
2With output b
2Between be ' with ' relation, the input b of output stage part
2And be non-relation between the output y.Wherein output stage is exactly triode Q
2The inverter of emitter grounding, Q
2Collector electrode has load resistance R
C2, Q
2Base stage b
2With above-mentioned b
2It is same point.The logic level part by penetrating pipe Q more
1, emitter follower Q
3With unsteady bleeder pipe Q
4Constitute.Input signal x
1, x
2Receive and penetrate pipe Q more
1Two emitters, because of penetrate more the pipe Q
1Base stage b
1Be connected to emitter follower Q
3Base stage; So Q
1The emitter-base bandgap grading input signal through Q
1Base stage be coupled to Q
3Base stage, form Ji-Ji coupling, be coupled to Q
3Base flow pass through Q
3After tube current amplifies, again from Q
3Emitter-base bandgap grading output to inverter Q
2Base stage b
2Bleeder pipe Q floats
4Emitter-base bandgap grading and collector electrode receive Q respectively
1Collector electrode c
1And Q
2Base stage b
2, and Q
1And Q
4Base stage receive the 1.5V power supply by base electrode bias resistance separately respectively.
An above-mentioned multi-emitter pipe Q
1Two triode Q that available two base stages link to each other and link to each other with two collector electrodes
11And Q
12Equivalent electric circuit replace.Remove output stage triode Q
2Outside the available anti-saturation triode, all triodes of logic level are all without the anti-saturation triode.
Unsteady bleeder pipe Q of the present invention
4Can use the bleeder resistance R that floats
B2Replace.A multi-emitter pipe Q
1The emission number of poles can be greater than 2, or multi-emitter pipe Q
1A plurality of triode (the Q more than 2 that available each base stage links to each other and links to each other with each collector electrode
11, Q
12, Q
13... Q
1k, k＞2) equivalent electric circuit replace.
Output stage triode Q of the present invention
2The load resistance R of collector electrode
C2Can use high f
TLongitudinal P NP pipe Q
5Replace Q
5Base stage connect Q
2Base stage, Q
5Collector electrode connect Q
2Collector electrode, Q
5Emitter-base bandgap grading be connected to the 1.5V power supply.
Low-voltage high speed TTL NAND gate circuit of the present invention improves the method for the speed of service, and this method is:
(1) adopts Ji-Ji coupled modes, penetrate pipe Q more
1The emitter-base bandgap grading input signal through Q
1Base stage be coupled to emitter follower Q
3Base stage, and produce Q
3Base current, form Ji-Ji coupled modes thus, this be avoid penetrating more the pipe Q
1Move back saturated influence, realize catching up with fast one of initial conditions.
(2) adopt the bleeder pipe Q that floats
4, bleeder pipe Q floats
4Collector electrode one termination Q
2Base stage b
2, Q
4Emitter-base bandgap grading one termination penetrate more the pipe Q
1(or Q
11And Q
12) collector electrode c
1, collector electrode c
1Current potential is at Q
2Unlatching current potential V
T2That change up and down or unsteady, not fixed potential.Bleeder pipe Q floats
4Cut much ice to improving the speed of service:
1. at Q
2Procedures of turn-off is worked as c
1Current potential drops to and is lower than V
T2The time, Q
4Provide the low-resistance path of releasing, Q
4Conducting resistance is very lowly optional, produces very big Q thus
2Base stage is oppositely extracted electric current out, quickens ending of output stage.
2. at Q
2Turn on process is worked as c
1Current potential is raised to and is higher than V
T2The time, Q
4The jet of pipe is reduced to very soon near 0, stops on the one hand by penetrating pipe Q more
1(or Q
11And Q
12) collector electrode c
1To Q
2Base stage b
2Or Q
3The path of emitter-base bandgap grading, make to penetrate more and guarantee adequate food and state does not influence other parts, manage Q because of path stops to make to penetrate more on the other hand
1Base flow reduces, thereby increases emitter follower Q
3Base flow is because of Q
3Jet is Q
3The β of base flow doubly produces very big Q thus
3Jet also promptly produces Q
2The very big forward drive current of base stage is quickened the conducting of output stage.
Available unsteady bleeder resistance R
B2Replace the bleeder pipe Q that floats
4, it improves speed of service effect slightly inferior to unsteady bleeder pipe Q
4
(3) an emitter follower Q is arranged in the logic level
3, Q
3Do not have saturation condition, all triodes of logic level are not the anti-saturation triodes, and do not need to use the anti-saturation triode.Work as Q
1Base stage b
1When current potential rises, because penetrate pipe Q more
1To Q
3Coupling be Ji-Ji coupling, the emitter follower multiplication factor is 1, i.e. Q
3Emitter-base bandgap grading output b
2Variable quantity and penetrate more the pipe Q
1Base stage b
1Variable quantity identical, so c
1Variable quantity and b
2Variable quantity this shows much at one, inner all each point b
1, c
1And b
2Variable quantity much at one, relatively change minimum between each point.Because the unnecessary stored charge overwhelming majority is at base and collector region, the emitter region is few, and b
1, c
1And b
2Variation is minimum relatively between each point, so still can keep its state to the triode of locating saturation condition, can not move back the speed that improves logic level under the saturated conditions.
Above-mentioned three characteristics make logic level partly form the inner member indivisible integrated circuit structure that feedback is arranged mutually, claim that this is that feedback is caught up with and floating type logic level circuit.Based on this method, operating voltage is the low-voltage high speed TTL NAND gate circuit average transfer delay time t of 1.5V
PdBe generally less than 0.4ns, can reach 0.2ns or littler.
Description of drawings
Fig. 1. be one of prior art 74/54 serial TTL NAND gate of the present invention circuit diagram.
Fig. 2. be two circuit diagrams of prior art 74/54 serial TTL NAND gate of the present invention.
Fig. 3. be the Schottky transistor circuit figure of Fig. 1 of the present invention.
Fig. 4. be the bleed-off circuit circuit diagram of Fig. 1 of the present invention.
Fig. 5. penetrate the pipe circuit diagram more.
Fig. 6. be one of 1.5 volts of TTL NAND gate of the present invention circuit diagram.
Fig. 7. be two circuit diagrams of 1.5 volts of TTL NAND gate of the present invention.
Fig. 8. be the three-circuit figure of 1.5 volts of TTL NAND gate of the present invention.
Fig. 9. be four circuit diagrams of 1.5 volts of TTL NAND gate of the present invention.
Figure 10. one of computer simulation waveform of NAND gate Fig. 6 has V
X1, V
X2, V
y, V
B1, V
C1And V
B2Totally six components.
Figure 11. the waveform to Fig. 6 amplifies has V
X1, V
X2, V
y, V
B1, V
C1And V
B2Totally six components.
Figure 12. the waveform to Figure 11 amplifies again has V
X1, V
X2, V
y, V
B1, V
C1And V
B2Totally six components.
Figure 13. two of the computer simulation waveform of NAND gate Fig. 6 has V
B1-V
C1, V
B1-V
B2, V
B2-V
C1, V
C1-V
X1, V
C1-V
X2With＜V
X1, V
X2, V
yTotally six components.
Figure 14. one of waveform that Figure 13 is amplified has V
B1-V
C1, V
B1-V
B2, V
B2-V
C1, V
C1-V
X1, V
C1-V
X2With＜V
X1, V
X2, V
ySix components.
Figure 15. three of the computer simulation waveform of NAND gate Fig. 6 has I
B2,-I
E3,-I
C4, I
E4, I
E11With＜V
X1, V
X2, V
yTotally six components.
Figure 16. the waveform to Figure 15 amplifies has I
B2,-I
E3,-I
E4With＜V
X1, V
X2, V
yTotally six components.
Figure 17 .t
PdThe computer simulation waveform of=0.2ns NAND gate Fig. 6 has V
X1, V
X2, V
yWith-I
VcTotally four components.
Figure 18. one of waveform that Figure 17 is amplified has V
X1, V
X2, V
yWith-I
VcTotally four components.
Figure 19. two of the waveform that Figure 17 is amplified has V
X1, V
X2, V
yWith-I
VcTotally four components.
Figure 20. one of computer simulation waveform of NAND gate Fig. 7 has V
X1, V
X2, V
y, V
B1, V
C1And V
B2Totally six components.
Figure 21. the waveform to Figure 20 amplifies has V
X1, V
X2, V
y, V
B1, V
C1And V
B2Totally six components.
Figure 22. two of the computer simulation waveform of NAND gate Fig. 7 has I
B2,-I
E3, I
Rb2, I
E11, I
E12And V
X1, V
X2, V
yTotally six components.
Figure 23. work as V
X1, V
X2To the computer simulation waveform of NAND gate Fig. 6, V is arranged during by 0.5 → 1.2 volt
X1, V
X2And V
yTotally three components.
Figure 24. the waveform to Figure 23 amplifies has V
X1, V
X2And V
yTotally three components.
Embodiment:
Symbol among the figure: V
X1=V (x1), V
X2=V (x2), V
y=V (y), V
B1=V (b1), V
C1=V (c1), V
B2=V (b2), I
B2=IB (Q2), I
E3=IE (Q3), I
E4=IE (Q4), I
C4=IC (Q4), I
E11=IE (Q11), I
E12=IE (Q12), I
Rb2=I (Rb2), I
Vc=I (V
C).
TTL NAND gate circuit of the present invention comprises logic level and output stage two parts.The input of logic level is x
1And x
2, logic level output is Q
2The base stage b of pipe
2, input x
1, x
2With output b
2Between be ' with ' relation, i.e. b
2=x
1X
2Output stage is an inverter, output stage input b
2And be non-relation between the output y.Earlier complete all triodes of logic level are not proposed concrete regulation, comprise and move back saturation time t
sSize, as long as the logic level input and output can reach fast and follow, and forward is driven and the purpose of oppositely extraction gets final product counter then pushing away the wherein requirement of each triode.Relative potential change is very little if logic level is imported inner each point, promptly inside is respectively pressed same speed and is caught up with input fast, can finish the index that necessary forward is driven and oppositely extracted out, allow triode to be in the speed that realizes improving this logic level under the saturation condition.Is that mutual indivisible integral body is considered with logic level as an each several part, by the whole input and output of the logic level minimizing of time of delay, reach the purpose of raising speed, by the bulk velocity requirement, the state of each pipe of decision logic level, the pipe that has not necessarily requires to move back saturated, does not even move back the saturated raising speed that is beneficial on the contrary, and what taked is the local mode in whole earlier back.
Circuit diagram 6～Fig. 9 structure of the present invention and characteristics:
Fig. 5 shows a multi-emitter pipe Q
1, can two triode Q of equivalence
11And Q
12, connecting by mode among the figure, two base stages link to each other, and two collector electrodes link to each other, and emitter is independent.Therefore the logic level principle of Fig. 6～Fig. 9 is identical, Q
1Or Q
11And Q
12Collector electrode be designated as c
1, Q
1Or Q
11And Q
12Base stage be designated as b
1
Corresponding coupling is base stage-base stage coupling in Fig. 6～Fig. 9 logic level, abbreviates Ji-Ji coupling as, and promptly input signal passes through Q
1Or Q
11And Q
12Base stage b
1Be coupled to Q
3Base stage b
3Ji-Ji coupling can avoid input pipe to move back saturated influence, and this is to realize catching up with fast one of initial conditions.
Adopt the bleeder pipe Q that floats among Fig. 6～Fig. 9
4Or unsteady bleeder resistance R
B2, bleeder pipe Q floats
4Or unsteady bleeder resistance R
B2A termination Q
2Base stage, another termination input pipe Q
1Or Q
11And Q
12Collector electrode c
1, collector electrode c
1Current potential is at Q
2Unlatching current potential V
T2Changing up and down, or float, is not fixed potential.
Bleeder pipe Q floats
4Effect:
1. at Q
2Procedures of turn-off is worked as c
1Current potential drops to and is lower than V
T2The time, Q
4Or R
B2The low-resistance path of releasing is provided, and conducting resistance is optionally very low, produces big reverse extraction electric current thus, quickens ending of output stage;
2. at Q
2Turn on process is worked as c
1Current potential is raised to and is higher than V
T2The time, Q
4It is nearly 0 that the jet of pipe is reduced to very much, stops through c on the one hand
1With input pipe Q
1(or Q
11And Q
12) path, make the input pipe saturation condition not influence other parts, because of path stops the input pipe base flow is reduced on the other hand, so emitter follower Q
3Base flow increases, Q
3Jet is Q
3The β of base flow times, producing big forward drive current thus (is Q
3Jet), quicken the conducting of output stage.
Q in Fig. 6～Fig. 9 logic level
3Be emitter follower, do not have saturation condition, all triodes of logic level are not the anti-saturation triodes, and do not need to use the anti-saturation triode.Because Q
3With input pipe be Ji-Ji coupling, the emitter follower multiplication factor is 1, i.e. Q
3Emitter-base bandgap grading output b
2Variable quantity and input pipe base stage b
1Variable quantity identical, so c
1Variable quantity and b
2Variable quantity is identical, inner like this all each point b
1, c
1And b
2Variable quantity much at one, relatively change minimum between their each points.Because the unnecessary stored charge overwhelming majority is at base and collector region, the emitter region is few, and b
1, c
1And b
2Each point between relatively change minimum.So, can not move back the speed that improves logic level under the saturated conditions wherein if there is triode place saturation condition still can keep its state.
Above-mentioned three characteristics make logic level form the inner member indivisible integrated circuit structure that feedback is arranged mutually, claim that this is that feedback is caught up with and floating type logic level circuit.
Feedback is caught up with process and the principle that improves speed with floating type logic level circuit.
The input of Fig. 6～Fig. 9 logic level is x
1And x
2, output is Q
2The base stage b of pipe
2, under the prerequisite that satisfies the input and output logical relation, observe output b
2Waveform is to input x
1And x
2The tracking velocity of waveform.Average transfer delay time t
PdIt is the leading indicator of evaluation speed.t
Pd=(t
PHL+ t
PLH)/2,50% (in the input 50% of hopping amplitude, promptly the importing the mid point of rising edge) of wherein importing the waveform rising edge to the output waveform trailing edge 50% (output down hopping amplitude 50%, promptly export the mid point of trailing edge) the time interval be called t
PHLSimilar, 50% time interval of 50% to the output waveform rising edge of input waveform trailing edge is called t
PLHAnd t
PHLAnd t
PLHAll obtain by measurement.Relative time postpones also according to said method to measure between the inner each point of circuit.For convenience of description, note Q
1The base stage of pipe (or Q
11Pipe and Q
12The common base of pipe) is middle output b
1, note Q
1The collector electrode of pipe (or Q
11Pipe and Q
12The common collector of pipe) is another middle output c
1At x
1And x
2Two inputs are not under the same waveform as situation, and four kinds of possibility transient process are arranged: (1) one is input as high level, and another input is changed to high level by low level; (2) one are input as high level, and another input is changed to low level by high level; (3) one are input as low level, and another input is changed to low level by high level; (4) one are input as low level, and another input is changed to high level by low level.Observe under four kinds of situations and import waveform, output b
2Waveform and middle output b
1C
1Waveform, thus their time of delay studied.
Fig. 6 is carried out the PSPICE computer simulation by ambipolar circuit technology, draw input and output, the output voltage of each point and the waveform of electric current show as Figure 10～Figure 16 in the middle of comprising.Be input as x among the figure
1And x
2, output stage y output, logic level b
2Output, intermediate point has b
1And c
1Output.Find out whole gate circuit output y output and input x by Figure 10
1And x
2, satisfy and the non-y=x that concerns
1x
2Logic level output b
2With input x
1And x
2, satisfy and concern y=x
1x
2Also being found out by Figure 10, is that 5～10ns model comprises the four kinds of transient process in (1)～(4) in again at abscissa, and each takes place near the comfortable 5.6ns, and near the 6.5ns, near the 8.0ns and near the 9.5ns, it is as follows to describe corresponding transition state behavior respectively:
Research speed sees that mainly the transition statusline is, following four kinds of transient process are arranged:
(1) input x
1Be high level, input x
2Change to high level by low level.Near Figure 10 abscissa 5.4～7.4ns, should scheme to amplify, draw Figure 11.By finding out V near the 5.6ns among Figure 11
B1, V
C1, V
B2And x
2Almost rise with speed, the relative delay is very little.Amplify ordinate again near the mid point of trailing edge or rising edge separately, abscissa amplifies near 5.6ns, draw Figure 12.Obtaining each point by near Figure 12 (for accurately checking, also can further amplify the 5.6ns again) is relative time of delay: t
PLH(b
1To x
2The 0.0027ns of)=-, t
PLH(c
1To x
2The 0.0056ns of)=-, t
PLH(b
2To x
2)=0.00126ns, t
PHL(y is to x
2)=0.307ns.Show V
B1, V
C1, V
B2And x
2Relative time of delay is very little, can ignore the influence of input stage speed.Like this, although beginning Q
12Be in dark saturation condition, its basic radio position is V
Be12=V
Bes12(base is penetrated saturation voltage drop) works as x
2The fast rise Δ
2The time, Q
12Have little time to move back saturated, be in dark saturation condition, so Q
12Base potential V
B1With fast rising Δ, the emitter follower Q that is coupled to through Ji-Ji
3Base stage, because of the emitter follower multiplication factor is 1, make Q
3Emitter potential V
B2Also with fast rising Δ, Q as a result
12Collector potential V
C1With fast rising Δ.Obviously, in fact each point rising size is not definitely to be congruent to Δ, inner each point V
B1, V
C1And V
B2Differ very little separately, show as Figure 13 and Figure 14.Because emitter follower Q
3The effect of following, form feedback loop, make V
B1, V
C1, V
B2And x
2Almost with fast rising Δ, the relative current potential of each point is constant, so allow Q
12Keep saturated.Work as x
2Behind 0.7V, find out Q at 5.6ns by Figure 15 abscissa
2Forward drive current I
B2, I
B2Mainly be Q
3Emitter current-I
E3Provide.Find out at 5.6ns by Figure 16 abscissa, and-I
E4Little spike is arranged earlier, reduce to 0 very soon, promptly show as high resistant, stop Q
12Through Q
4The collection penetrate between to b
2Path, so Q
12Do not move back saturated and do not influence speed.
Saturated pipe Q
12The unnecessary stored charge overwhelming majority at base and collector region, Q
12The emitter region does not almost have unnecessary stored charge, emitter-base bandgap grading input voltage x
2Q when low level rises
12The emitter region does not exist moves back saturation problem, and works as x
2Rise to Q behind the high level
12Pipe is in inversion state (or inverted running state), the current amplification factor β of inversion state
rVery little, be about 0.01～0.05, calculating shows, inversion state be in reverse magnifying state, far apart from saturation condition, oppositely the emitter region of magnifying state does not still almost have unnecessary stored charge, the emitter current of flowing through is summed up as emission depletion region change in charge, and this is x
2Rise to the theoretical foundation that high level does not influence speed from low level.Annotate: with this while Q
4Emitter voltage also rises, but finds out from Figure 13 the 3rd component, near abscissa 5.6ns, and V
B2-V
C1Change very little, i.e. Q
4Collection radio position changes very little, thereby Q
4Jet I
E4Change also very for a short time, be reduced to closely 0 very soon, show figure as Figure 16.
(2) input x
2Be high level, input x
1Change to low level by high level.Near Figure 10 abscissa 6.5ns, if output stage Q
2Do not have saturation condition, do not have and move back saturation problem, this transient process can be seen the inverse process of above-mentioned transient process (1) as so.Yet Q
2Be in saturation condition, remove b
2Moved back outside saturation history influences emitter follower Q with y voltage
3The effect of following also moved back saturation history and influenced.By above-mentioned same quadrat method, with amplifying near Fig. 10 abscissa 6.5ns, drawing the each point relative delay be: t
PHL(b
1To x
1)=0.034ns, t
PHL(c
1To x
1)=0.054ns, t
PHL(b
2To x
1)=0.15ns, t
PLH(y is to x
1)=0.42ns.Show b
1And c
1Voltage influenced very little, V
B1, V
C1With x
1Voltage almost descends with speed.V
B2It is slower to descend, and less than generally moving back saturation time, this is because the bleeder pipe Q that floats
4The effect of releasing.By finding out V near Figure 14 abscissa 6.5ns
C1-V
X1With x
1Voltage almost drops to nearly 0 with speed, and at the corresponding abscissa position Q of Figure 16
2Reversed peak base flow I is arranged
B2Extract out, mainly by bleeder pipe afflux I
C4Provide, part is by the I of emitter follower
E3Provide.As reduce Q
4Base resistance, can make I
C4Increase, meanwhile V
B2Decline accelerates, and notes: Q
2The time constant of pipe collector load also works.
More than change with input in (1) and (2) described process output y also changed, below (3) and (4) described process be another type, change with input that to export the y perseverance be high level, should not change.Wish V
B2Below stopping potential 0.5V, Q
2Remain off, y keeps high level, not influenced by input.
(3) input x
1Be low level, input x
2Change to low level by high level.Near Figure 10 abscissa 8ns, because x
2Be negative saltus step, it makes V
B1, V
C1And V
B2Little negative saltus step occurs, show near three components in bottom (the abscissa 8ns), V as Figure 10
B2Descend and be more conducive to Q
2End,, do not imported x so y still keeps high level
2It is the influence of negative saltus step.
(4) input x
2Be low level, input x
1Change to high level by low level.Near Figure 10 abscissa 9.5ns, because x
1Be positive transition, it makes V
B1, V
C1And V
B2Little positive transition occurs, show near three components in bottom (the abscissa 9.5ns), V as Figure 10
B2The spike of positive transition is 0.2V, below stopping potential 0.5V, and Q
2Still end,, do not imported x so y keeps high level
2It is the influence of negative saltus step.
Its reason is: because saturated pipe Q
11The unnecessary stored charge overwhelming majority at base and collector region, the emitter region does not almost have unnecessary stored charge, Q
11Emitter-base bandgap grading input voltage x
1When low level rises, do not exist and move back saturation problem, and work as x
1Rise to Q behind the high level
11Pipe is in inversion state (or inverted running state), the current amplification factor β of inversion state
rVery little, be about 0.01～0.05, calculating shows, inversion state be in reverse magnifying state, far apart from saturation condition, and inversion state be in reverse magnifying state, the oppositely Q of magnifying state
11The emitter region does not still almost have unnecessary stored charge, notes Q
12Locate saturation condition this moment, works as V
X1After rising to high level, the emitter quantity of electric charge of flowing through that is produced is summed up as emission depletion region change in charge, it and saturated pipe Q
12Unnecessary stored charge to compare be very little, can not make Q
12Move back saturated, to such an extent as to V
B2Still below stopping potential 0.5V.
Figure 10～16th, the result under the situation that drives similar load door (four), existing known t
PHL(y is to x
2)=0.307ns and t
PLH(y is to x
1)=0.42ns asks its mean value, draws average transfer delay time t
PdBe 0.37ns.The averaged static power consumption of Fig. 6 circuit is 2.7mW.As not being to drive with load class door, but drive CMOS door (being equivalent to connect capacitive load), the same method is carried out the PSPICE computer simulation, draws Figure 17～19, and Figure 18 and Figure 19 are that Fig. 17 (respectively is 5.05ns near output y rising edge and trailing edge.And near the 5.8ns) the abscissa enlarged drawing, find t by figure
PHL(y is to x
1)=0.18ns and t
PLH(y is to x
2)=0.21ns asks its mean value, draws average transfer delay time t
PdBe 0.195ns.The averaged static power consumption of this circuit is 5mW.As efferent duct Q with Fig. 6
2Change the Schottky triode into, then 1.5 volts of TTL NAND gate circuit shown in Figure 6 because the Schottky triode has anti-saturation effect, Q
2Unnecessary stored charge greatly reduce, speed will further be improved.
Fig. 6 and Fig. 8 adopt the bleeder pipe Q that floats
4, another way is to adopt the bleeder resistance R that floats
B2Show as Fig. 7 and Fig. 9 (Fig. 6 and Fig. 8 correspondence), to the closely capable as stated above PSPICE computer simulation of Fig. 7, draw Figure 20～22, for finding out the relative delay of each point accurately, near Figure 20 abscissa 11.5ns, Figure 20 is amplified, draw Figure 21, wherein the abscissa scope, is obtained each point thus and is relative time of delay to 11.787ns by 11.427ns: t
PLH(b
1To x
2The 0.021ns of)=-, t
PLH(c
1To x
2The 0.007ns of)=-, t
PLH(b
2To x
2)=0.0025ns, t
PHL(y is to x
2)=0.297ns.This shows, with V
X2Rise V
B1, V
C1And V
B2Relative delay minimum, almost rise the influence that the same reason, speed are not subjected to speed.Attention: R flows through
B2Electric current occur reducing earlier, change direction then, so Q
3Basic radio position rise Q a little
3Jet will rise to some extent, give Q like this
2Bigger forward base drive electric current is provided, find out by Figure 22, this moment I
E3Positive spike occurs, be beneficial to and quicken Q
2Conducting.Near Figure 20 abscissa 13.5ns, amplify, obtain each point thus and be relative time of delay: t
PHL(b
1To x
1)=0.039ns, t
PHL(c
1To x
1)=0.047ns, t
PHL(b
2To x
1)=0.59ns, t
PLH(y is to x
1)=0.485ns.Existing known t
PHL(y is to x
2)=0.297ns and t
PLH(y is to x
1)=0.485ns asks its mean value, draws average transfer delay time t
PdBe 0.39ns.The averaged static power consumption of Fig. 7 circuit is 3.14mW.For Q
2Same forward base drive electric current is because Fig. 7 adopts the fixing unsteady bleeder resistance R of resistance
B2, do not have to block among Fig. 6 input pipe (Q
12Or Q
11) through Q
4The collection penetrate between to b
2The effect of path, R flows through
B1Current segment be transfused to pipe base bleeder current, so the R among Fig. 7
B1Than the R among Fig. 6
B1Little.In addition, the R among Fig. 7
B2Resistance can not be too little, and the unsteady bleeder pipe among Fig. 7 is passable.
Find out input high level V by Figure 23 and Figure 24
IH〉=1.2 volts, input low level V
IL≤ 0.5 volt, output high level V
OH〉=1.3 volts, output low level V
OL≤ 0.35 volt.
Claims (4)
1. low-voltage high speed TTL NAND gate circuit, operating voltage is 1.5V, the composition of this circuit comprises logic level and output stage two parts; The input x of logic level part
1, x
2With output b
2Between be ' with ' relation, the input b of output stage part
2And be non-relation between the output y; Wherein output stage is exactly triode Q
2The inverter of emitter grounding, Q
2Collector electrode has load resistance R
C2, Q
2Base stage b
2With above-mentioned b
2It is same point; The logic level part by penetrating pipe Q more
1, emitter follower Q
3With unsteady bleeder pipe Q
4Constitute; Input signal x
1, x
2Receive and penetrate pipe Q more
1Two emitters, because of penetrate more the pipe Q
1Base stage b
1Be connected to emitter follower Q
3Base stage, so Q
1The emitter-base bandgap grading input signal through Q
1Base stage be coupled to Q
3Base stage, form Ji-Ji coupling, be coupled to Q
3Base flow pass through Q
3After tube current amplifies, again from Q
3Emitter-base bandgap grading output to inverter Q
2Base stage b
2Bleeder pipe Q floats
4Emitter-base bandgap grading and collector electrode receive Q respectively
1Collector electrode c
1And Q
2Base stage b
2, and Q
1And Q
4Base stage receive the 1.5V power supply by base electrode bias resistance separately respectively;
An above-mentioned multi-emitter pipe Q
1Two triode Q that available two base stages link to each other and link to each other with two collector electrodes
11And Q
12Equivalent electric circuit replace; Remove output stage triode Q
2Outside the available anti-saturation triode, all triodes of logic level are all without the anti-saturation triode.
2. according to claim 1 described a kind of low-voltage high speed TTL NAND gate circuit, operating voltage is 1.5V, it is characterized in that: bleeder pipe Q floats
4Can use the bleeder resistance R that floats
B2Replace; A multi-emitter pipe Q
1The emission number of poles can be greater than 2, or multi-emitter pipe Q
1A plurality of triode (the Q more than 2 that available each base stage links to each other and links to each other with each collector electrode
11, Q
12, Q
13... Q
1k, k＞2) equivalent electric circuit replace.
3. according to claim 1 described a kind of low-voltage high speed TTL NAND gate circuit, operating voltage is 1.5V, it is characterized in that: output stage triode Q
2The load resistance R of collector electrode
C2Can use high f
TLongitudinal P NP pipe Q
5Replace Q
5Base stage connect Q
2Base stage, Q
5Collector electrode connect Q
2Collector electrode, Q
5Emitter-base bandgap grading be connected to the 1.5V power supply.
4. a low-voltage high speed TTL NAND gate circuit improves the method for the speed of service, and this method is:
(1) adopts Ji-Ji coupled modes, penetrate pipe Q more
1The emitter-base bandgap grading input signal through Q
1Base stage be coupled to emitter follower Q
3Base stage, and produce Q
3Base current, form Ji-Ji coupled modes thus, this be avoid penetrating more the pipe Q
1Move back saturated influence, realize catching up with fast one of initial conditions;
(2) adopt the bleeder pipe Q that floats
4, bleeder pipe Q floats
4Collector electrode one termination Q
2Base stage b
2, Q
4Emitter-base bandgap grading one termination penetrate more the pipe Q
1(or Q
11And Q
12) collector electrode c
1, collector electrode c
1Current potential is at Q
2Unlatching current potential V
T2That change up and down or unsteady, not fixed potential; Bleeder pipe Q floats
4Cut much ice to improving the speed of service:
1. at Q
2Procedures of turn-off is worked as c
1Current potential drops to and is lower than V
T2The time, Q
4Provide the low-resistance path of releasing, Q
4Conducting resistance is very lowly optional, produces very big Q thus
2Base stage is oppositely extracted electric current out, quickens ending of output stage;
2. at Q
2Turn on process is worked as c
1Current potential is raised to and is higher than V
T2The time, Q
4The jet of pipe is reduced to very soon near 0, stops on the one hand by penetrating pipe Q more
1(or Q
11And Q
12) collector electrode c
1To Q
2Base stage b
2Or Q
3The path of emitter-base bandgap grading, make to penetrate more and guarantee adequate food and state does not influence other parts, manage Q because of path stops to make to penetrate more on the other hand
1Base flow reduces, thereby increases emitter follower Q
3Base flow is because of Q
3Jet is Q
3The β of base flow doubly produces very big Q thus
3Jet also promptly produces Q
2The very big forward drive current of base stage is quickened the conducting of output stage;
Available unsteady bleeder resistance R
B2Replace the bleeder pipe Q that floats
4, it improves speed of service effect slightly inferior to unsteady bleeder pipe Q
4
(3) an emitter follower Q is arranged in the logic level
3, Q
3Do not have saturation condition, all triodes of logic level are not the anti-saturation triodes, and do not need to use the anti-saturation triode; Work as Q
1Base stage b
1When current potential rises, because penetrate pipe Q more
1To Q
3Coupling be Ji-Ji coupling, the emitter follower multiplication factor is 1, i.e. Q
3Emitter-base bandgap grading output b
2Variable quantity and penetrate more the pipe Q
1Base stage b
1Variable quantity identical, so c
1Variable quantity and b
2Variable quantity this shows much at one, inner all each point b
1, c
1And b
2Variable quantity much at one, relatively change minimum between each point; Because the unnecessary stored charge overwhelming majority is at base and collector region, the emitter region is few, and b
1, c
1And b
2Variation is minimum relatively between each point, so still can keep its state to the triode of locating saturation condition, can not move back the speed that improves logic level under the saturated conditions;
Above-mentioned three characteristics make logic level partly form the inner member indivisible integrated circuit structure that feedback is arranged mutually, claim that this is that feedback is caught up with and floating type logic level circuit; Based on this method, operating voltage is the low-voltage high speed TTL NAND gate circuit average transfer delay time t of 1.5V
PdBe generally less than 0.4ns, can reach 0.2ns or littler.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510009707XA CN1306707C (en) | 2005-02-04 | 2005-02-04 | Low voltage high speed TTL and Not gate circuit and its method for improving operation speed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510009707XA CN1306707C (en) | 2005-02-04 | 2005-02-04 | Low voltage high speed TTL and Not gate circuit and its method for improving operation speed |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1649271A true CN1649271A (en) | 2005-08-03 |
| CN1306707C CN1306707C (en) | 2007-03-21 |
Family
ID=34875418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200510009707XA Expired - Fee Related CN1306707C (en) | 2005-02-04 | 2005-02-04 | Low voltage high speed TTL and Not gate circuit and its method for improving operation speed |
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| Country | Link |
|---|---|
| CN (1) | CN1306707C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107508613A (en) * | 2017-07-04 | 2017-12-22 | 广州致远电子有限公司 | Transmission circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57188138A (en) * | 1981-05-15 | 1982-11-19 | Nec Corp | Logical gate circuit |
| US4607175A (en) * | 1984-08-27 | 1986-08-19 | Advanced Micro Devices, Inc. | Non-inverting high speed low level gate to Schottky transistor-transistor logic translator |
| CN1184380A (en) * | 1996-12-06 | 1998-06-10 | 张宗雪 | Integrated circuit or refresh technology |
-
2005
- 2005-02-04 CN CNB200510009707XA patent/CN1306707C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107508613A (en) * | 2017-07-04 | 2017-12-22 | 广州致远电子有限公司 | Transmission circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1306707C (en) | 2007-03-21 |
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