CN1184380A - Integrated circuit or refresh technology - Google Patents

Integrated circuit or refresh technology Download PDF

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Publication number
CN1184380A
CN1184380A CN96117362A CN96117362A CN1184380A CN 1184380 A CN1184380 A CN 1184380A CN 96117362 A CN96117362 A CN 96117362A CN 96117362 A CN96117362 A CN 96117362A CN 1184380 A CN1184380 A CN 1184380A
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new
note
suspense
chain
circuit
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张宗雪
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Priority to CN96117362A priority Critical patent/CN1184380A/en
Priority to AU51867/98A priority patent/AU5186798A/en
Priority to PCT/CN1997/000138 priority patent/WO1998025344A1/en
Publication of CN1184380A publication Critical patent/CN1184380A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/355—Monostable circuits

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  • Power Engineering (AREA)
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  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

The present invention is an epoch-making integrated circuit or a new technology. It features that (1) only one OR gate can be used to form new RS trigger and monostable trigger, and compared with original technique, it has the advantages of saving a lot of elements and internal lines, high speed, low power consumption and high reliability. (2) The BiCMOS stable new technology can greatly simplify and optimize large-scale integrated circuits. (3) R and C are not changed, and the transient time of the monostable trigger and the frequency of the pulse oscillator are directly controlled to change in a large range by using the level. (4) A new device with special multifunction can greatly reduce the variety of integrated circuits, and has wide application and convenient and flexible use. The invention will certainly bring great changes to the integrated circuit.

Description

Integrated circuit or note new technology
Integrated circuit or note new technology are that inventor Zhang Zongxue utilization oneself proposes " or the note circuit is surely remembered law " in May, 1986 and reach " or note circuit suspense law " and the epoch-making invention of great significance that obtains is remembered new technology.It comprises that integrated circuit remembers that surely new technology, integrated circuit suspense new technology and one of integrated circuit have special multifunctional novel technology.
Steady note circuit and suspense circuit
Circuit can be stablized the circuit function of (promptly irrelevant with the time) or certain hour ground replacement input signal, thereby the output state when making circuit still stable or certain hour ground behind blackout keep moment to finish the replacement signal, such logical circuit claims memory circuit.
The memory of signal is not changed in time, and promptly the memory circuit of memory signal stably claims steady note circuit.The output Q of steady note circuit xExpression.
For example rest-set flip-flop, d type flip flop, JK flip-flop, magnetic memory, counter, digital register, shift register etc. all are surely to remember circuit.
To behind the signal memory certain hour and erase automatically,, claim the suspense circuit promptly to the time dependent memory circuit of the memory of signal.
For example monostable flipflop, multivibrator and multifunctional pulse oscillator all are the suspense circuit.
The suspense circuit of suspense high level or low level signal claims high level or low level monostable flipflop in the past, its output Q +Expression.Pulse oscillator output is represented with Q .
Similar or logic
1. import codomain and output codomain
The permission value zone of input signal logic level claims the input codomain.The permission region of variation of signal output logic level claims to export codomain.
2. the foreign peoples exports input and similar output input
The signal value output territory is not within the signal input value territory or sign is exported, the physical quantity of input logic state is different in nature, and promptly both are not same class physical quantitys, and such output and input claim foreign peoples's output and import that the abbreviation foreign peoples exports input.
The signal value output territory claims similar output and input in the output and the input of (as long as the signal value output territory is within the input codomain at a signal input part) within the signal input value territory, is called for short similar output input.
3. similar or logic
Between the similar output input " as long as there is one to be input as 1 (1 expression has signal), then output is exactly and imports similar 1 " this logical relation, claim similar or logic.Sometimes be called for short similar or.Similar or logic is the basis that replaces memory.
The memory chain
Signal output send back to replace input after, can replace the circuit function of input signal, thereby make output behind blackout, still keep moment to finish output state when replacing signal, the input circuit of this output claims to remember chain.The memory chain claims memory fact again.
Replace input and claim to remember chain end, with j or j cExpression.The memory chain be the external cause that realize to replace memory function, adequate condition, must be through bridge.The memory chain has two kinds on steady note chain and suspense chain.
1. surely remember chain
Signal output send back to replace input after, can be stably (promptly with time irrespectively) replace the circuit function of input signal, thereby the output state when making output still stably keep replacing signal behind blackout, such memory chain claims surely to remember beam.Claim the steady note factor again.Steady note chain end is represented with j.
The circuit form of steady note chain mainly contains two kinds, and a kind of is the steady note chain of an on line; Another kind is the steady note chain of band controlled switch.
Steady note chain with the most use is the steady note chain of an on line.With an on line output of signal or note circuit (treating aftermentioned) is linked to each other with its replacement input j, just constitute the steady note chain of an on line, very simple.The steady note chain of an on line is memoryless signal or the qualitative change of note circuit steady note circuit.Its logical symbol be "
Figure A9611736200051
"
2. suspense chain
The principle of utilizing the electric capacity both end voltage not suddenly change, the output of signal by electric capacity send back to replace input after, through putting, charging of RC circuit and circuit function that can certain hour ground replacement input signal, thereby make output output state when replacing signal still behind blackout, behind the corresponding maintenance certain hour and erase automatically, such memory chain claims the suspense chain.Suspense chain end j cExpression.
The suspense chain has two kinds on monodrome suspense chain and diadic suspense chain.
(1) monodrome suspense chain
The circuit of monodrome suspense chain is by timing level V z, timing resistor R z, timing capacitor C zForm.C zMust be connected on the output and the suspense chain end j of signal or note circuit cBetween, R zBe connected on j cHold and connect regularly level V zBetween the end, shown in Fig. 1 (a).(2) diadic suspense chain diadic suspense chain circuit is by the timing high level
Figure A9611736200052
Timing resistor R zAnd R ' z, timing capacitor C zForm with the non-door switch N of single tube of signal or note circuit output control.Equally, C zMust be connected on signal or note circuit output end and suspense chain end j cBetween.R zBe the empty resistance of arteries and veins, R ' zBe pulsewidth resistance.Diadic suspense chain circuit is shown in Fig. 1 (b).
Memory chain principle and replacement memory two criterions
1. remember the chain principle
Exclusive similar or logic just has the memory chain, and other any logics, as with all memoryless chains such as logic, foreign peoples or logic, NAND Logic, NOR-logic.
2. replace memory two criterions
Realize the replacement memory to input signal, must follow two criterions: one must be the similar or logic of signal, and two must connect memory chain similar or that logic is exclusive.Criterion one is basis, internal cause, the necessary condition that replaces memory.Criterion two is external cause, the adequate condition that replace memory.
Or note logic
Not only have similar between the output input or logic (containing the similar or logic of equivalence), and more important more usefully by connecing the logic function of remembering input signal behind its exclusive memory chain in addition, the logical relation between this output input claims or remembers logic.Perhaps briefly, similar or logic (contain equivalence similar or logic) and its memory chain exclusive and to be connect are called or remember logic.
Signal or note circuit
Can realize that circuit signal or the note logic claims signal or note circuit, be called for short or note circuit or or note door.
Input signal and its output are similar or the note circuit input end, claim or note circuit in-phase input end, represent with H.
Input signal and its output are anti-phase or the note circuit input end, claim or note circuit inverting input, represent with F.
Or the note circuit all has signal in-phase input end H and signal inversion input F.Or note circuit memory chain end exclusive and to be connect, promptly replace input j, obviously at in-phase input end.
Or note only provide in-phase input end H in the circuit, claim H or note door.
According to level signal is constituted or note Men Laifen, three kinds at low level or note door, high level or note door and high-low level or note door arranged.
1. low level or note door are exactly to be or note door (containing equivalent low level or note door) to low level signal.
2. high level or note door are exactly to be or the note door to high level signal.
3. high-low level or note door concerning high level signal and low level signal all are or the note door exactly.High-low level or note door claim single input or note door, homophase device again.
According to constituting or the circuit structure of note door divides, mainly contain or type or note door, equivalence or note door, expansion or note door, collector electrode output or note door.
1. or type or note door, be exactly or the type circuit structure or the note door.Have or type low level or note door or type high level or note door or type low level H or note door or type high level H or note door or input of type list or note door.
2. equivalence or note door claim again or non-or note door.It is to constitute an equivalent HF input or note door by two NOR gate.
3. expansion or note door, actual be exactly high level with or door, promptly low level or with door.
4. integrated utmost point output or note door, it is the low level or the note door of transistor collector output.
Or the logic diagram of note door for example
Fig. 2 (a) is or the logic diagram of type low level or note door, (b) be or the logic diagram of type high level or note door, (c) be or the logic diagram of type low level H or note door, (d) be the logic diagram of single input of CMOS or note door, (e) be the logic diagram of input of bipolar integrated circuit or type list or note door, (f) be or the logic diagram of non-low level or note door (g) be or the logic diagram of non-high level or note etc.
The problems referred to above go up volume detail as per inventor's monograph " or note opinion ".
Or the note circuit is surely remembered law
After signal or note circuit connect its exclusive steady note chain, claim steady note cell.It is surely to remember the signal of in-phase input end with the signal homomorphism; Surely to remember the signal of inverting input with the anti-attitude of signal.The reentry signal, the note attitude is constant.Signal works, and the time that can not withdraw equals the time that it replaces signal.Or the note circuit is obstructed, and then it loses the memory of.Or the steady note of note circuit is by one or more steady note cell organic composition.
High level and low level remember that surely cell claims high level and low level HF surely to remember device again, claim it is high level and low level rest-set flip-flop by the past.
Or note circuit suspense law
Signal or note circuit connect the suspense chain, can suspense signal certain hour after and erase automatically, claim the suspense cell.It with the signal of signal homomorphism suspense in-phase input end; With with the signal of the anti-attitude suspense of signal inverting input.The reentry signal, the note attitude is constant.Close the door with signal, then it is not remembered.The time that signal works, can not withdraw equals the time that it replaces signal.Memory time and level regularly, resistance, electric capacity are relevant.
High level and low level suspense cell claim high level and low level suspense device again, claim it is high level and low level monostable flipflop by the past.
Or relation between the note
Similar or and memory between relation be called for short or note between relation.
Or have inherent and external substantial connection between the note.
Or the inherent substantial connection between the note
This similar or characteristic of " as long as an input is arranged is 1; then output is exactly and imports similar 1 " between the similar output input (contain equivalence similar or) is basis, the internal cause that replaces the memory logic function, and the memory logic function is similar or characteristic special and profound performance form and the highest application form.
Or the external substantial connection between the note
Signal or note door have similar or and memory two big logic functions.Specifically, signal or note door generally have four kinds of operating states and four kinds of respective logic functions.
1. when signal or note door did not connect its exclusive memory chain, it was exactly memoryless similar or a door or non-equivalent similar or (the signal NOR gate) of signal.It is in similar or the logic working state, follows memoryless similar or rule.
2. after signal or note door connect its exclusive steady note chain, just be changed into the steady note circuit of a steady note in-phase input end or inverting input signal by a memoryless signal or note door, it is in the operating state of steady note input signal, follows or remembers that circuit surely remembers law.
3. after signal or note door connect its monodrome suspense chain, just there are a memoryless signal or note door to be changed into the suspense circuit of a suspense in-phase input end or inverting input signal, it is in suspense input signal operating state during suspense, follows or remembers circuit suspense law.
4. after signal or note door connect its diadic suspense chain, just be changed into an output and replace suspense j with high-low level by a memoryless signal or note door cGive birth to the controlled multifunctional novel pulse oscillator of high and low level signal in the end.The empty time-delay of its frequency of oscillation and arteries and veins and timing high level, timing resistor, timing capacitor are relevant, and pulsewidth and pulsewidth resistance, electric capacity are relevant.
Signal or note door, signal remember that surely the common inner core of circuit (signal is surely remembered cell), signal suspense circuit (signal suspense cell), these four kinds of different operating circuit of pulse oscillator is signal or note door (internal cause), just do not connecing the memory chain, connecing steady note chain, order value suspense chain, connecing under these four kinds of different external conditions (external cause) of diadic suspense chain, and four kinds of different circuit and four kinds of respective logic functions of producing.This erect image crystal triode transistor is the same.Transistor is with same internal cause condition (the internal structure feature of transistor), and under three kinds of extraneous conditions of work of difference (base stage bias current I BIn the amplification region, I BIn the saturation region, I BAt cut-off region), then have amplification, saturated, by these three kinds of different operating states.
With CMOS and LSTTL integrated circuit is that example illustrates that integrated circuit surely remembers new technology.
Integrated circuit is surely remembered the feature of new technology
Integrated circuit remembers that surely new technical feature one is, integrated circuits such as LSTTL, TTL, HTL, ECL, new technology only just can constitute a new low level HF with one or type low level or note door or one or type high level or note door and surely remember device (claiming it is new low level rest-set flip-flop by the past).Its logic diagram is shown in Fig. 3 (a) and (b).Former technology then is to constitute a former traditional low level rest-set flip-flop with two low level NOR gate or two high level NOR gate.Obviously, the new technology circuit is greatly simplified and is optimized than former technology circuit.
Integrated circuit remembers that surely new technical feature two is, connect the steady note chain of an on line and by meeting in-phase input end H and the inverting input F that the silicon diode way provides low level signal or high level signal with single input of CMOS or note door (a homophase device), thereby constitute the new low level of CMOS or new high level HF surely remembers device (claiming it is new low level or new high level rest-set flip-flop by the past).Its logic diagram is shown in Fig. 3 (c), (d).And former technology is to constitute low level or high level rest-set flip-flop with two low level NOR gate or two high level NOR gate.Obviously, the new technology circuit is very simpler than former technology circuit.
The logic diagram of former traditional rest-set flip-flop is shown in Fig. 4 (a) and (b).
Integrated circuit remembers that surely new technical feature three is, connect the steady note chain of an on line and, surely remember device (claiming it is the controlled new low level rest-set flip-flop of BiCMOS) with single input of a CMOS or note door by the past thereby constitute the controlled new low level HF of BiCMOS by meeting in-phase input end H and the inverting input F that TTL high level NAND gate way provides its output low level signal.Its logic diagram as shown in Figure 5.
Integrated circuit is surely remembered new technology (is example with LSTTL, CMOS, BiCMOS) for example
The CMOS computer keyboard disappears and trembles new technology
Fig. 6 (a) trembles former technical unit circuit for the CMOS computer keyboard disappears.(b) and (b ') be the new technology element circuit.The used element of former technology is three times of new technology, and former technology power consumption is 1000 times of new technology approximately.Obviously, the new technology circuit is very superior.
Fig. 7 (a) is for to constitute former low level rest-set flip-flop with two low level NOR gate.(b) constitute new low level rest-set flip-flop for a steady note chain that connects an on line with or type low level or note door.(c) and (d) be to connect the steady note chain of an on line and constitute the new low level rest-set flip-flop of the little amplitude of oscillation with a little amplitude of oscillation or type low level or note door.Obviously, the new technology circuit is greatly simplified and is optimized than former technology circuit.
The new low level HF of CMOS surely remembers device (claiming it is new low level rest-set flip-flop by the past)
Fig. 8 (a) is the former traditional low level rest-set flip-flop of CMOS.(b) be the new low level rest-set flip-flop of CMOS.
Fig. 9 surely remembers device (claiming it is controlled new low level rest-set flip-flop by the past) for the controlled new low level HF of BiCMOS.
Figure 10 is the new d type flip flop circuit of BiCMOS.It is the new low level rest-set flip-flop of CMOS at full note circuit newly.
Figure 11 is new eight ternary register 1/8 circuit of BiCMOS.It is the new low level rest-set flip-flop of CMOS at full note circuit newly.
Figure 12 is the new JK flip-flop of BiCMOS.It is the new low level rest-set flip-flop of CMOS at full note circuit newly.
Figure 13 is that BiCMOS two claps the group of four figures register circuit of work.
The BiCMOS that circuit is greatly simplified and optimized remembers that surely new technology is most valuable, has great practical value.It can make on a large scale, very lagre scale integrated circuit (VLSIC) is simplified greatly and optimize.
Figure 14 (a) is the former static storage cell of CMOS.(b) be the new static storage cell of CMOS.New static storage cell is simpler than former static storage cell, the saving element.
Figure 15 (a) is the former d type flip flop circuit of LSTTL.(b) be the new d type flip flop circuit of LSTTL.It is the new low level rest-set flip-flop of LSTTL at full note circuit newly.(c) be the new d type flip flop of the little amplitude of oscillation of LSTTL.It is the new low level rest-set flip-flop of the little amplitude of oscillation of LSTTL at full note circuit newly.
Figure 16 (a) is the former JK flip-flop circuit of LSTTL.(b) be the new JK flip-flop circuit of LSTTL.It is the new low level rest-set flip-flop of LSTTL at full note circuit newly.(c) be the new JK flip-flop of the little amplitude of oscillation of LSTTL.It is the new low level rest-set flip-flop of the little amplitude of oscillation of LSTTL at full note circuit newly.
With CMOS and LSTTL integrated circuit is that example illustrates integrated circuit suspense new technology.
The feature of integrated circuit suspense new technology
The feature one of suspense new technology is that new monodrome suspense chain circuit is by timing level V z, timing resistor R z, timing capacitor C zForm.C zMust be connected on output Q +With suspense chain end j cBetween, R zBe connected on j cHold and connect regularly level V zBetween the end.The V of new monodrome suspense chain z, R z, C zThe three determines memory time length.Former monodrome suspense chain circuit is by timing level R z, timing capacitor C zForm.Equally, C zMust be connected on output Q +With suspense chain end j cBetween, timing resistor R zOne terminates at j cThe end, and the other end be connected on " " or supply voltage on.New monodrome suspense chain has comprised former monodrome suspense chain.Former monodrome suspense chain is timing level V in the new monodrome suspense chain zTerminate at " " or supply voltage on an edge end special case.The R of former monodrome suspense chain z, C zBoth decide memory time length.
Suspense new technical feature two is R z, C zConstant, can be directly with timing level V zControl suspense device memory time length.And the memory time of new technology is than long several times to tens times (both R of the memory time of former technology z, C zThe same).
Connect new monodrome suspense chain and constitute brand-new suspense device (claiming it is brand-new monostable flipflop) with one or type or note door by the past.Connect new monodrome suspense chain and by meeting the inverting input F that the silicon diode way provides low level signal (perhaps high level signal) with single input of CMOS or note door, thereby constitute the brand-new monostable flipflop of CMOS.Form an equivalence or note door with a NOR gate and not gate, connect new monodrome suspense chain again and constitute new suspense device (new monostable flipflop).Figure 17 (a) is the logic diagram with or type low level H or the brand-new low level monostable flipflop of note door formation.(b) be a logic diagram with one or type high level H or the brand-new high level monostable flipflop of note door formation.(c) for constitute the logic diagram of the brand-new low level monostable flipflop that low level signal imported by in-phase input end H with one or type low level or note door.(d) for constitute the logic diagram of the brand-new low level monostable flipflop that low level signal imported by inverting input F with one or type low level or note door.(e) be with one or a type high level or a note brand-new high level monostable flipflop logic diagram that the formation high level signal is imported by in-phase input end H.(f) for constitute the logic diagram of the brand-new high level monostable flipflop that high level signal imported by inverting input F with one or type high level or note door.(g) for connecting new monodrome suspense chain with single input of CMOS or note door and by meeting the inverting input F that the silicon diode way provides low level signal, thus the logic diagram of the brand-new low level monostable flipflop of formation CMOS.(h) be the logic diagram of the brand-new high level monostable flipflop of CMOS.(i) be a logic diagram with one or non-equivalent low level H or the new low level monostable flipflop of note door formation.
The logic diagram of former traditional low level monostable flipflop is shown in Figure 18 (a).The logic diagram of former traditional cmos high level monostable flipflop is shown in Figure 18 (b).
The memory time of brand-new and new monostable flipflop is than much longer (both R of the memory time of former monostable flipflop z, C zThe same).With "
Figure A9611736200091
" represent that the input low level signal works, can not withdraw the low level in moment; With "
Figure A9611736200092
" represent that the input high level signal works, can not withdraw the high level in moment.Do not mark dot with the upper right corner
Figure A9611736200093
Perhaps Represent no significant level signal.
Three, suspense new technical feature three is, with timing high level V zDirectly the arteries and veins of the new pulse oscillator of control is empty than changing, from greater than 1 to equal 1 and much smaller than 1 or the arteries and veins sky change significantly and pulsewidth is constant.The frequency of new pulse oscillator is by the timing high level
Figure A9611736200095
, timing resistor R z, R z, timing capacitor C zDecide.And the frequency of former pulse oscillator is by R z, C zDecide.
Connect diadic suspense chain and constitute the multifunctional novel pulse oscillator with one or type or note door or single input of CMOS or note door or one or non-equivalence or note door.
Connect diadic suspense chain and constitute the multifunctional novel pulse oscillator with one or type low level H or note door or one or type high level H or note door or single input of CMOS or note door or CMOS low level H or note door etc., its logic diagram is respectively shown in Figure 19 (a) and (b), (c), (d).Wherein (d) becomes the window pulse oscillator for Fixed width.
Integrated circuit suspense new technology for example
New, the former monostable flipflop of CMOS integrated circuit for example
Figure 20 (a) is the former low level monostable flipflop of CMOS.(b) be the new low level monostable flipflop of CMOS.It is new at monodrome suspense chain newly.(c) be the new low level monostable flipflop of CMOS.(d) be the brand-new low level monostable flipflop of CMOS.It newly monodrome suspense chain and or note door all be new.
New, the former monostable flipflop of LSTTL integrated circuit for example
Figure 21 (a) is the former low level monostable flipflop of LSTTL.(b) and (c) be the brand-new low level monostable flipflop of LSTTL.They newly monodrome suspense chain and or note door all be new.(d) be the brand-new high level monostable flipflop of LSTTL.It newly monodrome suspense chain and or note door all be new.
CMOS and the new pulse oscillator of LSTTL integrated circuit are for example
Figure 22 (a) is the multi-functional controlled new pulse oscillator circuit of CMOS.(b) be CMOS multifunctional novel pulse oscillator circuit.(c) be the multi-functional controlled new pulse oscillator circuit of LSTTL.
Two laws disclose integrated logic circuit that tradition divides, sequence circuit, impulse circuit three's common inner core-or note circuit first.Common inner core or note circuit are united the three, have removed three artificial wide gaps can not more getting between the three.So can design and produce one and have special multi-functional new unit.A special multifunctional novel device, not only purposes is wide, use is extremely convenient, the more important thing is, can significantly reduce the integrated circuit kind.This design to the production of manufacturer and user, use, maintenance etc. all bring great benefit and convenient.A special multifunctional novel device is very popular.
Figure 23 is for designing the omnipotent basic new unit ZC01 line map of the CMOS that produces.
Figure 24 is for designing the special multifunctional novel device of the LSTTL ZL01 line map of producing.
The omnipotent basic new unit ZC01 of CMOS mainly contains following logic function: or door, NOR gate, with door, NAND gate, with or the door, AND and low level HF surely remember device (low level rest-set flip-flop), high level HF surely remembers device, digital register, D surely remembers device (d type flip flop), JK surely remembers device (JK flip-flop) and new high level suspense device (new high level monostable flipflop), new low level suspense device, level is directly controlled frequency divider on a large scale, level is directly controlled continuously adjustable timing and delayer on a large scale, Schmidt trigger, square-wave generator, controlled square-wave generator, multivibrator, can empty multivibrator, blocking oscillator, triggered blocking generator, regularly high level is directly controlled the empty size of vibration arteries and veins, and the constant new oscillator of pulsewidth, regularly directly to control arteries and veins empty than from changing to 1 and much smaller than 1 pulse oscillator greater than 1 for high level, ultralow frequency pulse oscillator etc.

Claims (10)

  1. One, integrated circuit remembers that surely new technology claim one is, the new HF of bipolar integrated circuit LSTTL, FLSTTL, TTL, ECL, HTL etc. remembers that surely device (new rest-set flip-flop) is only to connect its exclusive on line with one or type HF or note surely to remember chain and constitute.And former technology HF remembers that surely device (former rest-set flip-flop) is to form equivalent HF or note door with two NAND gate or two NOR gate or two AND, connects the steady note chain of an on line again and constitutes.
  2. Two, integrated circuit remembers that surely new technology claim two is, the new D of bipolar integrated circuit remembers that surely the full note circuit of doing output in that device (new d type flip flop), new JK surely remember device (new JK flip-flop), various refresh counter, new register, new shift register etc. or the steady note of the note circuit new unit all is surely to remember device (contain little amplitude of oscillation HF and surely remember device) with greatly simplifying the new HF that optimizes.
  3. Three, integrated circuit remembers that surely new technology claim three is, the new HF of CMOS integrated circuit surely remember device be with single input of CMOS or note door connect an on line steady note chain and with connect the silicon diode way provide the in-phase input end H of signal and inverting input F and constitute the new high level HF of CMOS surely remember device or newly low level HF surely remember device.Connect the steady note chain of an on line and, surely remember device with single input of a CMOS or note door thereby constitute the controlled new low level HF of BiCMOS by meeting in-phase input end H and the inverting input F that TTL high level NAND gate way provides its output low level signal.
  4. Four, claim four is, BiCMOS remembers that surely the full note circuit in the new d type flip flop of new technology, new JK flip-flop, various counter, the register etc. all is the new low level rest-set flip-flop of CMOS.
  5. Five, the CMOS computer keyboard shake new technology element circuit that disappears is that the new HF of CMOS of claim three remembers that surely device constitutes.Two resistance that do not have former technology.The element of new technology is 1/3 of a former technology, and power consumption is 1/1000 of a former technology.
  6. Six, the group of four figures register of BiCMOS two bat work is that claim three is mixed formation.Be that clear terminal provides with connecing the silicon diode way, and the inverting input that receives digital output low level signal is to provide with connecing TTL high level NAND gate way.
  7. Seven, integrated circuit suspense new technology claim one is, new monodrome suspense chain circuit is by timing level V z, timing resistor R z, timing capacitor C zForm.C zMust be connected on output Q +With suspense chain end j cBetween, R zBe connected on j cHold and connect regularly level V zBetween the end.The V of new monodrome suspense chain z, R z, C zThe three decides memory time length.Former monodrome suspense chain circuit is by timing resistor R z, timing capacitor C zForm.Timing resistor R zOne terminates at j cThe end, and the other end be connected on " " or supply voltage on.New monodrome suspense chain has comprised former monodrome suspense chain.Former monodrome suspense chain be in the new monodrome suspense chain regularly level be connected on " " or supply voltage on an edge special case.The R of former monodrome suspense chain z, C zBoth decide memory time length.Integrated circuit suspense new technology can make R z, C zConstant, and directly with timing level V zControl memory time length.And the new memory time is than normal several times to tens times (both R of the memory time of former technology z, C zThe same).
    Integrated circuit suspense new technology claim one specifically is, connects new monodrome suspense chain and constitutes brand-new suspense device (claiming it is brand-new monostable flipflop by the past) with one or type or note door (one or type HF or note door or one or type H or note door or equivalent F or note door).Connect new monodrome suspense chain and by meeting the inverting input F that the silicon diode way provides low level signal (perhaps high level signal) with single input of CMOS or note door, thereby constitute the brand-new monostable flipflop of CMOS.Form an equivalence or note door with a NOR gate and not gate, connect new monodrome suspense chain again and constitute new suspense device (new monostable flipflop).Memory time brand-new and new monostable flipflop is grown several times to tens times (both R than the memory time of former monostable flipflop z, C zThe same).
  8. Eight, suspense new technology claim two is to use high level
    Figure A9611736200021
    Directly the arteries and veins of the new pulse oscillator of control empty than from greater than 1 change to equal 1 and much smaller than 1 or control arteries and veins sky change significantly and pulsewidth is constant.The frequency of new pulse oscillator is by the timing high level Timing resistor R z, R zWith timing capacitor C zFour decide.And the frequency of former pulse oscillator is by R z, C zBoth decide.Connect diadic suspense chain and constitute the multifunctional novel pulse oscillator with one or type or note door or single input of CMOS or note door or equivalence or note door.Can constitute CMOS ultralow frequency pulse oscillator.
  9. Nine, claim nine is, the new static storage cell of CMOS is the single line read-write, rather than the two-wire write circuit structure of former technology.
  10. Ten, claim ten is, one have special multifunctional novel technology be the integrated logic circuit that discloses with two laws, sequence circuit, impulse circuit three common inner core-or the note circuit be core, this core is multi-functional comprehensive or note circuit, be with D outward and remember partly that once circuit, JK remember partly that once circuit matches, connect steady note chain, monodrome suspense chain, diadic suspense chain of an on line etc. respectively, just can constitute one and have special multi-functional new unit.
CN96117362A 1996-12-06 1996-12-06 Integrated circuit or refresh technology Pending CN1184380A (en)

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CN96117362A CN1184380A (en) 1996-12-06 1996-12-06 Integrated circuit or refresh technology
AU51867/98A AU5186798A (en) 1996-12-06 1997-12-03 An or-type memorizing integrated circuit
PCT/CN1997/000138 WO1998025344A1 (en) 1996-12-06 1997-12-03 An or-type memorizing integrated circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1306707C (en) * 2005-02-04 2007-03-21 黑龙江大学 Low voltage high speed TTL and Not gate circuit and its method for improving operation speed

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JPS5915567B2 (en) * 1979-07-19 1984-04-10 富士通株式会社 CMOS Schmitt circuit
GB8420651D0 (en) * 1984-08-14 1984-09-19 British Telecomm Interface circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1306707C (en) * 2005-02-04 2007-03-21 黑龙江大学 Low voltage high speed TTL and Not gate circuit and its method for improving operation speed

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