WO1998025344A1 - An or-type memorizing integrated circuit - Google Patents

Abstract

An OR-Type memorized integrated circuit, characterized that RS trigger and monostable trigger etc. are constituted by one OR gate instead of by two gates as in the prior art, and that the temporarily memorizing time of the monostable trigger can be controlled by timing level and oscillating frequency can be changed in a wide range, both of them are determined by timing level, resistor and capacitor. The BiMOS circuit disclosed in the present invention is of simple structure and has good performances. A fundamental new CMOS device having variety of functions is also provided by the present invention.

Description

 FIELD OF THE INVENTION Field of the Invention

 The present invention generally relates to integrated circuits, and more particularly, to memory integrated circuits. Background technique

 In the prior art, in order to constitute a basic RS flip-flop or a monostable flip-flop, two NAND gates or two NOR gates are required. Therefore, there are disadvantages such as using a large number of components, having a large number of internal wiring, low speed, high power consumption, low reliability, and large size. At the same time, because the temporary recording time of the original monostable flip-flop is determined by both the timing resistor and the timing capacitor, there is a disadvantage that the temporary recording time is not easy to control. The oscillation frequency of the original pulse oscillator is also determined by both the timing resistor and the timing capacitor, so there is a disadvantage that the oscillation frequency is not easy to control.

 Therefore, an object of the present invention is to provide a basic RS flip-flop and a monostable flip-flop (^ In the present invention, a circuit having memory properties such as an RS flip-flop and a monostable flip-flop is collectively referred to as or a memory circuit ), They have the advantages of fewer components, so fewer internal connections, high speed, low power consumption, high reliability, small size and so on. Technical solutions

 In order to achieve the above objective, the present invention provides a NOR memory integrated circuit, which includes an OR gate and a memory chain, the OR gate includes an output terminal (Q) and a plurality of replacement input terminals (r). At the internal input, the memory link is between the output of the OR gate and the replacement input.

 The invention also provides a new device with special multi-function, which includes three parts of a double-valued signal input circuit, a once-and-a-half circuit, and two-level signal expansion or gate.

 It can be seen from the technical solution of the invention that the present invention implements a memory IC with only one OR gate, so it has fewer components, so fewer internal connections, high speed, low power consumption, high reliability, Small size and other advantages. Because the present invention also introduces timing levels in the single-valued memory chain and the double-valued memory chain at the same time, so that the temporary recording time of the monostable flip-flop and the oscillation frequency of the pulse oscillator are easy to control.

Brief description of the drawings

In order to better understand the present invention, the following describes the advantages of the present invention by referring to the accompanying drawings. The alternative embodiment is described in detail. In the drawings:

 Figure 1 is an example of a diode low-level hetero OR gate, where (a) is a circuit diagram and (b) is a logic diagram;

 FIG. 2 is an example of an emitter output high-level hetero-OR gate, where (a) is a circuit diagram, and (b) is a logic diagram;

 1

 Figure 3 is a 74LS08 low-level homologous OR gate circuit diagram; 1

 Figure 4 is the same high-level OR gate circuit diagram of S32;

 4

 FIG. 5 is an example of a connected stable memory chain, where (a) is a logic diagram of a low-level OR memory circuit, and (b) is a logic diagram of a low-level CI memory stabilizer of the present invention;

 FIG. 6 is an example of a single-valued temporary diary chain of the present invention, where (a) is a low-level OR circuit diagram, and (b) is a logic diagram of the low-level diary of the present invention;

 7 is an example of a double-valued temporary register chain, where (a) is a logic diagram of a low-level OR register circuit, and (b) is a logic diagram of a controllable multifunctional pulse oscillator of the present invention;

 FIG. 8 is an analog suspense chain, where (a) is a low-level C or gate logic diagram, (b) is a low-level analog stylus logic diagram of the present invention, and (c) is a high-level C or gate gate A logic diagram, (d) is a logic diagram of a high-level analog register of the present invention;

 Figure 9 is the LSTTL or low-level or gated circuit diagram;

 Figure 10 is a LSTTL or high-level or gated circuit diagram;

 Figure 11 is an ECL or high-level or gated wiring diagram;

 Figure 12 is a TTL two-gate equivalent low-level or gate-keeping circuit diagram;

 Figure 13 is a LSTTL or high-level extension or i-gate circuit diagram;

 Figure 14 is a low-level or gated circuit diagram of the TTL collector output;

 Figure 15 is a CM 0 S single input or gated wiring diagram;

FIG. 16 is a conventional high-level monostable flip-flop (t _T 0.7R _t C _t ) of the CM OS, where (a) is a circuit diagram, and (b) is a logic diagram;

FIG. 17 is a low-level monostable flip-flop (t _T >> t _T »0.7R _t C _t ) of the CM OS of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

FIG. 18 is a CM OS high-level monostable flip-flop (t _T 〉> t _T ≦ 0.7R _t C _t ) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

19 is a CM OS multi-function pulse oscillator of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram; 20 is a CM OS controllable multifunctional oscillator according to the present invention, where (a) is a circuit diagram, (b) is a logic diagram, (c) is a circuit diagram, and (d) is a logic diagram;

 FIG. 21 is a CMOS original high-level RS flip-flop, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 22 is a CM 0 S low-level C I stabilizing device (^ invention CM O S low-level RS flip-flop) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 23 is a CM 0 S high level C I stable register of the present invention (^ invention CM O S high level RS flip-flop), where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 24 is a unit circuit of a computer keyboard CMOS debounce original technology, where (a) is a circuit diagram, and (b) is a logic diagram;

 25 is one of the CM 0 S debounce unit circuits of the computer keyboard of the present invention, where (a) is a circuit diagram and (b) is a logic diagram;

 FIG. 26 is the second circuit of the CM 0 S debounce unit of the computer keyboard of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 27 is a CMOS original static memory cell circuit, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 28 is a single-line read / write CM OS static storage unit according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 29 is a BiCM 03 controllable (1 stable register (^ invention 8 1 ^ 0 S controllable high-level RS flip-flop) of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 30 is a four-digit digital register of B iCM 0 S working in the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 31 is a D-type flip-flop of BiCM 0 S according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 1

 FIG. 32 is a circuit diagram (tri-state) of the circuit diagram of the B iC M 0 S eight-bit register of the present invention;

 0

 FIG. 33 is a circuit diagram of a D flip-flop of BiCM 0 S of the present invention; FIG.

 FIG. 34 is a circuit diagram of a JK flip-flop of B iC M 0 S of the present invention; FIG.

 FIG. 35 is a circuit diagram of a B iCM 0 S four-bit binary counter according to the present invention; FIG.

FIG. 36 is an LSTTL low-level monostable flip-flop of the present invention (t _T >> t _T ≦ 0.7R _t C _t ), where (a) is a circuit diagram, and (b) is a logic diagram;

FIG. 37 is a LSTTL original traditional low-level monostable flip-flop (t _T ). 7R _t C _t ), where (a) is a circuit diagram, and (b) is a logic diagram; FIG. 38 is a LSTTL negative single pulse generator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 39 is a LSTTL low-level Schmitt trigger according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 40 is a LSTTL original low-level Schmitt trigger, where (a) is a circuit diagram, and (b) is a logic diagram;

 41 is a LSTTL controllable multi-function pulse oscillator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 Figure 42 is the LSTTL high level monostable flip-flop of the present invention

(t _T »t _T « 0.7R _t C _t ), where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 43 is a LSTTL positive single pulse generator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 44 is a LSTTL high-level Schmitt trigger of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 45 is a LSTTL low-level C I stable register (^ invented low-level RS trigger) of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 46 is a L ST T L original low-level C I stabilizing device (formerly a conventional low-level RS trigger), where (a) is a circuit diagram, and (b) is a logic diagram;

FIG. 47 is an LSTTL low-level monostable flip-flop (t _T »t _T ) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 48 is a low-level CI stable register (small-swing level RS flip-flop) of the LSTTL small swing output of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 49 is a circuit diagram of the LSTTL-D flip-flop of the present invention;

 Figure 50 is the original D flip-flop circuit diagram of LSTTL;

 FIG. 51 is a circuit diagram of the LSTTL-J flip-flop of the present invention;

 Figure 52 is a circuit diagram of the LSTTL small swing output D flip-flop of the present invention;

 FIG. 53 is a LSTTL high-level C I stable register of the present invention (high-level RS trigger of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;

FIG. 54 is a LSTTL high-level monostable flip-flop (t _T »t _T ) of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;

 FIG. 55 is an ECL high-level C I stable register of the present invention (ECL high-level RS flip-flop of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;

FIG. 56 is an ECL original conventional high-level RS flip-flop, where (a) is a circuit diagram, (b) is a logic diagram;

 FIG. 57 is a circuit diagram of the L ST TL ― D transflective register (digital latch) of the present invention; FIG. 58 is a circuit diagram of the original D transflective register of LSTTL;

 Figure 59 is the CM OS universal basic new device ZC 01 circuit diagram;

 Figure 60 is the logic diagram of the CM OS universal new basic device ZC 01;

 Figure 61 is the LSTTL universal basic new device ZL03 circuit diagram;

 Figure 62 is the logic diagram of the LSTTL universal new basic device ZL 03;

 FIG. 63 (ai) is a logic diagram of various functions corresponding to the CM 0 S and LSTTL universal basic new devices of the present invention. Detailed description of the invention

 The memory-type memory integrated circuit of the present invention is a great invention memory integrated circuit obtained by the inventor, Zhang Zongxue, using the "law of stable circuit-keeping" and "temporary law of circuit-keeping" proposed by himself in May 1986. It includes the invention or memory type integrated circuit, invention or memory type integrated circuit, invention B iCM 0 S memory and integrated circuit, and a new device with special multi-function (also known as universal basic new device).

 The NOR memory integrated circuit of the present invention uses only one NOR gate to form a basic RS flip-flop and a monostable flip-flop. The original technology uses two NAND gates or two NOR gates to form a basic RS trigger Trigger and a traditional monostable trigger. Therefore, the invention or memory memory integrated circuit is called a memory integrated circuit, and the original technology is two memory integrated circuits. Obviously, compared with the original technology, the inventive technology has the advantages of saving a large number of components and internal wiring, high speed, low power consumption, high reliability, and small size.

 Invented monostable flip-flops can use levels to directly control the temporary recording time to continuously change over a wide range. The temporary recording time is determined by three levels: timing level, timing resistance, and timing capacitor. It is determined by both the timing resistor and the timing capacitor. It cannot directly control the temporary recording time with the level.

 The invented pulse oscillator has multi-function oscillation. It is even more valuable that the frequency can be directly controlled to continuously change in a large range with a timing high level. The oscillation frequency is determined by the timing high level, the timing resistance, and the timing capacitor. The original pulse oscillator has a single oscillation function and cannot directly control the frequency with the level. The frequency of the original pulse oscillator is determined by both the timing resistor and the timing capacitor. It must be emphasized that the change in the timing high level causes the charging voltage ratio and the discharging voltage ratio on the timing capacitor to change accordingly, thereby directly making the frequency continuously change in a large range. This is fundamentally different from voltage-controlled oscillators that use level changes to control the change in the output resistance of the amplifying element, thereby making the frequency change.

The invented circuit greatly simplified and optimized the BICM 0 S. It is remembered that the integrated circuit has great practical value in medium-scale, large-scale, and ultra-large-scale integrated circuits. A new multifunctional device not only makes the basic logic device extremely rich and versatile, it is very convenient and flexible to design, use, and maintain. It is even more valuable that it can greatly reduce the basic variety of integrated circuits. This brings great benefits to manufacturers and users, and will surely be welcomed by users and manufacturers.

 The theoretical basis of the present invention is described in detail below.

 1. The theoretical basis of the present invention

 -The output state of the circuit when the signal of "Holding Circuit Stability Law" and "Holding Circuit Provisional Law" is called signal output. The signal acting on the circuit means that at the moment the signal is applied, the entire circuit is in the state of opening the signal, allowing the signal to pass through to the output. A signal acting on a circuit is not the same as a signal input circuit. A signal input circuit is not necessarily capable of acting on a circuit. If the circuit is in the closed state, the input signal has no effect on the circuit, that is, although there is a signal input, it does not work; if the entire circuit is in the open state of the input signal, the input signal can have an effect on the circuit.

 Definition of no-memory circuit The output logic state of a circuit exists according to the existence of an input signal, and the disappearance of the input signal disappears, that is, after the signal disappears, the circuit cannot maintain the output state when the signal is acting. Such a logic circuit is called a no-memory circuit. The output of the memoryless circuit is represented by Q.

 For example, L ST TL, CMOS, TTL, ECL, HTL and other integrated circuits such as various high-level OR gates (actually described later as high-level OR gates) and low-level OR gates (that is, high-level AND gates) (It is actually a low level or gate as described later) is a memoryless circuit. In addition, NAND gates, NOR gates, AND gates, XOR gates, XOR gates, half-adders, full-adders, decoders, encoders, data selection circuits, etc., all previously described combinational logic circuits have no Memory circuit.

 The memory circuit defines that the circuit has the function of stably (ie, does not change with time) or replace the input signal within a certain time. Even if the input signal disappears immediately after the circuit replaces it, the circuit can still be stable or maintained for a certain time. Signal output status. This logic circuit is called a memory circuit.

 A complex logic circuit control system is an organic combination of memory circuits and memoryless circuits.

 Classification of memory circuits According to whether the memory of a signal changes with time, memory circuits can be divided into two categories: stable circuits and temporary circuits.

The memory of the signal by the stable memory circuit does not change with time, that is, the memory circuit that stably stores the signal is called a stable memory circuit. The output of the stable circuit is represented by Q _s .

Such as traditional RS flip-flops, D flip-flops, JK flip-flops, magnetic memory and various new CI stabilizers described later, new! ) Stable memory, new JK stable memory, and various counters, digital registers, shift registers, etc. formed by them are all stable memory circuits. A useful and stable memory circuit, which can not only memorize signals, but also easily erase information number.

 The temporary circuit is automatically erased after the signal is memorized for a certain period of time. That is, the circuit in which the memory of the signal changes with time is called a temporary circuit.

 For example, conventional monostable flip-flops, multivibrators, various new registers as described later, and multifunctional new pulse oscillators are all temporary circuits.

A single-valued temporary circuit for temporarily high-level or low-level signals (ie, a high-level or low-level temporary register described later), whose output is represented by Q _T. A double-valued temporary circuit for temporarily recording internally generated high and low level signals, that is, the output of the pulse oscillator is represented by Q 0.

 The output state of the circuit that memorizes the input signal is referred to as the record state; the output state of the circuit that stably memorizes the input signal is referred to as the steady state; the circuit output state that temporarily stores the input signal is referred to as the temporary state.

 According to the materials constituting the memory circuit, the memory circuit includes a memory circuit of a memory type, a magnetic memory circuit, a capacitive memory circuit, and a photoelectric memory circuit.

 OR memory circuit The OR memory circuit formed by connecting the OR memory circuit (also known as OR memory gate) described later to its unique memory chain is called OR memory circuit, also known as the replacement memory circuit.

 OR memory circuits are divided into OR memory circuits and OR memory circuits. For example, traditional RS flip-flops, D flip-flops, JK flip-flops, and various new CI stabilisers described later, new! ) Stable memory, new JK stabilizer, and various counters, digital registers, shift registers, etc., which are composed of them and control circuits, belong to or memory type memory circuits. The suspense circuits listed earlier are OR-type suspense circuits. Orbital memory circuit occupies the primacy of various integrated circuits, and it is the most important and widely used logic circuit.

 Magnetic-type memory circuit Magnetic-type memory circuit uses the remanence characteristic after magnetization of a magnetic substance to replace the signal and memorizes the signal. At the moment when the current signal is applied, the residual magnetic properties of the magnetic substance endogenously replace the role of the current signal, so that after the current signal disappears, the magnetic substance still maintains the state of the magnetic flux when the current signal is applied, that is, the current signal is kept in mind. For example, magnetic memories that store digital signals, magnetic disks, and audio tapes and video tapes that store analog signals are all magnetic memory circuits. The latter memorizes signals through acoustic, electrical, magnetic, and optical, electrical, and magnetic conversions.

 Capacitive memory circuits Capacitive memory circuits use the charge storage effect of capacitors to store signals instead of signals. For example, a dynamic M 0 S FET memory cell.

 Photoelectric Memory Circuits Photoelectric memory circuits use the photoelectric effect to replace signals and memorize them. An example is a compact disc.

 Input value range The allowable value range of the input signal logic level when the signal output takes a fixed value is called the input value range, which is represented by (i).

For example, L ST TL, the input range of the TTL integrated circuit low-level signal is generally specified as 0V to 0.8V, that is, a _L = [0.8V, 0V]. The input range of its high level signal, Generally, it is 2V to 5V, that is, otjH = [5V, 2V]. For another example, the input range of the low-level signal of the CM 0 S integrated circuit is generally specified as 0V to 30% of the power supply voltage V _DD . If V _DD = 5V, the input range of the low-level signal of the CM 0 S is 0V. To 1.5V, ie (L = [1.5V, 0V]. The input value range of the CM OS high-level signal is generally specified as 70% of the power supply voltage V _DU to V _nD . If V _DD = 5V, the CM OS is high. The input range of the level signal is 3.5V to 5V, that is, a _ai = [5V, 3.5V].

 Output value range The allowable change range of the signal output logic level when the input signal takes a fixed value is called the output value range, and α is used. Means.

For example, LSTTL, TTL integrated circuit output logic low-level value range, which is set to 0V to 0.4V, that is a _oL = [0.4V, 0V]. The output logic high level value range is generally specified as 2.4V to 3.6V, that is, α ₀ „= [3.6V, 2.4V].

 Heterogeneous output input signal output range is not within the signal input range or the physical quantity characterizing the logical state of the output or input is heterogeneous, that is, the two are not the same type of physical quantity. Such output and input are called heterogeneous output and input, referred to as heterogeneous output input .

 The expression is in the formula, α. Indicates the signal output value range, indicates the signal input value range, and "ο" indicates the left α. Comma not in oti on the right.

 Heterogeneous or logical As long as one input between heterogeneous output and input is "1" ("1" means there is a signal), the output is heterogeneous with input "1". This logical relationship is called heterogeneous or logic. Because it only has heterogeneous OR logic functions, it is also called exclusive OR logic.

 A logic circuit capable of implementing a heterogeneous OR logic is called a heterogeneous OR gate.

 Figure 1 (a) is a low-level heterogeneous OR gate of a diode with heterogeneous output and input, and figure (b) is its logic diagram. Its high and low level signal outputs and its high and low level input signals are heterogeneous. The high and low logic levels are referred to as high and low.

Assume that the low-level signal is 0V and the high-level signal is 3V. Its low-level signal input range (L = 0V, and low-level signal output range ot. _L = 0.7V, obviously, α.ι ^ ο ^. Its high-level signal input range a _ai = 3V, and the high-level signal output value range α. _Η = 3.7V, obviously, a. _L cta _ffl is the same type of input and output. It can be seen that this circuit is a heterogeneous output and input circuit of low-level signals. In terms of level signals, the logic relationship of the circuit is heterogeneous OR logic, so it is a diode low-level OR gate.

Figure 2 (a) is a high-level heterogeneous OR gate circuit with the emitter output of a high-level signal heterogeneous output input, and Figure (b) is its logic diagram. Its high-level signal input value range is otiH = 3V, and its high-level signal output value range is α. _Η = 2.3V, obviously, α. „(ΤαίΗ. So the circuit Is an emitter output high-level XOR gate.

 In the logic diagram of a heterogeneous OR gate, the small circle "O" in the upper left corner indicates a high-level heterogeneous OR gate; the small circle marked in the lower left corner indicates a low-level heterogeneous OR gate.

 Similar output and input The outputs and inputs whose signal output range is within the signal input range (the signal output value range is only within the input range of one signal input end) are called the same output and input, and are referred to as the same output and input for short.

 Its expression is

a ₀ ci (i

 In the formula, "c" represents the signal output value range a. Logical symbol within signal input range a ,.

 Same or logical As long as one of the same output and input is "1" ("1" indicates a signal), the output is the same as the input "1". This logical relationship is called homogeneous or logical. Sometimes referred to as homogeneous or. Homology or logic is the basis for achieving replacement of memory. Circuits capable of implementing homogeneous or logic are called homogeneous or gates.

 In the same OR gate circuit diagram, the small dots "·" above the input terminals r and C indicate homogeneous OR gates for high-level signals; the small dots "·" below r and C indicate low Level signals are homogeneous OR gates.

 Figure 3 is a two-input high-level AND gate

+ 74L S08 wiring diagram. Its high and low level signal outputs are similar to its high and low level input signals. Its high-level signal input value range a _ai -generally takes 2V to 5V, that is 0Ci „= [5V, 2V], and the high-level signal output value range a. _H -generally takes 2.4V to 3.6V , That is a. „= 〔3.6V, 2.4V】, it can be seen that a ₀ „ ca _ai . Its low-level signal input value range a _{L is} generally 0V to 0.8V, that is (L = 〔0.8V, 0V], and the low-level signal output value range a. _{L is} generally taken from 0V to 0.4V, that is a. _L = C 0.4V, 0V], it can be seen that a. _L ca _L. From this we can know that the 7 S08 circuit It is a high-level and low-level signal homogeneous output and input circuit. For low-level signals, the logical relationship between the output and input of the 74LS08 circuit is homogeneous or logical. Therefore, the 74LS08 circuit is a low-level homogeneous OR gate. It is called or low-level C or gate in the OR gate.

 Figure 4 is the original two-input high-level OR gate

+ 7 S32 circuit diagrams. Similarly, its high and low level signal outputs are the same as its high and low level signal inputs, namely aoHdociH, aoLdOtiL. Therefore, the 7 S32 circuit is a similar output and input circuit. For a high-level signal, the logical relationship between its output and input is homogeneous or logic. Therefore, the 74LS32 circuit is a high-level homogeneous OR gate. It is called a high-level C or gate in the OR gate. The definition of the memory chain sends the signal output back to the replacement input. At this time, regardless of whether the input signal disappears or not, it can stably (ie, not change with time) or replace the role of the input signal within a certain period of time. The input circuit of this output is called a memory chain. Memory chain is also called memory factor.

An input terminal that uses a signal output to replace an input signal is referred to as an input terminal, which is also called the end of a memory chain, and is represented by Γ, r _c , r _s .

 The signal output is sent back to replace the input terminal. It cannot replace the input signal. The input circuit of this output is not a memory chain, or the circuit has no memory chain and does not replace the input terminal.

 The memory chain is an external cause, sufficient condition, and a necessary bridge to realize the function of replacing the logic of memory. There are four types of memory chains: digital input signal stable chain, digital input signal single-value temporary chain, digital input signal double-value temporary chain, and analog input signal temporary chain. They are referred to as stable memory chain and single-value temporary chain. , Double-valued suspense chain and simulated suspense chain. Suspense chains include single-valued suspense chains, double-valued suspense chains, and simulated suspense chains. Single-valued suspense chains and double-valued suspense chains are called digital suspense chains.

 Definition of stability chain The signal output is sent back to replace the input end. At this time, regardless of whether the input signal disappears or not, it can stably replace the role of the input signal. The input circuit of this signal output is called a steady chain. Steady chain is also called steady factor. The end of the chain is represented by r.

 There are two main types of circuit of stable memory chain: one is the first-line stable memory chain; the other is the stable memory chain with controlled electronic switch. The most commonly used memorizing chain is a connected memorizing chain. Using a connection to connect the output of a signal OR circuit (see below) with its replacement input terminal Γ constitutes a stable chain of connections, which is very simple. A wired memory chain changes the quality of a memoryless signal or memory circuit into a memory circuit.

 Figure 5 (a) is a logic diagram of a memoryless or low-level OR circuit. Figure (b) is a logic diagram of the new low-level C I stabilizing device connected to the low-level OR circuit connected to a connected stable stabilizing chain. At this time, the r terminal can stably replace the low-level signal input from the similar input terminal C or the inverting input terminal I, so that the output stably remembers the low-level signal of the C terminal or I terminal. It can be seen that a connected stable memory chain turns the memoryless or low-level OR circuit quality into a new low-level CI stable register (referred to as the new low-level RS trigger in the past).

The definition of the digital suspense chain uses the principle that the voltage across the capacitor cannot be abruptly changed, and the signal output is returned to the input terminal through the capacitor. At this time, whether the input signal disappears or not, it can be discharged and charged in the RC circuit at a certain time. Replaces the role of the input signal. The input circuit for this signal output is called a digital temporary chain. The number suspense chain is also called the number suspense factor, and the end of the number suspense chain is represented by r _c .

The new single-valued temporary chain is composed of timing level V _t , timing resistance R _t , Composed of timing capacitor C _t . C _t must be connected between the output end of the signal OR circuit and the end of the temporary chain r _c , and R _{t is} connected between the r _c terminal and the timing level V _t terminal, as shown in FIG. 6 (b). Figure 6 (a) is a logic diagram of a low-level OR memory circuit. FIG. 6 (b) is a logic diagram of a new low-level temporary register formed by connecting the low-level OR circuit with a new single-valued temporary storage chain. Regarding V _t , R _t and C _{t will be} described later.

The original single value temporary chain circuit is composed of a timing resistor R _t and a timing capacitor C _t . R _t — Terminate on r _c and connect the other end to “ground” or to power.

A single-valued temporary recorder is linked to a signal or circuit with no memory. It can only temporarily record high-level signals or low-level signals. Therefore, it is called a single-valued suspense chain, which is also called a single-valued suspense factor. Double value suspense chain The double value suspense chain circuit is composed of a timing high level V _t , timing resistors R _t and R _t , a timing capacitor C _t and an output temporary state Q. Controlled NPN type or NM 0 S single tube electronic switch S. Composed of. Similarly, C _t must be connected between the output of the signal OR circuit and the end of the temporary chain r _c . The timing resistance R _{t is} called a pulse-space resistance, and the timing resistance R _{t is} called a pulse-width resistance. The double-valued temporary chain circuit is shown in Figure 7 (b). FIG. 7 (a) is a logic diagram of a low-level OR gate, and FIG. 7 (b) is a logic diagram of a new controllable multi-function pulse oscillator by using the low-level OR circuit to connect a two-value temporary register chain. V _t will be described later on.

A new multi-function pulse oscillator constructed by linking a double-valued temporary record to a signal or a circuit can alternately temporarily record the high and low-level signals generated in the r- _c terminal, that is, pulse oscillation is generated. Mind chain, also known as its double-valued temporary factor.

 The level of the analog input signal below the threshold level (refer to the threshold level below) is called an analog low-level signal; the level above the threshold level is called an analog high-level signal.

The analog suspense chain defines the output of the analog low-level signal. The low voltage obtained by replacing the input can replace the analog low-level signal through the voltage dividing circuit (non-linear or linear) connected to the output and the analog signal input The effect (only the low-level OR gate can be realized) is different from the effect of replacing the digital input signal. This replacement effect is after the analog low-level signal disappears (that is, it becomes an analog high-level signal). Hold for a certain time and terminate; at the same time, the analog high-level signal starts to work, but its output enables the high level obtained by replacing the input terminal to be maintained but not to replace the role of the analog high-level signal, that is, the analog high The output of the level signal exists with the existence of the analog high-level signal, disappears and disappears (because the sustain period is a high-level AND gate). The output of the analog high-level signal uses a voltage divider circuit to replace the high level obtained at the input end to replace the role of the analog high-level signal (only high-level homologous OR gates can achieve); and in this case, the analog low level The output of the level signal enables the low level obtained by replacing the input terminal to be maintained but not the role of the analog low level signal (because the low level AND gate is maintained during the sustain period). This analog input signal output The input circuit is called an analog suspense chain. The analog suspense chain is also called analog suspense factor. The end of the analog suspense chain is represented by r _s .

 Analog suspense chain circuit The common circuit of the analog suspense chain of the signal or recording circuit is a resistor R connected between the output terminal and the input terminal. And a non-linear voltage divider circuit composed of a diode D and a resistor connected between the replacement input terminal and the analog signal input terminal, as shown in Fig. 8 (1) and ((1). R., R] is the voltage division Resistors and diodes function as level shifting and switching. The analog input signal is represented by l. Figure 8 (a) is a logic diagram of an OR-type low-level C OR circuit (see below, for example, + 74L S 08 circuit). Figure 8 (b) is a new analog temporary register for temporarily simulating low-level signals formed by connecting an analog temporary link, which is referred to as a new low-level analog temporary register.

(c) Logic diagram of OR-type high-level C or memory circuit (such as 74L S 32 circuit). Figure 8 (d) is a new analog temporary register for the high-level C or gate circuit connected to the analog temporary chain to form a temporary analog high-level signal, referred to as a new high-level analog temporary register. The analog register is the original Schmitt trigger.

 From the above definitions of the memory chain, homogeneous output input, and heterogeneous output input, it can be known that: if the signal output and input signal are heterogeneous, it is impossible to use the signal output to replace the role of the input signal; if the signal output and the input signal are homogeneous It is only possible to use the signal output to replace the role of the input signal.

 Principle of memory chain Only the same or logic can have a memory chain, and no other logic, such as AND logic, heterogeneous or logic, NAND logic, or non-logic, etc. has no memory chain. The principle of memory chain is a proof-free principle based on the definition of memory chain and homogeneous or logical characteristics.

 Two Guidelines for Replacing Memory To achieve the replacement of input signals, two criteria must be followed: one must be the same or logic of the signal; the other must be connected to a unique memory chain of the same logic. The first criterion is to replace the internal factors and necessary conditions of memory. The second criterion is to replace the external factors and sufficient conditions of memory.

 There is not only homogeneous or logical (including equivalent homogeneous or logical) between logical output and input, but also more important and useful. By connecting its unique memory chain, there is also a logic function of memorizing input signals. The logical relationship between them is called or remembering logic. Or, simply, homology or logic (including equivalent homology or logic) and its unique and waiting memory chain can implement or memorize logic. A large amount of profound logic exists in machinery, jets, logic circuits, integrated circuits and other fields.

 Signal or memory circuit A circuit that can implement a signal or memory logic is called a signal or memory circuit, referred to as a circuit or circuit or a gate for short.

The input signal of the OR circuit is the same as its output, and its input terminal is called the same input terminal of OR circuit, which is represented by C. The input signal of the OR circuit and its output are opposite logic In the level state, its input terminal is called the inverting input terminal of the OR circuit, which is represented by I. The OR circuit has a signal input terminal C and a signal inverting input terminal I. But I can do it or not. The end of the memory chain, which is unique to the HJ circuit, is to replace the input, which is obviously at the same input. The signal OR circuit is the same OR gate with C, I input terminal or C terminal only.

 The types of OR circuits are divided according to OR gates for level signals. There are three types: low level OR gates, high level OR gates, and high level or OR gates.

 Low-level OR gate is the OR gate for low-level signals (including low-level equivalent OR gate). The small dot "·" marked in the lower left corner of its logic diagram indicates that the gate is YES for low-level signals.

 A high-level OR gate is an OR gate for high-level signals. The small dot "·" marked in the upper right corner of the logic diagram indicates that the gate is OR-coded for high-level signals.

 High or low level OR gate is OR gate for both high level signal and low level signal. The high or low level or gate is also called single input or gate, inverter. There are no dots on its logic diagram.

 According to the circuit structure that constitutes or gates, there are mainly or gates or gates (also known as one gate or gates), two equivalent gates, expansion or gates, collector output or gates.

 The OR gate is the OR gate of the OR circuit structure. There are or type low level or gate, or type high level or gate, or type low level C or gate, or type high level C or gate, or type single input or gate. OR type C OR gates are AND gates and OR gates (as used to say) in various integrated circuits. They are all gates or gatekeepers.

 Two equivalent OR gates It consists of two NOR gates to form a two equivalent OR gates. It is also called a NOR gate. There are two equivalent C or gatekeepers.

 Expansion OR gate In fact, it is a high-level AND gate or a low-level OR gate. It includes an OR-type expansion or gate (ie, a gate-type expansion or gate) and two equivalent expansion or gates.

 Collector output or gate It is the low level or gate of the triode collector output. It belongs to two equivalent low level or gates.

In the circuit diagram of the OR gate, the small dot "·" marked above the similar input terminal C and the inverting input terminal I indicates that the valid input signal is a high level signal, that is, for a high level signal, it is a OR gate. ; The small dots "·" below them indicate that they are OR gates for low-level signals. An example of a OR gate The 74L S 08 circuit shown in FIG. 3 is an OR-type low-level C OR gate, and the aforementioned circuit of FIG. 4 + 74L S 32 is an OR type high-level C-OR gate. Adding very few components gives the inverting input I of the low-level signal of the 74L S 08 circuit to form a The circuit diagram of LSTTL or low level or gate is shown in Figure 9. Adding very few components gives

4 The 74LS32 circuit's inverting input terminal I of a high-level signal constitutes a LSTTL or high-level OR gate. The wiring diagram is shown in Figure 10. Figure 11 is a circuit diagram of an ECL or high-level OR gate, Figure 12 is a circuit diagram of two low-level equivalent OR gates formed by two TTL NAND gates, and Figure 13 is an LSTTL or high-level extension A circuit diagram of the OR gate, FIG. 14 is a low-level OR gate of the TTL collector output, and FIG. 15 is a circuit diagram of a CM 0 S single input or gate circuit formed by connecting two inverters in series.

The threshold level of the signal or gate. The door opening level V 0 N and the gate closing level V ₀ p _P of the signal or gate are close to L. In order to facilitate the analysis, the ideal voltage transmission characteristic (polyline) is used to replace its actual The voltage transmission characteristics (curves) are considered to be approximately equal. The ideal opening or closing level of a signal or gate is called the threshold level (or threshold level) of the signal or gate, which is represented by V _T.

The time of the temporary signal is referred to as the temporary time. The levels, resistances, and capacitances that determine the length of the temporary record are called timing levels, timing resistances, and timing capacitors, respectively. The timing resistance is denoted by R _t , the timing capacitance is denoted by C _t , and the pending timing level is generally denoted by V _t . When the power-on level should be a logic level above the threshold level, the timing high level is called V _t ; when the timing level is below the threshold level, it is called the timing low level. Use \ f _t means.

Because of the value of the level V _t , one is to directly determine whether the temporary register can temporarily record the input signal, and the other is to directly determine the length of the temporary register's input signal time (R _t , C _t — fixed), so it is named Is the timing level.

 Definition of charge-to-charge voltage ratio The ratio of the charge-to-charge voltage on the capacitor when the signal is temporarily recorded by the temporary register is called the charge-to-charge voltage ratio, which is expressed by η.

 Definition of Loss Voltage Ratio The ratio of the discharge voltage on the capacitor to the discharge voltage (or equivalent discharge voltage) when the signal is temporarily registered by the temporary register is called the discharge voltage ratio and is expressed by β.

From the charging and discharging laws of the RC circuit, it can be known that the larger η and β, the longer the temporary recording time; conversely, the smaller η and β, the shorter the temporary recording time. The timing level V _t changes (R _t , C _{t is} constant), so that η and β change accordingly, so that the temporary recording time and the oscillation frequency continuously change in a wide range. The temporary time of the temporary register of the present invention (that is, the monostable flip-flop in the past) and the frequency of the pulse oscillator are not only related to the timing resistor R _t and the timing capacitor C _t , but the most useful and valuable is that it is related to the timing The level V _{t is} directly related. It is emphasized again that changing the timing high level ( _Rt , _{Ct is} constant) directly makes the oscillation frequency continuously change in a wide range, which is similar to using the changed level to control the output resistance or output current of the amplification element, so that The voltage-controlled oscillator that changes the oscillation frequency is fundamentally different. So far, no one in the world has proposed homology or logic, and no one has discovered the scientific mystery between homology or logic and memory. "Or Chronicles" is a scientific work based on modern theories and principles of modern natural sciences by the inventors to use new concepts, new theories, and new technologies to discuss similar or logical memory science laws. Its contents include important discoveries of OR logic, OR law of circuit stability, OR law of circuit temporary memory, and four basic universal new devices.

 The law of steadily remembering a circuit or signal is connected to the stability chain, which is called a stable memory cell. It uses signals in the same state to keep the signals of the same type of input terminals intact, and uses signals in the inverse state to keep the signals of the inverting input terminals. It reenters the signals and keeps the state unchanged. Time; or the circuit is not working, then it loses its memory. A memorable circuit consists of one or more organic cells.

 High-level and low-level stable cells are also called high-level and low-level C I stabilizing devices, which used to be high-level and low-level RS triggers.

 The law of temporary circuit temporariness 1. A signal or temporary circuit connected to a digital temporary chain can tentatively erase a signal after a certain period of time, which is called a temporary cell. It uses signal homomorphism to temporarily record the signal of the same input terminal, and signal inverse state to temporarily record the signal of the inverting input terminal; reenter the signal, and keep the state unchanged; the time when the signal is active and cannot be evacuated equals the time it replaces the signal. Time; when the door is closed with a signal, it is not remembered; the temporary time is determined by the timing level, resistance and capacitance.

 The law of temporary circuit temporariness II The signal or temporary circuit connected to the analog temporary chain can temporize the analog low-level or analog high-level signal, which is called analog temporary cell. When the frequency and amplitude of the analog input signal are constant, the disappearance time is related to the voltage division ratio of the analog temporary chain; the longer it is, the greater the difference between the gender trigger voltage and vice versa.

 The relationship between jiji The relationship between homogeneity or logic and memory is simply the relationship between jiji. The concept of "or ji" has two meanings: one is that it has two major logical functions of homology or memory; the other is that homology or series is the basis, internal cause, and necessary condition to replace memory, and memory function is a special kind or characteristic , Deep expression and highest application form. There is a close relationship between internal and external.

 The internal close relationship between the jiji, as long as there is one input between the same type of input and output is

"1", then the output is the same kind or characteristic (including the equivalent kind or equivalent) as the input of the same kind "1" is the basis and internal cause to replace the memory logic function, and the memory logic function is a special and profound expression of the same kind or characteristic Form and highest application form.

 The external relationship between the jiji The signal or jimen has two logic functions: homogeneous or memory. Specifically, signals or gatekeepers generally have five working states and five corresponding logic functions.

 When the signal or gate is not connected to its unique memory chain, it is a homogeneous or gate with no memory or a homogeneous or gate with a nonsignal (signal or NOT). It is in the same or logical working state and follows the same or law without memory.

The signal or gate is connected to the stable chain, and then a memoryless signal or gate becomes a The circuit for stably remembering the signals of the same type of input terminal or the inverting input terminal, it is in the working state of stably remembering the input signal, and follows or remembers the law of circuit stability.

 After the signal or gate is connected to a single value suspense chain, it changes from a no-memory signal or gate quality to a suspense circuit that temporarily records signals of the same type of input or inverted input. The working state of the input signal should follow or record the temporary law 1 of the circuit.

Or write circuit connected to the signal binary clearing chain, it consists of a non-memory signal or write gate becomes a matter of alternating high and low output in the high r _c suspense end endogenous, low-level signals controlled multifunction Pulse oscillator. Its oscillation frequency and pulse-space delay are related to the timing high level, timing resistance, and timing capacitance, and the pulse width is related to the pulse width resistance and capacitance.

 After the signal or gate is connected to the analog suspense chain, it changes from a memoryless signal or gate quality to an analog suspense circuit that temporarily records analog low (or high) signals, that is, Schmitt trigger , Follow or memorize the circuit temporary law two.

The common core of the five different logic functional circuits: signal OR gate, signal stabilizing circuit (signal stabilizing cell), signal single-value staging circuit (signal single-value staging cell), pulse oscillator, and analog staging circuit. The signal or gate (internal factor) is only under the five different external conditions (external factor): not connected to the memory chain, connected to the stable chain, connected to the single value temporary chain, connected to the double value temporary chain, and connected to the analog temporary chain. The resulting five different logic circuits and five corresponding logic functions. This is just like the working state of the transistor, which is based on an internal cause (the internal structural characteristics of the transistor), and under three different external operating conditions (base bias current I _B in the amplification region, I _B in the saturation region, In the cut-off area), there are three different working states: amplification, saturation, and cut-off.

For a detailed discussion of the new concepts and new theories of the present invention, please refer to the inventor's special book "The Chronicle". The memory memory integrated circuit of the present invention is described below. In the single-value temporary register chain of the present invention, the circuit is composed of a timing high level Ϋ _t , or a timing low level γ t, a timing resistor R _t , and a timing capacitor C _t . C _t must be connected between the output terminal of the signal OR circuit and the replacement input terminal r _c , R _t —terminated at the terminal r _c and the other terminal Ϋ _t or \ _t .

The original single-valued temporary register chain is composed of a timing resistor R _t and a timing capacitor C ^. C _t must be connected between the output terminal of the signal or gate and the substitute input terminal r _c , one end of R _t is connected to r _c , and the other end is connected to “ground” or power voltage. The so-called double value temporary chain, its circuit is a timing high voltage V _t , timing resistance R _t and R _t , timing capacitor C _t and NPN type or NMOS single-tube electronic switch S controlled by the output of a signal or memory circuit. Composed of. Similarly, (^ must be connected to the output of the signal or memory circuit and replace Between the input terminals r _c . Regarding R _t , R _t , So, V _t are connected in two ways: One way is

R _t - r _c terminated at the end, the other end of R _t - terminal contact, and the other end of the V _t R _t, So end a "ground", S. The output is terminated where R _t and R _t meet. Another connection method is R _t — terminated at r _c , the other end is connected to V _t , one end of R _t is connected to r _c , and the other end is connected to S. Output, S. The other end is "grounded". So there are two types of double-valued suspicious chain circuits, the former type of double-valued suspicious chain is commonly used.

The so-called analog suspense chain is a non-linear or linear voltage divider circuit, one end of which is connected to the output end of a signal or recorder circuit, the other end is connected to an analog signal input end, and the voltage divider output is connected to a substitute input end r _s . A common circuit is a resistor R connected between the signal output terminal and the replacement input terminal r _s . And diode D connected in series between the replacement input terminal and the analog signal input terminal], resistor R! Composition of a non-linear voltage divider circuit. For low-level or gate-keeping, the negative pole must be connected to r _s terminal, and for high-level or gate-keeping, D! IL pole must be connected instead of input terminal r _s .

 The so-called 4½-line stable memory chain is a circuit that connects the output end of a signal or memory circuit with the input end.

The dipstick is a monostable flip-flop in the past, and the low-level and high-level dipsticks are low- and high-level monostable flip-flops in the past. The analogue dipstick is a Schmitt trigger. The analog register that records the analog low-level and high-level signals is called a low-level and high-level analog temporary register, that is, a low-level and high-level Schmitt trigger; the CI stable register is an RS trigger in the past. Low- and high-level CI stabilisers are, in the past, low- and high-level RS flip-flops. h represents a logic high level, L represents a logic low level; L 'represents a logic low level during which the low-level input signal is active and cannot be withdrawn; Logic high. The new monostable trigger temporarily records the low-level input signal L 'or the high-level input signal H. The temporary time is represented by t _T ; when R _t and C _{t are} constant, the minimum temporary time is represented by t _{Tm "in} "; the original traditional monostable flip-flop temporary input signal is represented by t _T , t _T «0.7R _t C _t ; in the circuit diagram C, the effective level signal of the asynchronous input is high Signal; C, ί indicates that the effective level signal of the asynchronous input is a low-level signal.

After using two CM OS high-level NOR gates to form a two-gate equivalent high-level NOR gate, connect the original single-value temporary chain to form a high-level signal H. The circuit diagram and logic diagram of the original traditional high-level monostable flip-flop temporary circuit of COS are shown in Figure 16 (a) and (b). Its temporary time t _T «0.7R _t C _t .

A CM 0 S single input or gate made of two CM 0 S NOT gates connected in series is connected to an invention single value temporary staging chain composed of a timing low level Y t and a timing resistor timing capacitor C _t , and The anode of the diode is connected in series with the two NOT gates, and its anode is used as the inverting input terminal I of the low-level signal. This constitutes the CM OS low-level monostable trigger temporary circuit of the present invention. The logic diagram is shown in Figures 17 (a) and (b). Its temporary time t _T »t _T ~ 0.7R _t C _t .

The positive and negative poles of the diode are reversely connected in FIG. 17 (a), and the timing low level Y _{t is} replaced with the timing high level to form the CM OS high level monostable flip-flop temporary register circuit of the present invention. The sum logic diagram is shown in Figures 18 (a) and (b).

A CM 0 S single input or gate connected with two CM 0 S NOT gates connected in series is connected to a double value temporary chain to form the CM OS multi-function pulse oscillator of the present invention. The circuit diagram and logic diagram are as shown in the figure. 19 (a) and (b). It can be as high degree of precise control of the square wave side with V _t the timing of the square wave oscillator, as a multivibrator high frequency timing control V _t with variations, as high V _t the timing control frequency is continuously changed in a wide range of a given batch pulse oscillator as a high level V _t the timing control frequency is continuously changed in a wide range of variable width intermittent oscillator as a high level V _t the timing control Ultra-low frequency oscillator with continuously changing frequency over a wide range (from 20 seconds to 1 hour). It is called a multi-function pulse oscillator.

 The positive stage of a diode is connected in series with the two NOT gates in Fig. 19 (a), and the negative electrode is used as the low-level signal inverting input terminal I for controlling whether to oscillate. Pulse oscillator, its two circuit diagrams and logic diagrams are shown in Figure 20 (a) and (b) and (c) and (d).

 Figures 21 (a) and (b) consist of two CM 0 S high-level NOR gates to form a two-gate equivalent high-level NOR gate, and then connect a connected stable chain to form the CM OS. The circuit diagram and logic diagram of the original traditional high-level RS flip-flop circuit are shown in Figure 21 (a) and (b).

A CM 0 S single input or gate made of two CM OS NOT gates connected in series is connected to a wired stability chain, and a diode anode is connected at the junction of the two NOT gates. An inverting input terminal I of the level signal is connected to the anode of another diode instead of the input terminal r, and its negative electrode is used as a similar input C of the low-level signal, which constitutes the CM 0 S low-level RS trigger of the present invention. The device keeps in mind the circuit, and its wiring diagram and logic diagram are shown in Figure 22 (a) and (b).

 The positive and negative * 1 ^ of the two diodes in FIG. 22 (a) are connected to form the CM OS high-level RS flip-flop stabilizing circuit of the present invention. The circuit diagram and logic diagram are shown in FIG. 23 (a) and (b ).

 Figures 24 (a) and (b) are circuit diagrams and logic diagrams of the computer keyboard CM 0 S debouncer technology unit circuit.

 A CM OS single input or gate made of two CM 0 S NOT gates connected in series is connected to a stable recording chain connected to the wire, and then the replacement input terminal r is connected to the normally open contact terminal of the key switch. The non-gate series connection is connected to the normally closed contact end of the key switch, the positive stage of a diode is connected to the common end of the key switch, and the negative pole of the diode is connected to "ground", which constitutes the computer keyboard CM OS of the present invention. One of the unit circuits has a wiring diagram and a logic diagram shown in Figures 25 (a) and (b).

The inverting input terminal I of the CM OS high-level RS flip-flop circuit diagram of the invention in FIG. 23 (a) is connected to the normally closed contact terminal of the key switch, and the similar input terminal C is connected to the normally open contact terminal of the key switch. The common terminal power supply voltage of the key switch + V _D1) , which constitutes the second circuit of the computer keyboard CM 0 S debounce unit of the present invention. The circuit diagram and logic diagram are shown in Figure 26 (a) and (b).

 The components used in the computer keyboard CM OS debouncing original technology unit circuit are the invention

The C OS debounce unit circuit is three times as powerful, and its power consumption is 1000 times that of the CM OS debounce unit circuit of the present invention.

 Figure 27 (a) and (b) are the circuit diagram and logic diagram of the CM OS original static memory cell circuit.

 A CM 0 S single input or gate made by connecting two CM 0 S non-gates in series is connected to a stable chain of f½ line, and then the input end is connected in series with the first and second NM OS switch tubes and The data line D is connected, the first NM OS switch is controlled by the row selection Xi, and the second NM OS switch is controlled by the column selection signal yi, which constitutes a single-line read-write CM OS static memory of the present invention. The circuit diagram and inverse diagram are shown in Figure 28 (a) and (b).

The BiCM OS controllable CI stabilizer (BiCM OS controllable high-level RS flip-flop) of the present invention consists of a CM OS low-level CI stabilizer (CM OS low-level RS flip-flop) and high level The signal input consists of a TTL control circuit. TTL input control circuit It consists of two two-input TTL high-level NAND gates. One input terminal of the first NAND gate is an input terminal of a high-level signal, and the other input terminal is connected to a clock pulse CP, and an output thereof is connected to a similar input terminal of the CM OS low-level CI stabilizing device of the present invention; One input terminal of the second NAND gate is the other input terminal for asynchronous input of the high-level signal. The other input terminal is connected to the CP pulse, and the output is connected to the inverse of the CM OS low-level CI stable register of the present invention. Phase input. The circuit diagram and logic diagram are shown in Figure 29 (a) and (b).

 Figures 30 (a) and (b) are circuit diagrams and logic diagrams of a four-digit digital register with BiCM 0 S two-shot operation of the present invention; Figures 31 (a) and (b) are BiCM 0 SD-type stable registers of the present invention ( D-type stable register) circuit diagram and logic diagram; Figures 32 (a) and (b) are the B iCM 0 S eight-bit register circuit diagram (tri-state) of the present invention. They are all composed of the original TTL control circuit of the CMOS low-level RS flip-flop and signal input of the present invention.

 FIG. 33 is a circuit diagram of a BiCM O S D flip-flop of the present invention; FIG. 34 is a circuit diagram of a BiCM 0 S J flip-flop of the present invention; and FIG. 35 is a circuit diagram of a B iC M 0 S four-bit binary counter of the present invention. Their all-remember circuits are the CM 0 S low-level RS triggers of the present invention, and the once-and-a-remember circuits are the original TTL once-and-a-rememory circuits. It should be noted that

The resistance in the TTL part of BiCM 0 S is much larger than the value in the TTL integrated circuit. This is because the current required by the TTL circuit required by the CM O S low-level RS flip-flop of the present invention in a BiCM 0 S or memory-type stable memory circuit is extremely small.

 The invention's or temporary memory integrated circuit is composed of a memoryless or low-level C or gate, which is an AND gate of various integrated circuits (LSTTL, CM OS, TTL, H TL, etc.) in the past. Connected to the suspense chain. As mentioned earlier, the suspense chain includes the value suspense chain of the present invention, the original single value suspense chain, the double value suspense chain, and the simulated suspense chain. The single value suspense chain of the present invention includes the original single value suspense chain. The original single value suspense chain is a special case of the lower edge of the single value suspense chain of the present invention. The implementation examples are as follows:

For example, a non-memory LSTTL or low-level C OR gate, that is, a 74LS08 two-input AND gate, which was said in the past, is connected to a timing high-level V _t , a timing resistor R _t , and a timing capacitor C _t The single value suspense chain of the present invention constitutes the LSTTL low-level monostable flip-flop temporary suspense circuit of the present invention. The circuit diagram and logic diagram are shown in Figure 36 (a) and (b).

Figure 37 (a) and (b) are a two-gate equivalent low-level OR gate with two high-level NAND gates (two low-level NOR gates). The circuit diagram and logic diagram of the original traditional LSTTL low-level monostable flip-flop, which forms the low-level signal L 'and is input from the I terminal. Its temporary time t _T «0.7R _t C _t . Use a memoryless LSTTL or a low-level C or a gate, which is what one said in the past! The 74LS08 two-input AND gate is connected to the original single-value temporary chain consisting of a timing capacitor C _t and a timing resistor R _t connected to a power source at one end, and a switching pulse generating circuit is connected to a similar input terminal C, thereby forming the LSTTL negative of the present invention. Single pulse generator. Its circuit diagram and logic diagram are shown in Figure 38 (a) and (b). Use a memoryless LSTTL or low-level C OR gate, which is a + 74LS08 two-input AND gate The LSTTL low-level analog temporary register (ie, the low-level Schmitt trigger) of the present invention is constituted by connecting the low-level analog temporary register, and its circuit diagram and logic diagram are shown in Figure 39 (a) and (b ). The so-called low-level analog suspense chain is an analog suspense chain with the anode of the diode connected in place of the input. Figure 40 (a) and (b) use a low-level NOR gate (high-level NAND gate) Gate) and an NOT gate to form a two-gate equivalent low-level C OR gate, and then connect a low-level analog suspense chain to form the LSTTL original low-level Schmitt trigger circuit and logic diagram. A no-memory or low-level C or gatekeeper, that is a +7 entry S08 two inputs Gate, connected to two-value clearing chain, constitute LSTTL Multifunctional controlled oscillator of the present invention the suspense circuit and a logic circuit diagram shown in Figure 41 (a) and (b) shown in FIG.

 In the present invention, the temporary memory integrated circuit uses a memoryless or high-level C or gate, that is, an OR gate of various integrated circuits (LSTTL, CM OS, TTL, H TL) in the past. Constitute on the chain. The implementation examples are as follows:

For example, use a memoryless LSTTL or high-level C OR gate, that is, a + 74LS32 two-input OR gate in the past, connected to a timing low level Y _t , a timing resistor R _t , and a timing capacitor C _t The single-value temporary register chain of the present invention constitutes the LSTTL high-level monostable trigger temporary register circuit of the present invention. The circuit diagram and logic diagram are shown in Figure 42 (a) and (b).

 Use a memoryless LSTTL or a high-level C or gate, as previously said

+ 7 S32 two-input OR gates, connected to the original single-value temporary chain consisting of a timing capacitor C _t and one end connected to a “ground” timing resistor R _t , and connected to a switching pulse generating circuit at the same input end, thereby constituting the present Inventing the LSTTL positive single pulse generator, its circuit diagram and logic diagram are shown in Figures 43 (a) and (b).

 Use a memoryless LSTTL or a high-level C or gate, as previously said

+ 74LS32 two-input OR gate, connected to a high-level analog suspense chain, constitutes the LSTTL high-level analog suspense device (ie, high-level Schmitt trigger) of the present invention, its circuit diagram and The W logic diagram is shown in Figures 44 (a) and (b). The so-called high-level analog suspense chain is an analog suspense chain with the anode of the diode connected to the input end.

 Use a memoryless LSTTL or a high-level C or gate, as previously said

4 74LS32 two-input OR gates, connected with a double-valued temporary chain, constitute the LSTTL controllable multi-function pulse oscillator of the present invention, and its circuit diagram and logic diagram are omitted.

 A no-memory or low-level CI or gate (referred to as a low-level or gate). It is a low-level C or gate. Phase input I. In the final analysis, it is the use of various integrated circuits

An AND gate (LSTTL, CM OS, TTL, Η TL, Ε C L, etc.), a memoryless low-level homogeneous OR gate formed by adding very few components to give its low-level signal inverting input.

 The memory integrated circuit of the present invention is formed by using a memoryless or low-level C I or gate connected to a memory chain. The implementation examples are as follows:

 For example: Use a memoryless LSTTL or low-level CI OR gate, that is, a "74LS08 two-input AND gate" in the past that has a low-level signal inverting input terminal. This constitutes the LSTTL low-level CI stable register (low-level RS flip-flop) of the present invention, and its circuit diagram and logic diagram are shown in Figures 45 (a) and (b). Figures 46 (a) and (b) are Two high-level NAND gates (two low-level NOR gates) are used to form a two-gate equivalent CI OR gate, and then a wired stable chain is connected to form the original LSTTL low-level RS trigger. And logic diagrams of the controller.

Use a non-memory LSTTL or low-level CI OR gate, that is, a 7-input S 08 two-input AND gate with a low-level signal inverting input, which is connected by the timing low-level Y t, A single-valued temporary chain of the present invention composed of a timing resistor R _t and a timing capacitor C _t , and a similar input terminal C is connected to a high level, which constitutes a low-level signal of the LSTTL low-level signal of the present invention input through an inverting input terminal. The circuit diagram and logic diagram of the steady-state trigger temporary circuit are shown in Fig. 47 (a) and (b). The temporary time t _T »t _T.

 LSTTL or low-level CI or gate. When I terminal is connected to high level, it becomes LSTTL or low-level C or gate. At this time, it is used to form the low-level monostable state of LSTTL of the present invention. The triggers, negative single pulse generators, low-level Schmitt triggers, and controllable multi-function pulse oscillators are exactly the same as LSTTL or low-level C or gatekeeper methods, and are omitted here.

The circuit diagram and logic diagram of a low-level CI stable register (low-level RS flip-flop with small-swing output) of the LSTTL small-swing output of the present invention are shown in Figure 48 (a) and (b) As shown. Its circuit is made of anti-saturation triode! ^ And ^, Schottky diode DD! , D ₂ , D 2, D 2, diode D (silicon diode or Schottky diode), resistors ^ and 1 ₂ , low-level signal input terminals and I, output terminals Q _s and Q _s .

The emitter of T 2 is connected to the anode of D, and the anode of D is connected to "ground"; one end of R 1 is connected to the collector, the other end is connected to the power supply voltage + V _cc , and one end of R ₂ is connected to the collector of T ₂ Electrode, the other end of R ₂ is connected to the power supply voltage + V _cc ; the positive end of 0 ₁ is connected to ₁ 1 to 1, and the negative end of 0! Is the same type of low-level input terminal (:; the negative end of D! Is connected to ^! ! ^, D is positive then T collector _2;!! D as protective diode ς terminal, the negative electrode of D i connection), a negative electrode, D ϋ to cathode of the "ground"; positive then T ₂ jfel 0 _2, and The negative electrode of D ₂ is used as the low-level signal inverting input terminal. I; the negative electrode of D ₂ is connected to D ₂ of D _2- , the positive electrode of D ₂ is connected to the collector, D _{2 is} used as the protection diode of the terminal, and the negative electrode of D ₂ is connected D ₂ is a negative electrode, D 2 connected to the positive electrode "ground"; T ₂ as a collector output terminal Q _s, the collector of the inverting output terminal Q s.

 Figure 49 is a circuit diagram of the LSTTL D flip-flop of the present invention. Its one-and-a-half-time circuit, that is, the trigger guide circuit in the past, is original, and its full-memory circuit, that is, the basic trigger in the past, is the LSTTL low-level RS flip-flop of the present invention. Figure 50 is a circuit diagram of the original LSTTL D flip-flop.

 Figure 51 is a circuit diagram of the LSTTL JK flip-flop of the present invention. Similarly, its one-and-a-half-time circuit, that is, the trigger guide circuit in the past, is the original, and its full-memory circuit, that is, the basic RS trigger in the past, is the LSTTL low-level RS flip-flop of the present invention.

 Figure 52 is a circuit diagram of the LSTTL small swing output D flip-flop of the present invention. Its once-and-a-half circuit is original, and its all-memory circuit is a low-level RS flip-flop of the LSTTL small swing output of the present invention.

 To sum up, the LSTTL D flip-flop, LSTTL J flip-flop, LSTTL various counters, various digital registers, various shift registers, etc. of the present invention, the invention is that their all-memory circuits are the LSTTL of the present invention Low-level RS flip-flop. The D flip-flops, flip-flops, various counters, various digital registers, various shift registers, etc. of the LSTTL small-swing output of the present invention are the invention of their all-remember circuit (the basic flip-flop in the past) ) Are low-level RS flip-flops of the LSTTL small swing output of the present invention.

A no-memory or high-level CI or gate (referred to as a high-level or gate), it is a high-level C or gate, with very few components to give its high-level signal. Phase Constituted by the input terminal I. In the final analysis, it is an OR gate of various integrated circuits (LSTTL, CM OS, TTL, HTL, ECL, etc.) that was said in the past, and it provides the high-level signal at the inverting input terminal by adding very few components. Memory logic circuit.

 The memory or integrated circuit of the present invention is formed by using a memoryless or high-level C I or gate connected to a memory chain. The implementation examples are as follows:

 A memoryless LSTTL or high-level CI or gate is used, that is, a + 74LS32 two-input or gate with a high-level signal inverting input in the past, connected to a first-line stable chain to form the present invention. LSTTL high-level CI stabilizing device (high-level RS flip-flop), its wiring diagram and logic diagram are shown in Figure 53 (a) and (b).

Use a non-memory LSTTL or high-level CI or gate, that is, a 74LS32 two-input or gate with a high-level signal inverting input, which is connected by a timing high-level V _t and a timing resistor R _t , a single value temporary chain of the present invention composed of a timing capacitor ^, and the same type of input terminal is connected to a low level, which constitutes a high level signal, and the LSTTL high level monostable flip-flop of the present invention is input through the inverting input Remember the circuit, its wiring diagram and logic diagram are shown in Figure 54 (a) and (b). Its temporary time t _T »t _T.

 A memoryless LSTTL or high-level C I or gate is connected to a temporary register chain to form another LSTTL register circuit of the present invention, which is omitted here.

 As another example, a memoryless ECL or high-level CI OR gate, that is, an EC L OR gate in the past with a high-level inverting input terminal, connected to a ½-line stable memory chain, constitutes the present invention. ECL High CI Stabilizer (ECL High RS Trigger). Figures 55 (a) and (b) are circuit diagrams and logic diagrams of the ECL high-level RS flip-flops with 0 and 1 set in the present invention. Figure 56 (a) and (b) are composed of two high-level NOR gates to form a two-gate equivalent high-level NOR gate, and then connect a connected stable chain to form the EC L original high voltage Circuit diagram and logic diagram of the flat RS flip-flop.

 The memory or memory circuit of the present invention is formed by a memoryless memory or memory expansion or memory gate connected to a connected memory chain. The OR-type extended OR gate is a high-level AND gate in various integrated circuits (LSTTL, CM OS, TTL, HTL, E C L, etc.) said in the past. The implementation examples are as follows:

Use a memoryless LSTTL two-input two-or-type high-level OR gate to extend the OR gate, that is, a LSTTL two-input two-level high-level AND gate, and one end of one of the two input terminals is connected to a one-wire stable chain. 1. The other end is connected to a clock pulse other than CP, one end of the other two input ends is connected to a clock pulse CP, and the other end is connected to a binary signal D. This constitutes the present invention. LSTTL D transflective register (digital latch). The circuit diagram is shown in Figure 57. Figure 58 shows the original LSTTL! ) Semi-transparent circuit (digital latch) circuit diagram, which is composed of two gates.

 The present invention has a special multifunctional CM OS basic new device, referred to as CM O S universal basic new device, which is represented by ZC01, and its circuit diagram and logic diagram are shown in FIG. 59 and FIG. 60. A new type of LSTTL basic new device with special functions, referred to as LSTTL universal basic new device, is represented by ZL03. Its circuit diagram and logic diagram are shown in Figure 61 and Figure 62.

ZC 01 and ZL 03 are composed of a three-valued signal input circuit, a once-and-a-half circuit, and two levels of signal extension or gate. ZL03 has one more voltage-controlled pulse oscillator function than ZC 01, and other functions are exactly the same. The input of ZC01 has r, C (),

ϊ, Ι, Ε, CP, D, J, K; output terminal Q, inverting output terminal Q, drain ¾ phase output terminal Q 0 D. Γ terminal is used instead of input terminal when ZC 01 is used as a memory circuit Yes, C _Q is used as a similar input terminal when ZC 01 is used as a low-level signal or memory circuit or directly set as 0 when ZC 01 is used as a D flip-flop and J flip-flop. . 01 for low-level signal or memory circuit as the inverting input or ZC 01! ) Triggers and JK triggers are set directly as 1 terminal, C and Ϊ are used as high-level signal or memory circuit in ZC01 for similar inputs and inverting inputs, E is for bidirectional analog control of CM OS Control signal input terminal for switch on or off, CP is the clock pulse input terminal, D is the input terminal of D flip-flop, J, K is the input terminal of JK flip-flop. The input terminal V _b of ZL03 is used as the input terminal of control voltage when ZL03 is used for voltage controlled pulse oscillation. The other input terminals r, Go, Ji, C, I, R, CP, D, J, have the same meaning as ZC01; output terminal Q, inverting output Q, current collector ^ L ^ phase output Q oc

ZC 01's QQD terminal with sink current load capacity is 80m A, ZL03's QQ _C terminal with sink current load capacity is 60m A (designed as 100m A).

ZC 01 universal basic new device has the following special functions: 1. Can be used as high-level AND gate (CP = L, D = J = Κ = Φ, Ε = L, I, = h. Ϊ = L); 2 Can be used as high-level NOR gate (input terminal setting conditions are the same as 1), the equivalent logic diagram of 1 and 2 is shown in Figure 63 (a); 3. Can be used as a digital latch (CP-L, D = J = = Φ, Ε = h, Ιι = h, ϊ = L), and its equivalent logic diagram is shown in Figure 63 (b). L is a logic low level, h is a logic high level, and Φ is L or h; 4. Can be a low-level homologous OR gate (ie, high-level AND gate) (CP = L, D = J = K

= Φ, E = L,. = H, C = L, R = Φ. 1 = L); 5. Can be used as high-level NAND gate (input terminal setting conditions are the same as 4), 4 and 5 are equivalent The logic diagram is shown in Figure 63 (c); 6. Can be used as a low-level RS flip-flop (CP = L, D = J = = Φ _¾ C

= i = L, E = h, R = Φ), its equivalent logic diagram is shown in Figure 63 (d); 7. Can be used as a single pulse generator (input terminal setting conditions are the same as 6), its equivalent logic As shown in Figure 63 (e); 8. It can be a low-level monostable flip-flop with a timing low level Y _{t to} directly control the temporary change of the continuous time within a large range, and its temporary time is determined by Y _t and R _t And C _t

(CP = L, D = J = K = 0, Ε = L, C = I = L, C ₀ = h, R

== Φ), its equivalent logic diagram is shown in Figure ⁶³ (f); 9. Low-level monostable flip-flops that can be used to control the timing high-level V _{t to} directly control the continuous change of the temporary recording time in a large range ( CP

= L, D = J = Κ = Φ. Ε = L. C = ϊ = L, R = Φ, Ji = h), the temporary time is determined by V _t , R _t , C _t , which are equivalent The logic diagram is shown in Figure 63 (g); 10. It can be used as a positive single pulse generator (input terminal setting condition 8), and its equivalent logic diagram is shown in Figure 63 (h); 11. It can be used as a negative single pulse Generator (input terminal setting conditions are the same as 9), its equivalent logic diagram is shown in Figure 63 (i); 12. can be used as a low-level Schmitt trigger (input terminal setting conditions are the same as 9), etc. The effect logic diagram is shown in Figure 63 (j). 13. The square wave generator (the square wave square accuracy is called squareness) and the frequency can be adjusted continuously and accurately can be used as the high level timing. CP = L, D = J = K = 0, Co = Ii = h. C = ϊ = L, E = L, R = Φ), and its frequency is determined by the timing high level, timing resistance, and timing capacitor. 14. Multi-vibrator that can control the continuous high-frequency and change the frequency continuously (the setting condition of the input terminal is the same as 13), and its frequency is determined by three of the high-level timing, timing resistance and timing capacitor; Timing high direct Pulse control space (pulse space referred to as pulse space) A constant pulse width (pulse width referred to as pulse width) that varies continuously over a wide range. An intermittent oscillator (the input terminal setting conditions are the same as 13), and its frequency is determined by timing high level, timing The resistance and the timing capacitor are determined. 16. An intermittent oscillator with continuously adjustable pulse width and a continuously adjustable pulse width can be directly controlled by timing high level. The frequency is set by 13 Timing high, timing resistance, timing The three capacitors are determined; 17. The ultra-low frequency pulse oscillator (the input terminal setting conditions are the same as 13) that can directly control the pulse space to continuously change the pulse high level at the timing high level, the timing capacitor C _t and the timing resistor R _t (pulse The value of air resistance) is large, and its oscillation period continuously changes from 20 seconds to 1 hour. The equivalent logic diagrams of 13, 14, 15, 16, and 17 are shown in Figure 63 (k);

18. Can be used as the above-mentioned, controllable square wave generator (terminated control signal, others are the same as 13);

19. Can be used as the above-mentioned, controllable multivibrator; 20. Can be used as the above-mentioned, controllable fixed-pulse-width intermittent oscillator; 21. Can be used as above-mentioned, controllable variable-pulse-width intermittent oscillator, 19 The setting conditions of the input terminals of 20, 21 and 18 are the same as the equivalent logic diagrams of 18, 18, 19, 20, and 21, as shown in Figure 63 (I). 22. Can be used as high-level homologous OR gate (CP = L,

D = J = = Φ, E = L, Co = ii = h, i = L, R = h); 23. Can be used as high-level NOR gate (setting conditions are the same as 22), 22 and 23 are equivalent The logic diagram is shown in Figure 63 (m); 24. Can be used as a high-level RS flip-flop (CP = L, D = J = KK = Φ, E = h, Co = Ii = = h), its equivalent logic The figure is shown in Figure 63 (n); 25. High-level monostable flip-flops (CP = L, D = J = κ = Φ) that can be used to directly control the temporal change of the temporary recording time in a large range. Ε = L, Q ο = I

! = R = h. C = L), its temporary recording time is determined by the timing high level, timing resistance, and timing capacitor. The equivalent logic diagram is shown in Figure 63 (0); High-level monostable flip-flop with continuous level change in level control

(CP = L, D = J = = Φ, E = L, Q ₀ = Ii = R = h, i = L), and its temporary time is determined by the timing low level, timing resistance, and timing capacitor. The equivalent logic diagram is shown in Figure 63 (p); 27. Can be used as a high-level Schmitt trigger (setting conditions are the same as 26), the logic diagram is shown in Figure 63 (q), high-level CI or The gate is the same as the low-level CI or gate described above. It can be used as three types of single pulse generators and uncontrollable and controllable multi-function pulse oscillators. Here-omitted; 28. Can be used as a D flip-flop. (CP is connected to the clock pulse, J = L, K = h, E = h, Go and Ji are connected to control the negative pulse, C

= ϊ = L, R = Φ), its equivalent logic diagram is shown in Figure 63 (r); 29. Can be used as a J flip-flop (D = L, CP is connected to the clock pulse, E = h, Co and 接 are connected to control Negative pulse, C = ϊ = L, R = Φ), and its equivalent logic diagram is shown in Figure 63 (s).

1. RS triggers, monostable triggers, Schmitt triggers, keyboard anti-shake unit circuits, and single pulse generators of the original technology are all composed of two NAND gates or two NOR gates, and The technology of the present invention is constituted by only one OR pattern or gate. Obviously, the present invention or the memory circuit has the advantages of saving a large number of components and connections, high speed, low power consumption, high reliability, small size, and the like. In particular, the CM 0 S debounce circuit of the computer keyboard of the present invention is constituted by a CM 0 S single input or gate. Its components are 1/3 of the original technology, and its power consumption is 1Λ000 of the original technology.

2. The monostable flip-flop of the present invention not only greatly simplifies the circuit, but also is very valuable. It can use the timing level to directly control the temporary recording time to continuously change within the range of 1 to nearly 20 times of the original technical temporary recording time (both R _t Same as C _t ), the temporary recording time is determined by the timing level, the timing resistance, and the timing capacitor. The original technology cannot use the level to control the length of the temporary recording time. It is determined by the user that the suspense time of the original technology is the minimum value of the suspense time of the technology of the present invention. The temporary recording time of the monostable flip-flop of the present invention is nearly 20 times that of the original technology (the two R _t and C _{t are the} same).

 3. The pulse oscillator of the present invention has two valuable advantages: one is that it has multiple (9 kinds) oscillation functions; the other is that the pulse-to-space ratio can be directly controlled by timing high level (pulse-to-space ratio = pulse-to-space: pulse width) at Continuously change in the range of more than 0.8 to 300 or more than 1Λ8 to 100. The frequency is determined by the timing high level, timing resistance, and timing capacitor. The original pulse oscillator has a single oscillation function, and cannot directly use the level to control the frequency change. The frequency of the original pulse oscillator is determined by both the timing resistor and the timing capacitor.

 4. The special multifunctional new device of the present invention has two valuable advantages: one is that it has many functions and is widely used; it is very convenient and flexible for design, use and maintenance; and the other is that it can greatly reduce the variety of integrated circuits and is greatly appreciated. Users and manufacturers are welcome.

 5. The B iCM 0 S stable memory integrated circuit of the present invention has two outstanding advantages: one is that the circuit is very simple; the other is that it has the advantages of a CMOS integrated circuit and a TTL integrated circuit. The resistance value of TTL in B iC M 0 S is 6 to 10 times that of TTL integrated circuit.

Claims

Rights to —

1. A NOR memory integrated circuit, comprising a NOR gate and a memory chain, the NOR gate includes an output terminal (Q) and a plurality of replacement input terminals

(r), the memory link is between the output end of the OR gate and the replacement input end.

 A NOR memory integrated circuit according to claim 1, wherein said OR gate is a OR-type high-level I-OR gate.

 A NOR memory integrated circuit according to claim 2, characterized in that the logical function of the NOR high-level OR gate is Q = r + T.

 4. The OR memory memory integrated circuit according to claim 3, wherein the logic function is

Q = r + DOR high-level I-OR gate is composed of a first inverter (T1), a second inverter (T2) and a diode, the first inverter (T1) The output terminal of the second inverter (T2) is connected to the positive terminal of the diode and the positive terminal of the diode at the same time, and the output terminal of the second inverter (T2) is used as the The output terminal, the input terminal of the first inverter (T1) and the negative terminal of the diode are used as the replacement input terminal and the control input terminal of the OR gate respectively.

 5. The OR memory memory integrated circuit according to claim 1, wherein the OR memory gate is an OR low-level I memory gate.

 6. The NOR memory integrated circuit according to claim 5, characterized in that the logical function of the OR low-level I-OR gate is Q = rding.

 7. The NOR memory integrated circuit according to claim 6, characterized in that the OR gate having a logic function of Q = rT is composed of a first inverter (T1), a second inverter (T2) and a diode. The output terminal of the first inverter (T1) is simultaneously connected to the input terminal of the second inverter (T2) and the negative terminal of the diode, and the output terminal of the second inverter (T2) is The output terminal is used as the output terminal of the OR memory integrated circuit, and the input terminal of the first inverter (T1) and the positive terminal of the diode are used as the replacement input terminal and Control input.

 8. The NOR memory integrated circuit according to claim 1, wherein said OR gate is an OR low-level C OR gate.

 The OR memory IC as claimed in claim 8, characterized in that said OR type low-level C OR gate is an AND gate.

10. The OR memory integrated circuit according to claim 9, wherein said AND gate is 1

One CC4081 circuit.

 4

 1 1. The OR memory integrated circuit according to claim 9, wherein the AND gate is 1

A: 74LS08 circuit.

 4

 12. The NOR memory integrated circuit according to claim 1, wherein said OR gate is an OR high-level C OR gate.

 13. The NOR memory integrated circuit according to claim 12, wherein the OR high-level C OR gate is an OR gate.

 14. The OR memory memory integrated circuit according to claim 13, characterized in that said OR gate 1

It is a CC4071 circuit.

15. An OR memory memory integrated circuit according to claim 13, characterized in that said OR gate 1

Is a ^ 74LS32 circuit.

16. A NOR memory integrated circuit according to claim 1, wherein said OR gate is an OR low-level OR gate.

 17. The OR memory memory integrated circuit according to claim 16, wherein the OR memory

 1

The low-level OR gate is composed of ^ 74LS08 circuit plus two Schottky diodes, the anodes of the two Schottky diodes are docked, and the anodes of the two Schottky diodes are respectively

1

It is connected to the ground potential of the Schizaky transistor T101 in the 74LS08 circuit.

18. A NOR memory integrated circuit according to claim 1, wherein said NOR gate is an NOR high-level NOR gate.

 19. The NOR memory integrated circuit according to claim 18, characterized in that the NOR high-level OR gate comprises a first inverter (T1), a second inverter (T2) and at least one A first diode and at least one second diode, an input terminal of the first inverter is connected to a positive terminal of the at least one first diode, and the first inverter

The output terminal of (T1) is connected to the input terminal of the second inverter (T2) and the positive terminal of the at least one second diode at the same time, and the output terminal of the second inverter (T2) is used as The output terminal of the OR memory integrated circuit, the negative terminal of the at least one first diode and the negative terminal of the at least one second diode are respectively used as substitute inputs of the OR memory integrated circuit. And control inputs.

20. The NOR-type memory integrated circuit according to claim 1, wherein the NOR-type gate is an OR-type CI or NOR gate.

21. The OR memory IC according to claim 20, characterized in that the OR CI or OR gate is composed of a first inverter (T1) and a second inverter (T2) connected in series. An input terminal of the first inverter (T1) is used as the in-phase input terminal (C) of the OR type CI or gate, and an input terminal of the second inverter (T2) is used as the OR type CI The inverting input terminal (I) of the OR gate, and the output terminal of the second inverter (T2) serves as the output terminal (Q) of the OR type CI OR gate.

 22. The NOR memory integrated circuit according to claim 1, wherein said OR gate is a single input terminal or OR gate.

 23. The NOR memory integrated circuit according to claim 22, wherein said single input terminal or NOR gate is a CMOS same gate.

 24. The NOR memory integrated circuit of claim 23, wherein the CMOS gate is formed by connecting two CMOS NOT gates in series.

 25. The or memory memory integrated circuit according to any one of claims 1 to 24, wherein said memory chain is a double-valued temporary memory chain.

26. The OR memory memory integrated circuit according to claim 25, wherein said double-valued suspense chain is a first type of double-valued suspense chain, and said first type of double-valued suspense chain is input by a timing level Terminal (V _t ), a timing capacitor (), a first timing resistor (R _t ), a second timing resistor (R _t ), and a switching tube (So), wherein the timing capacitor (C _t ) Is connected between the output end of the OR gate and the replacement input end of the OR gate, one end of the switch tube (So) is connected to a predetermined potential, and the other end of the switch tube (So) Connected to the replacement input terminal of the OR gate through a resistor R _t , the switch tube

The other end (So) is further connected to the timing input level (V _t :) first through the timing resistor (R _t).

27. The OR memory memory integrated circuit according to claim 25, wherein said double-valued suspense chain is a first type of double-valued suspense chain, and said first type of double-valued suspense chain is input by a timing level Terminal (V _t ), a timing capacitor (C _t ), a first timing resistor (R _t ), a second timing resistor (R _t ), and a switch (So), wherein the timing capacitor (C _t ) Is connected between the output end of the OR gate and the replacement input end of the OR gate, one end of the switch tube (So) is connected to a predetermined potential, and the other end of the switch tube (So) _t remember the door or to the input terminal through a resistor substituent R, the substituted or write gate input terminal further connected to the timing input level (V _t) by a first timing resistor (R _t).

 28. The or memory memory integrated circuit according to any one of claims 1 to 15, characterized in that said memory chain is a single-valued temporary memory chain.

 29. The OR memory memory integrated circuit according to claim 16, wherein said memory chain is a single-valued temporary memory chain.

30. A NOR memory integrated circuit according to claim 29, wherein said NOR low-level OR gate includes a first anti-saturation transistor (;) and a second anti-saturation transistor. And a transistor (T ₂ ), a resistor () connected between a collector of the first anti-saturation transistor (T,) and a power source (+ Vcc), a collector connected to the second anti-saturation transistor The resistance (R ₂ ) between the electrode (T ₂ ) and the power source (+ Va), one positive electrode is connected to the collector of the first anti-saturation transistor (T,), and the negative electrode is connected to the second anti-saturation transistor (T ₂ ). A base-connected diode (), a diode (D,) with a positive electrode connected to the collector of a second anti-saturation transistor (T ₂ ), a negative electrode connected to the base of the first anti-saturation transistor (L), and a positive electrode connected to the two anti-saturation transistor base (Τ ₂₎ coupled to the source, the diode (D ₂₎ is connected to the negative terminal of the J, a positive electrode and a first anti-saturation transistor (T,) is connected to the base, and the negative electrode (: a diode connected ( ), A diode with a positive pole connected to the ground potential and a negative pole connected to the (; terminal), a diode with a positive pole connected to the ground potential and a negative pole connected to the .1 terminal (D ₂ ), a positive pole connected to the first reactance at the same time Emitter of saturation transistor (L) and second anti-saturation transistor (T ₂₎ connected to the emitter, the diode cathode connected to earth potential (D), wherein the collector of the second anti-saturation transistor (Τ ₂₎ is also connected to terminal Qs, and D "D ,, D,, D 2 , D ₂ and D ₂ are Schottky diodes.

 31. The OR memory memory integrated circuit according to claim 17, characterized in that said memory chain is a single value temporary memory chain, and the in-phase input terminal (C) of the OR low-level or memory gate is maintained as High level, the control signal is input by the inverting input terminal (I) of the OR low level or gate.

 32. The OR memory memory integrated circuit according to claim 17, wherein said memory chain is a single-valued temporary memory chain, and said OR input low-level OR memory gate's inverting input terminal (I) is maintained as High level, the control signal is input from the in-phase input terminal (C) of the OR low level or gate.

 33. The or memory memory integrated circuit according to any one of claims 18 to 21, wherein said memory chain is a single-valued temporary memory chain.

Recordable or any one of IC memory 33, characterized in that said clearing chain is comprised of a single value of a timer input level (V _t), - - 34. claimed in claim 28 as a timing resistor

(Rt) and a timing capacitor (), the timing capacitor () is connected between the output terminal of the OR gate and the replacement terminal of the OR gate, and the timing resistor (R _t ) is connected at Between the replacement input terminal of the OR gate and the timing level input terminal (V _t ).

 35. The OR memory integrated circuit according to any one of claims 1 to 15, 5, 18 or 19, characterized in that said memory chain is a stable memory chain.

 36. The or memory memory integrated circuit according to claim 16, wherein said memory chain is a stable memory chain.

37. The NOR memory integrated circuit according to claim 34, characterized in that the NOR low-level OR gate comprises a first inverter (T1), a second inverter (T2) and at least one A first diode and at least one second diode, an input terminal of the first inverter is connected to a negative terminal of the at least one first diode, and the first inverter The output terminal of (Tl) is connected to the input terminal of the second inverter (T2) and the negative terminal of the at least one second diode at the same time, and the output terminal of the second inverter (T2) is used as The output terminal of the OR memory integrated circuit, the negative terminal of the at least one diode and the positive terminal of the at least one second diode are respectively used as a substitute input terminal and a control input of the OR memory integrated circuit. end.

 38. The or memory memory integrated circuit according to claim 37, wherein said at least one first diode is one and said at least one second diode is one.

 39. The OR memory memory integrated circuit according to claim 37, wherein said at least one first diode is two and said at least one second diode is two.

 40. A NOR memory integrated circuit according to claim 38, further comprising a first TTL high-level NAND gate (AN1) and a second TTL high-level NAND gate (AN2), said first The output terminal of the TTL high-level NAND gate (AN1) is connected to the second inverter

(T2) the other end of the diode of the input terminal is connected, the second TTL high-level NAND gate (AN2) is connected to the other end of the diode connected to the input terminal of the first Schottky transistor (T1), the first TTL Each of the high-level NAND gate (AN1) and the second TTL high-level NAND gate (AN2) has an input terminal connected to the control terminal (CP), and the first TTL high-level NAND gate ( AN1) has another input terminal as a non-inverting input terminal (C), and the other input terminal of the second TTL high-level NAND gate (AN2) serves as an inverting input terminal (I).

 41. A full memory circuit using the OR memory memory integrated circuit as claimed in claim 38 for a BiCMOS new D flip-flop, a Bi CMOS new JK flip-flop, a BiCMOS new counter and a new Bi CMOS new register, and one of the half-write circuits Or the control circuit of the input signal is a TTL circuit.

 42. The OR memory memory integrated circuit according to claim 17, wherein said memory chain is a stable memory chain.

 44. Use of the OR memory integrated circuit as claimed in any one of claims 42 or 43 as a new D register (new D trigger), a new JK register (new JK trigger), a new counter, new The register and the output of the new shift register are all written in the circuit.

 45. The or memory memory integrated circuit according to any one of claims 20 or 21, wherein said memory chain is a stable memory chain.

 46. A keyboard anti-shake unit circuit composed of a memory or memory integrated circuit according to claim 45, comprising a diode and a single-pole double-throw switch, the negative terminal of the diode is grounded, and the positive terminal of the diode is connected to the single-pole double-pole. The fixed point of the throw switch can be connected to the non-inverting input terminal (C) or the inverting input terminal (I) of the memory integrated circuit of claim 38 in response to the operation.

 47. The keyboard anti-shake unit circuit according to claim 46, characterized in that said OR memory integrated circuit can also be NMOS or LSTTL or memory integrated circuit.

48. The or memory memory integrated circuit according to any one of claims 22 to 24, wherein said memory chain is a stable memory chain.

49. A static memory unit composed of the CMOS memory integrated circuit according to claim 48, characterized in that an input terminal of the CMOS memory integrated circuit is connected in series by a first switching tube (Π) and a The second switch tube (K2) is connected to the data line (D), wherein the first switch tube (K1) and the second switch tube K2 are controlled by a row escape signal and a column selection signal, respectively.

 50. A NAND memory integrated circuit according to any one of claims 35, 36, 42, 45 or 48, wherein said stable chain is a conductive connection.

 51. The or memory memory integrated circuit according to claim 19, wherein said at least one first diode is one and said at least one second diode is one.

 52. The OR memory integrated circuit according to claim 51, wherein said memory chain is a stable memory chain.

 53. A computer keyboard anti-shake unit circuit composed of the memory IC of claim 52, characterized in that the inverting input terminal I of the memory IC is connected to a normally closed contact of a key switch Terminal, the same input terminal C of the said memory integrated circuit is connected to the normally open contact terminal of the key switch, and the common terminal of the key switch is connected to the power supply voltage + VDD „

54. A basic new CMOS device with special multi-function, consisting of three parts: a double-valued signal input circuit, a once-and-a-half circuit, and a two-level signal extension or gate. The input terminal has it! ^. , ^,. , ^ ^ ,. ? ^,],! ^, The output terminal has an output terminal Q, an inverting output terminal Q, a drain inverting output terminal _QQD , and the r terminal is used instead of the input terminal when used as a memory circuit, C. Low-level signal or memory circuit is used as a similar input terminal or D flip-flop and JK flip-flop are directly set to 0, 1! For low-level signal or memory circuit, it is inverted The input terminal can be directly set to 1 when used as D flip-flop and JK flip-flop. When C and I are used as high-level signal or memory circuit, it can be used as similar input and inverting input. S Two-way analog switch control signal input terminal on or off, CP is the clock pulse input terminal, D is! ) The input of the trigger, J, is the input of the JK trigger.

55. A basic new LSTTL device with special multi-function, consisting of a three-valued signal input circuit, one-and-a-half-time circuit, and two-level signal extension or gate. The input terminals have r and C. ^ C, I, R, E, CP, D, J, K, the output terminal has an output terminal Q, an inverting output terminal Q, a collector inverting output terminal Q oc, and r is used as a memory circuit. Instead of the input terminal, C 0 is used as a low-level signal or a memory circuit of the same type or used as a D flip-flop and a JK flip-flop. Inverted input terminal for memory circuit or as direct input terminal for flip-flops and JK flip-flops, and C and I for high-level signal or for inverting input circuit of memory circuit For the input terminal, E is for controlling the on / off control of the CMOS bidirectional analog switch Signal input, CP is the clock pulse input, D is the input of D flip-flop, J,

K is the input terminal of the JK flip-flop, and Vb is used as the input terminal of the control voltage when the LSTTL is used as a voltage-controlled pulse oscillator.