WO1998025344A1 - An or-type memorizing integrated circuit - Google Patents

An or-type memorizing integrated circuit Download PDF

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Publication number
WO1998025344A1
WO1998025344A1 PCT/CN1997/000138 CN9700138W WO9825344A1 WO 1998025344 A1 WO1998025344 A1 WO 1998025344A1 CN 9700138 W CN9700138 W CN 9700138W WO 9825344 A1 WO9825344 A1 WO 9825344A1
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WIPO (PCT)
Prior art keywords
memory
level
gate
integrated circuit
input
Prior art date
Application number
PCT/CN1997/000138
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French (fr)
Chinese (zh)
Inventor
Zongxue Zhang
Original Assignee
Zongxue Zhang
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Publication date
Application filed by Zongxue Zhang filed Critical Zongxue Zhang
Priority to AU51867/98A priority Critical patent/AU5186798A/en
Publication of WO1998025344A1 publication Critical patent/WO1998025344A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/355Monostable circuits

Definitions

  • the present invention generally relates to integrated circuits, and more particularly, to memory integrated circuits. Background technique
  • an object of the present invention is to provide a basic RS flip-flop and a monostable flip-flop ( ⁇
  • a circuit having memory properties such as an RS flip-flop and a monostable flip-flop is collectively referred to as or a memory circuit )
  • They have the advantages of fewer components, so fewer internal connections, high speed, low power consumption, high reliability, small size and so on.
  • the present invention provides a NOR memory integrated circuit, which includes an OR gate and a memory chain, the OR gate includes an output terminal (Q) and a plurality of replacement input terminals (r). At the internal input, the memory link is between the output of the OR gate and the replacement input.
  • the invention also provides a new device with special multi-function, which includes three parts of a double-valued signal input circuit, a once-and-a-half circuit, and two-level signal expansion or gate.
  • the present invention implements a memory IC with only one OR gate, so it has fewer components, so fewer internal connections, high speed, low power consumption, high reliability, Small size and other advantages. Because the present invention also introduces timing levels in the single-valued memory chain and the double-valued memory chain at the same time, so that the temporary recording time of the monostable flip-flop and the oscillation frequency of the pulse oscillator are easy to control.
  • Figure 1 is an example of a diode low-level hetero OR gate, where (a) is a circuit diagram and (b) is a logic diagram;
  • FIG. 2 is an example of an emitter output high-level hetero-OR gate, where (a) is a circuit diagram, and (b) is a logic diagram;
  • Figure 3 is a 74LS08 low-level homologous OR gate circuit diagram
  • Figure 4 is the same high-level OR gate circuit diagram of S32;
  • FIG. 5 is an example of a connected stable memory chain, where (a) is a logic diagram of a low-level OR memory circuit, and (b) is a logic diagram of a low-level CI memory stabilizer of the present invention
  • FIG. 6 is an example of a single-valued temporary diary chain of the present invention, where (a) is a low-level OR circuit diagram, and (b) is a logic diagram of the low-level diary of the present invention;
  • FIG. 7 is an example of a double-valued temporary register chain, where (a) is a logic diagram of a low-level OR register circuit, and (b) is a logic diagram of a controllable multifunctional pulse oscillator of the present invention
  • FIG. 8 is an analog suspense chain, where (a) is a low-level C or gate logic diagram, (b) is a low-level analog stylus logic diagram of the present invention, and (c) is a high-level C or gate gate A logic diagram, (d) is a logic diagram of a high-level analog register of the present invention;
  • Figure 9 is the LSTTL or low-level or gated circuit diagram
  • Figure 10 is a LSTTL or high-level or gated circuit diagram
  • Figure 11 is an ECL or high-level or gated wiring diagram
  • Figure 12 is a TTL two-gate equivalent low-level or gate-keeping circuit diagram
  • Figure 13 is a LSTTL or high-level extension or i-gate circuit diagram
  • Figure 14 is a low-level or gated circuit diagram of the TTL collector output
  • Figure 15 is a CM 0 S single input or gated wiring diagram
  • FIG. 16 is a conventional high-level monostable flip-flop (t T 0.7R t C t ) of the CM OS, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 17 is a low-level monostable flip-flop (t T >> t T »0.7R t C t ) of the CM OS of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 18 is a CM OS high-level monostable flip-flop (t T ⁇ > t T ⁇ 0.7R t C t ) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • 19 is a CM OS multi-function pulse oscillator of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram; 20 is a CM OS controllable multifunctional oscillator according to the present invention, where (a) is a circuit diagram, (b) is a logic diagram, (c) is a circuit diagram, and (d) is a logic diagram;
  • FIG. 21 is a CMOS original high-level RS flip-flop, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 22 is a CM 0 S low-level C I stabilizing device ( ⁇ invention CM O S low-level RS flip-flop) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 23 is a CM 0 S high level C I stable register of the present invention ( ⁇ invention CM O S high level RS flip-flop), where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 24 is a unit circuit of a computer keyboard CMOS debounce original technology, where (a) is a circuit diagram, and (b) is a logic diagram;
  • CM 0 S debounce unit circuits of the computer keyboard of the present invention where (a) is a circuit diagram and (b) is a logic diagram;
  • FIG. 26 is the second circuit of the CM 0 S debounce unit of the computer keyboard of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 27 is a CMOS original static memory cell circuit, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 28 is a single-line read / write CM OS static storage unit according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 29 is a BiCM 03 controllable (1 stable register ( ⁇ invention 8 1 ⁇ 0 S controllable high-level RS flip-flop) of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 30 is a four-digit digital register of B iCM 0 S working in the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 31 is a D-type flip-flop of BiCM 0 S according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 32 is a circuit diagram (tri-state) of the circuit diagram of the B iC M 0 S eight-bit register of the present invention.
  • FIG. 33 is a circuit diagram of a D flip-flop of BiCM 0 S of the present invention.
  • FIG. 34 is a circuit diagram of a JK flip-flop of B iC M 0 S of the present invention.
  • FIG. 35 is a circuit diagram of a B iCM 0 S four-bit binary counter according to the present invention.
  • FIG. 36 is an LSTTL low-level monostable flip-flop of the present invention (t T >> t T ⁇ 0.7R t C t ), where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 37 is a LSTTL original traditional low-level monostable flip-flop (t T ). 7R t C t ), where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 38 is a LSTTL negative single pulse generator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 39 is a LSTTL low-level Schmitt trigger according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 40 is a LSTTL original low-level Schmitt trigger, where (a) is a circuit diagram, and (b) is a logic diagram;
  • 41 is a LSTTL controllable multi-function pulse oscillator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • Figure 42 is the LSTTL high level monostable flip-flop of the present invention
  • FIG. 43 is a LSTTL positive single pulse generator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 44 is a LSTTL high-level Schmitt trigger of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 45 is a LSTTL low-level C I stable register ( ⁇ invented low-level RS trigger) of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 46 is a L ST T L original low-level C I stabilizing device (formerly a conventional low-level RS trigger), where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 47 is an LSTTL low-level monostable flip-flop (t T »t T ) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 48 is a low-level CI stable register (small-swing level RS flip-flop) of the LSTTL small swing output of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 49 is a circuit diagram of the LSTTL-D flip-flop of the present invention.
  • Figure 50 is the original D flip-flop circuit diagram of LSTTL
  • FIG. 51 is a circuit diagram of the LSTTL-J flip-flop of the present invention.
  • Figure 52 is a circuit diagram of the LSTTL small swing output D flip-flop of the present invention.
  • FIG. 53 is a LSTTL high-level C I stable register of the present invention (high-level RS trigger of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 54 is a LSTTL high-level monostable flip-flop (t T »t T ) of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 55 is an ECL high-level C I stable register of the present invention (ECL high-level RS flip-flop of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;
  • FIG. 56 is an ECL original conventional high-level RS flip-flop, where (a) is a circuit diagram, (b) is a logic diagram;
  • FIG. 57 is a circuit diagram of the L ST TL ⁇ D transflective register (digital latch) of the present invention
  • FIG. 58 is a circuit diagram of the original D transflective register of LSTTL;
  • Figure 59 is the CM OS universal basic new device ZC 01 circuit diagram
  • Figure 60 is the logic diagram of the CM OS universal new basic device ZC 01;
  • Figure 61 is the LSTTL universal basic new device ZL03 circuit diagram
  • Figure 62 is the logic diagram of the LSTTL universal new basic device ZL 03;
  • FIG. 63 (ai) is a logic diagram of various functions corresponding to the CM 0 S and LSTTL universal basic new devices of the present invention. Detailed description of the invention
  • the memory-type memory integrated circuit of the present invention is a great invention memory integrated circuit obtained by the inventor, Zhang Zongxue, using the "law of stable circuit-keeping" and “temporary law of circuit-keeping” proposed by himself in May 1986. It includes the invention or memory type integrated circuit, invention or memory type integrated circuit, invention B iCM 0 S memory and integrated circuit, and a new device with special multi-function (also known as universal basic new device).
  • the NOR memory integrated circuit of the present invention uses only one NOR gate to form a basic RS flip-flop and a monostable flip-flop.
  • the original technology uses two NAND gates or two NOR gates to form a basic RS trigger Trigger and a traditional monostable trigger. Therefore, the invention or memory memory integrated circuit is called a memory integrated circuit, and the original technology is two memory integrated circuits.
  • the inventive technology has the advantages of saving a large number of components and internal wiring, high speed, low power consumption, high reliability, and small size.
  • Invented monostable flip-flops can use levels to directly control the temporary recording time to continuously change over a wide range.
  • the temporary recording time is determined by three levels: timing level, timing resistance, and timing capacitor. It is determined by both the timing resistor and the timing capacitor. It cannot directly control the temporary recording time with the level.
  • the invented pulse oscillator has multi-function oscillation. It is even more valuable that the frequency can be directly controlled to continuously change in a large range with a timing high level.
  • the oscillation frequency is determined by the timing high level, the timing resistance, and the timing capacitor.
  • the original pulse oscillator has a single oscillation function and cannot directly control the frequency with the level.
  • the frequency of the original pulse oscillator is determined by both the timing resistor and the timing capacitor. It must be emphasized that the change in the timing high level causes the charging voltage ratio and the discharging voltage ratio on the timing capacitor to change accordingly, thereby directly making the frequency continuously change in a large range. This is fundamentally different from voltage-controlled oscillators that use level changes to control the change in the output resistance of the amplifying element, thereby making the frequency change.
  • the invented circuit greatly simplified and optimized the BICM 0 S. It is remembered that the integrated circuit has great practical value in medium-scale, large-scale, and ultra-large-scale integrated circuits.
  • a new multifunctional device not only makes the basic logic device extremely rich and versatile, it is very convenient and flexible to design, use, and maintain. It is even more valuable that it can greatly reduce the basic variety of integrated circuits. This brings great benefits to manufacturers and users, and will surely be welcomed by users and manufacturers.
  • the signal acting on the circuit means that at the moment the signal is applied, the entire circuit is in the state of opening the signal, allowing the signal to pass through to the output.
  • a signal acting on a circuit is not the same as a signal input circuit.
  • a signal input circuit is not necessarily capable of acting on a circuit. If the circuit is in the closed state, the input signal has no effect on the circuit, that is, although there is a signal input, it does not work; if the entire circuit is in the open state of the input signal, the input signal can have an effect on the circuit.
  • no-memory circuit The output logic state of a circuit exists according to the existence of an input signal, and the disappearance of the input signal disappears, that is, after the signal disappears, the circuit cannot maintain the output state when the signal is acting. Such a logic circuit is called a no-memory circuit.
  • the output of the memoryless circuit is represented by Q.
  • L ST TL, CMOS, TTL, ECL, HTL and other integrated circuits such as various high-level OR gates (actually described later as high-level OR gates) and low-level OR gates (that is, high-level AND gates) (It is actually a low level or gate as described later) is a memoryless circuit.
  • high-level OR gates actually described later as high-level OR gates
  • low-level OR gates that is, high-level AND gates
  • the memory circuit defines that the circuit has the function of stably (ie, does not change with time) or replace the input signal within a certain time. Even if the input signal disappears immediately after the circuit replaces it, the circuit can still be stable or maintained for a certain time. Signal output status.
  • This logic circuit is called a memory circuit.
  • a complex logic circuit control system is an organic combination of memory circuits and memoryless circuits.
  • memory circuits According to whether the memory of a signal changes with time, memory circuits can be divided into two categories: stable circuits and temporary circuits.
  • the memory of the signal by the stable memory circuit does not change with time, that is, the memory circuit that stably stores the signal is called a stable memory circuit.
  • the output of the stable circuit is represented by Q s .
  • Stable memory such as traditional RS flip-flops, D flip-flops, JK flip-flops, magnetic memory and various new CI stabilizers described later, new! )
  • Stable memory new JK stable memory, and various counters, digital registers, shift registers, etc. formed by them are all stable memory circuits.
  • a useful and stable memory circuit which can not only memorize signals, but also easily erase information number.
  • the temporary circuit is automatically erased after the signal is memorized for a certain period of time. That is, the circuit in which the memory of the signal changes with time is called a temporary circuit.
  • a single-valued temporary circuit for temporarily high-level or low-level signals ie, a high-level or low-level temporary register described later
  • Q T A double-valued temporary circuit for temporarily recording internally generated high and low level signals, that is, the output of the pulse oscillator is represented by Q 0.
  • the output state of the circuit that memorizes the input signal is referred to as the record state; the output state of the circuit that stably memorizes the input signal is referred to as the steady state; the circuit output state that temporarily stores the input signal is referred to as the temporary state.
  • the memory circuit includes a memory circuit of a memory type, a magnetic memory circuit, a capacitive memory circuit, and a photoelectric memory circuit.
  • OR memory circuit formed by connecting the OR memory circuit (also known as OR memory gate) described later to its unique memory chain is called OR memory circuit, also known as the replacement memory circuit.
  • OR memory circuits are divided into OR memory circuits and OR memory circuits.
  • the suspense circuits listed earlier are OR-type suspense circuits.
  • Orbital memory circuit occupies the primacy of various integrated circuits, and it is the most important and widely used logic circuit.
  • Magnetic-type memory circuit uses the remanence characteristic after magnetization of a magnetic substance to replace the signal and memorizes the signal. At the moment when the current signal is applied, the residual magnetic properties of the magnetic substance endogenously replace the role of the current signal, so that after the current signal disappears, the magnetic substance still maintains the state of the magnetic flux when the current signal is applied, that is, the current signal is kept in mind.
  • magnetic memories that store digital signals, magnetic disks, and audio tapes and video tapes that store analog signals are all magnetic memory circuits. The latter memorizes signals through acoustic, electrical, magnetic, and optical, electrical, and magnetic conversions.
  • Capacitive memory circuits use the charge storage effect of capacitors to store signals instead of signals. For example, a dynamic M 0 S FET memory cell.
  • Photoelectric Memory Circuits use the photoelectric effect to replace signals and memorize them.
  • An example is a compact disc.
  • Input value range The allowable value range of the input signal logic level when the signal output takes a fixed value is called the input value range, which is represented by (i).
  • Output value range The allowable change range of the signal output logic level when the input signal takes a fixed value is called the output value range, and ⁇ is used. Means.
  • Heterogeneous output input signal output range is not within the signal input range or the physical quantity characterizing the logical state of the output or input is heterogeneous, that is, the two are not the same type of physical quantity. Such output and input are called heterogeneous output and input, referred to as heterogeneous output input .
  • Heterogeneous or logical As long as one input between heterogeneous output and input is “1" ("1" means there is a signal), the output is heterogeneous with input "1". This logical relationship is called heterogeneous or logic. Because it only has heterogeneous OR logic functions, it is also called exclusive OR logic.
  • a logic circuit capable of implementing a heterogeneous OR logic is called a heterogeneous OR gate.
  • Figure 1 is a low-level heterogeneous OR gate of a diode with heterogeneous output and input
  • figure (b) is its logic diagram. Its high and low level signal outputs and its high and low level input signals are heterogeneous. The high and low logic levels are referred to as high and low.
  • the low-level signal is 0V and the high-level signal is 3V.
  • L cta ffl is the same type of input and output. It can be seen that this circuit is a heterogeneous output and input circuit of low-level signals. In terms of level signals, the logic relationship of the circuit is heterogeneous OR logic, so it is a diode low-level OR gate.
  • Figure 2 (a) is a high-level heterogeneous OR gate circuit with the emitter output of a high-level signal heterogeneous output input
  • Figure (b) is its logic diagram.
  • the small circle "O" in the upper left corner indicates a high-level heterogeneous OR gate; the small circle marked in the lower left corner indicates a low-level heterogeneous OR gate.
  • the small dots " ⁇ " above the input terminals r and C indicate homogeneous OR gates for high-level signals; the small dots " ⁇ " below r and C indicate low Level signals are homogeneous OR gates.
  • Figure 3 is a two-input high-level AND gate
  • Figure 4 is the original two-input high-level OR gate
  • the 7 S32 circuit is a similar output and input circuit.
  • the 74LS32 circuit is a high-level homogeneous OR gate. It is called a high-level C or gate in the OR gate.
  • the definition of the memory chain sends the signal output back to the replacement input. At this time, regardless of whether the input signal disappears or not, it can stably (ie, not change with time) or replace the role of the input signal within a certain period of time.
  • the input circuit of this output is called a memory chain. Memory chain is also called memory factor.
  • An input terminal that uses a signal output to replace an input signal is referred to as an input terminal, which is also called the end of a memory chain, and is represented by ⁇ , r c , r s .
  • the signal output is sent back to replace the input terminal. It cannot replace the input signal.
  • the input circuit of this output is not a memory chain, or the circuit has no memory chain and does not replace the input terminal.
  • the memory chain is an external cause, sufficient condition, and a necessary bridge to realize the function of replacing the logic of memory.
  • Suspense chains include single-valued suspense chains, double-valued suspense chains, and simulated suspense chains. Single-valued suspense chains and double-valued suspense chains are called digital suspense chains.
  • the signal output is sent back to replace the input end. At this time, regardless of whether the input signal disappears or not, it can stably replace the role of the input signal.
  • the input circuit of this signal output is called a steady chain. Steady chain is also called steady factor.
  • the end of the chain is represented by r.
  • a wired memory chain changes the quality of a memoryless signal or memory circuit into a memory circuit.
  • Figure 5 (a) is a logic diagram of a memoryless or low-level OR circuit.
  • Figure (b) is a logic diagram of the new low-level C I stabilizing device connected to the low-level OR circuit connected to a connected stable stabilizing chain.
  • the r terminal can stably replace the low-level signal input from the similar input terminal C or the inverting input terminal I, so that the output stably remembers the low-level signal of the C terminal or I terminal.
  • a connected stable memory chain turns the memoryless or low-level OR circuit quality into a new low-level CI stable register (referred to as the new low-level RS trigger in the past).
  • the definition of the digital suspense chain uses the principle that the voltage across the capacitor cannot be abruptly changed, and the signal output is returned to the input terminal through the capacitor. At this time, whether the input signal disappears or not, it can be discharged and charged in the RC circuit at a certain time. Replaces the role of the input signal.
  • the input circuit for this signal output is called a digital temporary chain.
  • the number suspense chain is also called the number suspense factor, and the end of the number suspense chain is represented by r c .
  • the new single-valued temporary chain is composed of timing level V t , timing resistance R t , Composed of timing capacitor C t .
  • C t must be connected between the output end of the signal OR circuit and the end of the temporary chain r c , and R t is connected between the r c terminal and the timing level V t terminal, as shown in FIG. 6 (b).
  • Figure 6 (a) is a logic diagram of a low-level OR memory circuit.
  • FIG. 6 (b) is a logic diagram of a new low-level temporary register formed by connecting the low-level OR circuit with a new single-valued temporary storage chain. Regarding V t , R t and C t will be described later.
  • the original single value temporary chain circuit is composed of a timing resistor R t and a timing capacitor C t .
  • R t Terminate on r c and connect the other end to “ground” or to power.
  • a single-valued temporary recorder is linked to a signal or circuit with no memory. It can only temporarily record high-level signals or low-level signals. Therefore, it is called a single-valued suspense chain, which is also called a single-valued suspense factor.
  • Double value suspense chain The double value suspense chain circuit is composed of a timing high level V t , timing resistors R t and R t , a timing capacitor C t and an output temporary state Q. Controlled NPN type or NM 0 S single tube electronic switch S. Composed of. Similarly, C t must be connected between the output of the signal OR circuit and the end of the temporary chain r c .
  • the timing resistance R t is called a pulse-space resistance, and the timing resistance R t is called a pulse-width resistance.
  • the double-valued temporary chain circuit is shown in Figure 7 (b).
  • FIG. 7 (a) is a logic diagram of a low-level OR gate
  • FIG. 7 (b) is a logic diagram of a new controllable multi-function pulse oscillator by using the low-level OR circuit to connect a two-value temporary register chain. V t will be described later on.
  • a new multi-function pulse oscillator constructed by linking a double-valued temporary record to a signal or a circuit can alternately temporarily record the high and low-level signals generated in the r- c terminal, that is, pulse oscillation is generated.
  • Mind chain also known as its double-valued temporary factor.
  • the level of the analog input signal below the threshold level (refer to the threshold level below) is called an analog low-level signal; the level above the threshold level is called an analog high-level signal.
  • the analog suspense chain defines the output of the analog low-level signal.
  • the low voltage obtained by replacing the input can replace the analog low-level signal through the voltage dividing circuit (non-linear or linear) connected to the output and the analog signal input
  • the effect (only the low-level OR gate can be realized) is different from the effect of replacing the digital input signal. This replacement effect is after the analog low-level signal disappears (that is, it becomes an analog high-level signal).
  • the analog high-level signal starts to work, but its output enables the high level obtained by replacing the input terminal to be maintained but not to replace the role of the analog high-level signal, that is, the analog high
  • the output of the level signal exists with the existence of the analog high-level signal, disappears and disappears (because the sustain period is a high-level AND gate).
  • the output of the analog high-level signal uses a voltage divider circuit to replace the high level obtained at the input end to replace the role of the analog high-level signal (only high-level homologous OR gates can achieve); and in this case, the analog low level
  • the output of the level signal enables the low level obtained by replacing the input terminal to be maintained but not the role of the analog low level signal (because the low level AND gate is maintained during the sustain period).
  • This analog input signal output The input circuit is called an analog suspense chain.
  • the analog suspense chain is also called analog suspense factor.
  • the end of the analog suspense chain is represented by r s .
  • Analog suspense chain circuit The common circuit of the analog suspense chain of the signal or recording circuit is a resistor R connected between the output terminal and the input terminal. And a non-linear voltage divider circuit composed of a diode D and a resistor connected between the replacement input terminal and the analog signal input terminal, as shown in Fig. 8 (1) and ((1). R., R] is the voltage division Resistors and diodes function as level shifting and switching.
  • the analog input signal is represented by l.
  • Figure 8 (a) is a logic diagram of an OR-type low-level C OR circuit (see below, for example, + 74L S 08 circuit).
  • Figure 8 (b) is a new analog temporary register for temporarily simulating low-level signals formed by connecting an analog temporary link, which is referred to as a new low-level analog temporary register.
  • Figure 8 is a new analog temporary register for the high-level C or gate circuit connected to the analog temporary chain to form a temporary analog high-level signal, referred to as a new high-level analog temporary register.
  • the analog register is the original Schmitt trigger.
  • Principle of memory chain Only the same or logic can have a memory chain, and no other logic, such as AND logic, heterogeneous or logic, NAND logic, or non-logic, etc. has no memory chain.
  • the principle of memory chain is a proof-free principle based on the definition of memory chain and homogeneous or logical characteristics.
  • the first criterion is to replace the internal factors and necessary conditions of memory.
  • the second criterion is to replace the external factors and sufficient conditions of memory.
  • Signal or memory circuit A circuit that can implement a signal or memory logic is called a signal or memory circuit, referred to as a circuit or circuit or a gate for short.
  • the input signal of the OR circuit is the same as its output, and its input terminal is called the same input terminal of OR circuit, which is represented by C.
  • the input signal of the OR circuit and its output are opposite logic In the level state, its input terminal is called the inverting input terminal of the OR circuit, which is represented by I.
  • the OR circuit has a signal input terminal C and a signal inverting input terminal I. But I can do it or not.
  • the end of the memory chain, which is unique to the HJ circuit, is to replace the input, which is obviously at the same input.
  • the signal OR circuit is the same OR gate with C, I input terminal or C terminal only.
  • OR circuits are divided according to OR gates for level signals. There are three types: low level OR gates, high level OR gates, and high level or OR gates.
  • Low-level OR gate is the OR gate for low-level signals (including low-level equivalent OR gate).
  • the small dot " ⁇ " marked in the lower left corner of its logic diagram indicates that the gate is YES for low-level signals.
  • a high-level OR gate is an OR gate for high-level signals.
  • the small dot " ⁇ " marked in the upper right corner of the logic diagram indicates that the gate is OR-coded for high-level signals.
  • High or low level OR gate is OR gate for both high level signal and low level signal.
  • the high or low level or gate is also called single input or gate, inverter. There are no dots on its logic diagram.
  • gates or gates also known as one gate or gates
  • two equivalent gates expansion or gates, collector output or gates.
  • the OR gate is the OR gate of the OR circuit structure. There are or type low level or gate, or type high level or gate, or type low level C or gate, or type high level C or gate, or type single input or gate. OR type C OR gates are AND gates and OR gates (as used to say) in various integrated circuits. They are all gates or gatekeepers.
  • Two equivalent OR gates It consists of two NOR gates to form a two equivalent OR gates. It is also called a NOR gate. There are two equivalent C or gatekeepers.
  • Expansion OR gate In fact, it is a high-level AND gate or a low-level OR gate. It includes an OR-type expansion or gate (ie, a gate-type expansion or gate) and two equivalent expansion or gates.
  • Collector output or gate It is the low level or gate of the triode collector output. It belongs to two equivalent low level or gates.
  • the small dot " ⁇ " marked above the similar input terminal C and the inverting input terminal I indicates that the valid input signal is a high level signal, that is, for a high level signal, it is a OR gate. ;
  • the small dots " ⁇ ” below them indicate that they are OR gates for low-level signals.
  • An example of a OR gate The 74L S 08 circuit shown in FIG. 3 is an OR-type low-level C OR gate, and the aforementioned circuit of FIG. 4 + 74L S 32 is an OR type high-level C-OR gate. Adding very few components gives the inverting input I of the low-level signal of the 74L S 08 circuit to form a The circuit diagram of LSTTL or low level or gate is shown in Figure 9. Adding very few components gives
  • FIG. 4 The 74LS32 circuit's inverting input terminal I of a high-level signal constitutes a LSTTL or high-level OR gate.
  • the wiring diagram is shown in Figure 10.
  • Figure 11 is a circuit diagram of an ECL or high-level OR gate
  • Figure 12 is a circuit diagram of two low-level equivalent OR gates formed by two TTL NAND gates
  • Figure 13 is an LSTTL or high-level extension
  • FIG. 14 is a low-level OR gate of the TTL collector output
  • FIG. 15 is a circuit diagram of a CM 0 S single input or gate circuit formed by connecting two inverters in series.
  • the threshold level of the signal or gate The door opening level V 0 N and the gate closing level V 0 p P of the signal or gate are close to L.
  • the ideal voltage transmission characteristic polyline
  • the voltage transmission characteristics curves are considered to be approximately equal.
  • the ideal opening or closing level of a signal or gate is called the threshold level (or threshold level) of the signal or gate, which is represented by V T.
  • the time of the temporary signal is referred to as the temporary time.
  • the levels, resistances, and capacitances that determine the length of the temporary record are called timing levels, timing resistances, and timing capacitors, respectively.
  • the timing resistance is denoted by R t
  • the timing capacitance is denoted by C t
  • the pending timing level is generally denoted by V t .
  • V t When the power-on level should be a logic level above the threshold level, the timing high level is called V t ; when the timing level is below the threshold level, it is called the timing low level.
  • Use ⁇ f t means.
  • V t Because of the value of the level V t , one is to directly determine whether the temporary register can temporarily record the input signal, and the other is to directly determine the length of the temporary register's input signal time (R t , C t — fixed), so it is named Is the timing level.
  • charge-to-charge voltage ratio The ratio of the charge-to-charge voltage on the capacitor when the signal is temporarily recorded by the temporary register is called the charge-to-charge voltage ratio, which is expressed by ⁇ .
  • the ratio of the discharge voltage on the capacitor to the discharge voltage (or equivalent discharge voltage) when the signal is temporarily registered by the temporary register is called the discharge voltage ratio and is expressed by ⁇ .
  • the timing level V t changes (R t , C t is constant), so that ⁇ and ⁇ change accordingly, so that the temporary recording time and the oscillation frequency continuously change in a wide range.
  • the temporary time of the temporary register of the present invention that is, the monostable flip-flop in the past
  • the frequency of the pulse oscillator are not only related to the timing resistor R t and the timing capacitor C t , but the most useful and valuable is that it is related to the timing
  • the level V t is directly related.
  • a memorable circuit consists of one or more organic cells.
  • High-level and low-level stable cells are also called high-level and low-level C I stabilizing devices, which used to be high-level and low-level RS triggers.
  • a signal or temporary circuit connected to a digital temporary chain can tentatively erase a signal after a certain period of time, which is called a temporary cell. It uses signal homomorphism to temporarily record the signal of the same input terminal, and signal inverse state to temporarily record the signal of the inverting input terminal; reenter the signal, and keep the state unchanged; the time when the signal is active and cannot be evacuated equals the time it replaces the signal. Time; when the door is closed with a signal, it is not remembered; the temporary time is determined by the timing level, resistance and capacitance.
  • the law of temporary circuit temporariness II The signal or temporary circuit connected to the analog temporary chain can temporize the analog low-level or analog high-level signal, which is called analog temporary cell.
  • analog temporary cell When the frequency and amplitude of the analog input signal are constant, the disappearance time is related to the voltage division ratio of the analog temporary chain; the longer it is, the greater the difference between the gender trigger voltage and vice versa.
  • the relationship between jiji The relationship between homogeneity or logic and memory is simply the relationship between jiji.
  • the concept of "or ji" has two meanings: one is that it has two major logical functions of homology or memory; the other is that homology or series is the basis, internal cause, and necessary condition to replace memory, and memory function is a special kind or characteristic , Deep expression and highest application form. There is a close relationship between internal and external.
  • the output is the same kind or characteristic (including the equivalent kind or equivalent) as the input of the same kind "1" is the basis and internal cause to replace the memory logic function, and the memory logic function is a special and profound expression of the same kind or characteristic Form and highest application form.
  • the external relationship between the jiji has two logic functions: homogeneous or memory. Specifically, signals or gatekeepers generally have five working states and five corresponding logic functions.
  • the signal or gate When the signal or gate is not connected to its unique memory chain, it is a homogeneous or gate with no memory or a homogeneous or gate with a nonsignal (signal or NOT). It is in the same or logical working state and follows the same or law without memory.
  • the signal or gate is connected to the stable chain, and then a memoryless signal or gate becomes a
  • the signal or gate After the signal or gate is connected to a single value suspense chain, it changes from a no-memory signal or gate quality to a suspense circuit that temporarily records signals of the same type of input or inverted input.
  • the working state of the input signal should follow or record the temporary law 1 of the circuit.
  • write circuit connected to the signal binary clearing chain, it consists of a non-memory signal or write gate becomes a matter of alternating high and low output in the high r c suspense end endogenous, low-level signals controlled multifunction Pulse oscillator. Its oscillation frequency and pulse-space delay are related to the timing high level, timing resistance, and timing capacitance, and the pulse width is related to the pulse width resistance and capacitance.
  • the signal or gate After the signal or gate is connected to the analog suspense chain, it changes from a memoryless signal or gate quality to an analog suspense circuit that temporarily records analog low (or high) signals, that is, Schmitt trigger , follow or memorize the circuit temporary law two.
  • the common core of the five different logic functional circuits signal OR gate, signal stabilizing circuit (signal stabilizing cell), signal single-value staging circuit (signal single-value staging cell), pulse oscillator, and analog staging circuit.
  • the signal or gate is only under the five different external conditions (external factor): not connected to the memory chain, connected to the stable chain, connected to the single value temporary chain, connected to the double value temporary chain, and connected to the analog temporary chain.
  • the circuit is composed of a timing high level ⁇ t , or a timing low level ⁇ t, a timing resistor R t , and a timing capacitor C t .
  • C t must be connected between the output terminal of the signal OR circuit and the replacement input terminal r c , R t —terminated at the terminal r c and the other terminal ⁇ t or ⁇ t .
  • the original single-valued temporary register chain is composed of a timing resistor R t and a timing capacitor C ⁇ .
  • C t must be connected between the output terminal of the signal or gate and the substitute input terminal r c , one end of R t is connected to r c , and the other end is connected to “ground” or power voltage.
  • the so-called double value temporary chain its circuit is a timing high voltage V t , timing resistance R t and R t , timing capacitor C t and NPN type or NMOS single-tube electronic switch S controlled by the output of a signal or memory circuit. Composed of.
  • ( ⁇ must be connected to the output of the signal or memory circuit and replace Between the input terminals r c .
  • R t , R t , So, V t are connected in two ways: One way is
  • R t - r c terminated at the end, the other end of R t - terminal contact, and the other end of the V t R t, So end a "ground", S.
  • the output is terminated where R t and R t meet.
  • Another connection method is R t — terminated at r c , the other end is connected to V t , one end of R t is connected to r c , and the other end is connected to S.
  • Output, S. The other end is "grounded". So there are two types of double-valued suspicious chain circuits, the former type of double-valued suspicious chain is commonly used.
  • the so-called analog suspense chain is a non-linear or linear voltage divider circuit, one end of which is connected to the output end of a signal or recorder circuit, the other end is connected to an analog signal input end, and the voltage divider output is connected to a substitute input end r s .
  • a common circuit is a resistor R connected between the signal output terminal and the replacement input terminal r s .
  • diode D connected in series between the replacement input terminal and the analog signal input terminal], resistor R! Composition of a non-linear voltage divider circuit.
  • the negative pole must be connected to r s terminal, and for high-level or gate-keeping, D! IL pole must be connected instead of input terminal r s .
  • the so-called 41 ⁇ 2-line stable memory chain is a circuit that connects the output end of a signal or memory circuit with the input end.
  • the dipstick is a monostable flip-flop in the past, and the low-level and high-level dipsticks are low- and high-level monostable flip-flops in the past.
  • the analogue dipstick is a Schmitt trigger.
  • the analog register that records the analog low-level and high-level signals is called a low-level and high-level analog temporary register, that is, a low-level and high-level Schmitt trigger; the CI stable register is an RS trigger in the past.
  • Low- and high-level CI stabilisers are, in the past, low- and high-level RS flip-flops.
  • h represents a logic high level
  • L represents a logic low level
  • L ' represents a logic low level during which the low-level input signal is active and cannot be withdrawn
  • Logic high The new monostable trigger temporarily records the low-level input signal L 'or the high-level input signal H.
  • the temporary time is represented by t T ; when R t and C t are constant, the minimum temporary time is represented by t Tm "in "; the original traditional monostable flip-flop temporary input signal is represented by t T , t T «0.7R t C t ; in the circuit diagram C, the effective level signal of the asynchronous input is high Signal; C, ⁇ indicates that the effective level signal of the asynchronous input is a low-level signal.
  • a CM 0 S single input or gate made of two CM 0 S NOT gates connected in series is connected to an invention single value temporary staging chain composed of a timing low level Y t and a timing resistor timing capacitor C t , and The anode of the diode is connected in series with the two NOT gates, and its anode is used as the inverting input terminal I of the low-level signal.
  • the logic diagram is shown in Figures 17 (a) and (b). Its temporary time t T »t T ⁇ 0.7R t C t .
  • FIG. 17 (a) The positive and negative poles of the diode are reversely connected in FIG. 17 (a), and the timing low level Y t is replaced with the timing high level to form the CM OS high level monostable flip-flop temporary register circuit of the present invention.
  • the sum logic diagram is shown in Figures 18 (a) and (b).
  • a CM 0 S single input or gate connected with two CM 0 S NOT gates connected in series is connected to a double value temporary chain to form the CM OS multi-function pulse oscillator of the present invention.
  • the circuit diagram and logic diagram are as shown in the figure. 19 (a) and (b).
  • the positive stage of a diode is connected in series with the two NOT gates in Fig. 19 (a), and the negative electrode is used as the low-level signal inverting input terminal I for controlling whether to oscillate.
  • Pulse oscillator, its two circuit diagrams and logic diagrams are shown in Figure 20 (a) and (b) and (c) and (d).
  • Figures 21 (a) and (b) consist of two CM 0 S high-level NOR gates to form a two-gate equivalent high-level NOR gate, and then connect a connected stable chain to form the CM OS.
  • the circuit diagram and logic diagram of the original traditional high-level RS flip-flop circuit are shown in Figure 21 (a) and (b).
  • a CM 0 S single input or gate made of two CM OS NOT gates connected in series is connected to a wired stability chain, and a diode anode is connected at the junction of the two NOT gates.
  • An inverting input terminal I of the level signal is connected to the anode of another diode instead of the input terminal r, and its negative electrode is used as a similar input C of the low-level signal, which constitutes the CM 0 S low-level RS trigger of the present invention.
  • the device keeps in mind the circuit, and its wiring diagram and logic diagram are shown in Figure 22 (a) and (b).
  • the positive and negative * 1 ⁇ of the two diodes in FIG. 22 (a) are connected to form the CM OS high-level RS flip-flop stabilizing circuit of the present invention.
  • the circuit diagram and logic diagram are shown in FIG. 23 (a) and (b ).
  • Figures 24 (a) and (b) are circuit diagrams and logic diagrams of the computer keyboard CM 0 S debouncer technology unit circuit.
  • a CM OS single input or gate made of two CM 0 S NOT gates connected in series is connected to a stable recording chain connected to the wire, and then the replacement input terminal r is connected to the normally open contact terminal of the key switch.
  • the non-gate series connection is connected to the normally closed contact end of the key switch, the positive stage of a diode is connected to the common end of the key switch, and the negative pole of the diode is connected to "ground", which constitutes the computer keyboard CM OS of the present invention.
  • One of the unit circuits has a wiring diagram and a logic diagram shown in Figures 25 (a) and (b).
  • the inverting input terminal I of the CM OS high-level RS flip-flop circuit diagram of the invention in FIG. 23 (a) is connected to the normally closed contact terminal of the key switch, and the similar input terminal C is connected to the normally open contact terminal of the key switch.
  • the common terminal power supply voltage of the key switch + V D1) which constitutes the second circuit of the computer keyboard CM 0 S debounce unit of the present invention.
  • the circuit diagram and logic diagram are shown in Figure 26 (a) and (b).
  • the C OS debounce unit circuit is three times as powerful, and its power consumption is 1000 times that of the CM OS debounce unit circuit of the present invention.
  • Figure 27 (a) and (b) are the circuit diagram and logic diagram of the CM OS original static memory cell circuit.
  • a CM 0 S single input or gate made by connecting two CM 0 S non-gates in series is connected to a stable chain of f1 ⁇ 2 line, and then the input end is connected in series with the first and second NM OS switch tubes and The data line D is connected, the first NM OS switch is controlled by the row selection Xi, and the second NM OS switch is controlled by the column selection signal yi, which constitutes a single-line read-write CM OS static memory of the present invention.
  • the circuit diagram and inverse diagram are shown in Figure 28 (a) and (b).
  • the BiCM OS controllable CI stabilizer (BiCM OS controllable high-level RS flip-flop) of the present invention consists of a CM OS low-level CI stabilizer (CM OS low-level RS flip-flop) and high level
  • the signal input consists of a TTL control circuit.
  • TTL input control circuit It consists of two two-input TTL high-level NAND gates.
  • One input terminal of the first NAND gate is an input terminal of a high-level signal, and the other input terminal is connected to a clock pulse CP, and an output thereof is connected to a similar input terminal of the CM OS low-level CI stabilizing device of the present invention;
  • One input terminal of the second NAND gate is the other input terminal for asynchronous input of the high-level signal.
  • the other input terminal is connected to the CP pulse, and the output is connected to the inverse of the CM OS low-level CI stable register of the present invention.
  • Phase input The circuit diagram and logic diagram are shown in Figure 29 (
  • Figures 30 (a) and (b) are circuit diagrams and logic diagrams of a four-digit digital register with BiCM 0 S two-shot operation of the present invention
  • Figures 31 (a) and (b) are BiCM 0 SD-type stable registers of the present invention ( D-type stable register) circuit diagram and logic diagram
  • Figures 32 (a) and (b) are the B iCM 0 S eight-bit register circuit diagram (tri-state) of the present invention. They are all composed of the original TTL control circuit of the CMOS low-level RS flip-flop and signal input of the present invention.
  • FIG. 33 is a circuit diagram of a BiCM O S D flip-flop of the present invention
  • FIG. 34 is a circuit diagram of a BiCM 0 S J flip-flop of the present invention
  • FIG. 35 is a circuit diagram of a B iC M 0 S four-bit binary counter of the present invention.
  • Their all-remember circuits are the CM 0 S low-level RS triggers of the present invention, and the once-and-a-remember circuits are the original TTL once-and-a-rememory circuits. It should be noted that
  • the resistance in the TTL part of BiCM 0 S is much larger than the value in the TTL integrated circuit. This is because the current required by the TTL circuit required by the CM O S low-level RS flip-flop of the present invention in a BiCM 0 S or memory-type stable memory circuit is extremely small.
  • the invention's or temporary memory integrated circuit is composed of a memoryless or low-level C or gate, which is an AND gate of various integrated circuits (LSTTL, CM OS, TTL, H TL, etc.) in the past. Connected to the suspense chain.
  • the suspense chain includes the value suspense chain of the present invention, the original single value suspense chain, the double value suspense chain, and the simulated suspense chain.
  • the single value suspense chain of the present invention includes the original single value suspense chain.
  • the original single value suspense chain is a special case of the lower edge of the single value suspense chain of the present invention.
  • the implementation examples are as follows:
  • a non-memory LSTTL or low-level C OR gate that is, a 74LS08 two-input AND gate, which was said in the past, is connected to a timing high-level V t , a timing resistor R t , and a timing capacitor C t
  • the single value suspense chain of the present invention constitutes the LSTTL low-level monostable flip-flop temporary suspense circuit of the present invention.
  • the circuit diagram and logic diagram are shown in Figure 36 (a) and (b).
  • Figure 37 (a) and (b) are a two-gate equivalent low-level OR gate with two high-level NAND gates (two low-level NOR gates).
  • the 74LS08 two-input AND gate is connected to the original single-value temporary chain consisting of a timing capacitor C t and a timing resistor R t connected to a power source at one end, and a switching pulse generating circuit is connected to a similar input terminal C, thereby forming the LSTTL negative of the present invention.
  • Single pulse generator Its circuit diagram and logic diagram are shown in Figure 38 (a) and (b).
  • the LSTTL low-level analog temporary register ie, the low-level Schmitt trigger
  • the so-called low-level analog suspense chain is an analog suspense chain with the anode of the diode connected in place of the input.
  • Figure 40 (a) and (b) use a low-level NOR gate (high-level NAND gate) Gate) and an NOT gate to form a two-gate equivalent low-level C OR gate, and then connect a low-level analog suspense chain to form the LSTTL original low-level Schmitt trigger circuit and logic diagram.
  • a no-memory or low-level C or gatekeeper that is a +7 entry S08 two inputs Gate, connected to two-value clearing chain, constitute LSTTL Multifunctional controlled oscillator of the present invention the suspense circuit and a logic circuit diagram shown in Figure 41 (a) and (b) shown in FIG.
  • the temporary memory integrated circuit uses a memoryless or high-level C or gate, that is, an OR gate of various integrated circuits (LSTTL, CM OS, TTL, H TL) in the past. Constitute on the chain.
  • LSTTL high-level C or gate
  • CM OS complementary metal-oxide-semiconductor
  • TTL TTL
  • H TL high-level integrated circuits
  • the single-value temporary register chain of the present invention constitutes the LSTTL high-level monostable trigger temporary register circuit of the present invention.
  • the circuit diagram and logic diagram are shown in Figure 42 (a) and (b).
  • + 74LS32 two-input OR gate connected to a high-level analog suspense chain, constitutes the LSTTL high-level analog suspense device (ie, high-level Schmitt trigger) of the present invention, its circuit diagram and The W logic diagram is shown in Figures 44 (a) and (b).
  • the so-called high-level analog suspense chain is an analog suspense chain with the anode of the diode connected to the input end.
  • a no-memory or low-level CI or gate (referred to as a low-level or gate). It is a low-level C or gate.
  • Phase input I In the final analysis, it is the use of various integrated circuits
  • An AND gate (LSTTL, CM OS, TTL, ⁇ TL, ⁇ C L, etc.), a memoryless low-level homogeneous OR gate formed by adding very few components to give its low-level signal inverting input.
  • the memory integrated circuit of the present invention is formed by using a memoryless or low-level C I or gate connected to a memory chain.
  • the implementation examples are as follows:
  • LSTTL low-level CI stable register (low-level RS flip-flop) of the present invention
  • Figures 46 (a) and (b) are Two high-level NAND gates (two low-level NOR gates) are used to form a two-gate equivalent CI OR gate, and then a wired stable chain is connected to form the original LSTTL low-level RS trigger. And logic diagrams of the controller.
  • non-memory LSTTL or low-level CI OR gate that is, a 7-input S 08 two-input AND gate with a low-level signal inverting input, which is connected by the timing low-level Y t
  • a single-valued temporary chain of the present invention composed of a timing resistor R t and a timing capacitor C t , and a similar input terminal C is connected to a high level, which constitutes a low-level signal of the LSTTL low-level signal of the present invention input through an inverting input terminal.
  • the circuit diagram and logic diagram of the steady-state trigger temporary circuit are shown in Fig. 47 (a) and (b). The temporary time t T »t T.
  • LSTTL or low-level CI or gate When I terminal is connected to high level, it becomes LSTTL or low-level C or gate. At this time, it is used to form the low-level monostable state of LSTTL of the present invention.
  • the triggers, negative single pulse generators, low-level Schmitt triggers, and controllable multi-function pulse oscillators are exactly the same as LSTTL or low-level C or gatekeeper methods, and are omitted here.
  • FIG. 48 The circuit diagram and logic diagram of a low-level CI stable register (low-level RS flip-flop with small-swing output) of the LSTTL small-swing output of the present invention are shown in Figure 48 (a) and (b) As shown.
  • Its circuit is made of anti-saturation triode! ⁇ And ⁇ , Schottky diode DD! , D 2 , D 2, D 2, diode D (silicon diode or Schottky diode), resistors ⁇ and 1 2 , low-level signal input terminals and I, output terminals Q s and Q s .
  • the emitter of T 2 is connected to the anode of D, and the anode of D is connected to "ground"; one end of R 1 is connected to the collector, the other end is connected to the power supply voltage + V cc , and one end of R 2 is connected to the collector of T 2 Electrode, the other end of R 2 is connected to the power supply voltage + V cc ; the positive end of 0 1 is connected to 1 1 to 1, and the negative end of 0! Is the same type of low-level input terminal (:; the negative end of D! Is connected to ⁇ ! ! ⁇ , D is positive then T collector 2;!
  • D as protective diode ⁇ terminal, the negative electrode of D i connection), a negative electrode, D ⁇ to cathode of the "ground”; positive then T 2 jfel 0 2, and
  • the negative electrode of D 2 is used as the low-level signal inverting input terminal. I; the negative electrode of D 2 is connected to D 2 of D 2- , the positive electrode of D 2 is connected to the collector, D 2 is used as the protection diode of the terminal, and the negative electrode of D 2 is connected D 2 is a negative electrode, D 2 connected to the positive electrode "ground”; T 2 as a collector output terminal Q s, the collector of the inverting output terminal Q s.
  • Figure 49 is a circuit diagram of the LSTTL D flip-flop of the present invention. Its one-and-a-half-time circuit, that is, the trigger guide circuit in the past, is original, and its full-memory circuit, that is, the basic trigger in the past, is the LSTTL low-level RS flip-flop of the present invention.
  • Figure 50 is a circuit diagram of the original LSTTL D flip-flop.
  • Figure 51 is a circuit diagram of the LSTTL JK flip-flop of the present invention.
  • its one-and-a-half-time circuit that is, the trigger guide circuit in the past
  • its full-memory circuit that is, the basic RS trigger in the past
  • Figure 52 is a circuit diagram of the LSTTL small swing output D flip-flop of the present invention. Its once-and-a-half circuit is original, and its all-memory circuit is a low-level RS flip-flop of the LSTTL small swing output of the present invention.
  • the invention is that their all-memory circuits are the LSTTL of the present invention Low-level RS flip-flop.
  • the D flip-flops, flip-flops, various counters, various digital registers, various shift registers, etc. of the LSTTL small-swing output of the present invention are the invention of their all-remember circuit (the basic flip-flop in the past) ) Are low-level RS flip-flops of the LSTTL small swing output of the present invention.
  • a no-memory or high-level CI or gate (referred to as a high-level or gate), it is a high-level C or gate, with very few components to give its high-level signal.
  • Phase Constituted by the input terminal I In the final analysis, it is an OR gate of various integrated circuits (LSTTL, CM OS, TTL, HTL, ECL, etc.) that was said in the past, and it provides the high-level signal at the inverting input terminal by adding very few components.
  • Memory logic circuit LSTTL, CM OS, TTL, HTL, ECL, etc.
  • the memory or integrated circuit of the present invention is formed by using a memoryless or high-level C I or gate connected to a memory chain.
  • the implementation examples are as follows:
  • a memoryless LSTTL or high-level CI or gate is used, that is, a + 74LS32 two-input or gate with a high-level signal inverting input in the past, connected to a first-line stable chain to form the present invention.
  • LSTTL high-level CI stabilizing device high-level RS flip-flop
  • its wiring diagram and logic diagram are shown in Figure 53 (a) and (b).
  • non-memory LSTTL or high-level CI or gate that is, a 74LS32 two-input or gate with a high-level signal inverting input, which is connected by a timing high-level V t and a timing resistor R t
  • a single value temporary chain of the present invention composed of a timing capacitor ⁇ , and the same type of input terminal is connected to a low level, which constitutes a high level signal
  • the LSTTL high level monostable flip-flop of the present invention is input through the inverting input
  • a memoryless LSTTL or high-level C I or gate is connected to a temporary register chain to form another LSTTL register circuit of the present invention, which is omitted here.
  • a memoryless ECL or high-level CI OR gate that is, an EC L OR gate in the past with a high-level inverting input terminal, connected to a 1 ⁇ 2-line stable memory chain, constitutes the present invention.
  • ECL High CI Stabilizer ECL High RS Trigger.
  • Figures 55 (a) and (b) are circuit diagrams and logic diagrams of the ECL high-level RS flip-flops with 0 and 1 set in the present invention.
  • Figure 56 (a) and (b) are composed of two high-level NOR gates to form a two-gate equivalent high-level NOR gate, and then connect a connected stable chain to form the EC L original high voltage Circuit diagram and logic diagram of the flat RS flip-flop.
  • the memory or memory circuit of the present invention is formed by a memoryless memory or memory expansion or memory gate connected to a connected memory chain.
  • the OR-type extended OR gate is a high-level AND gate in various integrated circuits (LSTTL, CM OS, TTL, HTL, E C L, etc.) said in the past.
  • LSTTL, CM OS, TTL, HTL, E C L, etc. integrated circuits
  • LSTTL two-input two-or-type high-level OR gate to extend the OR gate, that is, a LSTTL two-input two-level high-level AND gate, and one end of one of the two input terminals is connected to a one-wire stable chain. 1. The other end is connected to a clock pulse other than CP, one end of the other two input ends is connected to a clock pulse CP, and the other end is connected to a binary signal D.
  • LSTTL D transflective register (digital latch).
  • the circuit diagram is shown in Figure 57.
  • Figure 58 shows the original LSTTL! ) Semi-transparent circuit (digital latch) circuit diagram, which is composed of two gates.
  • the present invention has a special multifunctional CM OS basic new device, referred to as CM O S universal basic new device, which is represented by ZC01, and its circuit diagram and logic diagram are shown in FIG. 59 and FIG. 60.
  • CM O S universal basic new device which is represented by ZC01
  • a new type of LSTTL basic new device with special functions referred to as LSTTL universal basic new device, is represented by ZL03. Its circuit diagram and logic diagram are shown in Figure 61 and Figure 62.
  • ZC 01 and ZL 03 are composed of a three-valued signal input circuit, a once-and-a-half circuit, and two levels of signal extension or gate.
  • ZL03 has one more voltage-controlled pulse oscillator function than ZC 01, and other functions are exactly the same.
  • the input of ZC01 has r, C (), ⁇ , ⁇ , ⁇ , CP, D, J, K; output terminal Q, inverting output terminal Q, drain 3 ⁇ 4 phase output terminal Q 0 D.
  • ⁇ terminal is used instead of input terminal when ZC 01 is used as a memory circuit Yes, C Q is used as a similar input terminal when ZC 01 is used as a low-level signal or memory circuit or directly set as 0 when ZC 01 is used as a D flip-flop and J flip-flop. . 01 for low-level signal or memory circuit as the inverting input or ZC 01!
  • Triggers and JK triggers are set directly as 1 terminal, C and ⁇ are used as high-level signal or memory circuit in ZC01 for similar inputs and inverting inputs, E is for bidirectional analog control of CM OS Control signal input terminal for switch on or off, CP is the clock pulse input terminal, D is the input terminal of D flip-flop, J, K is the input terminal of JK flip-flop.
  • the input terminal V b of ZL03 is used as the input terminal of control voltage when ZL03 is used for voltage controlled pulse oscillation.
  • the other input terminals r, Go, Ji, C, I, R, CP, D, J have the same meaning as ZC01; output terminal Q, inverting output Q, current collector ⁇ L ⁇ phase output Q oc
  • ZC 01's QQD terminal with sink current load capacity is 80m A
  • ZL03's QQ C terminal with sink current load capacity is 60m A (designed as 100m A).
  • the square wave generator (the square wave square accuracy is called squareness) and the frequency can be adjusted continuously and accurately can be used as the high level timing.
  • Multi-vibrator that can control the continuous high-frequency and change the frequency continuously (the setting condition of the input terminal is the same as 13), and its frequency is determined by three of the high-level timing, timing resistance and timing capacitor; Timing high direct Pulse control space (pulse space referred to as pulse space)
  • pulse width A constant pulse width (pulse width referred to as pulse width) that varies continuously over a wide range.
  • An intermittent oscillator (the input terminal setting conditions are the same as 13), and its frequency is determined by timing high level, timing The resistance and the timing capacitor are determined. 16.
  • An intermittent oscillator with continuously adjustable pulse width and a continuously adjustable pulse width can be directly controlled by timing high level. The frequency is set by 13 Timing high, timing resistance, timing The three capacitors are determined; 17.
  • the ultra-low frequency pulse oscillator (the input terminal setting conditions are the same as 13) that can directly control the pulse space to continuously change the pulse high level at the timing high level, the timing capacitor C t and the timing resistor R t (pulse The value of air resistance) is large, and its oscillation period continuously changes from 20 seconds to 1 hour.
  • the equivalent logic diagrams of 13, 14, 15, 16, and 17 are shown in Figure 63 (k);
  • the setting conditions of the input terminals of 20, 21 and 18 are the same as the equivalent logic diagrams of 18, 18, 19, 20, and 21, as shown in Figure 63 (I). 22.
  • Can be used as high-level homologous OR gate (CP L,
  • RS triggers, monostable triggers, Schmitt triggers, keyboard anti-shake unit circuits, and single pulse generators of the original technology are all composed of two NAND gates or two NOR gates, and The technology of the present invention is constituted by only one OR pattern or gate.
  • the present invention or the memory circuit has the advantages of saving a large number of components and connections, high speed, low power consumption, high reliability, small size, and the like.
  • the CM 0 S debounce circuit of the computer keyboard of the present invention is constituted by a CM 0 S single input or gate. Its components are 1/3 of the original technology, and its power consumption is 1 ⁇ 000 of the original technology.
  • the monostable flip-flop of the present invention not only greatly simplifies the circuit, but also is very valuable. It can use the timing level to directly control the temporary recording time to continuously change within the range of 1 to nearly 20 times of the original technical temporary recording time (both R t Same as C t ), the temporary recording time is determined by the timing level, the timing resistance, and the timing capacitor. The original technology cannot use the level to control the length of the temporary recording time. It is determined by the user that the suspense time of the original technology is the minimum value of the suspense time of the technology of the present invention. The temporary recording time of the monostable flip-flop of the present invention is nearly 20 times that of the original technology (the two R t and C t are the same).
  • the frequency is determined by the timing high level, timing resistance, and timing capacitor.
  • the original pulse oscillator has a single oscillation function, and cannot directly use the level to control the frequency change. The frequency of the original pulse oscillator is determined by both the timing resistor and the timing capacitor.
  • the special multifunctional new device of the present invention has two valuable advantages: one is that it has many functions and is widely used; it is very convenient and flexible for design, use and maintenance; and the other is that it can greatly reduce the variety of integrated circuits and is greatly appreciated. Users and manufacturers are welcome.
  • the B iCM 0 S stable memory integrated circuit of the present invention has two outstanding advantages: one is that the circuit is very simple; the other is that it has the advantages of a CMOS integrated circuit and a TTL integrated circuit.
  • the resistance value of TTL in B iC M 0 S is 6 to 10 times that of TTL integrated circuit.

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Abstract

An OR-Type memorized integrated circuit, characterized that RS trigger and monostable trigger etc. are constituted by one OR gate instead of by two gates as in the prior art, and that the temporarily memorizing time of the monostable trigger can be controlled by timing level and oscillating frequency can be changed in a wide range, both of them are determined by timing level, resistor and capacitor. The BiMOS circuit disclosed in the present invention is of simple structure and has good performances. A fundamental new CMOS device having variety of functions is also provided by the present invention.

Description

一种或记型记忆集成电路 发明领域  FIELD OF THE INVENTION Field of the Invention
本发明一般涉及集成电路, 尤其涉及或记型记忆集成电路。 背景技术  The present invention generally relates to integrated circuits, and more particularly, to memory integrated circuits. Background technique
在现有技术中, 人们为了构成一个基本 R S触发器或一个单稳态 触发器, 需要两个与非门或两个或非门。 因此存在所用元件多、 内部 连线多、 速度低、 功耗高、 可靠性低、 体积大等缺点。 同时, 因为原 单稳态触发器的暂记时间由定时电阻、 定时电容两者确定, 存在暂记 时间不易控制的缺点。 原脉冲振荡器的振荡频率也因为是由定时电 阻、 定时电容两者确定, 因此, 也存在振荡频率不易控制的缺点。  In the prior art, in order to constitute a basic RS flip-flop or a monostable flip-flop, two NAND gates or two NOR gates are required. Therefore, there are disadvantages such as using a large number of components, having a large number of internal wiring, low speed, high power consumption, low reliability, and large size. At the same time, because the temporary recording time of the original monostable flip-flop is determined by both the timing resistor and the timing capacitor, there is a disadvantage that the temporary recording time is not easy to control. The oscillation frequency of the original pulse oscillator is also determined by both the timing resistor and the timing capacitor, so there is a disadvantage that the oscillation frequency is not easy to control.
因此, 本发明的一个目的是提供一种基本 R S触发器和单稳态触 发器 (^本发明中将把 R S触发器、 单稳态触发器等具有记忆性质的电 路统称为或记型记忆电路), 它们具有所用的元件少, 因而内部连线 少、 速度高、 功耗低、 可靠性高、 体积小等优点。 技术方案  Therefore, an object of the present invention is to provide a basic RS flip-flop and a monostable flip-flop (^ In the present invention, a circuit having memory properties such as an RS flip-flop and a monostable flip-flop is collectively referred to as or a memory circuit ), They have the advantages of fewer components, so fewer internal connections, high speed, low power consumption, high reliability, small size and so on. Technical solutions
为了实现以上目的, 本发明提供了一种或记型记忆集成电路, 包 括一个或记门和一个记忆链, 所述或记门包括一个输出端( Q )和多 个包括取代输入端( r )在内的输入端, 所述记忆链接在或记门的输 出端和取代输入端之间。  In order to achieve the above objective, the present invention provides a NOR memory integrated circuit, which includes an OR gate and a memory chain, the OR gate includes an output terminal (Q) and a plurality of replacement input terminals (r). At the internal input, the memory link is between the output of the OR gate and the replacement input.
本发明还提供了一种具有特多功能新器件, 包括双值信号输入电 路、 一次半记电路、 两种电平信号的扩展或记门这三部分。  The invention also provides a new device with special multi-function, which includes three parts of a double-valued signal input circuit, a once-and-a-half circuit, and two-level signal expansion or gate.
发明的技术方案可看出, 本发明只用一个或记门就实现了或 记型记忆集成电路, 因此具有所用的元件少, 因而内部连线少、 速度 高、 功耗低、 可靠性高、 体积小等优点。 因为本发明同时还在单值记 忆链和双值记忆链中引入了定时电平, 从而使单稳态触发器的暂记时 间和脉冲振荡器的振荡频率易于控制。  It can be seen from the technical solution of the invention that the present invention implements a memory IC with only one OR gate, so it has fewer components, so fewer internal connections, high speed, low power consumption, high reliability, Small size and other advantages. Because the present invention also introduces timing levels in the single-valued memory chain and the double-valued memory chain at the same time, so that the temporary recording time of the monostable flip-flop and the oscillation frequency of the pulse oscillator are easy to control.
附图简要说明 Brief description of the drawings
为了能更好地理解本发明, 下面将通过参照附图, 对本发明的优 选实施例进行详细的描述。 附图中: In order to better understand the present invention, the following describes the advantages of the present invention by referring to the accompanying drawings. The alternative embodiment is described in detail. In the drawings:
图 1是二极管低电平异类或门的举例,其中( a )是电路图, ( b ) 是逻辑图;  Figure 1 is an example of a diode low-level hetero OR gate, where (a) is a circuit diagram and (b) is a logic diagram;
图 2是射极输出高电平异类或门的举例, 其中( a )是电路图, ( b )是逻辑图;  FIG. 2 is an example of an emitter output high-level hetero-OR gate, where (a) is a circuit diagram, and (b) is a logic diagram;
1  1
图 3是 74LS08低电平同类或门线路图; 1  Figure 3 is a 74LS08 low-level homologous OR gate circuit diagram; 1
图 4是;7札 S32高电平同类或门线路图;  Figure 4 is the same high-level OR gate circuit diagram of S32;
4  4
图 5是一根连线的稳记链举例, 其中( a )是低电平或记电路逻 辑图, ( b )是本发明低电平 C I稳记器逻辑图;  FIG. 5 is an example of a connected stable memory chain, where (a) is a logic diagram of a low-level OR memory circuit, and (b) is a logic diagram of a low-level CI memory stabilizer of the present invention;
图 6是本发明单值暂记链举例, 其中 ( a )是低电平或记电路迢 辑图, ( b )是本发明低电平暂记器逻辑图;  FIG. 6 is an example of a single-valued temporary diary chain of the present invention, where (a) is a low-level OR circuit diagram, and (b) is a logic diagram of the low-level diary of the present invention;
图 7是双值暂记链举例, 其中( a )是低电平或记电路逻辑图, ( b )是本发明可控多功能脉冲振荡器逻辑图;  7 is an example of a double-valued temporary register chain, where (a) is a logic diagram of a low-level OR register circuit, and (b) is a logic diagram of a controllable multifunctional pulse oscillator of the present invention;
图 8是模拟暂记链, 其中( a )是低电平 C或记门逻辑图, ( b ) 是本发明低电平模拟暂记器逻辑图, ( c )是高电平 C或记门逻辑图, ( d ) 是本发明高电平模拟暂记器逻辑图;  FIG. 8 is an analog suspense chain, where (a) is a low-level C or gate logic diagram, (b) is a low-level analog stylus logic diagram of the present invention, and (c) is a high-level C or gate gate A logic diagram, (d) is a logic diagram of a high-level analog register of the present invention;
图 9是 LSTTL或型低电平或记门线路图;  Figure 9 is the LSTTL or low-level or gated circuit diagram;
图 10是 LSTTL或型高电平或记门线路图;  Figure 10 is a LSTTL or high-level or gated circuit diagram;
图 11是 ECL或型高电平或记门线路图;  Figure 11 is an ECL or high-level or gated wiring diagram;
图 12是 TTL两门等效低电平或记门线路图;  Figure 12 is a TTL two-gate equivalent low-level or gate-keeping circuit diagram;
图 13是 LSTTL或型高电平扩展或 i己门线路图;  Figure 13 is a LSTTL or high-level extension or i-gate circuit diagram;
图 14是 TTL集电极输出的低电平或记门线路图;  Figure 14 is a low-level or gated circuit diagram of the TTL collector output;
图 15是 CM 0 S单输入或记门线路图;  Figure 15 is a CM 0 S single input or gated wiring diagram;
图 16是 CM O S原传统高电平单稳态触发器( tT 0.7RtCt ) , 其 中 ( a ) 是线路图, ( b ) 是逻辑图; FIG. 16 is a conventional high-level monostable flip-flop (t T 0.7R t C t ) of the CM OS, where (a) is a circuit diagram, and (b) is a logic diagram;
图 17是本发明 CM OS低电平单稳态触发器( tT〉>tT»0.7RtCt), 其中 ( a )是线路图, ( b )是逻辑图; FIG. 17 is a low-level monostable flip-flop (t T >> t T »0.7R t C t ) of the CM OS of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 18是本发明 CM O S高电平单稳态触发器( tT〉〉tT«0.7RtCt ), 其中 ( a ) 是线路图, ( b )是逻辑图; FIG. 18 is a CM OS high-level monostable flip-flop (t T 〉> t T ≦ 0.7R t C t ) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 19是本发明的 CM O S多功能脉冲振荡器, 其中 ( a ) 是线路 图, ( b )是逻辑图; 图 20是本发明的 CM O S可控多功能振荡器, 其中( a )是线路 图, ( b )是逻辑图, ( c ) 是线路图, ( d )是逻辑图; 19 is a CM OS multi-function pulse oscillator of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram; 20 is a CM OS controllable multifunctional oscillator according to the present invention, where (a) is a circuit diagram, (b) is a logic diagram, (c) is a circuit diagram, and (d) is a logic diagram;
图 21是 CM O S原传统高电平 RS触发器, 其中 ( a )是线路图, ( b ) 是逻辑图;  FIG. 21 is a CMOS original high-level RS flip-flop, where (a) is a circuit diagram, and (b) is a logic diagram;
图 22是本发明 CM 0 S低电平 C I稳记器(^发明 CM O S低电平 RS触发器), 其中( a ) 是线路图, ( b ) 是逻辑图;  FIG. 22 is a CM 0 S low-level C I stabilizing device (^ invention CM O S low-level RS flip-flop) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 23是本发明 CM 0 S高电平 C I稳记器(^发明 CM O S高电平 RS触发器), 其中( a ) 是线路图, ( b )是逻辑图;  FIG. 23 is a CM 0 S high level C I stable register of the present invention (^ invention CM O S high level RS flip-flop), where (a) is a circuit diagram, and (b) is a logic diagram;
图 24是计算机键盘 CM O S消抖原技术的单元电路, 其中( a ) 是线路图, ( b )是逻辑图;  FIG. 24 is a unit circuit of a computer keyboard CMOS debounce original technology, where (a) is a circuit diagram, and (b) is a logic diagram;
图 25是本发明计算机键盘 CM 0 S消抖单元电路之一,其中( a ) 是线路图, ( b )是逻辑图;  25 is one of the CM 0 S debounce unit circuits of the computer keyboard of the present invention, where (a) is a circuit diagram and (b) is a logic diagram;
图 26是本发明计算机键盘 CM 0 S消抖单元电路之二,其中( a ) 是线路图, ( b )是逻辑图;  FIG. 26 is the second circuit of the CM 0 S debounce unit of the computer keyboard of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 27是 CM O S原静态存储单元电路,其中( a )是线路图, ( b ) 是逻辑图;  FIG. 27 is a CMOS original static memory cell circuit, where (a) is a circuit diagram, and (b) is a logic diagram;
图 28是本发明单线读写 CM OS静态存储单元, 其中( a )是线 路图, ( b )是逻辑图;  FIG. 28 is a single-line read / write CM OS static storage unit according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 29是本发明 BiCM 03可控( 1稳记器(^发明8 1^ 0 S可控高 电平 RS触发器), 其中( a )是线路图, ( b ) 是逻辑图;  FIG. 29 is a BiCM 03 controllable (1 stable register (^ invention 8 1 ^ 0 S controllable high-level RS flip-flop) of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;
图 30是本发明 B iCM 0 S两拍工作四位数码寄存器, 其中( a ) 是线路图, ( b )是逻辑图;  FIG. 30 is a four-digit digital register of B iCM 0 S working in the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 31是本发明 BiCM 0 S的 D型触发器, 其中 ( a )是线路图, ( b ) 是逻辑图;  FIG. 31 is a D-type flip-flop of BiCM 0 S according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
1  1
图 32是本发明 B iC M 0 S八位寄存器线路图的 线路图(三态);  FIG. 32 is a circuit diagram (tri-state) of the circuit diagram of the B iC M 0 S eight-bit register of the present invention;
0  0
图 33是本发明 BiCM 0 S的 D 触发器线路图;  FIG. 33 is a circuit diagram of a D flip-flop of BiCM 0 S of the present invention; FIG.
图 34是本发明 B iC M 0 S的 JK 触发器线路图;  FIG. 34 is a circuit diagram of a JK flip-flop of B iC M 0 S of the present invention; FIG.
图 35是本发明 B iCM 0 S四位二进制计数器线路图;  FIG. 35 is a circuit diagram of a B iCM 0 S four-bit binary counter according to the present invention; FIG.
图 36是本发明 LSTTL低电平单稳触发器( tT>〉tT«0.7RtCt ) , 其中 ( a )是线路图, ( b )是逻辑图; FIG. 36 is an LSTTL low-level monostable flip-flop of the present invention (t T >> t T ≦ 0.7R t C t ), where (a) is a circuit diagram, and (b) is a logic diagram;
图 37是 LSTTL原传统低电平单稳态触发器( tT ).7RtCt ) , 其 中( a ) 是线路图, ( b )是逻辑图; 图 38是本发明 LSTTL 负单脉冲发生器, 其中( a )是线路图, ( b ) 是逻辑图; FIG. 37 is a LSTTL original traditional low-level monostable flip-flop (t T ). 7R t C t ), where (a) is a circuit diagram, and (b) is a logic diagram; FIG. 38 is a LSTTL negative single pulse generator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 39是本发明 LSTTL低电平施密特触发器, 其中( a )是线路 图, ( b )是逻辑图;  FIG. 39 is a LSTTL low-level Schmitt trigger according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 40是 LSTTL原低电平施密特触发器, 其中( a )是线路图, ( b )是逻辑图;  FIG. 40 is a LSTTL original low-level Schmitt trigger, where (a) is a circuit diagram, and (b) is a logic diagram;
图 41是本发明 LSTTL可控多功能脉冲振荡器, 其中( a )是线 路图, ( b ) 是逻辑图;  41 is a LSTTL controllable multi-function pulse oscillator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 42是本发明 LSTTL 高电平单稳态触发器  Figure 42 is the LSTTL high level monostable flip-flop of the present invention
( tT»tT«0.7RtCt ) , 其中 ( a )是线路图, ( b )是逻辑图; (t T »t T « 0.7R t C t ), where (a) is a circuit diagram, and (b) is a logic diagram;
图 43是本发明 LSTTL正单脉冲发生器, 其中( a )是线路图, ( b ) 是逻辑图;  FIG. 43 is a LSTTL positive single pulse generator according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 44是本发明 LSTTL 高电平施密特触发器, 其中( a )是线路 图, ( b )是逻辑图;  FIG. 44 is a LSTTL high-level Schmitt trigger of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 45是本发明 LSTTL低电平 C I稳记器(^发明低电平 RS触发 器), 其中 ( a )是线路图, ( b )是逻辑图;  FIG. 45 is a LSTTL low-level C I stable register (^ invented low-level RS trigger) of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 46是 L ST T L原低电平 C I稳记器(原传统低电平 R S触发器), 其中 ( a )是线路图, ( b )是逻辑图;  FIG. 46 is a L ST T L original low-level C I stabilizing device (formerly a conventional low-level RS trigger), where (a) is a circuit diagram, and (b) is a logic diagram;
图 47是本发明 LSTTL低电平单稳态触发器( tT»tT ) , 其中 ( a ) 是线路图, ( b )是逻辑图; FIG. 47 is an LSTTL low-level monostable flip-flop (t T »t T ) according to the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 48是本发明 LSTTL 小摆幅输出的低电平 C I稳记器(小摆幅 电平 RS触发器) , 其中 ( a )是线路图, ( b )是逻辑图;  FIG. 48 is a low-level CI stable register (small-swing level RS flip-flop) of the LSTTL small swing output of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 49是本发明 LSTTL - D 触发器线路图;  FIG. 49 is a circuit diagram of the LSTTL-D flip-flop of the present invention;
图 50是 LSTTL原 D 触发器线路图;  Figure 50 is the original D flip-flop circuit diagram of LSTTL;
图 51是本发明 LSTTL - J 触发器线路图;  FIG. 51 is a circuit diagram of the LSTTL-J flip-flop of the present invention;
图 52是本发明 LSTTL 小摆幅输出 D 触发器线路图;  Figure 52 is a circuit diagram of the LSTTL small swing output D flip-flop of the present invention;
图 53是本发明 LSTTL 高电平 C I稳记器(本发明高电平 RS触 发器) , 其中 ( a )是线路图, ( b )是逻辑图;  FIG. 53 is a LSTTL high-level C I stable register of the present invention (high-level RS trigger of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;
图 54是本发明 LSTTL 高电平单稳态触发器( tT»tT ), 其中 ( a ) 是线路图, ( b )是逻辑图; FIG. 54 is a LSTTL high-level monostable flip-flop (t T »t T ) of the present invention, where (a) is a circuit diagram, and (b) is a logic diagram;
图 55是本发明 ECL 高电平 C I稳记器(本发明 ECL 高电平 RS 触发器) , 其中 ( a ) 是线路图, ( b )是逻辑图;  FIG. 55 is an ECL high-level C I stable register of the present invention (ECL high-level RS flip-flop of the present invention), where (a) is a circuit diagram, and (b) is a logic diagram;
图 56是 ECL原传统高电平 RS触发器, 其中( a )是线路图, ( b )是逻辑图; FIG. 56 is an ECL original conventional high-level RS flip-flop, where (a) is a circuit diagram, (b) is a logic diagram;
图 57是本发明 L ST TL ― D半透半记器(数码锁存器) 线路图; 图 58是 LSTTL原 D半透半记器线路图;  FIG. 57 is a circuit diagram of the L ST TL ― D transflective register (digital latch) of the present invention; FIG. 58 is a circuit diagram of the original D transflective register of LSTTL;
图 59是 CM OS万能基本新器件 ZC 01线路图;  Figure 59 is the CM OS universal basic new device ZC 01 circuit diagram;
图 60是 CM OS万能基本新器件 ZC 01逻辑图;  Figure 60 is the logic diagram of the CM OS universal new basic device ZC 01;
图 61是 LSTTL万能基本新器件 ZL03线路图;  Figure 61 is the LSTTL universal basic new device ZL03 circuit diagram;
图 62是 LSTTL万能基本新器件 ZL 03逻辑图;  Figure 62 is the logic diagram of the LSTTL universal new basic device ZL 03;
图 63 ( ai )是本发明的 CM 0 S和 LSTTL万能基本新器件所 对应的各项功能的逻辑图。 发明详述  FIG. 63 (ai) is a logic diagram of various functions corresponding to the CM 0 S and LSTTL universal basic new devices of the present invention. Detailed description of the invention
本发明的或记型记忆集成电路是发明人张宗雪运用自己 1986年 5 月提出的 "或记电路稳记定律" 及 "或记电路暂记定律" 而获得的重 大发明记忆集成电路。 它包括发明或记型稳记集成电路、 发明或记型 暂记集成电路、 发明 B iCM 0 S稳记集成电路和一件具有特多功能的 新器件(又称万能基本新器件)。  The memory-type memory integrated circuit of the present invention is a great invention memory integrated circuit obtained by the inventor, Zhang Zongxue, using the "law of stable circuit-keeping" and "temporary law of circuit-keeping" proposed by himself in May 1986. It includes the invention or memory type integrated circuit, invention or memory type integrated circuit, invention B iCM 0 S memory and integrated circuit, and a new device with special multi-function (also known as universal basic new device).
本发明或记型记忆集成电路只用一个或型或记门构成一个基本 R S触发器和一个单稳态触发器, 而原技术是用两个与非门或者两个 或非门构成一个基本 RS触发器和一个传统单稳态触发器。 故称发明 或记型记忆集成电路为一门记忆集成电路, 原技术为两门记忆集成电 路。 显然, 发明技术和原技术相比, 具有大量节约元件和内部连线、 速度高、 功耗低、 可靠性高, 体积小等优点。  The NOR memory integrated circuit of the present invention uses only one NOR gate to form a basic RS flip-flop and a monostable flip-flop. The original technology uses two NAND gates or two NOR gates to form a basic RS trigger Trigger and a traditional monostable trigger. Therefore, the invention or memory memory integrated circuit is called a memory integrated circuit, and the original technology is two memory integrated circuits. Obviously, compared with the original technology, the inventive technology has the advantages of saving a large number of components and internal wiring, high speed, low power consumption, high reliability, and small size.
发明单稳态触发器可以用电平直接控制暂记时间在大范围内连续 变化, 暂记时间由定时电平、 定时电阻、 定时电容三者来确定, 而原 单稳态触发器的暂记时间由定时电阻、 定时电容两者来确定, 它不能 用电平直接控制暂记时间。  Invented monostable flip-flops can use levels to directly control the temporary recording time to continuously change over a wide range. The temporary recording time is determined by three levels: timing level, timing resistance, and timing capacitor. It is determined by both the timing resistor and the timing capacitor. It cannot directly control the temporary recording time with the level.
发明脉冲振荡器具有多功能振荡, 更可贵的是, 可以用定时高电 平直接控制频率在大范围内连续变化, 振荡频率由定时高电平、 定时 电阻、 定时电容三者来确定。 而原脉冲振荡器振荡功能单一, 不能用 电平直接控制频率, 原脉冲振荡器频率由定时电阻、 定时电容两者来 确定。 须强调指出, 用定时高电平的变化使定时电容上的充得电压比 和放失电压比随之变化, 从而直接使频率在大范围内连续变化。 这和 用电平变化来控制放大元件输出电阻变化, 从而使频率变化的压控振 荡器是根本不同的。  The invented pulse oscillator has multi-function oscillation. It is even more valuable that the frequency can be directly controlled to continuously change in a large range with a timing high level. The oscillation frequency is determined by the timing high level, the timing resistance, and the timing capacitor. The original pulse oscillator has a single oscillation function and cannot directly control the frequency with the level. The frequency of the original pulse oscillator is determined by both the timing resistor and the timing capacitor. It must be emphasized that the change in the timing high level causes the charging voltage ratio and the discharging voltage ratio on the timing capacitor to change accordingly, thereby directly making the frequency continuously change in a large range. This is fundamentally different from voltage-controlled oscillators that use level changes to control the change in the output resistance of the amplifying element, thereby making the frequency change.
发明的线路大大简化和优化的 B iCM 0 S稳记集成电路在中规 模、 大规模、 超大规模集成电路中, 具有重大实用价值。 一件具有特多功能新器件不仅使基本逻辑器件功能极大丰富, 用 途极广, 设计、 使用、 维修极方便灵活, 更可贵的是, 可以大大减少 集成电路基本品种。 这给生产厂家和用户带来巨大的好处, 必将深受 用户和生产厂家的欢迎 The invented circuit greatly simplified and optimized the BICM 0 S. It is remembered that the integrated circuit has great practical value in medium-scale, large-scale, and ultra-large-scale integrated circuits. A new multifunctional device not only makes the basic logic device extremely rich and versatile, it is very convenient and flexible to design, use, and maintain. It is even more valuable that it can greatly reduce the basic variety of integrated circuits. This brings great benefits to manufacturers and users, and will surely be welcomed by users and manufacturers.
下面详细描述本发明的理论依据。  The theoretical basis of the present invention is described in detail below.
1.本发明的理论依据  1. The theoretical basis of the present invention
- "或记电路稳记定律" 及 "或记电路暂记定律" 信号作用时电路的输出状态称信号输出。 信号作用于电路是指在 信号作用时刻, 整个电路对信号处于开门状态, 让信号通过而传输到 输出端。 信号作用于电路和信号输入电路不同, 信号输入电路不一定 就能够作用于电路。 如果电路对信号处于关门状态, 则输入信号对电 路就不起作用, 即虽有信号输入, 但它不起作用; 如果整个电路对输 入信号处于开门状态, 则输入信号就能够对电路产生作用。  -The output state of the circuit when the signal of "Holding Circuit Stability Law" and "Holding Circuit Provisional Law" is called signal output. The signal acting on the circuit means that at the moment the signal is applied, the entire circuit is in the state of opening the signal, allowing the signal to pass through to the output. A signal acting on a circuit is not the same as a signal input circuit. A signal input circuit is not necessarily capable of acting on a circuit. If the circuit is in the closed state, the input signal has no effect on the circuit, that is, although there is a signal input, it does not work; if the entire circuit is in the open state of the input signal, the input signal can have an effect on the circuit.
无记忆电路定义 电路的输出逻辑状态是依着输入信号的存在而 存在, 输入信号的消失而消失, 即信号消失后, 电路不能保持信号作 用时的输出状态, 这样的逻辑电路称无记忆电路。 无记忆电路的输出 用 Q 表示。  Definition of no-memory circuit The output logic state of a circuit exists according to the existence of an input signal, and the disappearance of the input signal disappears, that is, after the signal disappears, the circuit cannot maintain the output state when the signal is acting. Such a logic circuit is called a no-memory circuit. The output of the memoryless circuit is represented by Q.
例如 L ST T L , C M O S , T T L , E C L , H T L等集成电路中的 各种高电平或门(实为后述的高电平或记门)和低电平或门 (即高电 平与门, 实为后述的低电平或记门)是无记忆电路。 另外与非门、 或 非门、 与或门、 同或门、 异或门、 半加器、 全加器、 译码器、 编码器、 数据选择电路等过去所说的组合逻辑电路都是无记忆电路。  For example, L ST TL, CMOS, TTL, ECL, HTL and other integrated circuits such as various high-level OR gates (actually described later as high-level OR gates) and low-level OR gates (that is, high-level AND gates) (It is actually a low level or gate as described later) is a memoryless circuit. In addition, NAND gates, NOR gates, AND gates, XOR gates, XOR gates, half-adders, full-adders, decoders, encoders, data selection circuits, etc., all previously described combinational logic circuits have no Memory circuit.
记忆电路定义 电路具有稳定地 (即不随时间而变)或者在一定 时间内取代输入信号的作用, 即使输入信号在电路取代它的瞬间后立 即消失, 电路依然能够稳定地或者在一定时间内保持着信号的输出状 态。 这种逻辑电路称为记忆电路。  The memory circuit defines that the circuit has the function of stably (ie, does not change with time) or replace the input signal within a certain time. Even if the input signal disappears immediately after the circuit replaces it, the circuit can still be stable or maintained for a certain time. Signal output status. This logic circuit is called a memory circuit.
一个复杂的逻辑电路控制系统是由记忆电路和无记忆电路有机组 成的。  A complex logic circuit control system is an organic combination of memory circuits and memoryless circuits.
记忆电路分类 按照对信号的记忆是否随时间变化, 记忆电路可 分为稳记电路和暂记电路两大类。  Classification of memory circuits According to whether the memory of a signal changes with time, memory circuits can be divided into two categories: stable circuits and temporary circuits.
稳记电路 对信号的记忆不随时间变化, 即稳定地记忆信号的记 忆电路, 称稳记忆电路。 稳记电路的输出用 Q s表示。 The memory of the signal by the stable memory circuit does not change with time, that is, the memory circuit that stably stores the signal is called a stable memory circuit. The output of the stable circuit is represented by Q s .
例如传统的 R S触发器、 D触发器、 JK 触发器、 磁存储器和后 述的各种新 C I稳记器、 新!)稳记器、 新 JK 稳记器以及由它们构成 的各种计数器、 数码寄存器、 移位寄存器等都是稳记电路。 一个有使 用价值的稳记电路, 不仅能够稳记信号, 而且还能够方便地抹去信 号。 Such as traditional RS flip-flops, D flip-flops, JK flip-flops, magnetic memory and various new CI stabilizers described later, new! ) Stable memory, new JK stable memory, and various counters, digital registers, shift registers, etc. formed by them are all stable memory circuits. A useful and stable memory circuit, which can not only memorize signals, but also easily erase information number.
暂记电路 对信号记忆一定时间后而自动抹去, 即对信号的记忆 随时间变化的记电路, 称暂记电路。  The temporary circuit is automatically erased after the signal is memorized for a certain period of time. That is, the circuit in which the memory of the signal changes with time is called a temporary circuit.
例如传统的单稳态触发器、 多谐振荡器和后述的各种新暂记器以 及多功能新脉冲振荡器都是暂记电路。  For example, conventional monostable flip-flops, multivibrators, various new registers as described later, and multifunctional new pulse oscillators are all temporary circuits.
暂记高电平或者低电平信号的单值暂记电路(即后述的高电平或 者低电平暂记器), 其输出用 Q T表示。 暂记内生高低电平信号的双 值暂记电路, 即脉冲振荡器的输出用 Q 0表示。 A single-valued temporary circuit for temporarily high-level or low-level signals (ie, a high-level or low-level temporary register described later), whose output is represented by Q T. A double-valued temporary circuit for temporarily recording internally generated high and low level signals, that is, the output of the pulse oscillator is represented by Q 0.
记忆输入信号的电路输出状态简称记态; 稳定记忆输入信号的电 路输出状态简称为稳态; 暂时记忆输入信号的电路输出状态简称为暂 记态。  The output state of the circuit that memorizes the input signal is referred to as the record state; the output state of the circuit that stably memorizes the input signal is referred to as the steady state; the circuit output state that temporarily stores the input signal is referred to as the temporary state.
按照构成记忆电路物质的不同来分, 记忆电路有或记型记忆电 路、 磁型记忆电路、 电容型记忆电路、 光电型记忆电路等。  According to the materials constituting the memory circuit, the memory circuit includes a memory circuit of a memory type, a magnetic memory circuit, a capacitive memory circuit, and a photoelectric memory circuit.
或记型记忆电路 用后述的或记电路(又称或记门)接其独有的 记忆链后而构成的记忆电路, 称或记型记忆电路, 又称取代记忆电 路。  OR memory circuit The OR memory circuit formed by connecting the OR memory circuit (also known as OR memory gate) described later to its unique memory chain is called OR memory circuit, also known as the replacement memory circuit.
或记型记忆电路分为或记型稳记电路和或记型暂记电路两大类。 例如传统的 R S触发器、 D触发器、 JK 触发器和后述的各种新 C I 稳记器、 新!)稳记器、 新 JK 稳记器以及由它们与控制电路构成的各 种计数器、 数码寄存器、 移位寄存器等都属于或记型稳记电路。 前面 列举的暂记电路都是或记型暂记电路。 或记型记忆电路在各种集成电 路中居首要地位, 它是大量而广泛应用的、 最重要的逻辑电路。  OR memory circuits are divided into OR memory circuits and OR memory circuits. For example, traditional RS flip-flops, D flip-flops, JK flip-flops, and various new CI stabilisers described later, new! ) Stable memory, new JK stabilizer, and various counters, digital registers, shift registers, etc., which are composed of them and control circuits, belong to or memory type memory circuits. The suspense circuits listed earlier are OR-type suspense circuits. Orbital memory circuit occupies the primacy of various integrated circuits, and it is the most important and widely used logic circuit.
磁型记忆电路 磁型记忆电路是利用磁性物质磁化后的剩磁特性 来取代信号而记忆信号的。 在电流信号作用瞬间, 磁性物质的剩磁特 性就内生取代电流信号的作用, 从而在电流信号消失后, 使磁性物质 依然保持着电流信号作用时的磁通状态, 即稳记着电流信号。 例如稳 记数字信号的磁存储器、 磁盘及稳记模拟信号的录音磁帶、 录像磁带 都是磁型稳记电路。 后者经过声、 电、 磁和光、 电、 磁的转换而记忆 信号的。  Magnetic-type memory circuit Magnetic-type memory circuit uses the remanence characteristic after magnetization of a magnetic substance to replace the signal and memorizes the signal. At the moment when the current signal is applied, the residual magnetic properties of the magnetic substance endogenously replace the role of the current signal, so that after the current signal disappears, the magnetic substance still maintains the state of the magnetic flux when the current signal is applied, that is, the current signal is kept in mind. For example, magnetic memories that store digital signals, magnetic disks, and audio tapes and video tapes that store analog signals are all magnetic memory circuits. The latter memorizes signals through acoustic, electrical, magnetic, and optical, electrical, and magnetic conversions.
电容型记忆电路 电容型记忆电路是利用电容的电荷存储效应来 取代信号而记忆的。 例如动态 M 0 S场效应管存储单元。  Capacitive memory circuits Capacitive memory circuits use the charge storage effect of capacitors to store signals instead of signals. For example, a dynamic M 0 S FET memory cell.
光电型记忆电路 光电型记忆电路是利用光电效应来取代信号而 记忆的。 例如光盘。  Photoelectric Memory Circuits Photoelectric memory circuits use the photoelectric effect to replace signals and memorize them. An example is a compact disc.
输入值域 信号输出取定值时输入信号逻辑电平的允许取值范围 称输入值域, 用 ( i表示。  Input value range The allowable value range of the input signal logic level when the signal output takes a fixed value is called the input value range, which is represented by (i).
例如 L ST T L, T T L集成电路低电平信号的输入值域, 一般规定 为 0V到 0.8V , 即 aL = 〔 0.8V , 0V 〕。 其高电平信号的输入值域, 一般规定为 2V到 5V, 即 otjH = 〔 5V , 2V 〕。 再如 CM 0 S集成电 路低电平信号的输入值域, 一般规定为 0V到电源电压 V DD的 30 % , 若 V DD = 5V 时, 则 CM 0 S低电平信号的输入值域为 0V到 1.5V , 即 ( L = 〔 1.5V,0V 〕。 CM O S高电平信号的输入值域, 一般规定为 电源电压 VDU到 VnD的 70 %, 若 VDD = 5V , 则 CM O S高电平信号 的输入值域为 3.5V到 5V , 即 aai = 〔 5V , 3.5V 〕。 For example, L ST TL, the input range of the TTL integrated circuit low-level signal is generally specified as 0V to 0.8V, that is, a L = [0.8V, 0V]. The input range of its high level signal, Generally, it is 2V to 5V, that is, otjH = [5V, 2V]. For another example, the input range of the low-level signal of the CM 0 S integrated circuit is generally specified as 0V to 30% of the power supply voltage V DD . If V DD = 5V, the input range of the low-level signal of the CM 0 S is 0V. To 1.5V, ie (L = [1.5V, 0V]. The input value range of the CM OS high-level signal is generally specified as 70% of the power supply voltage V DU to V nD . If V DD = 5V, the CM OS is high. The input range of the level signal is 3.5V to 5V, that is, a ai = [5V, 3.5V].
输出值域 输入信号取定值时信号输出逻辑电平的允许变化范围 称输出值域, 用 α。表示。  Output value range The allowable change range of the signal output logic level when the input signal takes a fixed value is called the output value range, and α is used. Means.
例如 LSTTL , TTL集成电路输出逻辑低电平值域, 一 ¾定为 0V 到 0.4V , 即 aoL = 〔 0.4V , 0V 〕。 输出逻辑高电平值域, 一般规 定为 2.4V 到 3.6V , 即 α0„ = 〔 3.6V, 2.4V 〕 。 For example, LSTTL, TTL integrated circuit output logic low-level value range, which is set to 0V to 0.4V, that is a oL = [0.4V, 0V]. The output logic high level value range is generally specified as 2.4V to 3.6V, that is, α 0 „= [3.6V, 2.4V].
异类输出输入 信号输出值域不在信号输入值域之内或者表征输 出、 输入逻辑状态的物理量是异性的, 即两者不是同一类物理量, 这 样的输出和输入称异类输出和输入, 简称异类输出输入。  Heterogeneous output input signal output range is not within the signal input range or the physical quantity characterizing the logical state of the output or input is heterogeneous, that is, the two are not the same type of physical quantity. Such output and input are called heterogeneous output and input, referred to as heterogeneous output input .
其表达式为 式中, α。表示信号输出值域, 表示信号输入值域, "ο" 表示 左边的 α。不在右边的 oti之内的逗辑符号。  The expression is in the formula, α. Indicates the signal output value range, indicates the signal input value range, and "ο" indicates the left α. Comma not in oti on the right.
异类或逻辑 异类输出输入之间只要有一个输入为 " 1 " ( " 1 " 表示有信号), 则输出就是与输入异类 " 1 " , 这种逻辑关系称异类 或逻辑。 因它只有异类或逻辑功能, 故又称唯或逻辑。  Heterogeneous or logical As long as one input between heterogeneous output and input is "1" ("1" means there is a signal), the output is heterogeneous with input "1". This logical relationship is called heterogeneous or logic. Because it only has heterogeneous OR logic functions, it is also called exclusive OR logic.
能够实现异类或逻辑的逻辑电路称异类或门。  A logic circuit capable of implementing a heterogeneous OR logic is called a heterogeneous OR gate.
图 1 ( a ) 为异类输出输入的二极管低电平异类或门电路, 图 ( b )为其逻辑图。 它的高、 低电平信号输出和它的高、 低电平输入 信号是异类的。 迻辑高电平和逻辑低电平简称高电平和低电平。  Figure 1 (a) is a low-level heterogeneous OR gate of a diode with heterogeneous output and input, and figure (b) is its logic diagram. Its high and low level signal outputs and its high and low level input signals are heterogeneous. The high and low logic levels are referred to as high and low.
假设低电平信号取 0V , 高电平信号取 3V。 它的低电平信号输入 值域 ( L = 0V , 而低电平信号输出值域 ot。L = 0.7V , 显然, α。ι^ο^。 它的高电平信号输入值域 aai = 3V , 而高电平信号输出值域 α。Η = 3.7V , 显然, a。Lctaffl, 是同类输出输入。 由此可知, 该电路是一个 低电平信号的异类输出输入电路, 对低电平信号而言, 该电路的逻辑 关系是异类或逻辑, 因此, 它是二极管低电平异类或门。 Assume that the low-level signal is 0V and the high-level signal is 3V. Its low-level signal input range (L = 0V, and low-level signal output range ot. L = 0.7V, obviously, α.ι ^ ο ^. Its high-level signal input range a ai = 3V, and the high-level signal output value range α. Η = 3.7V, obviously, a. L cta ffl is the same type of input and output. It can be seen that this circuit is a heterogeneous output and input circuit of low-level signals. In terms of level signals, the logic relationship of the circuit is heterogeneous OR logic, so it is a diode low-level OR gate.
图 2 ( a )为高电平信号异类输出输入的射极输出高电平异类或 门电路, 图 ( b )为其逻辑图。 它的高电平信号输入值域 otiH = 3V , 而它的高电平信号输出值域 α。Η = 2.3V , 显然, α。„(ΤαίΗ。 故该电路 是一个射极输出高电平异类或门。 Figure 2 (a) is a high-level heterogeneous OR gate circuit with the emitter output of a high-level signal heterogeneous output input, and Figure (b) is its logic diagram. Its high-level signal input value range is otiH = 3V, and its high-level signal output value range is α. Η = 2.3V, obviously, α. „(ΤαίΗ. So the circuit Is an emitter output high-level XOR gate.
在异类或门逻辑图中, 左上角表示的小圓圈 "O " 表示高电平异 类或门; 左下角标示的小圓團表示低电平异类或门。  In the logic diagram of a heterogeneous OR gate, the small circle "O" in the upper left corner indicates a high-level heterogeneous OR gate; the small circle marked in the lower left corner indicates a low-level heterogeneous OR gate.
同类输出输入 信号输出值域在信号输入值域之内 (信号输出值 域只要在一个信号输入端的输入值域之内)的输出和输入, 称同类输 出和输入, 简称同类输出输入。  Similar output and input The outputs and inputs whose signal output range is within the signal input range (the signal output value range is only within the input range of one signal input end) are called the same output and input, and are referred to as the same output and input for short.
其表达式为  Its expression is
a0ci( i a 0 ci (i
式中, "c" 表示信号输出值域 a。 在信号输入值域 a,之内的逻 辑符号。  In the formula, "c" represents the signal output value range a. Logical symbol within signal input range a ,.
同类或逻辑 同类输出输入之间只要有一个为 " 1 " ( " 1 " 表 示有信号), 则输出就是与输入同类 " 1 " , 这种逻辑关系称同类或 逻辑。 有时简称同类或。 同类或逻辑是实现取代记忆的基础。 能够实 现同类或逻辑的电路称同类或门。  Same or logical As long as one of the same output and input is "1" ("1" indicates a signal), the output is the same as the input "1". This logical relationship is called homogeneous or logical. Sometimes referred to as homogeneous or. Homology or logic is the basis for achieving replacement of memory. Circuits capable of implementing homogeneous or logic are called homogeneous or gates.
在同类或门线路图中, 输入端 r和 C上方标示的小圓点 " · " 表 示对高电平信号而言是同类或门; r和 C 下方标示的小圓点 " · "表 示对低电平信号而言是同类或门。  In the same OR gate circuit diagram, the small dots "·" above the input terminals r and C indicate homogeneous OR gates for high-level signals; the small dots "·" below r and C indicate low Level signals are homogeneous OR gates.
图 3 是原称为二输入高电平与门, 现称为低电平同类或门的  Figure 3 is a two-input high-level AND gate
+ 74L S08的线路图。 它的高、 低电平信号输出和它的高、 低电平输 入信号是同类的。 它的高电平信号输入值域 aai—般取为 2V到 5V , 即 0Ci„ = 〔 5V , 2V 〕, 而高电平信号的输出值域 a。H—般取为 2.4V 到 3.6V , 即 a。„ = 〔 3.6V,2.4V 〕, 可见, a0„caai。 它的低电平信 号输入值域 aL—般取为 0V到 0.8V , 即 ( L = 〔 0.8V , 0V 〕, 而低电 平信号的输出值域 a。L一般取为 0V到 0.4V, 即 a。L = C 0.4V , 0V 〕, 可见, a。LcaL。 由此可知, 7 S08电路是一个高、 低电平信号同类 输出输入电路。 对低电平信号而言, 74LS08电路输出输入之间的逻 辑关系是同类或逻辑, 因此, 74LS08电路是低电平同类或门。 在后 述的或记门中称它或型低电平 C或记门。 + 74L S08 wiring diagram. Its high and low level signal outputs are similar to its high and low level input signals. Its high-level signal input value range a ai -generally takes 2V to 5V, that is 0Ci „= [5V, 2V], and the high-level signal output value range a. H -generally takes 2.4V to 3.6V , That is a. „= 〔3.6V, 2.4V】, it can be seen that a 0 „ ca ai . Its low-level signal input value range a L is generally 0V to 0.8V, that is (L = 〔0.8V, 0V], and the low-level signal output value range a. L is generally taken from 0V to 0.4V, that is a. L = C 0.4V, 0V], it can be seen that a. L ca L. From this we can know that the 7 S08 circuit It is a high-level and low-level signal homogeneous output and input circuit. For low-level signals, the logical relationship between the output and input of the 74LS08 circuit is homogeneous or logical. Therefore, the 74LS08 circuit is a low-level homogeneous OR gate. It is called or low-level C or gate in the OR gate.
图 4是原称为二输入高电平或门, 现称为高电平同类或门的  Figure 4 is the original two-input high-level OR gate
+ 7札 S32的线路图。 同样, 它的高、 低电平信号输出与它的高、 低 电平信号输入是同类的, 即 aoHdociH , aoLdOtiL . 所以, 7札 S32电路 是同类输出输入电路。 对高电平信号来说, 它的输出输入之间的逻辑 关系是同类或逻辑, 因此, 74LS32电路是高电平同类或门。 在或记 门中称它或型高电平 C或记门。 记忆链定义把信号输出送回到了取代输入端, 这时, 不管输入信 号消失与否, 能够稳定地(即不随时间而变)或者在一定时间内取代 输入信号的作用。 这种输出的输入电路称记忆链。 记忆链又称记忆因 子。 + 7 S32 circuit diagrams. Similarly, its high and low level signal outputs are the same as its high and low level signal inputs, namely aoHdociH, aoLdOtiL. Therefore, the 7 S32 circuit is a similar output and input circuit. For a high-level signal, the logical relationship between its output and input is homogeneous or logic. Therefore, the 74LS32 circuit is a high-level homogeneous OR gate. It is called a high-level C or gate in the OR gate. The definition of the memory chain sends the signal output back to the replacement input. At this time, regardless of whether the input signal disappears or not, it can stably (ie, not change with time) or replace the role of the input signal within a certain period of time. The input circuit of this output is called a memory chain. Memory chain is also called memory factor.
用信号输出来取代输入信号作用的输入端简称取代输入端, 又称 记忆链末端, 用 Γ, rc, rs表示。 An input terminal that uses a signal output to replace an input signal is referred to as an input terminal, which is also called the end of a memory chain, and is represented by Γ, r c , r s .
把信号输出送回到了取代输入端, 不能取代输入信号的作用, 这 种输出的输入电路不是记忆链, 或者说电路没有记忆链, 没有取代输 入端。  The signal output is sent back to replace the input terminal. It cannot replace the input signal. The input circuit of this output is not a memory chain, or the circuit has no memory chain and does not replace the input terminal.
记忆链是实现取代记忆逻辑功能的外因、 充分条件、 必经桥梁。 记忆链有四种: 数字输入信号稳记链、数字输入信号单值暂记链、 数字输入信号双值暂记链和模拟输入信号暂记链, 简称它们为稳记 链、 单值暂记链、 双值暂记链和模拟暂记链。 暂记链包括单值暂记链、 双值暂记链和模拟暂记链。 单值暂记链和双值暂记链称为数字暂记 链。  The memory chain is an external cause, sufficient condition, and a necessary bridge to realize the function of replacing the logic of memory. There are four types of memory chains: digital input signal stable chain, digital input signal single-value temporary chain, digital input signal double-value temporary chain, and analog input signal temporary chain. They are referred to as stable memory chain and single-value temporary chain. , Double-valued suspense chain and simulated suspense chain. Suspense chains include single-valued suspense chains, double-valued suspense chains, and simulated suspense chains. Single-valued suspense chains and double-valued suspense chains are called digital suspense chains.
稳记链定义 把信号输出送回到了取代输入端, 这时, 不管输入 信号消失与否, 能够稳定地取代输入信号的作用。 这种信号输出的输 入电路称稳记链。 稳记链又称稳记因子。 稳记链末端用 r表示。  Definition of stability chain The signal output is sent back to replace the input end. At this time, regardless of whether the input signal disappears or not, it can stably replace the role of the input signal. The input circuit of this signal output is called a steady chain. Steady chain is also called steady factor. The end of the chain is represented by r.
稳记链的电路形式主要有两种: 一种是一 线的稳记链; 另一 种是带受控电子开关的稳记链。 用得最多的稳记链是一根连线的稳记 链。 用一根连线把信号或记电路(见后述) 的输出与其取代输入端 Γ 相连, 便构成一根连线的稳记链, 十分简单。 一根连线的稳记链把无 记忆的信号或记电路质变为稳记电路。  There are two main types of circuit of stable memory chain: one is the first-line stable memory chain; the other is the stable memory chain with controlled electronic switch. The most commonly used memorizing chain is a connected memorizing chain. Using a connection to connect the output of a signal OR circuit (see below) with its replacement input terminal Γ constitutes a stable chain of connections, which is very simple. A wired memory chain changes the quality of a memoryless signal or memory circuit into a memory circuit.
图 5 ( a )为无记忆或型低电平或记电路的逻辑图。 图( b )为 该低电平或记电路接上一根连线的稳记链而构成新低电平 C I稳记器 的逻辑图。这时, r端就能够稳定取代由同类输入端 C 或者反相输入 端 I输入低电平信号的作用, 从而使输出稳记着 C端或者 I端的低电 平信号。 由此可见, 一根连线的稳记链把无记忆的或型低电平或记电 路质变成一个新低电平 C I稳记器(按过去说法称它为新低电平 R S 触发器。 )  Figure 5 (a) is a logic diagram of a memoryless or low-level OR circuit. Figure (b) is a logic diagram of the new low-level C I stabilizing device connected to the low-level OR circuit connected to a connected stable stabilizing chain. At this time, the r terminal can stably replace the low-level signal input from the similar input terminal C or the inverting input terminal I, so that the output stably remembers the low-level signal of the C terminal or I terminal. It can be seen that a connected stable memory chain turns the memoryless or low-level OR circuit quality into a new low-level CI stable register (referred to as the new low-level RS trigger in the past).
数字暂记链定义 利用电容两端电压不能突变的原理, 把信号的 输出通过电容送回到了取代输入端, 这时, 不管输入信号消失与否, 经过 R C 电路的放、 充电而能够在一定时间内取代输入信号的作用。 这种信号输出的输入电路称数字暂记链。 数字暂记链又称数字暂记因 子, 数字暂记链末端用 rc表示。 The definition of the digital suspense chain uses the principle that the voltage across the capacitor cannot be abruptly changed, and the signal output is returned to the input terminal through the capacitor. At this time, whether the input signal disappears or not, it can be discharged and charged in the RC circuit at a certain time. Replaces the role of the input signal. The input circuit for this signal output is called a digital temporary chain. The number suspense chain is also called the number suspense factor, and the end of the number suspense chain is represented by r c .
单值暂记链 新单值暂记链电路是由定时电平 V t、 定时电阻 R t、 定时电容 C t所组成。 C t必须接在信号或记电路的输出端和暂记链末 端 rc之间, R t接在 rc端和接定时电平 V t端之间,如图 6 ( b )所示。 图 6 ( a )为低电平或记电路逻辑图。 图 6 ( b )为用该低电平或记 电路接上新单值暂记链而构成新低电平暂记器的逻辑图。 关于 V t, R t, C t见后述。 The new single-valued temporary chain is composed of timing level V t , timing resistance R t , Composed of timing capacitor C t . C t must be connected between the output end of the signal OR circuit and the end of the temporary chain r c , and R t is connected between the r c terminal and the timing level V t terminal, as shown in FIG. 6 (b). Figure 6 (a) is a logic diagram of a low-level OR memory circuit. FIG. 6 (b) is a logic diagram of a new low-level temporary register formed by connecting the low-level OR circuit with a new single-valued temporary storage chain. Regarding V t , R t and C t will be described later.
原单值暂记链电路是由定时电阻 R t、 定时电容 C t所组成。 R t— 端接在 rc上, 而另一端接 "地" 或者接电源。 The original single value temporary chain circuit is composed of a timing resistor R t and a timing capacitor C t . R t — Terminate on r c and connect the other end to “ground” or to power.
把单值暂记链接在无记忆的信号或记电路上而构成的暂记器, 只 能暂记高电平信号或者低电平信号, 而不能交替暂记高电平信号和低 电平信号, 故取名为单值暂记链, 又称它为单值暂记因子。 双值暂记链 双值暂记链电路是由定时高电平 V t、 定时电阻 R t 及 R t、定时电容 C t和受输出暂记态 Q。控制的 N P N型或者 N M 0 S单 管电子开关 S。所组成。 同样, C t必须接在信号或记电路输出端和暂 记链末端 rc之间。定时电阻 R t称脉空电阻,定时电阻 R t称脉宽电阻。 双值暂记链电路如图 7 ( b )所示。 图 7 ( a )为低电平或记门逻辑 图, 图 7 ( b )为用该低电平或记电路接上双值暂记链而构成新可控 多功能脉冲振荡器的逻辑图。 关于 V t见后述。 A single-valued temporary recorder is linked to a signal or circuit with no memory. It can only temporarily record high-level signals or low-level signals. Therefore, it is called a single-valued suspense chain, which is also called a single-valued suspense factor. Double value suspense chain The double value suspense chain circuit is composed of a timing high level V t , timing resistors R t and R t , a timing capacitor C t and an output temporary state Q. Controlled NPN type or NM 0 S single tube electronic switch S. Composed of. Similarly, C t must be connected between the output of the signal OR circuit and the end of the temporary chain r c . The timing resistance R t is called a pulse-space resistance, and the timing resistance R t is called a pulse-width resistance. The double-valued temporary chain circuit is shown in Figure 7 (b). FIG. 7 (a) is a logic diagram of a low-level OR gate, and FIG. 7 (b) is a logic diagram of a new controllable multi-function pulse oscillator by using the low-level OR circuit to connect a two-value temporary register chain. V t will be described later on.
把双值暂记链接在信号或记电路上而构成的新多功能脉冲振荡器 能够交替暂记 rc端内生的高、 低电平信号, 即产生脉冲振荡, 故取名 为双值暂记链, 又称它双值暂记因子。 A new multi-function pulse oscillator constructed by linking a double-valued temporary record to a signal or a circuit can alternately temporarily record the high and low-level signals generated in the r- c terminal, that is, pulse oscillation is generated. Mind chain, also known as its double-valued temporary factor.
模拟输入信号的电平在阔值电平(阈值电平见后述) 以下的称模 拟低电平信号; 在阈值电平以上的称模拟高电平信号。  The level of the analog input signal below the threshold level (refer to the threshold level below) is called an analog low-level signal; the level above the threshold level is called an analog high-level signal.
模拟暂记链定义 模拟低电平信号的输出, 通过接在输出端和模 拟信号输入端的分压电路(非线性的或者线性的)使取代输入端获得 的低电平能够取代模拟低电平信号的作用(只有低电平同类或门才能 实现), 和取代数字输入信号的作用相比不同的是, 这种取代作用是 在模拟低电平信号消失(即变为模拟高电平信号)后保持一定时间而 终止; 与此同时, 模拟高电平信号开始起作用, 但它的输出使取代输 入端获得的高电平只能维持着而不能取代模拟高电平信号的作用, 即 模拟高电平信号的输出随着模拟高电平信号的存在而存在, 消失而消 失(因为维持期间是高电平与门)。 模拟高电平信号的输出, 通过分 压电路使取代输入端获得的高电平能够取代模拟高电平信号的作用 (只有高电平同类或门才能实现); 而这种情况下, 模拟低电平信号 的输出使取代输入端获得的低电平只能维持着而不能取代模拟低电 平信号的作用(因为维持期间是低电平与门)。 这种模拟输入信号输 出的输入电路称为模拟暂记链。 模拟暂记链又称模拟暂记因子。 模拟 暂记链末端用 rs表示。 The analog suspense chain defines the output of the analog low-level signal. The low voltage obtained by replacing the input can replace the analog low-level signal through the voltage dividing circuit (non-linear or linear) connected to the output and the analog signal input The effect (only the low-level OR gate can be realized) is different from the effect of replacing the digital input signal. This replacement effect is after the analog low-level signal disappears (that is, it becomes an analog high-level signal). Hold for a certain time and terminate; at the same time, the analog high-level signal starts to work, but its output enables the high level obtained by replacing the input terminal to be maintained but not to replace the role of the analog high-level signal, that is, the analog high The output of the level signal exists with the existence of the analog high-level signal, disappears and disappears (because the sustain period is a high-level AND gate). The output of the analog high-level signal uses a voltage divider circuit to replace the high level obtained at the input end to replace the role of the analog high-level signal (only high-level homologous OR gates can achieve); and in this case, the analog low level The output of the level signal enables the low level obtained by replacing the input terminal to be maintained but not the role of the analog low level signal (because the low level AND gate is maintained during the sustain period). This analog input signal output The input circuit is called an analog suspense chain. The analog suspense chain is also called analog suspense factor. The end of the analog suspense chain is represented by r s .
模拟暂记链电路 信号或记电路的模拟暂记链常用电路是由接在 输出端与取代输入端之间的电阻 R。和接在取代输入端和模拟信号输 入端之间的二极管 D卜 电阻 所组成的非线性分压电路, 如图 8 ( 1) )和( (1 )所示。 R。, R〗为分压电阻, 二极管 起电平偏移和 开关作用。 模拟输入信号用 l 表示。 图 8 ( a ) 为或型低电平 C或记电路(见后述, 例如 + 74L S 08 电路)的逻辑图, 图 8 ( b )为其接上模拟暂记链后而构成的暂记模 拟低电平信号的新模拟暂记器, 简称它为新低电平模拟暂记器。 图 8  Analog suspense chain circuit The common circuit of the analog suspense chain of the signal or recording circuit is a resistor R connected between the output terminal and the input terminal. And a non-linear voltage divider circuit composed of a diode D and a resistor connected between the replacement input terminal and the analog signal input terminal, as shown in Fig. 8 (1) and ((1). R., R] is the voltage division Resistors and diodes function as level shifting and switching. The analog input signal is represented by l. Figure 8 (a) is a logic diagram of an OR-type low-level C OR circuit (see below, for example, + 74L S 08 circuit). Figure 8 (b) is a new analog temporary register for temporarily simulating low-level signals formed by connecting an analog temporary link, which is referred to as a new low-level analog temporary register.
( c ) 为或型高电平 C或记电路(例如 74L S 32电路) 的逻辑图。 图 8 ( d )为该或型高电平 C或记门电路接上模拟暂记链而构成暂记 模拟高电平信号的新模拟暂记器, 简称它为新高电平模拟暂记器。 模 拟暂记器即原施密特触发器。 (c) Logic diagram of OR-type high-level C or memory circuit (such as 74L S 32 circuit). Figure 8 (d) is a new analog temporary register for the high-level C or gate circuit connected to the analog temporary chain to form a temporary analog high-level signal, referred to as a new high-level analog temporary register. The analog register is the original Schmitt trigger.
从上述记忆链、 同类输出输入、 异类输出输入三者的定义可知: 如果信号输出和输入信号是异类的, 则根本不可能用信号输出去取代 输入信号的作用; 如果信号输出和输入信号是同类的, 才有可能用信 号输出去取代输入信号的作用。  From the above definitions of the memory chain, homogeneous output input, and heterogeneous output input, it can be known that: if the signal output and input signal are heterogeneous, it is impossible to use the signal output to replace the role of the input signal; if the signal output and the input signal are homogeneous It is only possible to use the signal output to replace the role of the input signal.
记忆链原理 只 ^同类或逻辑才有记忆链, 而其它任何逻辑, 如 与逻辑、 异类或逻辑、 与非逻辑、 或非逻辑等均无记忆链。 记忆链原 理是根据记忆链定义和同类或逻辑特性而得出的不用证明的原理。  Principle of memory chain Only the same or logic can have a memory chain, and no other logic, such as AND logic, heterogeneous or logic, NAND logic, or non-logic, etc. has no memory chain. The principle of memory chain is a proof-free principle based on the definition of memory chain and homogeneous or logical characteristics.
取代记忆两准则 要实现对输入信号的取代记忆, 必须遵循两个 准则: 一是必须是信号的同类或逻辑; 二是必须接上同类逻辑独有的 记忆链。 准则一是取代记忆的 ^δ¾、 内因、 必要条件, 准则二是取代 记忆的外因、 充分条件。  Two Guidelines for Replacing Memory To achieve the replacement of input signals, two criteria must be followed: one must be the same or logic of the signal; the other must be connected to a unique memory chain of the same logic. The first criterion is to replace the internal factors and necessary conditions of memory. The second criterion is to replace the external factors and sufficient conditions of memory.
或记逻辑 输出输入之间不仅有同类或逻辑(含等效同类或逻 辑), 而且更重要更有用的通过接其独有的记忆链后还有记忆输入信 号的逻辑功能, 这种输出输入之间的逻辑关系称或记逻辑。 或者简单 地说, 同类或逻辑(含等效同类或逻辑)和它独有而待接的记忆链能 够实现或记逻辑。 或记逻辑大量、 深刻、 普遍地存在于机械、 射流、 逻辑电路、 集成电路等各个领域中。  There is not only homogeneous or logical (including equivalent homogeneous or logical) between logical output and input, but also more important and useful. By connecting its unique memory chain, there is also a logic function of memorizing input signals. The logical relationship between them is called or remembering logic. Or, simply, homology or logic (including equivalent homology or logic) and its unique and waiting memory chain can implement or memorize logic. A large amount of profound logic exists in machinery, jets, logic circuits, integrated circuits and other fields.
信号或记电路 能够实现信号或记逻辑的电路称信号或记电路, 简称或记电路或者或记门。  Signal or memory circuit A circuit that can implement a signal or memory logic is called a signal or memory circuit, referred to as a circuit or circuit or a gate for short.
或记电路的输入信号和它的输出是同类的, 其输入端称或记电路 的同类输入端, 用 C表示。 或记电路的输入信号和它输出是相反逻辑 电平状态的, 其输入端称或记电路的反相输入端, 用 I表示。 或记电 路都有信号同类输入端 C和信号反相输入端 I。 但 I端可以要, 也可 以不要。 或记电路独有而待接的记忆链末端, 即取代输入端, 显然在 同类输入端。信号或记电路就是有 C , I输入端或者只有 C端的同类 或门。 The input signal of the OR circuit is the same as its output, and its input terminal is called the same input terminal of OR circuit, which is represented by C. The input signal of the OR circuit and its output are opposite logic In the level state, its input terminal is called the inverting input terminal of the OR circuit, which is represented by I. The OR circuit has a signal input terminal C and a signal inverting input terminal I. But I can do it or not. The end of the memory chain, which is unique to the HJ circuit, is to replace the input, which is obviously at the same input. The signal OR circuit is the same OR gate with C, I input terminal or C terminal only.
或记电路的种类 按照对电平信号构成的或记门来分, 有低电平 或记门、 高电平或记门和高低电平或记门三种。  The types of OR circuits are divided according to OR gates for level signals. There are three types: low level OR gates, high level OR gates, and high level or OR gates.
低电平或记门 就是对低电平信号来说是或记门 (含低电平等效 或记门) 。 在其逻辑图左下角标示的小圆点 " · " 表示对低电平信号 是或记门。  Low-level OR gate is the OR gate for low-level signals (including low-level equivalent OR gate). The small dot "·" marked in the lower left corner of its logic diagram indicates that the gate is YES for low-level signals.
高电平或记门 就是对高电平信号来说是或记门。 在其逻辑图右 上角标示的小圆点 " · " 表示对高电平信号是或记门。  A high-level OR gate is an OR gate for high-level signals. The small dot "·" marked in the upper right corner of the logic diagram indicates that the gate is OR-coded for high-level signals.
高低电平或记门 就是对高电平信号和低电平信号来说都是或记 门。 高低电平或记门又称单输入或记门、 同相器。 在它的逻辑图上没 有标示小圆点。  High or low level OR gate is OR gate for both high level signal and low level signal. The high or low level or gate is also called single input or gate, inverter. There are no dots on its logic diagram.
按照构成或记门的电路结构来分, 主要有或型或记门 (又称一门 型或记门) 、 两门等效或记门、 扩展或记门、 集电极输出或记门。  According to the circuit structure that constitutes or gates, there are mainly or gates or gates (also known as one gate or gates), two equivalent gates, expansion or gates, collector output or gates.
或型或记门 即或型电路结构的或记门。 有或型低电平或记门、 或型高电平或记门、 或型低电平 C或记门、 或型高电平 C或记门、 或型单输入或记门。或型 C或记门就是各种集成电路中的与门及或门 (按过去说法)。 它们都是一门型或记门。  The OR gate is the OR gate of the OR circuit structure. There are or type low level or gate, or type high level or gate, or type low level C or gate, or type high level C or gate, or type single input or gate. OR type C OR gates are AND gates and OR gates (as used to say) in various integrated circuits. They are all gates or gatekeepers.
两门等效或记门 它是由两个或非门构成一个两门等效或记门, 又称它为或非非或记门。 还有两门等效 C或记门。  Two equivalent OR gates It consists of two NOR gates to form a two equivalent OR gates. It is also called a NOR gate. There are two equivalent C or gatekeepers.
扩展或记门 实际上它就是高电平与或门或者低电平或与门, 它 包括或型扩展或记门 (即一门型扩展或记门)和两门等效扩展或记 门。  Expansion OR gate In fact, it is a high-level AND gate or a low-level OR gate. It includes an OR-type expansion or gate (ie, a gate-type expansion or gate) and two equivalent expansion or gates.
集电极输出或记门 它是三极管集电极输出的低电平或记门, 它 属于两门等效低电平或记门。  Collector output or gate It is the low level or gate of the triode collector output. It belongs to two equivalent low level or gates.
在或记门线路图中, 同类输入端 C和反相输入端 I上方标示的小 圓点 " · " 表示有效输入信号是高电平信号, 即对高电平信号而言, 是或记门; 它们下方标示的小圆点 " · " 表示对低电平信号而言, 是 或 i己门。 或记门举例 前述图 3 74L S 08电路是一个或型低电平 C或记 门, 前述图 4 + 74L S 32电路是一个或型高电平 C或记门。 添极少元 件给出 74L S 08电路低电平信号的反相输入端 I , 便构成一个 LSTTL或型低电平或记门, 其线路图如图 9所示。 添极少元件给出 In the circuit diagram of the OR gate, the small dot "·" marked above the similar input terminal C and the inverting input terminal I indicates that the valid input signal is a high level signal, that is, for a high level signal, it is a OR gate. ; The small dots "·" below them indicate that they are OR gates for low-level signals. An example of a OR gate The 74L S 08 circuit shown in FIG. 3 is an OR-type low-level C OR gate, and the aforementioned circuit of FIG. 4 + 74L S 32 is an OR type high-level C-OR gate. Adding very few components gives the inverting input I of the low-level signal of the 74L S 08 circuit to form a The circuit diagram of LSTTL or low level or gate is shown in Figure 9. Adding very few components gives
4 74LS32电路高电平信号的反相输入端 I,便构成一个 LSTTL或型 高电平或记门, 其线路图如图 10所示。 图 11为 ECL或型高电平或 记门的线路图, 图 12为 TTL两个与非门构成的两门等效低电平或记 门线路图, 图 13为 LSTTL或型高电平扩展或记门的线路图, 图 14 为 TTL集电极输出的低电平或记门, 图 15为两个反相器串接而构成 的 CM 0 S单输入或记门线路图。 4 The 74LS32 circuit's inverting input terminal I of a high-level signal constitutes a LSTTL or high-level OR gate. The wiring diagram is shown in Figure 10. Figure 11 is a circuit diagram of an ECL or high-level OR gate, Figure 12 is a circuit diagram of two low-level equivalent OR gates formed by two TTL NAND gates, and Figure 13 is an LSTTL or high-level extension A circuit diagram of the OR gate, FIG. 14 is a low-level OR gate of the TTL collector output, and FIG. 15 is a circuit diagram of a CM 0 S single input or gate circuit formed by connecting two inverters in series.
信号或记门的阔值电平 信号或记门的开门电平 V 0 N和关门电平 V0pP是 L接近的, 为了便于分析, 用理想电压传输特性(折线)来代 替它的实际电压传输特性(曲线), 将两者视为近似相等。 把信号或 记门理想化的开门电平或者关门电平称作信号或记门的阈值电平(或 者门坎电平), 用 VT表示。 The threshold level of the signal or gate. The door opening level V 0 N and the gate closing level V 0 p P of the signal or gate are close to L. In order to facilitate the analysis, the ideal voltage transmission characteristic (polyline) is used to replace its actual The voltage transmission characteristics (curves) are considered to be approximately equal. The ideal opening or closing level of a signal or gate is called the threshold level (or threshold level) of the signal or gate, which is represented by V T.
暂记信号的时间, 简称暂记时间。 决定暂记时间长短的电平、 电 阻、 电容分别称定时电平、 定时电阻、 定时电容。 定时电阻用 Rt表示, 定时电容用 Ct表示, 泛指待定的定时电平用 Vt表示。 定电电平应为 阈值电平以上的逻辑电平时, 称定时高电平, 用 Vt表示; 定时电平应 为阈值电平以下的£辑电平时, 称定时低电平, 用 \ft表示。 The time of the temporary signal is referred to as the temporary time. The levels, resistances, and capacitances that determine the length of the temporary record are called timing levels, timing resistances, and timing capacitors, respectively. The timing resistance is denoted by R t , the timing capacitance is denoted by C t , and the pending timing level is generally denoted by V t . When the power-on level should be a logic level above the threshold level, the timing high level is called V t ; when the timing level is below the threshold level, it is called the timing low level. Use \ f t means.
因电平 V t的取值, 一是直接决定暂记器是否能够暂记输入信号, 二是直接决定暂记器暂记输入信号时间的长短( Rt, C t—定) , 故 取名为定时电平。 Because of the value of the level V t , one is to directly determine whether the temporary register can temporarily record the input signal, and the other is to directly determine the length of the temporary register's input signal time (R t , C t — fixed), so it is named Is the timing level.
充得电压比的定义 把暂记器暂记信号时电容上充得电压与充电 电压之比, 叫作充得电压比, 用 η表示。  Definition of charge-to-charge voltage ratio The ratio of the charge-to-charge voltage on the capacitor when the signal is temporarily recorded by the temporary register is called the charge-to-charge voltage ratio, which is expressed by η.
放失电压比的定义 把暂记器暂记信号时电容上放失电压与放电 电压(或者等效放电电压)之比, 叫作放失电压比, 用 β表示。  Definition of Loss Voltage Ratio The ratio of the discharge voltage on the capacitor to the discharge voltage (or equivalent discharge voltage) when the signal is temporarily registered by the temporary register is called the discharge voltage ratio and is expressed by β.
由 RC 电路的充电和放电规律可知: η和 β越大, 则暂记时间就 越长;反之, η和 β越小,则暂记时间就越短。定时电平 V t变化( R t, C t一定) , 使 η和 β随之变化, 从而使暂记时间和振荡频率在大范围 内连续变化。 本发明的暂记器(就是过去说的单稳态触发器)的暂记 时间和脉冲振荡器的频率不仅与定时电阻 R t, 定时电容 Ct有关, 而 最有用最可贵的是, 与定时电平 Vt直接密切有关。 再次强调指出, 用 变化的定时高电平( Rt, Ct一定) 直接使振荡频率在大范围内连续 变化, 这和用变化的电平来控制放大元件的输出电阻或者输出电流变 化, 从而使振荡频率变化的压控振荡器, 是根本不同的。 迄今为止, 世界上无人提出同类或逻辑, 更无人发现同类或逻辑 与记忆之间的科学奥秘。 《或记论》是发明人用全新概念、 全新理论、 全新技术来论述同类或逻辑记忆科学规律的一部现代自然科学基础 新理论的科学著作。 其内容有 "或记" 逻辑的重要发现、 或记电路稳 记定律、 或记电路暂记定律和万能基本新器件四章。 From the charging and discharging laws of the RC circuit, it can be known that the larger η and β, the longer the temporary recording time; conversely, the smaller η and β, the shorter the temporary recording time. The timing level V t changes (R t , C t is constant), so that η and β change accordingly, so that the temporary recording time and the oscillation frequency continuously change in a wide range. The temporary time of the temporary register of the present invention (that is, the monostable flip-flop in the past) and the frequency of the pulse oscillator are not only related to the timing resistor R t and the timing capacitor C t , but the most useful and valuable is that it is related to the timing The level V t is directly related. It is emphasized again that changing the timing high level ( Rt , Ct is constant) directly makes the oscillation frequency continuously change in a wide range, which is similar to using the changed level to control the output resistance or output current of the amplification element, so that The voltage-controlled oscillator that changes the oscillation frequency is fundamentally different. So far, no one in the world has proposed homology or logic, and no one has discovered the scientific mystery between homology or logic and memory. "Or Chronicles" is a scientific work based on modern theories and principles of modern natural sciences by the inventors to use new concepts, new theories, and new technologies to discuss similar or logical memory science laws. Its contents include important discoveries of OR logic, OR law of circuit stability, OR law of circuit temporary memory, and four basic universal new devices.
或记电路稳记定律 信号或记电路接上稳记链后, 称稳记细胞。 它用与信号同态来稳记同类输入端的信号, 用与信号反态来稳记反相 输入端的信号; 重入信号, 记态不变; 信号起作用、 不能撤离的时间 等于它取代信号的时间; 或记电路不通, 则它失去记忆。 或记型稳记 电路是由一个或多个稳记细胞有机组成。  The law of steadily remembering a circuit or signal is connected to the stability chain, which is called a stable memory cell. It uses signals in the same state to keep the signals of the same type of input terminals intact, and uses signals in the inverse state to keep the signals of the inverting input terminals. It reenters the signals and keeps the state unchanged. Time; or the circuit is not working, then it loses its memory. A memorable circuit consists of one or more organic cells.
高电平和低电平稳记细胞又称高电平和低电平 C I稳记器, 按过 去的说法是高电平和低电平 R S触发器。  High-level and low-level stable cells are also called high-level and low-level C I stabilizing devices, which used to be high-level and low-level RS triggers.
或记电路暂记定律一 信号或记电路接上数字暂记链能够暂记信 号一定时间后而自动抹去, 称暂记细胞。 它用与信号同态来暂记同类 输入端的信号, 用与信号反态来暂记反相输入端的信号; 重入信号, 记态不变; 信号起作用、 不能撤离的时间等于它取代信号的时间; 用 信号关门, 则它不记; 暂记时间由定时电平、 电阻、 电容确定。  The law of temporary circuit temporariness 1. A signal or temporary circuit connected to a digital temporary chain can tentatively erase a signal after a certain period of time, which is called a temporary cell. It uses signal homomorphism to temporarily record the signal of the same input terminal, and signal inverse state to temporarily record the signal of the inverting input terminal; reenter the signal, and keep the state unchanged; the time when the signal is active and cannot be evacuated equals the time it replaces the signal. Time; when the door is closed with a signal, it is not remembered; the temporary time is determined by the timing level, resistance and capacitance.
或记电路暂记定律二 信号或记电路接上模拟暂记链能够暂记模 拟低电平或者模拟高电平信号, 称模拟暂记细胞。 模拟输入信号频 率、 幅度一定时, 消失暂记时间与模拟暂记链分压比有关; 它越长, 则两性触发电压差就越大, 反之亦然。  The law of temporary circuit temporariness II The signal or temporary circuit connected to the analog temporary chain can temporize the analog low-level or analog high-level signal, which is called analog temporary cell. When the frequency and amplitude of the analog input signal are constant, the disappearance time is related to the voltage division ratio of the analog temporary chain; the longer it is, the greater the difference between the gender trigger voltage and vice versa.
或记之间关系 同类或逻辑与记忆之间的关系简称或记之间关 系。 "或记"概念有两个含义: 其一是有同类或和记忆两大逻辑功能; 其二是同类或£辑是取代记忆的基础、 内因、 必要条件, 而记忆功能 是同类或特性的特殊、 深刻表现和最高应用形式。 或记之间有内在和 外在的密切关系。  The relationship between jiji The relationship between homogeneity or logic and memory is simply the relationship between jiji. The concept of "or ji" has two meanings: one is that it has two major logical functions of homology or memory; the other is that homology or series is the basis, internal cause, and necessary condition to replace memory, and memory function is a special kind or characteristic , Deep expression and highest application form. There is a close relationship between internal and external.
或记之间的内在密切关系 同类输出输入之间只要有一个输入是 The internal close relationship between the jiji, as long as there is one input between the same type of input and output is
" 1 " , 则输出就是与输入同类 " 1 " 的这种同类或特性(含等效同 类或)是取代记忆逻辑功能的基础、 内因, 而记忆逻辑功能又是同类 或特性的特殊而深刻表现形式和最高应用形式。 "1", then the output is the same kind or characteristic (including the equivalent kind or equivalent) as the input of the same kind "1" is the basis and internal cause to replace the memory logic function, and the memory logic function is a special and profound expression of the same kind or characteristic Form and highest application form.
或记之间的外在关系 信号或记门有同类或和记忆两大逻辑功 能。 具体的讲, 信号或记门一般有五种工作状态和五大相应逻辑功 能。  The external relationship between the jiji The signal or jimen has two logic functions: homogeneous or memory. Specifically, signals or gatekeepers generally have five working states and five corresponding logic functions.
信号或记门不接其独有的记忆链时, 它就是一个无记忆同类或门 或者信号非的同类或门(信号或非门)。 它处在同类或逻辑工作状态, 遵循无记忆同类或规律。  When the signal or gate is not connected to its unique memory chain, it is a homogeneous or gate with no memory or a homogeneous or gate with a nonsignal (signal or NOT). It is in the same or logical working state and follows the same or law without memory.
信号或记门接上稳记链, 便由一个无记忆信号或记门质变成一个 稳记同类输入端或者反相输入端的信号的稳记电路, 它处在稳记输入 信号的工作状态, 遵循或记电路稳记定律。 The signal or gate is connected to the stable chain, and then a memoryless signal or gate becomes a The circuit for stably remembering the signals of the same type of input terminal or the inverting input terminal, it is in the working state of stably remembering the input signal, and follows or remembers the law of circuit stability.
信号或记门接上单值暂记链后, 便由一个无记忆信号或记门质变 成一个暂记同类输入端或者反相输入端信号的暂记电路, 在暂记期间 它处于暂记输入信号的工作状态, 遵循或记电路暂记定律一。  After the signal or gate is connected to a single value suspense chain, it changes from a no-memory signal or gate quality to a suspense circuit that temporarily records signals of the same type of input or inverted input. The working state of the input signal should follow or record the temporary law 1 of the circuit.
信号或记电路接上双值暂记链后, 便由一个无记忆信号或记门质 变成一个输出以高低电平交替暂记 rc端内生高、低电平信号的可控多 功能脉冲振荡器。 其振荡频率和脉空延时与定时高电平、 定时电阻、 定时电容有关, 而脉宽与脉宽电阻、 电容有关。 Or write circuit connected to the signal binary clearing chain, it consists of a non-memory signal or write gate becomes a matter of alternating high and low output in the high r c suspense end endogenous, low-level signals controlled multifunction Pulse oscillator. Its oscillation frequency and pulse-space delay are related to the timing high level, timing resistance, and timing capacitance, and the pulse width is related to the pulse width resistance and capacitance.
信号或记门接上模拟暂记链后, 便由一个无记忆信号或记门质变 成一个暂记模拟低电平(或者高电平)信号的模拟暂记电路, 即施密 特触发器, 遵循或记电路暂记定律二。  After the signal or gate is connected to the analog suspense chain, it changes from a memoryless signal or gate quality to an analog suspense circuit that temporarily records analog low (or high) signals, that is, Schmitt trigger , Follow or memorize the circuit temporary law two.
信号或记门、 信号稳记电路(信号稳记细胞) 、 信号单值暂记电 路(信号单值暂记细胞)、 脉冲振荡器、 模拟暂记电路这五种不同逻 辑功能电路的共同内核是信号或记门 (内因), 只是在不接记忆链、 接稳记链、 接单值暂记链、 接双值暂记链、 接模拟暂记链这五种不同 外界条件(外因)下, 而产生的五种不同逻辑电路和五大相应逻辑功 能。 这正像晶体三极管的工作状态一样, 晶体三极管以一个内因依据 (晶体三极管的内部构造特征), 而在三种不同外界工作条件下(基 极偏流 IB在放大区、 IB在饱和区、 在截止区), 则有放大、 饱和、 截止这三种不同工作状态。 The common core of the five different logic functional circuits: signal OR gate, signal stabilizing circuit (signal stabilizing cell), signal single-value staging circuit (signal single-value staging cell), pulse oscillator, and analog staging circuit. The signal or gate (internal factor) is only under the five different external conditions (external factor): not connected to the memory chain, connected to the stable chain, connected to the single value temporary chain, connected to the double value temporary chain, and connected to the analog temporary chain. The resulting five different logic circuits and five corresponding logic functions. This is just like the working state of the transistor, which is based on an internal cause (the internal structural characteristics of the transistor), and under three different external operating conditions (base bias current I B in the amplification region, I B in the saturation region, In the cut-off area), there are three different working states: amplification, saturation, and cut-off.
关于本发明的全新概念、 全新理论的展开详细论述, 请见发明人 的专箸《或记论》 。 下面描述本发明的或记型记忆集成电路。 本发明单值暂记链,其电路是由定时高电平 Ϋ t,或者定时低电平 γ t , 定时电阻 R t, 定时电容 C t所组成。 C t必须接在信号或记电路的 输出端和取代输入端 rc之间, R t—端接在 rc端、另一端接 Ϋ t或者 \ tFor a detailed discussion of the new concepts and new theories of the present invention, please refer to the inventor's special book "The Chronicle". The memory memory integrated circuit of the present invention is described below. In the single-value temporary register chain of the present invention, the circuit is composed of a timing high level Ϋ t , or a timing low level γ t, a timing resistor R t , and a timing capacitor C t . C t must be connected between the output terminal of the signal OR circuit and the replacement input terminal r c , R t —terminated at the terminal r c and the other terminal Ϋ t or \ t .
原单值暂记链, 其电路是由定时电阻 R t和定时电容 C ^斤组成。 C t须接在信号或记门的输出端和取代输入端 rc之间, R t一端接于 rc , 另一端接在 "地" 或者电源电压上。 所谓双值暂记链,其电路是由定时高电平 V t、定时电阻 R t及 R t、 定时电容 C t和受信号或记电路输出控制的 N P N型或者 N M O S单管 电子开关 S。所组成。 同样, (^必须接在信号或记电路输出端和取代 输入端 rc之间。 关于 R t, Rt, So, Vt的接法有两种: 一种接法是 The original single-valued temporary register chain is composed of a timing resistor R t and a timing capacitor C ^. C t must be connected between the output terminal of the signal or gate and the substitute input terminal r c , one end of R t is connected to r c , and the other end is connected to “ground” or power voltage. The so-called double value temporary chain, its circuit is a timing high voltage V t , timing resistance R t and R t , timing capacitor C t and NPN type or NMOS single-tube electronic switch S controlled by the output of a signal or memory circuit. Composed of. Similarly, (^ must be connected to the output of the signal or memory circuit and replace Between the input terminals r c . Regarding R t , R t , So, V t are connected in two ways: One way is
R t—端接在 rc端, 另一端与 Rt—端相接, 而 Rt的另一端接 Vt, So 一端接 "地" , S。输出端接在 R t和 Rt相接处。 另一种接法是 Rt— 端接在 rc端, 另一端接 Vt, R t一端接在 rc端, 另一端接在 S。的输出 端, S。的另一端接 "地"。 所以有两种双值暂记链电路, 常用前一种 双值暂记链。 R t - r c terminated at the end, the other end of R t - terminal contact, and the other end of the V t R t, So end a "ground", S. The output is terminated where R t and R t meet. Another connection method is R t — terminated at r c , the other end is connected to V t , one end of R t is connected to r c , and the other end is connected to S. Output, S. The other end is "grounded". So there are two types of double-valued suspicious chain circuits, the former type of double-valued suspicious chain is commonly used.
所谓模拟暂记链, 就是一个非线性或者线性分压电路, 它的一端 接在信号或记电路的输出端, 另一端接在模拟信号输入端, 分压输出 接在取代输入端 rs上。其常用电路是由接在信号或记电路输出端与取 代输入端 rs之间的电阻 R。和串接在取代输入端与模拟信号输入端之 间的二极管 D】、 电阻 R!所组成的非线性分压电路。 对低电平或记门 而言, 负极须接在 rs端, 对高电平或记门而言, D!iL极须接在取 代输入端 rs端。 The so-called analog suspense chain is a non-linear or linear voltage divider circuit, one end of which is connected to the output end of a signal or recorder circuit, the other end is connected to an analog signal input end, and the voltage divider output is connected to a substitute input end r s . A common circuit is a resistor R connected between the signal output terminal and the replacement input terminal r s . And diode D connected in series between the replacement input terminal and the analog signal input terminal], resistor R! Composition of a non-linear voltage divider circuit. For low-level or gate-keeping, the negative pole must be connected to r s terminal, and for high-level or gate-keeping, D! IL pole must be connected instead of input terminal r s .
所谓一 4½线的稳记链, 其电路就是连接信号或记电路输出端和 取代输入端的一根连线。  The so-called 4½-line stable memory chain is a circuit that connects the output end of a signal or memory circuit with the input end.
暂记器按过去说法是单稳态触发器, 低电平和高电平暂记器按过 去说法是低电平和高电平单稳态触发器; 模拟暂记器就是施密特触发 器, 暂记模拟低电平和高电平信号的模拟暂记器称低电平和高电平模 拟暂记器, 即低电平和高电平施密特触发器; C I稳记器按过去说法 是 R S触发器,低电平和高电平 C I稳记器按过去说法是低电平和高电 平 RS触发器。 h表示逻辑高电平、 L表示逻辑低电平; L'表示低电 平输入信号起作用、 不能撤离瞬间里的逻辑低电平; ri表示高电平输 入信号起作用、 不能撤离瞬间里的逻辑高电平。 新单稳态触发器暂记 低电平输入信号 L'或者高电平输入信号 H的暂记时间用 tT表示;在 R t, Ct一定时, 其暂记时间的最小值用 tTm in表示; 原传统单稳态触发器暂 记输入信号的暂记时间用 tT表示, tT«0.7RtCt; 在线路图中 C, 示异步输入的有效电平信号是高电平信号; C, ί表示异步输入的有效 电平信号是低电平信号。 The dipstick is a monostable flip-flop in the past, and the low-level and high-level dipsticks are low- and high-level monostable flip-flops in the past. The analogue dipstick is a Schmitt trigger. The analog register that records the analog low-level and high-level signals is called a low-level and high-level analog temporary register, that is, a low-level and high-level Schmitt trigger; the CI stable register is an RS trigger in the past. Low- and high-level CI stabilisers are, in the past, low- and high-level RS flip-flops. h represents a logic high level, L represents a logic low level; L 'represents a logic low level during which the low-level input signal is active and cannot be withdrawn; Logic high. The new monostable trigger temporarily records the low-level input signal L 'or the high-level input signal H. The temporary time is represented by t T ; when R t and C t are constant, the minimum temporary time is represented by t Tm "in "; the original traditional monostable flip-flop temporary input signal is represented by t T , t T «0.7R t C t ; in the circuit diagram C, the effective level signal of the asynchronous input is high Signal; C, ί indicates that the effective level signal of the asynchronous input is a low-level signal.
用两个 CM OS高电平或非门组成一个两门等效高电平或记门 后, 接上原单值暂记链而构成高电平信号 H由反相输入端 I输入的 C O S原传统高电平单稳态触发器暂记电路,其线路图和逻辑图如图 16 ( a )和( b )所示。 其暂记时间 tT«0.7RtCtAfter using two CM OS high-level NOR gates to form a two-gate equivalent high-level NOR gate, connect the original single-value temporary chain to form a high-level signal H. The circuit diagram and logic diagram of the original traditional high-level monostable flip-flop temporary circuit of COS are shown in Figure 16 (a) and (b). Its temporary time t T «0.7R t C t .
由两个 CM 0 S非门串接而成的 CM 0 S单输入或记门接上由定时 低电平 Y t、 定时电阻 定时电容 Ct所组成的发明单值暂记链, 并 将一个二极管的正极接在两非门串接处, 其负极作为低电平信号的反 相输入端 I , 这便构成本发明的 CM O S低电平单稳态触发器暂记电 路, 其线路图和逻辑图如图 17 ( a )和( b )所示。 其暂记时间 tT»tT~0.7R tC tA CM 0 S single input or gate made of two CM 0 S NOT gates connected in series is connected to an invention single value temporary staging chain composed of a timing low level Y t and a timing resistor timing capacitor C t , and The anode of the diode is connected in series with the two NOT gates, and its anode is used as the inverting input terminal I of the low-level signal. This constitutes the CM OS low-level monostable trigger temporary circuit of the present invention. The logic diagram is shown in Figures 17 (a) and (b). Its temporary time t T »t T ~ 0.7R t C t .
图 17 ( a ) 中二极管的正负极反过来接, 定时低电平 Y t换成定 时高电平 ,便构成本发明的 CM O S高电平单稳态触发器暂记电路, 其线路图和逻辑图如图 18 ( a )和( b ) 所示。 The positive and negative poles of the diode are reversely connected in FIG. 17 (a), and the timing low level Y t is replaced with the timing high level to form the CM OS high level monostable flip-flop temporary register circuit of the present invention. The sum logic diagram is shown in Figures 18 (a) and (b).
用两个 CM 0 S非门串接而成的 CM 0 S单输入或记门接上双值暂 记链, 便构成本发明的 CM O S多功能脉冲振荡器, 其线路图和逻辑 图如图 19 ( a )和( b )所示。 它可以作为用定时高电平 V t精确控 制方波方的程度的方波振荡器、 可作为用定时高电平 V t控制频率变化 的多谐振荡器、 可作为定时高电平 V t控制频率在大范围内连续变化的 定脉宽间歇振荡器、 可作为用定时高电平 V t控制频率在大范围内连续 变化的变脉宽间歇振荡器、 可作为用定时高电平 V t控制频率在大范围 内连续变化的超低频振荡器(从 20秒到 1小时)。 故称为多功能脉 冲振荡器。 A CM 0 S single input or gate connected with two CM 0 S NOT gates connected in series is connected to a double value temporary chain to form the CM OS multi-function pulse oscillator of the present invention. The circuit diagram and logic diagram are as shown in the figure. 19 (a) and (b). It can be as high degree of precise control of the square wave side with V t the timing of the square wave oscillator, as a multivibrator high frequency timing control V t with variations, as high V t the timing control frequency is continuously changed in a wide range of a given batch pulse oscillator as a high level V t the timing control frequency is continuously changed in a wide range of variable width intermittent oscillator as a high level V t the timing control Ultra-low frequency oscillator with continuously changing frequency over a wide range (from 20 seconds to 1 hour). It is called a multi-function pulse oscillator.
将一个二极管的正级接在图 19 ( a )中两非门串接处, 其负极作 为控制是否振荡的低电平信号反相输入端 I, 这便构成本发明的 CM O S可控多功能脉冲振荡器,其两种线路图和逻辑图如图 20 ( a ) 和( b )及( c )和( d ) 所示。  The positive stage of a diode is connected in series with the two NOT gates in Fig. 19 (a), and the negative electrode is used as the low-level signal inverting input terminal I for controlling whether to oscillate. Pulse oscillator, its two circuit diagrams and logic diagrams are shown in Figure 20 (a) and (b) and (c) and (d).
图 21 ( a )和( b ) 为用两个 CM 0 S高电平或非门组成一个两 门等效高电平或记门后, 接上一根连线的稳记链而构成 CM O S原传 统高电平 RS触发器稳记电路, 其线路图和逻辑图如图 21 ( a )和 ( b ) 所示。  Figures 21 (a) and (b) consist of two CM 0 S high-level NOR gates to form a two-gate equivalent high-level NOR gate, and then connect a connected stable chain to form the CM OS. The circuit diagram and logic diagram of the original traditional high-level RS flip-flop circuit are shown in Figure 21 (a) and (b).
由两个 CM O S非门串接而成的 CM 0 S单输入或记门接上一根连 线的稳记链, 并将一个二极管正极接在两非门串接处, 其负极作为低 电平信号的一个反相输入端 I, 将另一个二极管正极接在取代输入端 r, 其负极作为低电平信号的一个同类输入 C , 这便构成本发明的 CM 0 S低电平 RS触发器稳记电路, 其线路图和逻辑图如图 22 ( a ) 和( b ) 所示。 A CM 0 S single input or gate made of two CM OS NOT gates connected in series is connected to a wired stability chain, and a diode anode is connected at the junction of the two NOT gates. An inverting input terminal I of the level signal is connected to the anode of another diode instead of the input terminal r, and its negative electrode is used as a similar input C of the low-level signal, which constitutes the CM 0 S low-level RS trigger of the present invention. The device keeps in mind the circuit, and its wiring diagram and logic diagram are shown in Figure 22 (a) and (b).
图 22 ( a ) 中两个二极管的正负 *1 ^过来接, 便构成本发明的 CM OS高电平 RS触发器稳记电路, 其线路图和逻辑图如图 23 ( a ) 和( b ) 所示。  The positive and negative * 1 ^ of the two diodes in FIG. 22 (a) are connected to form the CM OS high-level RS flip-flop stabilizing circuit of the present invention. The circuit diagram and logic diagram are shown in FIG. 23 (a) and (b ).
图 24 ( a )和( b ) 为计算机键盘 CM 0 S消抖原技术单元电路 的线路图和逻辑图。  Figures 24 (a) and (b) are circuit diagrams and logic diagrams of the computer keyboard CM 0 S debouncer technology unit circuit.
由两个 C M 0 S非门串接而成的 CM OS单输入或记门接上一跟连 线的稳记链, 然后把取代输入端 r接在按键开关的常开触点端, 把两 非门串接处接在按键开关的常闭触点端, 把一个二极管的正级接在按 键开关公用端, 二极管的负极接 "地" , 这便构成本发明的计算机鍵 盘 CM OS消抖单元电路之一, 其线路图和逻辑图如图 25 ( a )和 ( b ) 所示。  A CM OS single input or gate made of two CM 0 S NOT gates connected in series is connected to a stable recording chain connected to the wire, and then the replacement input terminal r is connected to the normally open contact terminal of the key switch. The non-gate series connection is connected to the normally closed contact end of the key switch, the positive stage of a diode is connected to the common end of the key switch, and the negative pole of the diode is connected to "ground", which constitutes the computer keyboard CM OS of the present invention. One of the unit circuits has a wiring diagram and a logic diagram shown in Figures 25 (a) and (b).
图 23 ( a ) 中的发明 CM OS高电平 R S触发器线路图中的反相 输入端 I接在按键开关的常闭触点端, 同类输入端 C接在按键开关的 常开触点端, 按键开关的公用端接电源电压+ VD1), 这便构成本发明 计算机键盘 CM 0 S消抖单元电路之二。 其线路图和逻辑图如图 26 ( a )和( b )所示。 The inverting input terminal I of the CM OS high-level RS flip-flop circuit diagram of the invention in FIG. 23 (a) is connected to the normally closed contact terminal of the key switch, and the similar input terminal C is connected to the normally open contact terminal of the key switch. The common terminal power supply voltage of the key switch + V D1) , which constitutes the second circuit of the computer keyboard CM 0 S debounce unit of the present invention. The circuit diagram and logic diagram are shown in Figure 26 (a) and (b).
计算机键盘 CM OS消抖原技术单元电路所用元件是本发明  The components used in the computer keyboard CM OS debouncing original technology unit circuit are the invention
C OS消抖单元电路的 3倍, 其功耗是本发明 CM OS消抖单元电路 的 1000倍。 The C OS debounce unit circuit is three times as powerful, and its power consumption is 1000 times that of the CM OS debounce unit circuit of the present invention.
图 27 ( a )和( b )为 CM OS原静态存储单元电路的线路图和 逻辑图。  Figure 27 (a) and (b) are the circuit diagram and logic diagram of the CM OS original static memory cell circuit.
用两个 CM 0 S非门串接而成的 CM 0 S单输入或记门接上一f½ 线的稳记链, 然后输入端通过依次串接第一个和第二个 NM OS开关 管与数据线 D相连, 第一个 NM OS开关管受行选 Xi控制, 第二个 NM O S开关管受列选信号 yi控制, 这便构成本发明单线读写 CM OS 静态存储器。 其线路图和逆辑图如图 28 ( a )和( b ) 所示。  A CM 0 S single input or gate made by connecting two CM 0 S non-gates in series is connected to a stable chain of f½ line, and then the input end is connected in series with the first and second NM OS switch tubes and The data line D is connected, the first NM OS switch is controlled by the row selection Xi, and the second NM OS switch is controlled by the column selection signal yi, which constitutes a single-line read-write CM OS static memory of the present invention. The circuit diagram and inverse diagram are shown in Figure 28 (a) and (b).
本发明 BiCM OS可控 CI稳 i己器 ( BiCM OS可控高电平 RS触发 器)由一个本发明 CM OS低电平 C I稳记器( CM OS低电平 R S触发 器)和高电平信号输入的 TTL控制电路所组成。 TTL输入控制电路 是由两个二输入 TTL 高电平与非门组成。 第一个与非门的一个输入 端作高电平信号的一个输入端, 另一个输入端接时钟脉冲 CP , 其输 出接在本发明 CM OS低电平 C I稳记器的同类输入端上; 第二个与非 门的一个输入端作高电平信号异步输入的另一个输入端, 它的另一个 输入端接 CP脉冲, 其输出接在本发明 CM O S低电平 C I稳记器的反 相输入端上。 其线路图和逻辑图如图 29 ( a )和( b ) 所示。 The BiCM OS controllable CI stabilizer (BiCM OS controllable high-level RS flip-flop) of the present invention consists of a CM OS low-level CI stabilizer (CM OS low-level RS flip-flop) and high level The signal input consists of a TTL control circuit. TTL input control circuit It consists of two two-input TTL high-level NAND gates. One input terminal of the first NAND gate is an input terminal of a high-level signal, and the other input terminal is connected to a clock pulse CP, and an output thereof is connected to a similar input terminal of the CM OS low-level CI stabilizing device of the present invention; One input terminal of the second NAND gate is the other input terminal for asynchronous input of the high-level signal. The other input terminal is connected to the CP pulse, and the output is connected to the inverse of the CM OS low-level CI stable register of the present invention. Phase input. The circuit diagram and logic diagram are shown in Figure 29 (a) and (b).
图 30 ( a )和( b ) 为本发明 BiCM 0 S两拍工作的四位数码寄 存器的线路图和逻辑图; 图 31 ( a )和( b ) 为本发明 BiCM 0 S D 型稳记器( D型稳记器) 的线路图和逻辑图; 图 32 ( a )和( b ) 为本发明 B iCM 0 S八位寄存器 线路图(三态)。 它们都是由本发 明 CM O S低电平 RS触发器和信号输入的原 TTL控制电路所組成。  Figures 30 (a) and (b) are circuit diagrams and logic diagrams of a four-digit digital register with BiCM 0 S two-shot operation of the present invention; Figures 31 (a) and (b) are BiCM 0 SD-type stable registers of the present invention ( D-type stable register) circuit diagram and logic diagram; Figures 32 (a) and (b) are the B iCM 0 S eight-bit register circuit diagram (tri-state) of the present invention. They are all composed of the original TTL control circuit of the CMOS low-level RS flip-flop and signal input of the present invention.
图 33为本发明 BiCM O S D触发器的线路图; 图 34为本发明 BiCM 0 S J 触发器的线路图; 图 35为本发明 B iC M 0 S四位二进制 计数器的线路图。它们的全记电路都是本发明 CM 0 S低电平 RS触发 器, 而一次半记电路都是原 TTL一次半记电路。 须指出的是,  FIG. 33 is a circuit diagram of a BiCM O S D flip-flop of the present invention; FIG. 34 is a circuit diagram of a BiCM 0 S J flip-flop of the present invention; and FIG. 35 is a circuit diagram of a B iC M 0 S four-bit binary counter of the present invention. Their all-remember circuits are the CM 0 S low-level RS triggers of the present invention, and the once-and-a-remember circuits are the original TTL once-and-a-rememory circuits. It should be noted that
BiCM 0 S中 TTL部分里的电阻取值比 TTL集成电路中的数值要大得 多。 这是因为 BiCM 0 S或记型稳记电路中本发明 CM O S低电平 RS 触发器所需 TTL 电路供给的电流极小。 The resistance in the TTL part of BiCM 0 S is much larger than the value in the TTL integrated circuit. This is because the current required by the TTL circuit required by the CM O S low-level RS flip-flop of the present invention in a BiCM 0 S or memory-type stable memory circuit is extremely small.
本发明或记型暂记集成电路是由一个无记忆或型低电平 C或记 门, 即过去说的各种集成电路( LSTTL , CM O S , TTL , H TL 等) 中的一个与门, 接上暂记链而构成。 前已述及, 暂记链有本发明 值暂记链、 原单值暂记链、 双值暂记链、 模拟暂记链。 本发明单值 暂记链包括了原单值暂记链, 原单值暂记链是本发明单值暂记链的一 个下边沿特例。 实施举例如下:  The invention's or temporary memory integrated circuit is composed of a memoryless or low-level C or gate, which is an AND gate of various integrated circuits (LSTTL, CM OS, TTL, H TL, etc.) in the past. Connected to the suspense chain. As mentioned earlier, the suspense chain includes the value suspense chain of the present invention, the original single value suspense chain, the double value suspense chain, and the simulated suspense chain. The single value suspense chain of the present invention includes the original single value suspense chain. The original single value suspense chain is a special case of the lower edge of the single value suspense chain of the present invention. The implementation examples are as follows:
例如, 用一个无记忆的 LSTTL或型低电平 C或记门, 即一个过 去说的 74LS08二输入与门, 接上由定时高电平 Vt、 定时电阻 Rt、 定时电容 C t组成的本发明单值暂记链而构成本发明 LSTTL低电平单 稳态触发器暂记电路。 其线路图和逻辑图如图 36 ( a )和( b ) 所 示。 For example, a non-memory LSTTL or low-level C OR gate, that is, a 74LS08 two-input AND gate, which was said in the past, is connected to a timing high-level V t , a timing resistor R t , and a timing capacitor C t The single value suspense chain of the present invention constitutes the LSTTL low-level monostable flip-flop temporary suspense circuit of the present invention. The circuit diagram and logic diagram are shown in Figure 36 (a) and (b).
图 37 ( a )和( b )为用两个高电平与非门(两个低电平或非门) 组成一个两门等效低电平或记门, 接上原单值暂记链而构成低电平信 号 L'由 I端输入的原传统 LSTTL低电平单稳态触发器的线路图和逻辑 图。 其暂记时间 tT«0.7RtCt。 用一个无记忆 LSTTL或记低电平 C或记门, 即一个过去说的!" 74LS08二输入与门, 接上由定时电容 C t、 一端接电源的定时电阻 R t 组成的原单值暂记链, 并在同类输入端 C接上开关脉冲发生电路, 从 而构成本发明 LSTTL 负单脉冲发生器。 其线路图和逻辑图如图 38 ( a ) 和( b ) 所示。 用一个无记忆 LSTTL或型低电平 C或记门, 即一个过去说的+ 74LS08二输入与门, 接上低电平模拟暂记链, 便构成本发明 LSTTL 低电平模拟暂记器(即低电平施密特触发器), 其线路图和逻辑图如 图 39 ( a ) 和( b ) 所示。 所谓低电平模拟暂记链就是二极管负极 接在取代输入端的模拟暂记链。 图 40 ( a )和( b ) 为用一个低电 平或非门(即高电平与非门)和一个非门組成一个两门等效低电平 C 或记门后, 接上低电平模拟暂记链而构成 LSTTL原低电平施密特触 发器的线路图和逻辑图。 用一个无记忆或型低电平 C或记门, 即一个过去说的 + 7札 S08 二输入与门, 接上双值暂记链, 便构成本发明 LSTTL可控多功能脉 冲振荡器暂记电路, 其线路图和逻辑图如图 41 ( a )和( b )所示。 Figure 37 (a) and (b) are a two-gate equivalent low-level OR gate with two high-level NAND gates (two low-level NOR gates). The circuit diagram and logic diagram of the original traditional LSTTL low-level monostable flip-flop, which forms the low-level signal L 'and is input from the I terminal. Its temporary time t T «0.7R t C t . Use a memoryless LSTTL or a low-level C or a gate, which is what one said in the past! The 74LS08 two-input AND gate is connected to the original single-value temporary chain consisting of a timing capacitor C t and a timing resistor R t connected to a power source at one end, and a switching pulse generating circuit is connected to a similar input terminal C, thereby forming the LSTTL negative of the present invention. Single pulse generator. Its circuit diagram and logic diagram are shown in Figure 38 (a) and (b). Use a memoryless LSTTL or low-level C OR gate, which is a + 74LS08 two-input AND gate The LSTTL low-level analog temporary register (ie, the low-level Schmitt trigger) of the present invention is constituted by connecting the low-level analog temporary register, and its circuit diagram and logic diagram are shown in Figure 39 (a) and (b ). The so-called low-level analog suspense chain is an analog suspense chain with the anode of the diode connected in place of the input. Figure 40 (a) and (b) use a low-level NOR gate (high-level NAND gate) Gate) and an NOT gate to form a two-gate equivalent low-level C OR gate, and then connect a low-level analog suspense chain to form the LSTTL original low-level Schmitt trigger circuit and logic diagram. A no-memory or low-level C or gatekeeper, that is a +7 entry S08 two inputs Gate, connected to two-value clearing chain, constitute LSTTL Multifunctional controlled oscillator of the present invention the suspense circuit and a logic circuit diagram shown in Figure 41 (a) and (b) shown in FIG.
本发明或记型暂记集成电路是用一个无记忆或型高电平 C或记 门, 即过去说的各种集成电路( LSTTL , CM O S , TTL , H TL ) 中的一个或门, 接上暂记链而构成。 实施举例如下:  In the present invention, the temporary memory integrated circuit uses a memoryless or high-level C or gate, that is, an OR gate of various integrated circuits (LSTTL, CM OS, TTL, H TL) in the past. Constitute on the chain. The implementation examples are as follows:
例如, 用一个无记忆 LSTTL或型高电平 C或记门, 即一个过去 说的 + 74LS32二输入或门, 接上由定时低电平 Yt、 定时电阻 Rt、 定 时电容 C t组成的本发明单值暂记链而构成本发明 LSTTL高电平单稳 态触发器暂记电路。 其线路图和逻辑图如图 42 ( a )和( b )所示。 For example, use a memoryless LSTTL or high-level C OR gate, that is, a + 74LS32 two-input OR gate in the past, connected to a timing low level Y t , a timing resistor R t , and a timing capacitor C t The single-value temporary register chain of the present invention constitutes the LSTTL high-level monostable trigger temporary register circuit of the present invention. The circuit diagram and logic diagram are shown in Figure 42 (a) and (b).
用一个无记忆 LSTTL或型高电平 C或记门, 即过去说的  Use a memoryless LSTTL or a high-level C or gate, as previously said
+ 7札 S32二输入或门, 接上由定时电容 C t、 一端接 "地" 的定时电 阻 R t组成的原单值暂记链, 并在同类输入端接上开关脉冲发生电路, 从而构成本发明 LSTTL正单脉冲发生器, 其线路图和逻辑图如图 43 ( a )和( b ) 所示。 + 7 S32 two-input OR gates, connected to the original single-value temporary chain consisting of a timing capacitor C t and one end connected to a “ground” timing resistor R t , and connected to a switching pulse generating circuit at the same input end, thereby constituting the present Inventing the LSTTL positive single pulse generator, its circuit diagram and logic diagram are shown in Figures 43 (a) and (b).
用一个无记忆 LSTTL或型高电平 C或记门, 即过去说的  Use a memoryless LSTTL or a high-level C or gate, as previously said
+ 74LS32二输入或门, 接上高电平模拟暂记链, 便构成本发明 LSTTL 高电平模拟暂记器(即高电平施密特触发器) , 其线路图和 W 逻辑图如图 44 ( a )和( b )所示。 所谓高电平模拟暂记链就是二 极管正极接在取代输入端的模拟暂记链。 + 74LS32 two-input OR gate, connected to a high-level analog suspense chain, constitutes the LSTTL high-level analog suspense device (ie, high-level Schmitt trigger) of the present invention, its circuit diagram and The W logic diagram is shown in Figures 44 (a) and (b). The so-called high-level analog suspense chain is an analog suspense chain with the anode of the diode connected to the input end.
用一个无记忆 LSTTL或型高电平 C或记门, 即过去说的  Use a memoryless LSTTL or a high-level C or gate, as previously said
4 74LS32二输入或门,接以双值暂记链,便构成本发明 LSTTL可控 多功能脉冲振荡器, 其线路图和逻辑图从略。 4 74LS32 two-input OR gates, connected with a double-valued temporary chain, constitute the LSTTL controllable multi-function pulse oscillator of the present invention, and its circuit diagram and logic diagram are omitted.
一个无记忆或型低电平 C I或记门 (简称或型低电平或记门), 它是由一个或型低电平 C或记门,添极少元件给出其低电平信号反相 输入端 I而构成的。 或者说到底, 它就是用过去说的各种集成电路 A no-memory or low-level CI or gate (referred to as a low-level or gate). It is a low-level C or gate. Phase input I. In the final analysis, it is the use of various integrated circuits
( LSTTL , CM OS , TTL , Η TL , Ε C L等) 中的一个与门, 通 过添极少元件给出其低电平信号反相输入端而构成的无记忆低电平 同类或门。 An AND gate (LSTTL, CM OS, TTL, Η TL, Ε C L, etc.), a memoryless low-level homogeneous OR gate formed by adding very few components to give its low-level signal inverting input.
本发明或记型记忆集成电路是用一个无记忆或型低电平 C I或记 门接上记忆链而构成。 实施举例如下:  The memory integrated circuit of the present invention is formed by using a memoryless or low-level C I or gate connected to a memory chain. The implementation examples are as follows:
例如: 用一个无记忆 LSTTL或型低电平 C I或记门, 即一个有低 电平信号反相输入端的、 过去说的" 74LS08二输入与门, 接上一根 连线的稳记链, 便构成本发明 LSTTL低电平 C I稳记器(低电平 R S 触发器),其线路图和逻辑图如图 45 ( a )和( b )所示。图 46 ( a ) 和( b )为用两个高电平与非门(两个低电平或非门)组成一个两门 等效 C I或记门后, 接上一根连线的稳记链而构成原 LSTTL低电平 RS触发器的线路图和逻辑图。  For example: Use a memoryless LSTTL or low-level CI OR gate, that is, a "74LS08 two-input AND gate" in the past that has a low-level signal inverting input terminal. This constitutes the LSTTL low-level CI stable register (low-level RS flip-flop) of the present invention, and its circuit diagram and logic diagram are shown in Figures 45 (a) and (b). Figures 46 (a) and (b) are Two high-level NAND gates (two low-level NOR gates) are used to form a two-gate equivalent CI OR gate, and then a wired stable chain is connected to form the original LSTTL low-level RS trigger. And logic diagrams of the controller.
用一个无记忆 LSTTL或型低电平 C I或记门, 即一个有低电平信 号反相输入端、过去说的 " 7札 S 08二输入与门,接上由定时低电平 Y t、 定时电阻 Rt、 定时电容 Ct组成的本发明单值暂记链, 并且同类输 入端 C接高电平, 这便构成低电平信号由反相输入端输入的本发明 LSTTL低电平单稳态触发器暂记电路, 其线路图和逻辑图如图 47 ( a )和( b ) 所示。 其暂记时间 tT»tTUse a non-memory LSTTL or low-level CI OR gate, that is, a 7-input S 08 two-input AND gate with a low-level signal inverting input, which is connected by the timing low-level Y t, A single-valued temporary chain of the present invention composed of a timing resistor R t and a timing capacitor C t , and a similar input terminal C is connected to a high level, which constitutes a low-level signal of the LSTTL low-level signal of the present invention input through an inverting input terminal. The circuit diagram and logic diagram of the steady-state trigger temporary circuit are shown in Fig. 47 (a) and (b). The temporary time t T »t T.
LSTTL或型低电平 C I或记门, 当 I端接高电平时, 它就变成 LSTTL或型低电平 C或记门, 这时, 用它构成本发明 LSTTL的低 电平单稳态触发器、 负单脉冲发生器、 低电平施密特触发器和可控多 功能脉冲振荡器和 LSTTL或型低电平 C或记门的方法完全一样, 这 里 从略。  LSTTL or low-level CI or gate. When I terminal is connected to high level, it becomes LSTTL or low-level C or gate. At this time, it is used to form the low-level monostable state of LSTTL of the present invention. The triggers, negative single pulse generators, low-level Schmitt triggers, and controllable multi-function pulse oscillators are exactly the same as LSTTL or low-level C or gatekeeper methods, and are omitted here.
本发明一种或记型 LSTTL小摆幅输出的低电平 C I稳记器(小摆 幅输出的低电平 RS触发器),其线路图和逻辑图如图 48 ( a )和( b ) 所示。它的电路是由抗饱和三极管!^和^、肖特基二极管 D D !, D2, D 2 , D 2 , 二极管 D (硅二极管或者肖特基二极管)、 电阻 ^和1 2、 低电平信号输入端 ς和. I、 输出端 Qs和 Q s组成。 The circuit diagram and logic diagram of a low-level CI stable register (low-level RS flip-flop with small-swing output) of the LSTTL small-swing output of the present invention are shown in Figure 48 (a) and (b) As shown. Its circuit is made of anti-saturation triode! ^ And ^, Schottky diode DD! , D 2 , D 2, D 2, diode D (silicon diode or Schottky diode), resistors ^ and 1 2 , low-level signal input terminals and I, output terminals Q s and Q s .
和 T 2的发射极都与 D 的正极相接, D 的负极接 "地"; R 1的一端接 的集电极, 的另一端接电源电压 + Vcc, R2的一端接 T2的集电 极, R2的另一端接电源电压 + Vcc; 01的正极接了1的1 ?1, 0!的 负极作为低电平信号的同类输入端 (:; D !的负极接^的!^, D ! 的正极接 T 2的集电极; D !作为 ς端的保护二极管, D i的负极接!), 的负极, D ϋ的正极接"地"; 02的正极接 T2 jfel, D2的负极作为 低电平信号反相输入端. I; D 2的负极接丁2的^¾ -, D 2的正极接 的集电极, D 2作为 ί端的保护二极管, D 2的负极接 D2的负极, D 2 的正极接"地"; T2的集电极作为输出端 Q s, 的集电极作为反相 输出端 Q s. The emitter of T 2 is connected to the anode of D, and the anode of D is connected to "ground"; one end of R 1 is connected to the collector, the other end is connected to the power supply voltage + V cc , and one end of R 2 is connected to the collector of T 2 Electrode, the other end of R 2 is connected to the power supply voltage + V cc ; the positive end of 0 1 is connected to 1 1 to 1, and the negative end of 0! Is the same type of low-level input terminal (:; the negative end of D! Is connected to ^! ! ^, D is positive then T collector 2;!! D as protective diode ς terminal, the negative electrode of D i connection), a negative electrode, D ϋ to cathode of the "ground"; positive then T 2 jfel 0 2, and The negative electrode of D 2 is used as the low-level signal inverting input terminal. I; the negative electrode of D 2 is connected to D 2 of D 2- , the positive electrode of D 2 is connected to the collector, D 2 is used as the protection diode of the terminal, and the negative electrode of D 2 is connected D 2 is a negative electrode, D 2 connected to the positive electrode "ground"; T 2 as a collector output terminal Q s, the collector of the inverting output terminal Q s.
图 49为本发明 LSTTL D触发器的线路图。 它的一次半记电路, 即过去说的触发引导电路是原有的, 而它的全记电路, 即过去说的基 本触发器, 是本发明的 LSTTL低电平 RS触发器。 图 50为 LSTTL 原 D触发器的线路图。  Figure 49 is a circuit diagram of the LSTTL D flip-flop of the present invention. Its one-and-a-half-time circuit, that is, the trigger guide circuit in the past, is original, and its full-memory circuit, that is, the basic trigger in the past, is the LSTTL low-level RS flip-flop of the present invention. Figure 50 is a circuit diagram of the original LSTTL D flip-flop.
图 51为本发明 LSTTL JK 触发器的线路图。 同样, 它的一次半 记电路, 即过去说的触发引导电路, 是原有的, 它的全记电路, 即过 去说的基本 RS触发器, 是本发明 LSTTL低电平 RS触发器。  Figure 51 is a circuit diagram of the LSTTL JK flip-flop of the present invention. Similarly, its one-and-a-half-time circuit, that is, the trigger guide circuit in the past, is the original, and its full-memory circuit, that is, the basic RS trigger in the past, is the LSTTL low-level RS flip-flop of the present invention.
图 52为本发明 LSTTL小摆幅输出 D触发器的线路图。它的一次 半记电路是原有的, 而它的全记电路是本发明 LSTTL 小摆幅输出的 低电平 RS触发器。  Figure 52 is a circuit diagram of the LSTTL small swing output D flip-flop of the present invention. Its once-and-a-half circuit is original, and its all-memory circuit is a low-level RS flip-flop of the LSTTL small swing output of the present invention.
综而言之, 本发明的 LSTTL D 触发器、 LSTTL J 触发器、 LSTTL各种计数器、 各种数码寄存器、 各种移位寄存器等, 其发明 之处就是它们的全记电路都是本发明 LSTTL低电平 R S触发器。 本 发明的 LSTTL小摆幅输出的 D触发器、 触发器, 各种计数器、 各种数码寄存器、 各种移位寄存器等, 其发明之处就是它们的全记电 路(即过去说的基本触发器)都是本发明的 LSTTL 小摆幅输出的低 电平 RS触发器。  To sum up, the LSTTL D flip-flop, LSTTL J flip-flop, LSTTL various counters, various digital registers, various shift registers, etc. of the present invention, the invention is that their all-memory circuits are the LSTTL of the present invention Low-level RS flip-flop. The D flip-flops, flip-flops, various counters, various digital registers, various shift registers, etc. of the LSTTL small-swing output of the present invention are the invention of their all-remember circuit (the basic flip-flop in the past) ) Are low-level RS flip-flops of the LSTTL small swing output of the present invention.
一个无记忆或型高电平 C I或记门 (简称或型高电平或记门) , 它是由一个或型高电平 C或记门,添极少元件给出其高电平信号反相 输入端 I而构成的。 或者说到底, 它就是用过去说的各种集成电路 ( LSTTL , CM OS , TTL , HTL, E C L等) 中的一个或门, 通 过添极少元件给出其高电平信号反相输入端的无记忆逻辑电路。 A no-memory or high-level CI or gate (referred to as a high-level or gate), it is a high-level C or gate, with very few components to give its high-level signal. Phase Constituted by the input terminal I. In the final analysis, it is an OR gate of various integrated circuits (LSTTL, CM OS, TTL, HTL, ECL, etc.) that was said in the past, and it provides the high-level signal at the inverting input terminal by adding very few components. Memory logic circuit.
本发明或记型记忆集成电路是用一个无记忆或型高电平 C I或记 门接上记忆链而构成。 实施举例如下:  The memory or integrated circuit of the present invention is formed by using a memoryless or high-level C I or gate connected to a memory chain. The implementation examples are as follows:
用一个无记忆 LSTTL或型高电平 C I或记门, 即一个有高电平信 号反相输入端的、 过去说的 + 74LS32二输入或记门, 接上一 线 的稳记链, 便构成本发明 LSTTL 高电平 C I稳记器(高电平 RS触发 器) , 其线路图和逻辑图如图 53 ( a )和( b ) 所示。  A memoryless LSTTL or high-level CI or gate is used, that is, a + 74LS32 two-input or gate with a high-level signal inverting input in the past, connected to a first-line stable chain to form the present invention. LSTTL high-level CI stabilizing device (high-level RS flip-flop), its wiring diagram and logic diagram are shown in Figure 53 (a) and (b).
用一个无记忆 LSTTL或型高电平 C I或记门, 即一个有高电平信 号反相输入端的, 过去说的 74LS32二输入或记门, 接上由定时高 电平 Vt、 定时电阻 Rt、 定时电容^组成的本发明单值暂记链, 并且 同类输入端接低电平, 这便构成高电平信号由反相输入端输入的本发 明 LSTTL 高电平单稳态触发器暂记电路, 其线路图和逻辑图如图 54 ( a ) 和( b )所示。 其暂己时间 tT»tTUse a non-memory LSTTL or high-level CI or gate, that is, a 74LS32 two-input or gate with a high-level signal inverting input, which is connected by a timing high-level V t and a timing resistor R t , a single value temporary chain of the present invention composed of a timing capacitor ^, and the same type of input terminal is connected to a low level, which constitutes a high level signal, and the LSTTL high level monostable flip-flop of the present invention is input through the inverting input Remember the circuit, its wiring diagram and logic diagram are shown in Figure 54 (a) and (b). Its temporary time t T »t T.
用一个无记忆 LSTTL或型高电平 C I或记门,接上暂记链而构成 本发明 LSTTL其他暂记器电路, 这里——从略。  A memoryless LSTTL or high-level C I or gate is connected to a temporary register chain to form another LSTTL register circuit of the present invention, which is omitted here.
再例如, 用一个无记忆 ECL或型高电平 C I或记门, 即一个有高 电平反相输入端的、 过去说的 EC L或门, 接上一½线的稳记链, 便构成本发明 ECL 高电平 C I稳记器( ECL 高电平 RS触发器)。 图 55 ( a )和( b ) 为本发明有置 0置 1的 ECL 高电平 RS触发器 的线路图和逻辑图。 图 56 ( a ) 和( b ) 为用两个高电平或非门组 成一个两门等效高电平或记门后,接上一根连线的稳记链而构成 EC L 原高电平 R S触发器的线路图和逻辑图。  As another example, a memoryless ECL or high-level CI OR gate, that is, an EC L OR gate in the past with a high-level inverting input terminal, connected to a ½-line stable memory chain, constitutes the present invention. ECL High CI Stabilizer (ECL High RS Trigger). Figures 55 (a) and (b) are circuit diagrams and logic diagrams of the ECL high-level RS flip-flops with 0 and 1 set in the present invention. Figure 56 (a) and (b) are composed of two high-level NOR gates to form a two-gate equivalent high-level NOR gate, and then connect a connected stable chain to form the EC L original high voltage Circuit diagram and logic diagram of the flat RS flip-flop.
本发明或记型稳记电路是用一个无记忆或型扩展或记门接上一根 连线的稳记链而构成。 或型扩展或记门就是过去说的各种集成电路 ( LSTTL , CM OS , TTL , HTL , E C L等)中的高电平与或门。 实施举例如下:  The memory or memory circuit of the present invention is formed by a memoryless memory or memory expansion or memory gate connected to a connected memory chain. The OR-type extended OR gate is a high-level AND gate in various integrated circuits (LSTTL, CM OS, TTL, HTL, E C L, etc.) said in the past. The implementation examples are as follows:
用一个无记忆 LSTTL二两输入或型高电平扩展或记门, 即一个 过去说的 LSTTL二两输入高电平与或门, 它的一个两输入端的一端 接上一 ^线的稳记链、 另一端接时钟脉冲非 C P , 另一个两输入端 的一端接时钟脉冲 CP , 另一端接双值信号 D , 这便构成本发明 LSTTL D半透半记器(数码锁存器)。 其线路图如图 57所示。 图 58 为 LSTTL原!)半透半记器(数码锁存器)的线路图, 它是用两门构 成的。 Use a memoryless LSTTL two-input two-or-type high-level OR gate to extend the OR gate, that is, a LSTTL two-input two-level high-level AND gate, and one end of one of the two input terminals is connected to a one-wire stable chain. 1. The other end is connected to a clock pulse other than CP, one end of the other two input ends is connected to a clock pulse CP, and the other end is connected to a binary signal D. This constitutes the present invention. LSTTL D transflective register (digital latch). The circuit diagram is shown in Figure 57. Figure 58 shows the original LSTTL! ) Semi-transparent circuit (digital latch) circuit diagram, which is composed of two gates.
本发明一种具有特多功能的 CM OS基本新器件, 简称 CM O S万 能基本新器件, 用 ZC01表示, 其线路图和逻辑图如图 59和图 60所 示。 一种具有特多功能的 LSTTL基本新器件, 简称 LSTTL万能基 本新器件, 用 ZL03表示, 其线路图和逻辑图如图 61和图 62所示。  The present invention has a special multifunctional CM OS basic new device, referred to as CM O S universal basic new device, which is represented by ZC01, and its circuit diagram and logic diagram are shown in FIG. 59 and FIG. 60. A new type of LSTTL basic new device with special functions, referred to as LSTTL universal basic new device, is represented by ZL03. Its circuit diagram and logic diagram are shown in Figure 61 and Figure 62.
ZC 01和 ZL 03是由双值信号输入电路、 一次半记电路、 两种电平 信号的扩展或记门这三部分组成。 ZL03比 ZC 01多一种压控脉冲振 荡器功能, 其它功能完全一样。 ZC01的输入端有 r,C(),
Figure imgf000027_0001
ϊ,Ι ,Ε, CP,D,J,K ; 输出端 Q 、 反相输出端 Q 、 漏¾ ^相输出端 Q 0 D . Γ 端在 ZC 01作或记型记忆路时作取代输入端用, CQ在 ZC 01作低电平 信号的或记型记忆电路时作同类输入端用或者在 ZC 01作 D触发器和 J 触发器时作直接置 0端用, ^在?。 01作低电平信号的或记型记忆 电路时作反相输入端或者在 ZC 01作!)触发器和 JK 触发器时作直接 置 1端用, C和 Ϊ在 ZC01作高电平信号的或记型记忆电路时作同类输 入端和反相输入端用, E为控制 CM OS双向模拟开关接通或者断开 的控制信号输入端, CP为时钟脉冲输入端, D为 D触发器的输入 端, J、 K 为 JK 触发器的输入端。 ZL03的输入端 Vb在 ZL03作压 控脉冲振荡时作控制电压的输入端用, 其它输入端 r,Go, Ji, C , I, R , CP,D, J, 的意义同 ZC01 ; 输出端 Q 、 反相输出端 Q 、 集电 ^L^ 相输出端 Q o c
ZC 01 and ZL 03 are composed of a three-valued signal input circuit, a once-and-a-half circuit, and two levels of signal extension or gate. ZL03 has one more voltage-controlled pulse oscillator function than ZC 01, and other functions are exactly the same. The input of ZC01 has r, C (),
Figure imgf000027_0001
ϊ, Ι, Ε, CP, D, J, K; output terminal Q, inverting output terminal Q, drain ¾ phase output terminal Q 0 D. Γ terminal is used instead of input terminal when ZC 01 is used as a memory circuit Yes, C Q is used as a similar input terminal when ZC 01 is used as a low-level signal or memory circuit or directly set as 0 when ZC 01 is used as a D flip-flop and J flip-flop. . 01 for low-level signal or memory circuit as the inverting input or ZC 01! ) Triggers and JK triggers are set directly as 1 terminal, C and Ϊ are used as high-level signal or memory circuit in ZC01 for similar inputs and inverting inputs, E is for bidirectional analog control of CM OS Control signal input terminal for switch on or off, CP is the clock pulse input terminal, D is the input terminal of D flip-flop, J, K is the input terminal of JK flip-flop. The input terminal V b of ZL03 is used as the input terminal of control voltage when ZL03 is used for voltage controlled pulse oscillation. The other input terminals r, Go, Ji, C, I, R, CP, D, J, have the same meaning as ZC01; output terminal Q, inverting output Q, current collector ^ L ^ phase output Q oc
ZC 01的 Q Q D端带灌电流负载能力为 80m A, ZL03的 Q QC端带 灌电流负载能力为 60m A (设计为 100m A )。 ZC 01's QQD terminal with sink current load capacity is 80m A, ZL03's QQ C terminal with sink current load capacity is 60m A (designed as 100m A).
ZC 01万能基本新器件具有下列特多功能: 1.可以作高电平与或 门 ( CP = L、 D = J = Κ =Φ, Ε = L , I, = h . ϊ = L ); 2. 可以作高电平与或非门(输入端设定条件同 1 ), 1和 2的等效逻辑 图如图 63 ( a )所示; 3.可以作数码锁存器( CP - L、 D = J = =Φ, Ε = h , Ιι = h , ϊ= L ) , 其等效逻辑图如图 63 ( b )所 示, L表示逻辑低电平, h表示逻辑高电平, Φ表示为 L或者为 h; 4.可以作低电平同类或门 (即高电平与门) ( CP = L 、 D = J = K ZC 01 universal basic new device has the following special functions: 1. Can be used as high-level AND gate (CP = L, D = J = Κ = Φ, Ε = L, I, = h. Ϊ = L); 2 Can be used as high-level NOR gate (input terminal setting conditions are the same as 1), the equivalent logic diagram of 1 and 2 is shown in Figure 63 (a); 3. Can be used as a digital latch (CP-L, D = J = = Φ, Ε = h, Ιι = h, ϊ = L), and its equivalent logic diagram is shown in Figure 63 (b). L is a logic low level, h is a logic high level, and Φ is L or h; 4. Can be a low-level homologous OR gate (ie, high-level AND gate) (CP = L, D = J = K
=Φ、 E = L 、 . = h、 C = L 、 R =Φ. 1= L ) ; 5.可以作高电 平与非门(输入端设定条件同 4 ), 4和 5的等效逻辑图如图 63 ( c ) 所示; 6.可以作低电平 R S触发器( CP = L 、 D = J = =Φ ¾ C = Φ, E = L,. = H, C = L, R = Φ. 1 = L); 5. Can be used as high-level NAND gate (input terminal setting conditions are the same as 4), 4 and 5 are equivalent The logic diagram is shown in Figure 63 (c); 6. Can be used as a low-level RS flip-flop (CP = L, D = J = = Φ ¾ C
= i= L 、 E = h、 R =Φ ), 其等效逻辑图如图 63 ( d )所示; 7. 可以作单脉冲发生器(输入端设定条件同 6 ) , 其等效逻辑如图 63 ( e )所示; 8.可以作定时低电平 Y t直接控制暂记时间在大范围内连 续变化的低电平单稳态触发器, 其暂记时间由 Yt、 Rt、 Ct三者决定 = i = L, E = h, R = Φ), its equivalent logic diagram is shown in Figure 63 (d); 7. Can be used as a single pulse generator (input terminal setting conditions are the same as 6), its equivalent logic As shown in Figure 63 (e); 8. It can be a low-level monostable flip-flop with a timing low level Y t to directly control the temporary change of the continuous time within a large range, and its temporary time is determined by Y t and R t And C t
( CP = L , D = J = K =0、 Ε = L , C = I= L , C0 = h , R (CP = L, D = J = K = 0, Ε = L, C = I = L, C 0 = h, R
==Φ ) , 其等效逻辑图如图 63 ( f )所示; 9.可以作用定时高电平 V t直接控制暂记时间在大范围内连续变化的低电平单稳态触发器( CP == Φ), its equivalent logic diagram is shown in Figure 63 (f); 9. Low-level monostable flip-flops that can be used to control the timing high-level V t to directly control the continuous change of the temporary recording time in a large range ( CP
= L 、 D = J = Κ =Φ . Ε = L . C = ϊ= L , R = Φ , Ji = h ) , 其暂记时间由 Vt、 Rt、 Ct三者确定, 其等效逻辑图如图 63 ( g )所 示; 10.可以作正单脉沖发生器(输入端设定条件 8 ) , 其等效逻辑 图如图 63 ( h )所示; 11.可以作负单脉冲发生器(输入端设定条件 同 9 ) , 其等效逻辑图如图 63 ( i )所示; 12.可以作低电平施密特 触发器(输入端设定条件同 9 ) , 其等效逻辑图如图 63 ( j )所示; 13.可以作定时高电平直接精确控制方波方度(方波方的精确度称方 度)的、频率连续可调的方波发生器( CP = L、 D = J = K =0,C o = Ii = h . C = ϊ = L , E = L、 R =Φ ) , 其频率由定时高电平、 定时电阻、 定时电容三者确定; 14.可以作用定时高电平直接控制频 率连续变化的多谐振荡器(输入端设定条件同 13 ) , 其频率由定时 高电平、 定时电阻、 定时电容三者确定; 15.可以作用定时高电平直 接控制脉空(脉冲空度简称脉空)在大范围内连续变化的定脉宽(脉 冲宽度简称脉宽) 间歇振荡器(输入端设定条件同 13 ) , 其频率由 定时高电平、 定时电阻、 定时电容三者确定; 16.可以作用定时高电 平直接控制脉空在大范围内连续变化的、 脉宽连续可调的间歇振荡器 (输入端设定条件同 13 ) , 其频率由定时高电平、 定时电阻、 定时 电容三者确定; 17.可以作用定时高电平直接控制脉空在大范围内连 续变化的超低频脉冲振荡器(输入端设定条件同 13 ) , 定时电容 C t 和定时电阻 R t (脉空电阻)取值大, 其振荡周期从 20秒到 1小时连 续变化, 13、 14、 15、 16和 17的等效逻辑图如图 63 ( k )所示;= L, D = J = Κ = Φ. Ε = L. C = ϊ = L, R = Φ, Ji = h), the temporary time is determined by V t , R t , C t , which are equivalent The logic diagram is shown in Figure 63 (g); 10. It can be used as a positive single pulse generator (input terminal setting condition 8), and its equivalent logic diagram is shown in Figure 63 (h); 11. It can be used as a negative single pulse Generator (input terminal setting conditions are the same as 9), its equivalent logic diagram is shown in Figure 63 (i); 12. can be used as a low-level Schmitt trigger (input terminal setting conditions are the same as 9), etc. The effect logic diagram is shown in Figure 63 (j). 13. The square wave generator (the square wave square accuracy is called squareness) and the frequency can be adjusted continuously and accurately can be used as the high level timing. CP = L, D = J = K = 0, Co = Ii = h. C = ϊ = L, E = L, R = Φ), and its frequency is determined by the timing high level, timing resistance, and timing capacitor. 14. Multi-vibrator that can control the continuous high-frequency and change the frequency continuously (the setting condition of the input terminal is the same as 13), and its frequency is determined by three of the high-level timing, timing resistance and timing capacitor; Timing high direct Pulse control space (pulse space referred to as pulse space) A constant pulse width (pulse width referred to as pulse width) that varies continuously over a wide range. An intermittent oscillator (the input terminal setting conditions are the same as 13), and its frequency is determined by timing high level, timing The resistance and the timing capacitor are determined. 16. An intermittent oscillator with continuously adjustable pulse width and a continuously adjustable pulse width can be directly controlled by timing high level. The frequency is set by 13 Timing high, timing resistance, timing The three capacitors are determined; 17. The ultra-low frequency pulse oscillator (the input terminal setting conditions are the same as 13) that can directly control the pulse space to continuously change the pulse high level at the timing high level, the timing capacitor C t and the timing resistor R t (pulse The value of air resistance) is large, and its oscillation period continuously changes from 20 seconds to 1 hour. The equivalent logic diagrams of 13, 14, 15, 16, and 17 are shown in Figure 63 (k);
18.可以作上述的、可控的方波发生器( 端接控制信号,其他同 13 );18. Can be used as the above-mentioned, controllable square wave generator (terminated control signal, others are the same as 13);
19.可以作上述的、 可控的多谐振荡器; 20.可以作上述的、 可控的定 脉宽间歇振荡器; 21.可以作上述的、 可控的变脉宽间歇振荡器, 19、 20、 21的输入端设定条件同 18 , 18、 19、 20和 21的等效 逻辑图如图 63 ( I ) 所示; 22.可以作高电平同类或门 ( CP = L 、 19. Can be used as the above-mentioned, controllable multivibrator; 20. Can be used as the above-mentioned, controllable fixed-pulse-width intermittent oscillator; 21. Can be used as above-mentioned, controllable variable-pulse-width intermittent oscillator, 19 The setting conditions of the input terminals of 20, 21 and 18 are the same as the equivalent logic diagrams of 18, 18, 19, 20, and 21, as shown in Figure 63 (I). 22. Can be used as high-level homologous OR gate (CP = L,
D = J = =Φ , E = L 、 Co = ii = h、 i= L 、 R = h ) ; 23.可 以作高电平或非门 (设定条件同 22 ) , 22和 23的等效逻辑图如图 63 ( m )所示; 24.可以作高电平 R S触发器( C P = L 、 D = J = Κ = Φ、 E = h , Co = Ii = = h ) , 其等效逻辑图如图 63 ( n ) 所示; 25.可以作用高电平直接控制暂记时间在大范围内连续变化的 高电平单稳态触发器( CP = L 、 D = J = Κ =Φ . Ε = L , Q ο = I D = J = = Φ, E = L, Co = ii = h, i = L, R = h); 23. Can be used as high-level NOR gate (setting conditions are the same as 22), 22 and 23 are equivalent The logic diagram is shown in Figure 63 (m); 24. Can be used as a high-level RS flip-flop (CP = L, D = J = KK = Φ, E = h, Co = Ii = = h), its equivalent logic The figure is shown in Figure 63 (n); 25. High-level monostable flip-flops (CP = L, D = J = κ = Φ) that can be used to directly control the temporal change of the temporary recording time in a large range. Ε = L, Q ο = I
! = R = h . C = L ) , 其暂记时间由定时高电平、 定时电阻、 定时 电容三者确定, 其等效逻辑图如图 63 ( 0 )所示; 26.可以作用定时 低电平控制暂记时间在大范围内连续变化的高电平单稳态触发器 ! = R = h. C = L), its temporary recording time is determined by the timing high level, timing resistance, and timing capacitor. The equivalent logic diagram is shown in Figure 63 (0); High-level monostable flip-flop with continuous level change in level control
( CP = L 、 D = J = =Φ , E = L , Q0 = Ii = R = h , i= L ), 其暂记时间由定时低电平、 定时电阻、 定时电容三者确定, 其等效逻 辑图如图 63 ( p )所示; 27.可以作高电平施密特触发器(设定条件 同 26 ) , 其逻辑图如图 63 ( q ) 所示, 高电平 C I或记门和上述的 低电平 C I或记门一样, 可以作三种形式的单脉冲发生器及不可控和 可控的多功能脉冲振荡器,这里——从略; 28.可以作 D 触发器( CP 接时钟脉冲、 J = L 、 K = h、 E = h、 Go和 Ji接控制负脉冲、 C (CP = L, D = J = = Φ, E = L, Q 0 = Ii = R = h, i = L), and its temporary time is determined by the timing low level, timing resistance, and timing capacitor. The equivalent logic diagram is shown in Figure 63 (p); 27. Can be used as a high-level Schmitt trigger (setting conditions are the same as 26), the logic diagram is shown in Figure 63 (q), high-level CI or The gate is the same as the low-level CI or gate described above. It can be used as three types of single pulse generators and uncontrollable and controllable multi-function pulse oscillators. Here-omitted; 28. Can be used as a D flip-flop. (CP is connected to the clock pulse, J = L, K = h, E = h, Go and Ji are connected to control the negative pulse, C
= ϊ= L 、 R =Φ ) , 其等效逻辑图如图 63 ( r ) 所示; 29.可以作 J 触发器( D = L 、 CP接时钟脉冲、 E = h、 Co和 ίι接控制负脉 冲、 C = ϊ= L 、 R =Φ ) , 其等效逻辑图如图 63 ( s ) 所示。 = ϊ = L, R = Φ), its equivalent logic diagram is shown in Figure 63 (r); 29. Can be used as a J flip-flop (D = L, CP is connected to the clock pulse, E = h, Co and 接 are connected to control Negative pulse, C = ϊ = L, R = Φ), and its equivalent logic diagram is shown in Figure 63 (s).
1.原技术的 RS触发器、 单稳态触发器、 施密特触发器、 键盘消抖 单元电路、 单脉冲发生器都是用两个与非门或者两个或非门构成, 而 本发明技术是只用一个或型或记门构成。 显然, 本发明或记型记忆电 路具有节约大量元件和连线、 速度高、 功耗低、 可靠性高、 体积小等 优点。 特别是本发明计算机键盘 CM 0 S消抖电路是用一个 CM 0 S单 输入或记门构成, 其所用元件是原技术的 1/3, 其功耗是原技术的 1Λ000。 1. RS triggers, monostable triggers, Schmitt triggers, keyboard anti-shake unit circuits, and single pulse generators of the original technology are all composed of two NAND gates or two NOR gates, and The technology of the present invention is constituted by only one OR pattern or gate. Obviously, the present invention or the memory circuit has the advantages of saving a large number of components and connections, high speed, low power consumption, high reliability, small size, and the like. In particular, the CM 0 S debounce circuit of the computer keyboard of the present invention is constituted by a CM 0 S single input or gate. Its components are 1/3 of the original technology, and its power consumption is 1Λ000 of the original technology.
2.本发明单稳态触发器不仅线路大大简化, 而且十分宝贵的是, 可以用定时电平直接控制暂记时间在原技术暂记时间 1到近 20倍的 范围内连续变化(两者 Rt、 Ct一样) , 暂记时间由定时电平、 定时 电阻、 定时电容三者来确定, 而原技术不能用电平来控制暂记时间长 短, 原技术暂记时间由定时电阻和定时电容两者来确定, 原技术的暂 记时间是本发明技术暂记时间的最小值。 本发明单稳态触发器的暂记 时间是原技术暂记时间的近 20倍(两者 Rt、 Ct一样)。 2. The monostable flip-flop of the present invention not only greatly simplifies the circuit, but also is very valuable. It can use the timing level to directly control the temporary recording time to continuously change within the range of 1 to nearly 20 times of the original technical temporary recording time (both R t Same as C t ), the temporary recording time is determined by the timing level, the timing resistance, and the timing capacitor. The original technology cannot use the level to control the length of the temporary recording time. It is determined by the user that the suspense time of the original technology is the minimum value of the suspense time of the technology of the present invention. The temporary recording time of the monostable flip-flop of the present invention is nearly 20 times that of the original technology (the two R t and C t are the same).
3.本发明脉冲振荡器有两个可贵优点: 一是有多种( 9种)振荡 功能; 二是可用定时高电平直接控制脉空比(脉空比=脉冲空度: 脉 冲宽度)在 0.8到 300多或者 1Λ8到 100多的范围内连续变化, 其频 率由定时高电平、 定时电阻、 定时电容三者确定, 而原脉冲振荡器振 荡功能单一, 不能直接用电平来控制频率变化, 原脉冲振荡器的频率 是由定时电阻和定时电容两者确定。  3. The pulse oscillator of the present invention has two valuable advantages: one is that it has multiple (9 kinds) oscillation functions; the other is that the pulse-to-space ratio can be directly controlled by timing high level (pulse-to-space ratio = pulse-to-space: pulse width) at Continuously change in the range of more than 0.8 to 300 or more than 1Λ8 to 100. The frequency is determined by the timing high level, timing resistance, and timing capacitor. The original pulse oscillator has a single oscillation function, and cannot directly use the level to control the frequency change. The frequency of the original pulse oscillator is determined by both the timing resistor and the timing capacitor.
4.本发明特多功能新器件有两个可贵优点: 一是功能特多, 用途 十分广泛, 对设计、 使用、 维修来说, 十分方便灵活; 二是可以大大 减少集成电路的品种, 深受用户和生产厂家的欢迎。  4. The special multifunctional new device of the present invention has two valuable advantages: one is that it has many functions and is widely used; it is very convenient and flexible for design, use and maintenance; and the other is that it can greatly reduce the variety of integrated circuits and is greatly appreciated. Users and manufacturers are welcome.
5.本发明 B iCM 0 S稳记集成电路有两个突出优点: 一是线路很简 单;二是它具有 CM O S集成电路和 TTL集成电路的优点。 B iC M 0 S 中 TTL的电阻值是 TTL集成电路中电阻值的 6倍到 10倍。  5. The B iCM 0 S stable memory integrated circuit of the present invention has two outstanding advantages: one is that the circuit is very simple; the other is that it has the advantages of a CMOS integrated circuit and a TTL integrated circuit. The resistance value of TTL in B iC M 0 S is 6 to 10 times that of TTL integrated circuit.

Claims

权 利 要 — Rights to —
1. 一种或记型记忆集成电路,其特征在于包括一个或记门和一个 记忆链, 所述或记门包括一个输出端( Q )和多个包括取代输入端1. A NOR memory integrated circuit, comprising a NOR gate and a memory chain, the NOR gate includes an output terminal (Q) and a plurality of replacement input terminals
( r )在内的输入端, 所述记忆链接在或记门的输出端和取代输入端 之间。 (r), the memory link is between the output end of the OR gate and the replacement input end.
2.如权利要求 1的或记型记忆集成电路, 其特征在于所述或记门 是一个或型高电平 I或记门。  A NOR memory integrated circuit according to claim 1, wherein said OR gate is a OR-type high-level I-OR gate.
3.如权利要求 2的或记型记忆集成电路, 其特征在于所述或型高 电平或记门的逻辑功能是 Q = r + T。  A NOR memory integrated circuit according to claim 2, characterized in that the logical function of the NOR high-level OR gate is Q = r + T.
4.如权利要求 3的或记型记忆集成电路, 其特征在于逻辑功能为 4. The OR memory memory integrated circuit according to claim 3, wherein the logic function is
Q = r +丁的或型高电平 I或记门由一个第一反相器( T1 ) , 一个第 二反相器( Τ2 )和一个二极管组成, 所述第一反相器( T1 )的输出 端同时与所述第二反相器( Τ2 )的输入端及所述二极管的正端相连, 所述第二反相器( Τ2 ) 的输出端作为所述或记型记忆集成电路的输 出端, 所述第一反相器( T1 ) 的输入端及所述二极管的负端分别作 为所述或记门的取代输入端和控制输入端。 Q = r + DOR high-level I-OR gate is composed of a first inverter (T1), a second inverter (T2) and a diode, the first inverter (T1) The output terminal of the second inverter (T2) is connected to the positive terminal of the diode and the positive terminal of the diode at the same time, and the output terminal of the second inverter (T2) is used as the The output terminal, the input terminal of the first inverter (T1) and the negative terminal of the diode are used as the replacement input terminal and the control input terminal of the OR gate respectively.
5.如权利要求 1的或记型记忆集成电路, 其特征在于所迷或记门 是一个或型低电平 I或记门。  5. The OR memory memory integrated circuit according to claim 1, wherein the OR memory gate is an OR low-level I memory gate.
6.如权利要求 5的或记型记忆集成电路, 其特征在于所述或型低 电平 I或记门的逻辑功能是 Q = r丁。  6. The NOR memory integrated circuit according to claim 5, characterized in that the logical function of the OR low-level I-OR gate is Q = rding.
7.如权利要求 6的或记型记忆集成电路, 其特征在于逻辑功能为 Q = rT的或记门由一个第一反相器( T1 ) , 一个第二反相器( Τ2 ) 和一个二极管組成, 所述第一反相器( T1 ) 的输出端同时与所述第 二反相器( Τ2 ) 的输入端及所述二极管的负端相连, 所述第二反相 器( Τ2 ) 的输出端作为所述或记型记忆集成电路的输出端, 所述第 一反相器( T1 ) 的输入端及所述二极管的正端分别作为所述或记型 记忆集成电路的取代输入端和控制输入端。  7. The NOR memory integrated circuit according to claim 6, characterized in that the OR gate having a logic function of Q = rT is composed of a first inverter (T1), a second inverter (T2) and a diode. The output terminal of the first inverter (T1) is simultaneously connected to the input terminal of the second inverter (T2) and the negative terminal of the diode, and the output terminal of the second inverter (T2) is The output terminal is used as the output terminal of the OR memory integrated circuit, and the input terminal of the first inverter (T1) and the positive terminal of the diode are used as the replacement input terminal and Control input.
8.如权利要求 1的或记型记忆集成电路, 其特征在于所述或记门 是一个或型低电平 C或记门。  8. The NOR memory integrated circuit according to claim 1, wherein said OR gate is an OR low-level C OR gate.
9.如权利要求 8的或记型记忆集成电路, 其特征在于所述或型低 电平 C或记门是一个与门。  The OR memory IC as claimed in claim 8, characterized in that said OR type low-level C OR gate is an AND gate.
10.如权利要求 9的或记型记忆集成电路,其特征在于所述与门是 1 10. The OR memory integrated circuit according to claim 9, wherein said AND gate is 1
一个 CC4081电路。 One CC4081 circuit.
4  4
1 1.如权利要求 9的或记型记忆集成电路,其特征在于所述与门是 1  1 1. The OR memory integrated circuit according to claim 9, wherein the AND gate is 1
一个: 74LS08电路。 A: 74LS08 circuit.
4  4
12.如权利要求 1的或记型记忆集成电路,其特征在于所述或记门 是一个或型高电平 C或记门。  12. The NOR memory integrated circuit according to claim 1, wherein said OR gate is an OR high-level C OR gate.
1 3.如权利要求 12的或记型记忆集成电路, 其特征在于所述或型 高电平 C或记门是一个或门。  13. The NOR memory integrated circuit according to claim 12, wherein the OR high-level C OR gate is an OR gate.
14.如权利要求 1 3的或记型记忆集成电路, 其特征在于所述或门 1  14. The OR memory memory integrated circuit according to claim 13, characterized in that said OR gate 1
是一个 CC4071电路。 It is a CC4071 circuit.
15.如权利要求 13的或记型记忆集成电路, 其特征在于所述或门 1 15. An OR memory memory integrated circuit according to claim 13, characterized in that said OR gate 1
是一个 ^ 74LS32电路。 Is a ^ 74LS32 circuit.
16.如权利要求 1的或记型记忆集成电路,其特征在于所述或记门 是一个或型低电平或记门。 16. A NOR memory integrated circuit according to claim 1, wherein said OR gate is an OR low-level OR gate.
17.如权利要求 16的或记型记忆集成电路, 其特征在于所述或型  17. The OR memory memory integrated circuit according to claim 16, wherein the OR memory
1  1
低电平或记门是由 ^ 74LS08电路再加上两个肖特基二极管而组成, 所 述两个肖特基二极管的正极对接, 所述两个肖特基二极管的负极分别The low-level OR gate is composed of ^ 74LS08 circuit plus two Schottky diodes, the anodes of the two Schottky diodes are docked, and the anodes of the two Schottky diodes are respectively
1 1
与 ^ 74LS08电路中的肖特基晶体管 T101的基札 电源地电位相接。 It is connected to the ground potential of the Schizaky transistor T101 in the 74LS08 circuit.
18.如权利要求 1的或记型记忆集成电路,其特征在于所述的或记 门为或型高电平或记门。 18. A NOR memory integrated circuit according to claim 1, wherein said NOR gate is an NOR high-level NOR gate.
19.如权利要求 18的或记型记忆集成电路, 其特征在于所述或型 高电平或记门由一个第一反相器( T1 ), 一个第二反相器( T2 )和 至少一个第一二极管和至少一个第二二极管组成, 所述第一反相器的 输入端与所述至少一个第一二极管的正端相连, 所述第一反相器 19. The NOR memory integrated circuit according to claim 18, characterized in that the NOR high-level OR gate comprises a first inverter (T1), a second inverter (T2) and at least one A first diode and at least one second diode, an input terminal of the first inverter is connected to a positive terminal of the at least one first diode, and the first inverter
( T1 )的输出端同时与所述第二反相器( T2 )的输入端及所述至少 一个第二二极管的正端相连, 所述第二反相器( T2 ) 的输出端作为 所述或记型记忆集成电路的输出端, 所述至少一个第一二极管的负端 及所述至少一个第二二极管的负端分别作为所述或记型记忆集成电 路的取代输入端和控制输入端。 The output terminal of (T1) is connected to the input terminal of the second inverter (T2) and the positive terminal of the at least one second diode at the same time, and the output terminal of the second inverter (T2) is used as The output terminal of the OR memory integrated circuit, the negative terminal of the at least one first diode and the negative terminal of the at least one second diode are respectively used as substitute inputs of the OR memory integrated circuit. And control inputs.
20.如权利要求 1的或记型记忆集成电路,其特征在于所述的或记 门为或型 CI或记门。 20. The NOR-type memory integrated circuit according to claim 1, wherein the NOR-type gate is an OR-type CI or NOR gate.
21.如权利要求 20的或记型记忆集成电路, 其特征在于所述的或 型 CI或记门由一个第一反相器( T1 )和一个第二反相器( T2 ) 串 接而组成, 所述第一反相器( T1 )的输入端作为所述或型 CI或记门 的同相输入端( C ) , 所述第二反相器( T2 ) 的输入端作为所述或 型 C I或记门的反相输入端( I ), 所述第二反相器( T2 )的输出端 作为所述或型 CI或记门的输出端( Q )。 21. The OR memory IC according to claim 20, characterized in that the OR CI or OR gate is composed of a first inverter (T1) and a second inverter (T2) connected in series. An input terminal of the first inverter (T1) is used as the in-phase input terminal (C) of the OR type CI or gate, and an input terminal of the second inverter (T2) is used as the OR type CI The inverting input terminal (I) of the OR gate, and the output terminal of the second inverter (T2) serves as the output terminal (Q) of the OR type CI OR gate.
22.如权利要求 1的或记型记忆集成电路,其特征在于所述或记门 是一个单输入端或记门。  22. The NOR memory integrated circuit according to claim 1, wherein said OR gate is a single input terminal or OR gate.
23.如权利要求 22的或记型记忆集成电路, 其特征在于所述单输 入端或记门是一个 CMOS同门。  23. The NOR memory integrated circuit according to claim 22, wherein said single input terminal or NOR gate is a CMOS same gate.
24.如权利要求 23的或记型记忆集成电路, 其特征在于所述 CMOS 同门是由两个 CMOS非门串接而成。  24. The NOR memory integrated circuit of claim 23, wherein the CMOS gate is formed by connecting two CMOS NOT gates in series.
25.如权利要求 1 - 24的任一项的或记型记忆集成电路, 其特征 在于所述记忆链是双值暂记链。  25. The or memory memory integrated circuit according to any one of claims 1 to 24, wherein said memory chain is a double-valued temporary memory chain.
26.如权利要求 25的或记型记忆集成电路, 其特征在于所述双值 暂记链是第一种双值暂记链, 所述第一种双值暂记链由一个定时电平 输入端( Vt ), 一个定时电容( ) , —个第一定时电阻( Rt ) , — 个第二定时电阻( Rt )和一个开关管( So )组成, 其中所述定时电 容( Ct )接在所述或记门的输出端和所述或记门的取代输入端之间, 所述开关管( So )的一端接在某一预定电位, 所述开关管( So )的 另一端通过电阻 Rt接到所述或记门的所述取代输入端, 所述开关管26. The OR memory memory integrated circuit according to claim 25, wherein said double-valued suspense chain is a first type of double-valued suspense chain, and said first type of double-valued suspense chain is input by a timing level Terminal (V t ), a timing capacitor (), a first timing resistor (R t ), a second timing resistor (R t ), and a switching tube (So), wherein the timing capacitor (C t ) Is connected between the output end of the OR gate and the replacement input end of the OR gate, one end of the switch tube (So) is connected to a predetermined potential, and the other end of the switch tube (So) Connected to the replacement input terminal of the OR gate through a resistor R t , the switch tube
( So ) 的所述另一端还通过第一定时电阻( Rt )接到定时电平输入 端( Vt:)。 The other end (So) is further connected to the timing input level (V t :) first through the timing resistor (R t).
27.如权利要求 25的或记型记忆集成电路, 其特征在于所述双值 暂记链是第一种双值暂记链, 所述第一种双值暂记链由一个定时电平 输入端( Vt ), 一个定时电容( Ct ) , 一个第一定时电阻( Rt ), 一 个第二定时电阻( Rt )和一个开关管( So )组成, 其中所述定时电 容( Ct )接在所述或记门的输出端和所述或记门的取代输入端之间, 所述开关管( So )的一端接在某一预定电位, 所述开关管( So )的 另一端通过电阻 Rt接到所述或记门的所述取代输入端,所述或记门的 取代输入端还通过第一定时电阻( Rt )接到定时电平输入端( Vt )。 27. The OR memory memory integrated circuit according to claim 25, wherein said double-valued suspense chain is a first type of double-valued suspense chain, and said first type of double-valued suspense chain is input by a timing level Terminal (V t ), a timing capacitor (C t ), a first timing resistor (R t ), a second timing resistor (R t ), and a switch (So), wherein the timing capacitor (C t ) Is connected between the output end of the OR gate and the replacement input end of the OR gate, one end of the switch tube (So) is connected to a predetermined potential, and the other end of the switch tube (So) t remember the door or to the input terminal through a resistor substituent R, the substituted or write gate input terminal further connected to the timing input level (V t) by a first timing resistor (R t).
28.如权利要求 1 - 15的任一项的或记型记忆集成电路, 其特征 在于所述的记忆链是单值暂记链。  28. The or memory memory integrated circuit according to any one of claims 1 to 15, characterized in that said memory chain is a single-valued temporary memory chain.
29.如权利要求 16的或记型记忆集成电路, 其特征在于所述的记 忆链是单值暂记链。  29. The OR memory memory integrated circuit according to claim 16, wherein said memory chain is a single-valued temporary memory chain.
30.一种如权利要求 29的或记型记忆集成电路, 其特征在于所述 或型低电平或记门包括一个第一抗饱和三极管( ;)和一个第二抗饱 和三极管( T2 ), 一个连在所述第一抗饱和三极管( Τ, )的集电极和 电源( + Vcc )之间的电阻( ) , —个连在所述第二抗饱和三极管 的集电极( T2 )和电源( + Va )之间的电阻( R2 ) , —个正极与第 一抗饱和三极管( T, )的集电极相连、负极与第二抗饱和三极管( T2 ) 的基极相连的二极管( ), 一个正极与第二抗饱和三极管( Τ2 ) 的集电极相连、 负极与第一抗饱和三极管( L )的基极相连的二极管 ( D, ) , 一个正极与第二抗饱和三极管( Τ2 ) 的基极相连、 负极与 J 端相连的二极管( D2 ), 一个正极与第一抗饱和三极管( T, )的基极 相连、 负极与 (:相连的二极管( ) , —个正极与地电位相连、 负极 与 (;端相连的二极管( ) , —个正极与地电位相连、 负极与 .1端相 连的二极管( D2 ) , —个正极同时与第一抗饱和三极管( L ) 的发 射极和第二抗饱和三极管( T2 )的发射极相连、 负极与地电位相连的 二极管( D ) , 其中第二抗饱和三极管( Τ2 ) 的集电极还与 Qs端相 连, 并且 D" D,、 D, 、 D2、 D2、 D2 为肖特基二极管。 30. A NOR memory integrated circuit according to claim 29, wherein said NOR low-level OR gate includes a first anti-saturation transistor (;) and a second anti-saturation transistor. And a transistor (T 2 ), a resistor () connected between a collector of the first anti-saturation transistor (T,) and a power source (+ Vcc), a collector connected to the second anti-saturation transistor The resistance (R 2 ) between the electrode (T 2 ) and the power source (+ Va), one positive electrode is connected to the collector of the first anti-saturation transistor (T,), and the negative electrode is connected to the second anti-saturation transistor (T 2 ). A base-connected diode (), a diode (D,) with a positive electrode connected to the collector of a second anti-saturation transistor (T 2 ), a negative electrode connected to the base of the first anti-saturation transistor (L), and a positive electrode connected to the two anti-saturation transistor base (Τ 2) coupled to the source, the diode (D 2) is connected to the negative terminal of the J, a positive electrode and a first anti-saturation transistor (T,) is connected to the base, and the negative electrode (: a diode connected ( ), A diode with a positive pole connected to the ground potential and a negative pole connected to the (; terminal), a diode with a positive pole connected to the ground potential and a negative pole connected to the .1 terminal (D 2 ), a positive pole connected to the first reactance at the same time Emitter of saturation transistor (L) and second anti-saturation transistor (T 2) connected to the emitter, the diode cathode connected to earth potential (D), wherein the collector of the second anti-saturation transistor (Τ 2) is also connected to terminal Qs, and D "D ,, D,, D 2 , D 2 and D 2 are Schottky diodes.
31.如权利要求 1 7的或记型记忆集成电路, 其特征在于所述的记 忆链是单值暂记链, 且所述或型低电平或记门的同相输入端( C )保 持为高电平, 控制信号由所述或型低电平或记门的反相输入端( I ) 输入。  31. The OR memory memory integrated circuit according to claim 17, characterized in that said memory chain is a single value temporary memory chain, and the in-phase input terminal (C) of the OR low-level or memory gate is maintained as High level, the control signal is input by the inverting input terminal (I) of the OR low level or gate.
32.如权利要求 17的或记型记忆集成电路, 其特征在于所述的记 忆链是单值暂记链, 且所述或型低电平或记门的反相输入端( I )保 持为高电平, 控制信号由所述或型低电平或记门的同相输入端( C ) 输入。  32. The OR memory memory integrated circuit according to claim 17, wherein said memory chain is a single-valued temporary memory chain, and said OR input low-level OR memory gate's inverting input terminal (I) is maintained as High level, the control signal is input from the in-phase input terminal (C) of the OR low level or gate.
33.如权利要求 18 - 21的任一项的或记型记忆集成电路,其特征 在于所述的记忆链为单值暂记链。  33. The or memory memory integrated circuit according to any one of claims 18 to 21, wherein said memory chain is a single-valued temporary memory chain.
34.如权利要求 28 - 33的任一项的或记型记忆集成电路,其特征 在于所述单值暂记链由一个定时电平输入端( Vt ) , —个定时电阻Recordable or any one of IC memory 33, characterized in that said clearing chain is comprised of a single value of a timer input level (V t), - - 34. claimed in claim 28 as a timing resistor
( Rt )和一个定时电容( )組成, 所述定时电容( )接在所述或 记门的输出端和所述或记门的取代端之间, 所述定时电阻( Rt )接在 所述或 "ί己门的所述取代输入端和所述定时电平输入端( Vt )之间。 (Rt) and a timing capacitor (), the timing capacitor () is connected between the output terminal of the OR gate and the replacement terminal of the OR gate, and the timing resistor (R t ) is connected at Between the replacement input terminal of the OR gate and the timing level input terminal (V t ).
35.如权利要求 1 - 1 5 , 18或 1 9的任一项的或记型记忆集成电 路, 其特征在于所述的记忆链是稳记链。  35. The OR memory integrated circuit according to any one of claims 1 to 15, 5, 18 or 19, characterized in that said memory chain is a stable memory chain.
36.如权利要求 16的任一项的或记型记忆集成电路, 其特征在于 所述的记忆链是稳记链。  36. The or memory memory integrated circuit according to claim 16, wherein said memory chain is a stable memory chain.
37.如权利要求 34的或记型记忆集成电路, 其特征在于所述或型 低电平或记门由一个第一反相器( T1 ) , 一个第二反相器( T2 )和 至少一个第一二极管和至少一个第二二极管组成, 所述第一反相器的 输入端与所述至少一个第一二极管的负端相连, 所述第一反相器 ( Tl )的输出端同时与所述第二反相器( T2 )的输入端及所述至少 一个第二二极管的负端相连, 所述第二反相器( T2 ) 的输出端作为 所述或记型记忆集成电路的输出端, 所述至少一个二极管的负端及所 述至少一个第二二极管的正端分別作为所述或记型记忆集成电路的 取代输入端和控制输入端。 37. The NOR memory integrated circuit according to claim 34, characterized in that the NOR low-level OR gate comprises a first inverter (T1), a second inverter (T2) and at least one A first diode and at least one second diode, an input terminal of the first inverter is connected to a negative terminal of the at least one first diode, and the first inverter The output terminal of (Tl) is connected to the input terminal of the second inverter (T2) and the negative terminal of the at least one second diode at the same time, and the output terminal of the second inverter (T2) is used as The output terminal of the OR memory integrated circuit, the negative terminal of the at least one diode and the positive terminal of the at least one second diode are respectively used as a substitute input terminal and a control input of the OR memory integrated circuit. end.
38.如权利要求 37的或记型记忆集成电路, 其特征在于所述的至 少一个第一二极管为一个, 所述的至少一个第二二极管为一个。  38. The or memory memory integrated circuit according to claim 37, wherein said at least one first diode is one and said at least one second diode is one.
39.如权利要求 37的或记型记忆集成电路, 其特征在于所述的至 少一个第一二极管为两个, 所述的至少一个第二二极管为两个。  39. The OR memory memory integrated circuit according to claim 37, wherein said at least one first diode is two and said at least one second diode is two.
40.一种如权利要求 38的或记型记忆集成电路, 还包括一个第一 TTL高电平与非门 ( AN1 )和一个第二 TTL高电平与非门 ( AN2 ), 所述第一 TTL高电平与非门 ( AN1 )的输出端与接在所述第二反相器 40. A NOR memory integrated circuit according to claim 38, further comprising a first TTL high-level NAND gate (AN1) and a second TTL high-level NAND gate (AN2), said first The output terminal of the TTL high-level NAND gate (AN1) is connected to the second inverter
( T2 )输入端的二极管的另一端相连, 所述第二 TTL高电平与非门 ( AN2 ) 与接在第一肖特基晶体管( T1 )输入端的二极管的另一端 相连, 所述第一 TTL高电平与非门 ( AN1 )和所述第二 TTL高电平与 非门 ( AN2 )各有一个输入端接到控制端( CP )上, 所述第一 TTL 高电平与非门 ( AN1 )的另一输入端作为同相输入端( C ) , 所述第 二 TTL高电平与非门 ( AN2 ) 的另一输入端作为反相输入端( I )。 (T2) the other end of the diode of the input terminal is connected, the second TTL high-level NAND gate (AN2) is connected to the other end of the diode connected to the input terminal of the first Schottky transistor (T1), the first TTL Each of the high-level NAND gate (AN1) and the second TTL high-level NAND gate (AN2) has an input terminal connected to the control terminal (CP), and the first TTL high-level NAND gate ( AN1) has another input terminal as a non-inverting input terminal (C), and the other input terminal of the second TTL high-level NAND gate (AN2) serves as an inverting input terminal (I).
41.把如权利要求 38的或记型记忆集成电路用于 BiCMOS新 D触发 器、 Bi CMOS新 JK触发器、 BiCMOS新计数器和 B i CMOS新寄存器的全 记电路, 而其中的一次半记电路或者输入端信号的控制电路是 TTL电 路。  41. A full memory circuit using the OR memory memory integrated circuit as claimed in claim 38 for a BiCMOS new D flip-flop, a Bi CMOS new JK flip-flop, a BiCMOS new counter and a new Bi CMOS new register, and one of the half-write circuits Or the control circuit of the input signal is a TTL circuit.
42.如权利要求 1 7的或记型记忆集成电路, 其特征在于所述的记 忆链是稳记链。  42. The OR memory memory integrated circuit according to claim 17, wherein said memory chain is a stable memory chain.
44.将如权利要求 42或 43的任一项的或记型记忆集成电路用作新 D稳记器(新 D触发器)、 新 JK稳记器(新 JK触发器)、 新计数器、 新寄存器、 新移位寄存器的输出端全记电路。  44. Use of the OR memory integrated circuit as claimed in any one of claims 42 or 43 as a new D register (new D trigger), a new JK register (new JK trigger), a new counter, new The register and the output of the new shift register are all written in the circuit.
45.如权利要求 20或 21的任一项的或记型记忆集成电路,其特征 在于所述的记忆链为稳记链。  45. The or memory memory integrated circuit according to any one of claims 20 or 21, wherein said memory chain is a stable memory chain.
46.一种用权利要求 45的或记型记忆集成电路构成的键盘消抖单 元电路, 其特征在于包括一个二极管和一个单刀双掷开关, 二极管的 负端接地、 二极管的正端接单刀双掷开关的固定点, 单刀双掷开关可 响应操作而接到所述权利要求 38的或记型记忆集成电路的同相输入 端( C )或反相输入端( I )。  46. A keyboard anti-shake unit circuit composed of a memory or memory integrated circuit according to claim 45, comprising a diode and a single-pole double-throw switch, the negative terminal of the diode is grounded, and the positive terminal of the diode is connected to the single-pole double-pole. The fixed point of the throw switch can be connected to the non-inverting input terminal (C) or the inverting input terminal (I) of the memory integrated circuit of claim 38 in response to the operation.
47.如权利要求 46的键盘消抖单元电路, 其特征在于所述的或记 型记忆集成电路也可以是 NM0S或 LSTTL或记型记忆集成电路。  47. The keyboard anti-shake unit circuit according to claim 46, characterized in that said OR memory integrated circuit can also be NMOS or LSTTL or memory integrated circuit.
48.如权利要求 22 - 24的任一项的或记型记忆集成电路,其特征 在于所述的记忆链为稳记链。 48. The or memory memory integrated circuit according to any one of claims 22 to 24, wherein said memory chain is a stable memory chain.
49.一种用权利要求 48的或记型记忆集成电路构成的静态存储单 元, 其特征在于在所述的或记型记忆集成电路的输入端通过串联的一 个第一开关管( Π )和一个第二开关管( K2 )与数据线( D )相连, 其中所述第一开关管( K1 )和所述第二开关管 K2分别由行逸信号和 列选信号控制。 49. A static memory unit composed of the CMOS memory integrated circuit according to claim 48, characterized in that an input terminal of the CMOS memory integrated circuit is connected in series by a first switching tube (Π) and a The second switch tube (K2) is connected to the data line (D), wherein the first switch tube (K1) and the second switch tube K2 are controlled by a row escape signal and a column selection signal, respectively.
50.—种如权利要求 35, 36 , 42 , 45或 48的任一条的或记型 记忆集成电路, 其中所述的稳记链为一条导电连线。  50. A NAND memory integrated circuit according to any one of claims 35, 36, 42, 45 or 48, wherein said stable chain is a conductive connection.
51.如权利要求 19的或记型记忆集成电路, 其特征在于所述的至 少一个第一二极管为一个, 所述的至少一个第二二极管为一个。  51. The or memory memory integrated circuit according to claim 19, wherein said at least one first diode is one and said at least one second diode is one.
52.如权利要求 51的或记型记忆集成电路, 其特征在于所述的记 忆链为稳记链。  52. The OR memory integrated circuit according to claim 51, wherein said memory chain is a stable memory chain.
53.一种用权利要求 52 的或记型记忆集成电路构成的计算机键 盘消抖单元电路, 其特征在于所述或记型记忆集成电路的反相输入端 I接在按键开关的常闭触点端, 所述或记型记忆集成电路的同类输入 端 C接在按键开关的常开触点端, 按键开关公共端接电源电压 + VDD„ 53. A computer keyboard anti-shake unit circuit composed of the memory IC of claim 52, characterized in that the inverting input terminal I of the memory IC is connected to a normally closed contact of a key switch Terminal, the same input terminal C of the said memory integrated circuit is connected to the normally open contact terminal of the key switch, and the common terminal of the key switch is connected to the power supply voltage + VDD „
54.一种具有特多功能的 CMOS基本新器件, 由双值信号输入电 路、 一次半记电路、 两种电平信号的扩展或记门这三部分组成, 其 中输入端有!^。,^,。,^ ^,。?^,】,!^ , 输出端有输出端 Q 、 反 相输出端 Q 、漏极反相输出端 Q Q D, r端作或记型记忆路时作取代输 入端用, C。低电平信号的或记型记忆电路时作同类输入端用或者作 D 触发器和 JK 触发器时作直接置 0端用, 1!作低电平信号的或记型 记忆电路时作反相输入端或者作 D触发器和 JK 触发器时作直接置 1 端用, C和 I作高电平信号的或记型记忆电路时作同类输入端和反相 输入端用, E为控制 C M 0 S双向模拟开关接通或者断开的控制信号 输入端, C P为时钟脉冲输入端, D为!) 触发器的输入端, J、 为 JK 触发器的输入端。 54. A basic new CMOS device with special multi-function, consisting of three parts: a double-valued signal input circuit, a once-and-a-half circuit, and a two-level signal extension or gate. The input terminal has it! ^. , ^,. , ^ ^ ,. ? ^,],! ^, The output terminal has an output terminal Q, an inverting output terminal Q, a drain inverting output terminal QQD , and the r terminal is used instead of the input terminal when used as a memory circuit, C. Low-level signal or memory circuit is used as a similar input terminal or D flip-flop and JK flip-flop are directly set to 0, 1! For low-level signal or memory circuit, it is inverted The input terminal can be directly set to 1 when used as D flip-flop and JK flip-flop. When C and I are used as high-level signal or memory circuit, it can be used as similar input and inverting input. S Two-way analog switch control signal input terminal on or off, CP is the clock pulse input terminal, D is! ) The input of the trigger, J, is the input of the JK trigger.
55.一种具有特多功能的 LSTTL基本新器件, 由双值信号输入电 路、 一次半记电路、 两种电平信号的扩展或记门这三部分组成, 其 中输入端有 r, C。, ^ C , I,R , E,C P,D , J,K , 输出端有输出端 Q 、 反 相输出端 Q 、集电极反相输出端 Q o c , r端作或记型记忆路时作取代 输入端用, C 0作低电平信号的或记型记忆电路时作同类输入端用或 者作 D触发器和 JK 触发器时作直接置 0端用, 1,作低电平信号的或 记型记忆电路时作反相输入端或者作!)触发器和 JK 触发器时作直接 置 1端用, C和 I作高电平信号的或记型记忆电路时作同类输入端和 反相输入端用, E为控制 C M O S双向模拟开关接通或者断开的控制 信号输入端, CP为时钟脉冲输入端, D为 D触发器的输入端, J、55. A basic new LSTTL device with special multi-function, consisting of a three-valued signal input circuit, one-and-a-half-time circuit, and two-level signal extension or gate. The input terminals have r and C. ^ C, I, R, E, CP, D, J, K, the output terminal has an output terminal Q, an inverting output terminal Q, a collector inverting output terminal Q oc, and r is used as a memory circuit. Instead of the input terminal, C 0 is used as a low-level signal or a memory circuit of the same type or used as a D flip-flop and a JK flip-flop. Inverted input terminal for memory circuit or as direct input terminal for flip-flops and JK flip-flops, and C and I for high-level signal or for inverting input circuit of memory circuit For the input terminal, E is for controlling the on / off control of the CMOS bidirectional analog switch Signal input, CP is the clock pulse input, D is the input of D flip-flop, J,
K 为 JK 触发器的输入端, Vb在所述 LSTTL作压控脉冲振荡器时作 控制电压的输入端用。 K is the input terminal of the JK flip-flop, and Vb is used as the input terminal of the control voltage when the LSTTL is used as a voltage-controlled pulse oscillator.
PCT/CN1997/000138 1996-12-06 1997-12-03 An or-type memorizing integrated circuit WO1998025344A1 (en)

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EP0023127A1 (en) * 1979-07-19 1981-01-28 Fujitsu Limited CMOS Schmitt-trigger circuit
EP0176211A1 (en) * 1984-08-14 1986-04-02 BRITISH TELECOMMUNICATIONS public limited company CMOS Schmitt trigger

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Publication number Priority date Publication date Assignee Title
EP0023127A1 (en) * 1979-07-19 1981-01-28 Fujitsu Limited CMOS Schmitt-trigger circuit
EP0176211A1 (en) * 1984-08-14 1986-04-02 BRITISH TELECOMMUNICATIONS public limited company CMOS Schmitt trigger

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