CN1649142A - Static discharging protectire circuit and static discharging protective method - Google Patents

Static discharging protectire circuit and static discharging protective method Download PDF

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Publication number
CN1649142A
CN1649142A CN 200410039312 CN200410039312A CN1649142A CN 1649142 A CN1649142 A CN 1649142A CN 200410039312 CN200410039312 CN 200410039312 CN 200410039312 A CN200410039312 A CN 200410039312A CN 1649142 A CN1649142 A CN 1649142A
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silicon controlled
controlled rectifier
circuit
electrostatic discharge
transistor
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陈子平
张智毅
柯明道
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Priority to CN 200410039312 priority Critical patent/CN1649142A/en
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Abstract

This invention provides a static discharge protection circuit including a silicon controlled rectifier having a first dope-like matrix, a second dope-like semiconductor trap formed on the matrix, a first diffusion zone formed in the trap and a second dope-like second diffusion zone formed outside of the trap, a control circuit connected with the rectifier providing a first sustain voltage to the rectifier at the first state period, so that it's not locked, a second sustain voltage is provided to the rectifier at the second state period to keep it locked, the first sustain voltage is different from the second.

Description

Electrostatic storage deflection (ESD) protection circuit and electrostatic charge protection method
Technical field
The present invention relates to semiconductor subassembly, be particularly to can not take place during a kind of and the normal running static discharge (the Electrostatic Discharge of bolt-lock (latch-up); ESD) protection circuit.
Background technology
Semiconductor integrated circuit (IC) for example has high-order total oxygen half (MOS) transistorized IC, generally is subjected to the influence of Electrostatic Discharge all easily and goes to pot or damage.The high-order MOS transistor has traditionally such as short channel length, characteristics such as low critical voltage and thin grid oxide layer.These have the MOS transistor of lightly doped drain (LDD) structure and silicide blind zone with half (CMOS) the processing procedure manufacturing of the complementary total oxygen of deep-sub-micrometer, and the easier ESD of suffering destroys.
ESD is meant the electric current that has the plus or minus electric charge that flow to IC in short moment in a large number.The source of this big electric current has multiple, and for example human body and machine discharge is called human body discharging model (HBM) and machine discharging model (MM).IC is subjected to the destruction of HBM and MM easily during making, transmit or handling.
Known ESD safeguard structure with the manufacturing of CMOS processing procedure generally comprises NMOS/PMOS transistor, silicon controlled rectifier (SCR), diode, resistor, thick oxide layer assembly (FOD) and parasitic formula vertical/horizontal two-carrier junction transistor (BJT).In these known ESD safeguard structures, SCR for example hangs down and keeps voltage, and can bear higher ESD electric current under less layout area owing to self character.Yet the voltage of keeping that the general CMOS processing procedure of making SCR may be used than SCR is high supply voltage.For example, the voltage of keeping of known SCR generally is about 1 volt, and supply voltage then is 2.7 to 5 volts.As a result, possibly can't close by caused SCR bolt-lock of ESD or the instantaneous bolt-lock of SCR.In addition, SCR forms bolt-lock or instantaneous bolt-lock easily because of noises such as surging or electrophoresis during normal running.In case the SCR bolt-lock occurs, then the IC that SCR protected thus can't normal running, even is damaged during normal running.
Existing various technology is used for preventing that SCR from bolt-lock taking place during normal running.The example that is shown in Figure 1.Fig. 1 is a United States Patent (USP) the 6th, 031, the Fig. 4 of No. 405 (calling patent in the following text No. 405).No. 405 patent system gives people such as Yu, and its denomination of invention is " the ESD protection circuit of bolt-lock can not take place during the normal running ".No. 405 patent take off is a kind of ESD protection circuit that contains a SCR and an ON/OFF controller.This SCR is connected between an IC pad and the earth terminal to form an ESD path.The ON/OFF controller then is connected to the negative electrode of SCR.During normal running, even noise jamming occurs, the ON/OFF controller opens circuit this ESD path to prevent bolt-lock.
Yet, the ESD electric current SCR that not only flows through, switching transistor M1 also flows through.In view of this, the ON/OFF controller must be done to such an extent that enough pass through for the big electric current of ESD greatly.Must take than the transistor M1 of wafer dimensioned area with regard to undersized ESD guard assembly demand now, not only uneconomical, and also impracticable.
Shown in Figure 2 then is another prior art.Fig. 2 is a United States Patent (USP) the 6th, 172, Fig. 4 a of No. 404 (calling patent in the following text No. 404).No. 404 patent is given people such as Chen, and its denomination of invention is " can adjust the SCR ESD protection of keeping voltage ".No. 404 patent discloses a kind of SCR, and it has a n + District 40 is in the N of this SCR well region.Resistance 50 is formed at parasitic transistorized base stage of formula two-carrier of pnp and n +Between the district 40.Resistance 50 can make more that multiple current passes through, thereby makes this pnp two-carrier transistor be difficult to open.The result increases the voltage of keeping of this SCR.The size of keeping voltage depends on n +The position of district 40 in the N well region.
Though No. 404 patents can be promoted to the voltage of keeping of SCR to exceed supply voltage V DdThe position accurate, in case but this kind keep voltage and determine then can't add adjustment again.Have that this fixes, the SCR of high maintenance voltage can't bear big ESD electric current.In addition, constant down in other condition, the low SCR person who keeps voltage of the heat that SCR produced of high maintenance voltage is many.In addition, the SCR of high maintenance voltage is clamped to ESD than supply voltage V usually DdHigher voltage level so may destroy internal circuit.
Summary of the invention
Therefore, the present invention is relevant a kind of ESD protection circuit, can overcome the restriction of above-mentioned Prior Art or the problems that shortcoming is derived.
For reaching above-mentioned purpose, the invention provides a kind of integrated circuit of electrostatic discharge protective, comprise a silicon controlled rectifier (SCR), an and control circuit that is connected to SCR, during first situation, provide first of SCR to keep voltage so that the unlikely bolt-lock of SCR, and during second situation, provide second of SCR to keep voltage so that SCR remains in the bolt-lock state, wherein first keep voltage and be different from second and keep voltage.
In the present invention, SCR comprises a parasitic two-carrier transistor and a dead resistance that is connected between transistorized base stage of this parasitism two-carrier and emitter-base bandgap grading, and control circuit system is in parallel with dead resistance.
In the present invention, control circuit presents the resistance less than this dead resistance during first situation, and presents the resistance greater than this dead resistance during second situation.
The present invention also provides a kind of integrated circuit of electrostatic discharge protective, comprise the SCR that a MOS triggers, it comprises a silicon controlled rectifier (SCR) and and is connected to SCR golden oxygen half (MOS) transistor to trigger this SCR, an and control circuit, it is connected to SCR that MOS triggers to provide one first to keep SCR that voltage triggers to MOS so that the unlikely bolt-lock of SCR that MOS triggers during first situation, and during second situation, provide one second to keep SCR that voltage triggers to MOS so that the SCR that MOS triggers remains in the bolt-lock state, wherein first keep voltage and be different from second and keep voltage.
In the present invention, control circuit comprises a capacitor, and the one end is connected to the part ESD voltage of a contact pins with this contact pins that is coupled.
The present invention also provides a kind of integrated circuit of electrostatic discharge protective, comprise a silicon controlled rectifier (SCR), it has the matrix of one first doping type, one is formed in the matrix and is the semiconductor well region of second doping type, one is formed in the semiconductor well region and is first diffusion region of first doping type, and one be formed at the outer of semiconductor well region and be second diffusion region of second doping type, an and control circuit, its be connected to SCR with during first situation, provide one first keep voltage to SCR so that the unlikely bolt-lock of SCR, and during second situation, provide one second keep voltage to SCR so that SCR keeps the bolt-lock state, wherein first keep voltage and be different from second and keep voltage.
The present invention also provides a kind of static discharge about means of defence in addition, comprise and provide to have first silicon controlled rectifier (SCR) of keeping voltage, and the voltage of keeping of control SCR makes it be higher than a supply voltage so that the unlikely bolt-lock of SCR during first situation, and the voltage of keeping of control SCR makes it be lower than supply voltage so that SCR remains in the bolt-lock state during second situation.
In the present invention, other comprises SCR is connected between one first power circuit and the second source circuit.
The invention provides a kind of integrated circuit of electrostatic discharge protective, comprise a silicon controlled rectifier (SCR); The first transistor of one first conductivity type, one-body molded with SCR, have a first grid; The transistor seconds of one second conductivity type, one-body molded with SCR, have a second grid; And control circuit, in response in first voltage that is applied to first and second grid, provide one first keep voltage to SCR so that the unlikely bolt-lock of SCR, and in response in second voltage that is applied to first and second grid, provide one second keep voltage to SCR so that SCR remains in the bolt-lock state.
The present invention also provides a kind of integrated circuit of electrostatic discharge protective, comprises a silicon controlled rectifier (SCR); One and the integrated p transistor npn npn of SCR; One and the integrated n transistor npn npn of SCR; A control circuit that is connected to p type and n transistor npn npn, its provide one first voltage to SCR so that the unlikely bolt-lock of SCR, and provide one second voltage to SCR so that SCR remains in the bolt-lock state.
The present invention also provides a kind of integrated circuit of Electrostatic Discharge protection, comprises first power circuit with first voltage level; Second source circuit with second voltage level; A plurality of contact pins; A plurality of silicon controlled rectifiers (SCR), each SCR all comprise a p transistor npn npn and a n transistor npn npn, and this p type and n transistor npn npn and SCR are one-body molded; And control circuit, via p type and n transistor npn npn provide one first keep voltage to these SCR so that the unlikely bolt-lock of these SCR, and via p type and n transistor npn npn provide one second keep voltage to these SCR so that these SCR remain in the bolt-lock state in during esd pulse appears at one ESD of first power circuit or contact pins.
The present invention also provides a kind of method of electrostatic discharge protective, and comprising provides to have a silicon controlled rectifier (SCR) of keeping voltage; The first transistor and the SCR of one first conductivity type is one-body molded, and the first transistor has a first grid; The transistor seconds and the SCR of one second conductivity type is one-body molded, and transistor seconds has a second grid; What provide that one first signal to first and second grid improves SCR keeps voltage so that the unlikely bolt-lock of SCR; And provide that a secondary signal to first and second grid reduces SCR keep voltage so that SCR remains in the bolt-lock state.
A kind of method that provides Electrostatic Discharge to protect to internal circuit also is provided in addition in the present invention, and first power circuit that provides to have first voltage level is provided; Second source circuit with second voltage level is provided; A plurality of contact pins are provided; A plurality of silicon controlled rectifiers (SCR) are provided, and each SCR all comprises a p transistor npn npn and a n transistor npn npn, and this p type and n transistor npn npn and SCR are one-body molded; Via p type and n transistor npn npn provide one first keep voltage to these SCR so that the unlikely bolt-lock of these SCR; And via p type and n transistor npn npn provide one second keep voltage to these SCR so that these SCR remain in the bolt-lock state in during esd pulse appears at one ESD of first power circuit or contact pins.
Description of drawings
Fig. 1 is the circuit diagram of known ESD guard assembly;
Fig. 2 is the cutaway view of another known ESD guard assembly;
Fig. 3 is the SCR of the embodiment of the invention and the circuit diagram of control circuit;
Fig. 4 is the I-V curve chart of circuit shown in Figure 3;
Fig. 5 is the layout cutaway view of ESD protection circuit;
Fig. 6 is the layout cutaway view of another ESD protection circuit;
Fig. 7 is the SCR of another embodiment of the present invention and the circuit diagram of control circuit;
Fig. 8 is the layout of the ESD protection circuit of the embodiment of the invention;
Fig. 9 is the layout of another ESD protection circuit;
Figure 10 is the ESD protection circuit of the embodiment of the invention;
Figure 11 is another ESD protection circuit of the embodiment of the invention;
Figure 12 is the input ESD protection circuit of the embodiment of the invention;
Figure 13 is another input ESD protection circuit of the embodiment of the invention;
Figure 14 is the output ESD protection circuit of the embodiment of the invention;
Figure 15 is another output ESD protection circuit of the embodiment of the invention;
Figure 16 exports the protection circuit into ESD for the mixed pressure power supply of the embodiment of the invention;
Figure 17 is the mixed pressure power supply ESD protection circuit schematic diagram of the embodiment of the invention;
Figure 18 is the mixed pressure power supply ESD protection circuit that the use NMOS of the embodiment of the invention triggers SCR;
Figure 19 is the mixed pressure power supply ESD protection circuit that the use PMOS of one embodiment of the invention triggers SCR;
Figure 20 A is the cutaway view of the SCR of the embodiment of the invention;
Figure 20 B is the control circuit of the embodiment of the invention;
Figure 21 is the ESD protection circuit of another embodiment of the present invention;
Figure 22 is the ESD protection circuit of further embodiment of this invention;
Figure 23 is the ESD protection circuit of yet another embodiment of the invention.
Embodiment
The invention provides a kind of ESD protection circuit, it has the control circuit that a silicon controlled rectifier (SCR) and is connected to SCR, make the unlikely bolt-lock of SCR during first situation, to provide first of SCR to keep voltage, and during second situation, provide second of SCR to keep voltage to make SCR be the bolt-lock state.That is the voltage of keeping of SCR is adjustable.Concrete, the voltage of keeping of SCR is promoted to and is higher than first of supply voltage and keeps voltage, so that SCR unlikely bolt-lock during normal running, and with the value that voltage is brought down below supply voltage of keeping of SCR, so that SCR keeps bolt-lock during ESD.
Fig. 3 is the SCR 60 of one embodiment of the invention and the circuit diagram of control circuit 74.See also Fig. 3, SCR 60 comprises parasitic formula pnp two-carrier transistor 62, one a parasitic formula npn two-carrier transistor 64, a N well region resistance 66, a matrix resistance 68 (R Sub) and be formed at dead resistance 70 (R between the parasitic formula transistor 62,64 S1) and 72 (R S2).SCR 60 keeps voltage V HBe meant the pressure drop of 78 on the anode 76 of SCR 60 and negative electrode.Control circuit 74 has the resistance of a R in this circuit.Resistance R and matrix resistance R with control circuit 74 SubParallel connection, V HCan represent by following formula:
V HV cep+V ben×[1+R S2/(R sub//R)]
V wherein CepBe the collection utmost point of pnp transistor 62 and the voltage between emitter-base bandgap grading, V BenBe the base stage of npn transistor 64 and the voltage between emitter-base bandgap grading.Therefore, when R much smaller than R SubThe time, V HValue rises, if R is much larger than R SubV then HValue descend.
Fig. 4 is the I-V characteristic curve of SCR 60 shown in Figure 3.SCR 60 has the voltage of keeping V HAnd trigger voltage V TrigSee also Fig. 4, V HCan be at V H1With V H2Between do dynamic adjustment.If R is much smaller than R Sub, then the I-V curve of SCR 60 is a curve A.If R is much larger than R Sub, then the I-V curve of SCR 60 is a curve B.That is by changing and the matrix resistance R SubAnd the resistance of the R that connects, can be with SCR 60 keep voltage V HBring up to than supply voltage V DdBig V H2, or with V HDowngrade and compare V DdLittle V H1In one embodiment, V H1Approximate V greatly HAnd in another embodiment, V H1Be about 1 volt.
Fig. 5 is the layout profile of the ESD protection circuit 82 of one embodiment of the invention.See also Fig. 5, ESD protection circuit 82 comprises SCR 84 and control circuit 86.SCR 84 has a p mold base 88, n well region 90, be formed at a p type diffusion region 92, part in the n well region 90 is formed at the 2nd p type diffusion region 94 in the n well region 90 and part and is formed at a n type diffusion region 96 in another n well region 98.The one p type diffusion region 92, n well region 90 are respectively the transistorized emitter-base bandgap grading of parasitic pnp two-carrier, base stage and the collection utmost point with p mold base 88.N well region 90, p mold base 88 and 96 of p type diffusion regions are respectively the transistorized collection utmost point of parasitic npn, base stage and emitter-base bandgap grading.SCR 84 also comprises a grid 100 that is positioned at channel top, and this channel then is formed between first and second p type diffusion region 92,94.Thick oxide layer 102 is used for doing the usefulness of electric insulation.The one p type district 92, grid 100 and the 2nd n type district 104 are connected to contact pins 108, for example are that (I/O) pad is gone in output.The one n type district 96 and the 3rd p type district 106 are connected to a reference voltage such as V SsOr ground connection.
Control circuit 86 comprises nmos pass transistor 107, resistance 110 and electric capacity 112.Nmos pass transistor 107 has a drain electrode that is connected to the 2nd p type diffusion region 94 of SCR 84.One end of resistance 110 is connected to the grid of electric capacity 112 and nmos pass transistor 107, and the other end then is connected to supply voltage V DdOne end of electric capacity 112 is connected to the grid of resistance 110 and nmos pass transistor 107, and the other end then is connected to V SsIn the ESD protection circuit 82, control circuit 86 has the resistance less than the matrix resistance of SCR 84 when nmos pass transistor 107 is opened, and has the resistance greater than the matrix resistance of SCR 84 when nmos pass transistor 107 is closed.
During normal running, the RC circuit of forming by resistance 110 and electric capacity 112 provide a high levels signal to nmos pass transistor 107 grid and start nmos pass transistor 107.As a result, the resistance that presents of control circuit 86 is little than the matrix resistance of SCR 84.The voltage of keeping of SCR 84 is increased to and is higher than V DdThe position accurate, make SCR 84 unlikely bolt-locks.
During ESD, the RC circuit provide a low level signal to nmos pass transistor 107 grid and close nmos pass transistor 107.As a result, the resistance that presents of control circuit 86 than the matrix resistance of SCR 84 for big.The voltage of keeping of SCR 84 downgrades less than V DdThe position accurate, for example about 1 volt, make SCR 84 remain in the bolt-lock state with discharging ESD electric current.For making the RC circuit that the grid of nmos pass transistor 107 is remained in low-voltage position standard when ESD takes place, the RC time delay of RC circuit be set at about 300 how second (ns) how second to 500, the 150ns to 300ns of general esd pulse is for long.
Fig. 6 is another ESD protection circuit 114 of the embodiment of the invention.See also Fig. 6, ESD protection circuit 114 has SCR 84 and control circuit 116.Control circuit comprises PMOS transistor 118, inverter 124, diode 126, resistance 120 and electric capacity 122.PMOS transistor 118 has one source pole and is connected to SCR 84 the 2nd p type diffusion region 94.Inverter 124 has the grid that an output is connected to PMOS transistor 118.One end of resistance 110 is connected to an input of electric capacity 122 and inverter 124, and the other end then is connected to V DdOne end of electric capacity 122 is connected to the input of resistance 120 and inverter 124, and the other end then is connected to V SsIn the ESD protection circuit 114, control circuit 116 presents the resistance less than the matrix resistance of SCR 84 when PMOS transistor 118 is opened, and presents the resistance greater than the matrix resistance of SCR 84 when PMOS transistor 118 is closed.
During normal running, the RC circuit of forming by resistance 120 and electric capacity 122 via inverter 124 provide a low level signal to PMOS transistor 118 grid and start PMOS transistor 118.As a result, the resistance that presents of control circuit 116 is little than the matrix resistance of SCR 84.The voltage of keeping of SCR 84 is increased to and is higher than V DdThe position accurate, make SCR 84 unlikely bolt-locks.
During ESD, because time delay, the RC circuit keeps the input of inverter 124 in low-voltage position standard.Simultaneously, make inverter 124 outputs one high voltage level close PMOS transistor 118 from the part ESD voltage of contact pins 108 to inverter 124 bias voltages to the grid of PMOS transistor 118.As a result, the resistance that presents of control circuit 116 than the matrix resistance of SCR 84 for big.The voltage of keeping of SCR 84 downgrades less than V DdThe position accurate, for example about 1 volt, make SCR 84 remain in the bolt-lock state with discharging ESD electric current.
Fig. 7 is the SCR 128 of the embodiment of the invention and the circuit diagram of control circuit 130.See also Fig. 7, SCR 128 comprises parasitic formula pnp two-carrier transistor 132, one a parasitic formula npn two-carrier transistor 134, a N well region resistance 136 or a R NW, a matrix resistance 138 and be formed at dead resistance 140 (R between the parasitic formula transistor 132,134 S3) and 142 (R S4).SCR 128 keeps voltage V hBe meant the pressure drop of 148 on the anode 146 of SCR 128 and negative electrode.Control circuit 130 has a R in this circuit " resistance.Resistance R with control circuit 130 " and the matrix resistance R NWParallel connection, SCR 128 keeps voltage V hCan represent by following formula:
V hV cen+V bep×[1+R S3/(R NW//R”)]
V wherein CenBe the collection utmost point of npn transistor 134 and the voltage between emitter-base bandgap grading, R S3For being formed at the dead resistance between the parasitic formula transistor 132,134, V BepBe the base stage of pnp transistor 132 and the voltage between emitter-base bandgap grading.Therefore, work as R " less than R NWThe time, V hValue rises, if R " greater than R NWV then hValue descend.The I-V characteristic curve of Fig. 7 is similar to Fig. 4 person, does not therefore add description in addition.
Fig. 8 is the ESD protection circuit 150 of the embodiment of the invention.See also Fig. 8, ESD protection circuit 150 comprises SCR 128 and control circuit 130.SCR 128 has a p mold base 152, n well region 154, be formed at a p type diffusion region 156, part in the n well region 154 is formed at a n type diffusion region 158 in the n well region 154 and part and is formed at the 2nd n type diffusion region 160 in another n well region 162.The one p type diffusion region 156, n well region 154 are respectively the transistorized emitter-base bandgap grading of parasitic pnp two-carrier, base stage and the collection utmost point with p mold base 152.N well region 154, p mold base 152 and the 2nd 160 of n type diffusion regions are respectively the transistorized collection utmost point of parasitic npn, base stage and emitter-base bandgap grading.SCR 128 also comprises a grid 164 that is positioned at channel top, and this channel then is formed between first and second n type diffusion region 158,160.The one p type district 156 and the 3rd n type district 168 are connected to contact pins 170.The 2nd n type district 160 and the 2nd 172 in p type district are connected to V Ss
Control circuit 130 comprises PMOS transistor 174, inverter 176, diode 178, resistance 180 and electric capacity 182.PMOS transistor 174 has a drain electrode that is connected to the n type diffusion region 158 of SCR 128.Inverter 176 has the grid that an output (not label) is connected to PMOS transistor 174.One end of resistance 180 is connected to the input of electric capacity 182 and inverter 176, and the other end then is connected to diode 178 and V DdOne end of electric capacity 182 is connected to the input of resistance 180 and inverter 176, and the other end then is connected to V SsIn the ESD protection circuit 150, control circuit 130 has the resistance less than the n well region resistance of SCR 128 when PMOS transistor 174 is opened, and has the resistance greater than the n well region resistance of SCR 128 when PMOS transistor 174 is closed.
During normal running, the RC circuit of forming by resistance 180 and electric capacity 182 via inverter 176 provide a low level signal to PMOS transistor 174 grid and start PMOS transistor 174.As a result, the resistance that control circuit 130 presents is little than the n well region resistance of SCR 128, and the voltage of keeping of SCR 128 is increased to and is higher than V DdThe position accurate, make SCR 128 unlikely bolt-locks.
During ESD, because time delay, the RC circuit keeps the input of inverter 176 in low-voltage position standard.Simultaneously, make inverter 176 outputs one high voltage level close PMOS transistor 174 from the part ESD voltage of contact pins 170 to inverter 176 bias voltages to the grid of PMOS transistor 174.As a result, the resistance that presents of control circuit 130 than the n well region resistance of SCR 128 for big.The voltage of keeping of SCR 128 downgrades less than V DdThe position accurate, for example about 1 volt, make SCR 128 remain in the bolt-lock state with discharging ESD electric current.
Fig. 9 is the ESD protection circuit 184 of the embodiment of the invention.See also Fig. 9, ESD protection circuit 184 comprises SCR 128 and control circuit 186.Control circuit 186 comprises nmos pass transistor 188, resistance 190 and electric capacity 192.Nmos pass transistor 188 has a source electrode that is connected to the n type diffusion region 158 of SCR 128.One end of resistance 190 is connected to the grid of electric capacity 192 and nmos pass transistor 188, and the other end then is connected to supply voltage V DdOne end of electric capacity 192 is connected to the grid of resistance 190 and nmos pass transistor 188, and the other end then is connected to V SsIn the ESD protection circuit 184, control circuit 186 has the resistance less than the n well region resistance of SCR 128 when nmos pass transistor 188 is opened, and has the resistance greater than the n well region resistance of SCR 128 when nmos pass transistor 188 is closed.
During normal running, the RC circuit of forming by resistance 190 and electric capacity 192 provide a high levels signal to nmos pass transistor 188 grid and start nmos pass transistor 188.As a result, the resistance that presents of control circuit 186 is little than the n well region resistance of SCR 128.The voltage of keeping of SCR 128 is increased to and is higher than V DdThe position accurate, make SCR 128 unlikely bolt-locks.
During ESD, because time delay, the RC circuit keeps the grid of nmos pass transistor 188 to close nmos pass transistor 188 in low-voltage position standard.As a result, the resistance that presents of control circuit 186 than the n well region resistance of SCR 84 for big.The voltage of keeping of SCR 128 is turned down to less than V DdThe position accurate, for example about 1 volt, make SCR 128 remain in the bolt-lock state with discharging ESD electric current.
Figure 10 is for being used for V DdTo V SsThe ESD protection circuit 194 of ESD protection.See also Figure 10, ESD protection circuit 194 comprises PMOS and triggers SCR 196 and control circuit 198.The structure of ESD protection circuit 194 is similar to the circuit of Fig. 5 82, but contains a PMOS transistor 200 in addition.PMOS triggers SCR 196 and comprises a SCR and PMOS transistor 200.This SCR has p mold base 406 (P Sub), n well region 404 (NW), p type diffusion region 402 (p+), n type diffusion region 408 (n+) and dead resistance 410 (R NW), 412 (R Sub).PMOS transistor 200 has one source pole and is connected to p+ district 402, a drain electrode and is connected to the n well region 404 that p mold base 406 and a matrix are connected to SCR.Control circuit 198 comprises nmos pass transistor 202, resistance 204 and electric capacity 206.One end of resistance 204 is connected to the grid of electric capacity 206, PMOS transistor 200 and the grid of nmos pass transistor 202, and the other end then is connected to V DdOne end of electric capacity 206 is connected to the grid of resistance 204, PMOS transistor 200 and the grid of nmos pass transistor 202, and the other end then is connected to V SsIn the ESD protection circuit 194, control circuit 198 has the resistance that triggers the matrix resistance of SCR 196 less than PMOS when nmos pass transistor 202 is opened, and has the resistance that triggers the matrix resistance of SCR 196 greater than PMOS when nmos pass transistor 202 is closed.
During normal running, the RC circuit of being formed by resistance 204 and electric capacity 206 provide a high levels signal to the grid of PMOS transistor 200 and nmos pass transistor 202 to close PMOS transistor 200 and to open nmos pass transistor 202.As a result, the resistance that presents of control circuit 198 is little than the matrix resistance that PMOS triggers SCR196.The voltage of keeping that PMOS triggers SCR 196 is increased to and is higher than V DdThe position accurate, make PMOS trigger SCR 196 unlikely bolt-locks.
During ESD, for example there is positive polarity ESD to appear at V DdCircuit because time delay, the RC circuit provide a low level signal to the grid of PMOS transistor 200 and nmos pass transistor 202 to open PMOS transistor 200 and to close nmos pass transistor 202.As a result, the resistance that presents of control circuit 198 triggers the matrix resistance of SCR 196 for big than PMOS.PMOS triggers the voltage of keeping of SCR 196 and turns down to less than V DdThe position accurate, for example about 1 volt, make PMOS trigger SCR 196 and remain in the bolt-lock state with discharging ESD electric current.
Figure 11 is for being used for V DdTo V SsAnother ESD protection circuit 208 of ESD protection.See also Figure 11, ESD protection circuit 208 comprises NMOS and triggers SCR 210 and control circuit 212.The structure of ESD protection circuit 208 is similar to the circuit of Fig. 8 150, but contains a nmos pass transistor 214 in addition.NMOS triggers SCR 210 and comprises a SCR and nmos pass transistor 214.This SCR has p type diffusion region 414 (p+), n well region 416 (NW), p mold base 418 (P Sub), n type diffusion region 420 (n+) and dead resistance 422 (R NW), 424 (R Sub).Nmos pass transistor 214 has a drain electrode and is connected to n+ district 420, one source pole and is connected to the p mold base 418 that n well region 416 and a matrix are connected to SCR.Control circuit 212 comprises PMOS transistor 216, inverter 218, resistance 220 and electric capacity 222.Inverter 218 has an output and is connected to the grid of nmos pass transistor 214 and the grid of PMOS transistor 216.One end of resistance 220 is connected to the input of electric capacity 222 and inverter 218, and the other end then is connected to V DdOne end of electric capacity 222 is connected to the input of resistance 220 and inverter 218, and the other end then is connected to V SsIn the ESD protection circuit 208, control circuit 212 has the resistance that triggers the n well region resistance of SCR 210 less than NMOS when PMOS transistor 216 is opened, and has the resistance that triggers the n well region resistance of SCR 210 greater than NMOS when PMOS transistor 216 is closed.
During normal running, the RC circuit of being formed by resistance 220 and electric capacity 222 via inverter 218 provide a low level signal to the grid of nmos pass transistor 214 and PMOS transistor 216 to close nmos pass transistor 214 and to open PMOS transistor 216.As a result, the resistance that presents of control circuit 212 is little than the n well region resistance that NMOS triggers SCR 210.The voltage of keeping that NMOS triggers SCR 210 is increased to and is higher than V DdThe position accurate, make NMOS trigger SCR 210 unlikely bolt-locks.
During ESD, for example there is positive polarity ESD to appear at V DdCircuit because time delay, the RC circuit via inverter 218 provide a high levels signal to the grid of nmos pass transistor 214 and PMOS transistor 216 to open nmos pass transistor 214 and to close PMOS transistor 216.As a result, the resistance that presents of control circuit 212 triggers the n well region resistance of SCR 210 for big than NMOS.The voltage of keeping that NMOS triggers SCR 210 downgrades less than V DdThe position accurate, for example about 1 volt, make NMOS trigger SCR 210 and remain in the bolt-lock state with discharging ESD electric current.
Figure 12 is the input stage ESD protection circuit 224 of the embodiment of the invention.See also Figure 12, ESD protection circuit 224 comprises PMOS and triggers SCR 226, first control circuit 228, NMOS triggering SCR 230 and second control circuit 232.PMOS triggers SCR 226 and comprises a SCR and PMOS transistor 234.First control circuit 228 comprises resistance 236, electric capacity 238 and nmos pass transistor 240.NMOS triggers SCR 230 and comprises another SCR and nmos pass transistor 242.Second control circuit 232 comprises resistance 244, electric capacity 246 and PMOS transistor 248.
During normal running, with regard to PMOS triggered SCR 226, PMOS transistor 234 was closed then unlatching of nmos pass transistor 240.Because the nmos pass transistor 240 of first control circuit 228 is opened, the voltage of keeping that PMOS triggers SCR 226 is increased to and is higher than V DdThe position accurate, make PMOS trigger SCR 226 unlikely bolt-locks.
With regard to NMOS triggered SCR 230, nmos pass transistor 242 was closed then unlatching of PMOS transistor 248 in addition.Because the PMOS transistor 248 of second control circuit 232 is opened, the voltage of keeping that NMOS triggers SCR 230 is increased to and is higher than V DdThe position accurate, make NMOS trigger SCR 230 unlikely bolt-locks.
In positive polarity to V Ss(PS) during the pattern ESD, the part ESD voltage of electric capacity 246 coupling contact pins 250 is to the grid of nmos pass transistor 242 with PMOS transistor 248.Therefore, the grid of nmos pass transistor 242 and PMOS transistor 248 is subjected to positive bias that nmos pass transistor 242 is opened and PMOS transistor 248 is closed.Because the PMOS transistor 248 of second control circuit 232 is closed, NMOS triggers the voltage of keeping of SCR 230 and turns down to less than V DdThe position accurate, for example about 1 volt, make NMOS trigger SCR 230 and remain in the bolt-lock state.In addition, because nmos pass transistor 242 is opened, NMOS triggers SCR 230 can open the electric current with discharging ESD rapidly.ESD protection circuit 224 will appear at the positive polarity ESD voltage clamp of contact pins 250 in about 1 volt.
In negative polarity to V Dd(ND) during the pattern ESD, the part ESD voltage of electric capacity 238 coupling contact pins 250 is to the grid of nmos pass transistor 240 with PMOS transistor 234.Therefore, nmos pass transistor 240 is subjected to back bias voltage that nmos pass transistor 240 is closed and 234 unlatchings of PMOS transistor with the grid of PMOS transistor 234.Because the nmos pass transistor 240 of first control circuit 228 is closed, PMOS triggers the voltage of keeping of SCR 226 and turns down to less than V DdThe position accurate, for example about-1 volt, make PMOS trigger SCR 226 and remain in the bolt-lock state.In addition, because PMOS transistor 234 is opened, PMOS triggers SCR 226 can open the electric current with discharging ESD rapidly.ESD protection circuit 224 will appear at the negative polarity ESD voltage clamp of contact pins 250 in-1 volt approximately.
Figure 13 is the input stage ESD protection circuit 252 of another embodiment of the present invention.See also Figure 13, ESD protection circuit 252 comprises PMOS and triggers SCR 254, first control circuit 256, NMOS triggering SCR 258 and second control circuit 260.PMOS triggers SCR 254 and comprises a SCR and PMOS transistor 262.First control circuit 256 comprises resistance 264, inverter 266 and nmos pass transistor 268.NMOS triggers SCR 258 and comprises another SCR and nmos pass transistor 270.Second control circuit 260 comprises resistance 272, inverter 274 and PMOS transistor 276.
During normal running, with regard to PMOS triggered SCR 254, inverter 266 provided a high voltage level to the grid of PMOS transistor 262 and nmos pass transistor 268 that PMOS transistor 262 is closed and nmos pass transistor 268 unlatchings.Because the nmos pass transistor 268 of first control circuit 256 is opened, the voltage of keeping that PMOS triggers SCR 254 is increased to and is higher than V DdThe position accurate, make PMOS trigger the unlikely bolt-lock of SCR254.
With regard to NMOS triggered SCR 258, inverter 274 provided a low-voltage position standard to the grid of nmos pass transistor 270 and PMOS transistor 276 that nmos pass transistor 270 is closed and 276 unlatchings of PMOS transistor in addition.Because the PMOS transistor 276 of second control circuit 260 is opened, the voltage of keeping that NMOS triggers SCR 258 is increased to and is higher than V DdThe position accurate, make NMOS trigger SCR 258 unlikely bolt-locks.
During PS pattern ESD, inverter 274 is subjected to the part ESD voltage bias of contact pins 278 and provides a high voltage level to the grid of nmos pass transistor 270 with PMOS transistor 276.Therefore, the grid of nmos pass transistor 270 and PMOS transistor 276 is subjected to positive bias that nmos pass transistor 270 is opened and PMOS transistor 276 is closed.Because the PMOS transistor 276 of second control circuit 260 is closed, NMOS triggers the voltage of keeping of SCR 258 and turns down to less than V DdThe position accurate, for example about 1 volt, make NMOS trigger SCR 258 and remain in the bolt-lock state.In addition, because nmos pass transistor 270 is opened, NMOS triggers SCR 258 can open the electric current with discharging ESD rapidly.ESD protection circuit 252 will appear at the positive polarity ESD voltage clamp of contact pins 278 in about 1 volt.
During ND pattern ESD, inverter 266 is subjected to the part ESD voltage bias of contact pins 278 and provides a low-voltage position standard to the grid of nmos pass transistor 268 with PMOS transistor 262.Therefore, nmos pass transistor 268 is subjected to back bias voltage that nmos pass transistor 268 is closed and 262 unlatchings of PMOS transistor with the grid of PMOS transistor 262.Because the nmos pass transistor 268 of first control circuit 256 is closed, PMOS triggers the voltage of keeping of SCR 254 and turns down to less than V DdThe position accurate, for example about-1 volt, make PMOS trigger SCR 254 and remain in the bolt-lock state.In addition, because PMOS transistor 262 is opened, PMOS triggers SCR 254 can open the electric current with discharging ESD rapidly.ESD protection circuit 252 will appear at the negative polarity ESD voltage clamp of contact pins 278 in-1 volt approximately.
Figure 14 is the output stage ESD protection circuit 280 of the embodiment of the invention.See also Figure 14, ESD protection circuit 280 comprises PMOS and triggers SCR 282, first control circuit 284, NMOS triggering SCR 286 and second control circuit 288.PMOS triggers SCR 282 and comprises a SCR and PMOS transistor 290.First control circuit 284 comprises resistance 292, electric capacity 294 and nmos pass transistor 296.NMOS triggers SCR 286 and comprises another SCR and nmos pass transistor 298.Second control circuit 288 comprises resistance 300, electric capacity 302 and PMOS transistor 304.First buffer 306 and second buffer 308 are used for cushioning by the internal circuit (not shown) to be sent to the signal of contact pins 310.
During normal running, with regard to PMOS triggered SCR 282, PMOS transistor 290 was connected to V with the grid of nmos pass transistor 296 via resistance 292 Dd, PMOS transistor 290 is closed and nmos pass transistor 296 unlatchings.Because the nmos pass transistor 296 of first control circuit 284 is opened, the voltage of keeping that PMOS triggers SCR 282 is increased to and is higher than V DdThe position accurate, make PMOS trigger SCR 282 unlikely bolt-locks.
With regard to NMOS triggered SCR 286, nmos pass transistor 298 was connected to V with the grid of PMOS transistor 304 via resistance 300 in addition Ss, nmos pass transistor 298 is closed and 304 unlatchings of PMOS transistor.Because the PMOS transistor 304 of second control circuit 288 is opened, the voltage of keeping that NMOS triggers SCR 286 is increased to and is higher than V DdThe position accurate, make NMOS trigger SCR 286 unlikely bolt-locks.
During PS pattern ESD, the part ESD voltage of electric capacity 302 coupling contact pins 310 is to the grid of nmos pass transistor 298 with PMOS transistor 304.Therefore, the grid of nmos pass transistor 298 and PMOS transistor 304 is subjected to positive bias that nmos pass transistor 298 is opened and PMOS transistor 304 is closed.Because the PMOS transistor 304 of second control circuit 288 is closed, NMOS triggers the voltage of keeping of SCR 286 and turns down to less than V DdThe position accurate, for example about 1 volt, make NMOS trigger SCR 286 and remain in the bolt-lock state.In addition, because nmos pass transistor 298 is opened, NMOS triggers SCR 286 can open the electric current with discharging ESD rapidly.ESD protection circuit 280 will appear at the positive polarity ESD voltage clamp of contact pins 310 in about 1 volt.
During ND pattern ESD, the part ESD voltage of electric capacity 294 coupling contact pins 310 is to the grid of nmos pass transistor 296 with PMOS transistor 290.Therefore, nmos pass transistor 296 is subjected to back bias voltage that nmos pass transistor 296 is closed and 290 unlatchings of PMOS transistor with the grid of PMOS transistor 290.Because the nmos pass transistor 296 of first control circuit 284 is closed, PMOS triggers the voltage of keeping of SCR 282 and turns down to less than V DdThe position accurate, for example about-1 volt, make PMOS trigger SCR 282 and remain in the bolt-lock state.In addition, because PMOS transistor 290 is opened, PMOS triggers SCR 282 can open the electric current with discharging ESD rapidly.ESD protection circuit 280 will appear at the negative polarity ESD voltage clamp of contact pins 310 in-1 volt approximately.
Figure 15 is the output stage ESD protection circuit 312 of another embodiment of the present invention.See also Figure 15, ESD protection circuit 312 comprises PMOS and triggers SCR 314, first control circuit, NMOS triggering SCR 316 and second control circuit.PMOS triggers SCR 314 and comprises a SCR and PMOS transistor 318.First control circuit comprises resistance 320, electric capacity 322 and nmos pass transistor 324.NMOS triggers SCR 316 and comprises another SCR and nmos pass transistor 326.Second control circuit comprises resistance 320, inverter 328 and PMOS transistor 330.First buffer 332 and second buffer 334 are used for cushioning by the internal circuit (not shown) to be sent to the signal of contact pins 336.
During normal running, with regard to PMOS triggers SCR 314, the RC circuit of being formed by resistance 320 and electric capacity 322 provide a high levels signal to the grid of PMOS transistor 318 and nmos pass transistor 324 to close PMOS transistor 318 and to open nmos pass transistor 324.Because the nmos pass transistor 324 of first control circuit is opened, the voltage of keeping that PMOS triggers SCR 314 is increased to and is higher than V DdThe position accurate, make PMOS trigger SCR 314 unlikely bolt-locks.
With regard to NMOS triggered SCR 316, this RC circuit provided a low-voltage position standard to the grid of nmos pass transistor 326 and PMOS transistor 330 that nmos pass transistor 326 is closed and 330 unlatchings of PMOS transistor via inverter 328 in addition.Because the PMOS transistor 330 of second control circuit is opened, the voltage of keeping that NMOS triggers SCR 316 is increased to and is higher than V DdThe position accurate, make NMOS trigger SCR 316 unlikely bolt-lock during normal running.
During PS pattern ESD, part ESD electric current flow to V via a parasitic diode (not shown) DdCircuit, this parasitic diode is formed by p type diffusion region (not shown) and the n well region in the PMOS transistor of second buffer 334.The RC circuit provides a high voltage level to the grid of nmos pass transistor 326 and PMOS transistor 330 that nmos pass transistor 326 unlatching PMOS transistors 330 are closed because of time delay via inverter 328.Because the PMOS transistor 330 of second control circuit is closed, NMOS triggers the voltage of keeping of SCR 316 and turns down to less than V DdThe position accurate, for example about 1 volt, make NMOS trigger SCR 316 and remain in the bolt-lock state.In addition, because nmos pass transistor 326 is opened, NMOS triggers SCR 316 can open the electric current with discharging ESD rapidly.ESD protection circuit 312 will appear at the positive polarity ESD voltage clamp of contact pins 336 in about 1 volt.
During ND pattern ESD, part ESD electric current flow to V via a parasitic diode (not shown) SsCircuit, this parasitic diode system is formed by n type diffusion region (not shown) and p well region in the nmos pass transistor of second buffer 334.Because the part ESD voltage of electric capacity 322 coupling contact pins 336, RC circuit provide a low-voltage position standard to the grid of nmos pass transistor 324 with PMOS transistor 318, and nmos pass transistor 324 is closed and 318 unlatchings of PMOS transistor.Because the nmos pass transistor 324 of first control circuit is closed, PMOS triggers the voltage of keeping of SCR 314 and turns down to less than V DdThe position accurate, for example about-1 volt, make PMOS trigger SCR 314 and remain in the bolt-lock state.In addition, because PMOS transistor 318 is opened, PMOS triggers SCR 314 can open the electric current with discharging ESD rapidly.ESD protection circuit 312 will appear at the negative polarity ESD voltage clamp of contact pins 336 in-1 volt approximately.
Figure 16 is the mixed pressure input and output level ESD protection circuit 338 of the embodiment of the invention.See also Figure 16, ESD protection circuit 338 comprises PMOS and triggers SCR 340 and control circuit.PMOS triggers SCR 340 and comprises a SCR and PMOS transistor 342.Control circuit comprises resistance 344, electric capacity 346 and nmos pass transistor 348.
During normal running, the RC circuit of being formed by resistance 344 and electric capacity 346 provide a high levels signal to the grid of nmos pass transistor 348 and PMOS transistor 342 to open nmos pass transistor 348 and to close PMOS transistor 342.Because the nmos pass transistor 348 of control circuit is opened, the voltage of keeping that PMOS triggers SCR 340 is increased to and is higher than V DdThe position accurate, make PMOS trigger SCR 340 unlikely bolt-locks.During normal running, PMOS transistor 342 may be opened the existence of grid voltage is unexpected because of the positive polarity source electrode, causes leakage current.In embodiments of the present invention, producing leakage current for preventing PMOS transistor 342 during normal running, is diode string 350 to be connected to PMOS trigger SCR 340.
During ESD, for example there is positive polarity ESD to appear at contact pins 352, the ESD electric current flow to diode string 350 via a parasitic diode 354 and triggers SCR 340 with PMOS, and this parasitic diode 354 is that drain electrode and the matrix by PMOS transistor 356 formed.Because time delay, the RC circuit provide a low level signal to the grid of nmos pass transistor 348 and PMOS transistor 342 to close nmos pass transistor 348 and to open PMOS transistor 342.Because nmos pass transistor 348 is closed, the voltage of keeping that PMOS triggers SCR340 downgrades less than V DdThe position accurate, make PMOS trigger SCR 340 and remain in the bolt-lock state.In addition, because PMOS transistor 342 is opened, PMOS triggers SCR 340 can open the electric current with discharging ESD rapidly.ESD protection circuit 338 with positive polarity ESD voltage clamp in being lower than V DdThe position accurate, and this standard must be decided on the number of diodes in the diode string 350.
Figure 17 is the circuit diagram of the mixed pressure power supply ESD protection circuit 338 of the embodiment of the invention.See also Figure 17, this circuit was connected in the ESD protection circuit 358 between high-voltage circuit and low-voltage lines except embodiment discusses as mentioned before, also comprised to be connected in two high-voltage circuit V Dd1, V Dd2With two low-voltage lines V Ss1, V Ss2Between ESD protection circuit 360.
Figure 18 uses NMOS for the embodiment of the invention and triggers the circuit diagram of the mixed pressure power supply ESD protection circuit 362 of SCR 364.See also Figure 18, ESD protection circuit 362 is connected between first power circuit 368 and the second source circuit 370.In one embodiment, first power circuit 368 is all the high voltage source circuit with second source circuit 370, and for example phase XOR same electrical is pressed the accurate V in position Dd1, V Dd2In another embodiment, first power circuit 368 is all the low-tension supply circuit with second source circuit 370, and for example phase XOR same electrical is pressed the accurate V in position Ss1, V Ss2 ESD protection circuit 362 comprises that NMOS triggers a SCR 364 and a control circuit 366.NMOS triggers SCR 364 and comprises a SCR and nmos pass transistor 372.Control circuit 366 comprises resistance 374, electric capacity 376 and PMOS transistor 378.
Suppose that the voltage level of first power circuit 368 is higher than the voltage level of second source circuit 370, for example V Dd1＞V Dd2, during normal running, the RC circuit of being made up of resistance 374 and electric capacity 376 provides V Dd2Voltage level to nmos pass transistor 372 grid with PMOS transistor 378.At this moment, PMOS transistor 378 is to open because of its source potential, i.e. V Dd1, greater than its grid potential V Dd2Simultaneously, nmos pass transistor 372 is all V for closing because of its grid and source electrode equipotential Dd2Because the PMOS transistor 378 of control circuit 366 is opened, the voltage of keeping that NMOS triggers SCR 364 is increased to and is higher than V Dd1The position accurate, make NMOS trigger SCR 364 unlikely bolt-locks.
ESD appears at V if any positive polarity Dd1Circuit 368 and V Dd2Circuit 370 ground connection, because the ESD voltage of electric capacity 376 coupling units, the RC circuit provides a positive voltage to the grid of nmos pass transistor 372 with PMOS transistor 378, and nmos pass transistor 372 is closed and 378 unlatchings of PMOS transistor.Because the PMOS transistor 378 of control circuit 366 is closed, NMOS triggers the voltage of keeping of SCR 364 and turns down to less than V Dd1The position accurate, for example about 1 volt, make NMOS trigger SCR 364 and remain in the bolt-lock state.In addition, because nmos pass transistor 372 is opened, NMOS triggers SCR 364 can open the electric current with discharging ESD rapidly, and with positive polarity ESD voltage clamp in about 1 volt.
ESD appears at V if any negative polarity Dd2Circuit 370 and V Dd1Circuit 368 ground connection, because time delay, the RC circuit provides an earthed voltage to the grid of nmos pass transistor 372 with PMOS transistor 378.At this moment, PMOS transistor 378 is all earthing potential for closing because of its source electrode and grid equipotential.In addition, nmos pass transistor 372 for open because of its grid potential greater than its source potential.Because the PMOS transistor 378 of control circuit 366 is closed, NMOS triggers the voltage of keeping of SCR 364 and turns down to less than-1 volt approximately, makes NMOS trigger SCR 364 and remains in the bolt-lock state.Simultaneously, because nmos pass transistor 372 is opened, NMOS triggers SCR 364 can open the electric current with discharging ESD rapidly, and with negative polarity ESD voltage clamp in-1 volt approximately.
ESD appears at V if any positive polarity Dd2Circuit 370 and V Dd1Circuit 368 ground connection, diode 380 are along partially, with positive polarity ESD voltage clamp in the critical voltage of diode 380.
ESD appears at V if any negative polarity Dd1Circuit 368 and V Dd2Circuit 370 ground connection, diode 380 are along partially, with negative polarity ESD voltage clamp in the critical voltage of diode 380.
Figure 19 uses PMOS for the embodiment of the invention and triggers the circuit diagram of the mixed pressure power supply ESD protection circuit 382 of SCR 384.See also Figure 19, ESD protection circuit 382 is connected between first power circuit 388 and the second source circuit 390.In one embodiment, first power circuit 388 is all the high voltage source circuit with second source circuit 390, and for example phase XOR same electrical is pressed the accurate V in position Dd1, V Dd2In another embodiment, first power circuit 388 is all the low-tension supply circuit with second source circuit 390, and for example phase XOR same electrical is pressed the accurate V in position Ss1, V Ss2ESD protection circuit 382 comprises that PMOS triggers a SCR 384 and a control circuit 386.PMOS triggers SCR 384 and comprises a SCR and PMOS transistor 392.Control circuit 386 comprises resistance 394, electric capacity 396 and nmos pass transistor 398.
Suppose that the voltage level of first power circuit 388 is higher than the voltage level of second source circuit 390, for example V Dd1＞V Dd2, during normal running, the RC circuit of being made up of resistance 394 and electric capacity 396 provides V Dd1Voltage level to PMOS transistor 392 grid with nmos pass transistor 398.At this moment, nmos pass transistor 398 is to open because of its grid potential, i.e. V Dd1, greater than its source potential V Dd2Simultaneously, PMOS transistor 392 is all V for closing because of its grid and source electrode equipotential Dd1Because the nmos pass transistor 398 of control circuit 386 is opened, the voltage of keeping that PMOS triggers SCR 384 is increased to and is higher than V Dd1The position accurate, make PMOS trigger SCR 384 unlikely bolt-locks.
ESD appears at V if any positive polarity Dd1Circuit 388 and V Dd2Circuit 390 ground connection, because time delay, the RC circuit is exported an earthed voltage to the grid of PMOS transistor 392 with nmos pass transistor 398.At this moment, nmos pass transistor 398 is all earthing potential for closing because of its source electrode and grid equipotential.In addition, PMOS transistor 392 for open because of its source potential greater than its grid potential.Because the nmos pass transistor 398 of control circuit 386 is closed, PMOS triggers the voltage of keeping of SCR 384 and turns down to less than about 1 volt, makes PMOS trigger SCR 384 and remains in the bolt-lock state.Simultaneously, because PMOS transistor 392 is opened, PMOS triggers SCR 384 can open the electric current with discharging ESD rapidly, and with positive polarity ESD voltage clamp in about 1 volt.
ESD appears at V if any negative polarity Dd2Circuit 390 and V Dd1Circuit 388 ground connection, because the ESD voltage of electric capacity 396 coupling units, the RC circuit provides a negative voltage to the grid of PMOS transistor 392 with nmos pass transistor 398, PMOS transistor 392 is opened and nmos pass transistor 398 is closed.Because the nmos pass transistor 398 of control circuit 386 is closed, PMOS triggers the voltage of keeping of SCR 384 and turns down to less than V Dd1The position accurate, for example about-1 volt, make PMOS trigger SCR 384 and remain in the bolt-lock state.In addition, because PMOS transistor 392 is opened, PMOS triggers SCR 384 can open the electric current with discharging ESD rapidly, and with negative polarity ESD voltage clamp in-1 volt approximately.
ESD appears at V if any positive polarity Dd2Circuit 390 and V Dd1Circuit 388 ground connection, diode 400 are along partially, with positive polarity ESD voltage clamp in the critical voltage of diode 400.
ESD appears at V if any negative polarity Dd1Circuit 388 and V Dd2Circuit 390 ground connection, diode 400 are along partially, with negative polarity ESD voltage clamp in the critical voltage of diode 400.
Therefore the present invention provides a kind of means of defence of static discharge, comprise providing to have a silicon controlled rectifier (SCR) of keeping voltage, and the voltage of keeping of control SCR makes it be higher or lower than a supply voltage V DdConcrete, method of the present invention will be kept voltage and be promoted to and be higher than V during normal running DdSo that the unlikely bolt-lock of SCR, and during ESD, will keep voltage and turn down to being lower than V DdSo that SCR remains in the bolt-lock state.
Figure 20 A is the cutaway view of the SCR 500 of the embodiment of the invention.The structure of SCR 500 is similar to the SCR 128 of the SCR of Fig. 5 84 or Fig. 9, but the nmos pass transistor 188 of the nmos pass transistor 107 of Fig. 5 control circuit 86 or Fig. 9 control circuit 186 is to be embedded among the SCR 500.MOS transistor in the script control circuit is integrated among the SCR can simplifies the SCR layout, reduce the complexity of SCR size and simplified control circuit.
See also Figure 20 A, SCR 500 comprises that a p mold base 502, a n type well region 504, are formed at a p type diffusion region 506 in the n type well region 504, part and are formed at a n type diffusion region 510 and that the 2nd p type diffusion region 508 in the n well region 504, part be formed at another n well region 512 and are formed at the 2nd n type diffusion region 514 in the p mold base 502.The 2nd n type diffusion region 514 is by a metal level or aim at metal silicide (salicide) layer 516 automatically and be connected to the 2nd p type diffusion region 508.P transistor npn npn 520 is one-body molded with SCR 500 with n transistor npn npn 530.P transistor npn npn 520 has a grid 522, a side wall spacers 524 and is formed at the channel in the n well region 504.The one p type diffusion region 506 and the 2nd p type diffusion region 508 are respectively as the source electrode and the drain electrode of p transistor npn npn 520.N transistor npn npn 530 has a grid 532, a side wall spacers 534 and is formed at the channel in the p mold base 502.The one n type diffusion region 510 and the 2nd n type diffusion region 514 are respectively as the source electrode and the drain electrode of n transistor npn npn 530.The effect of P transistor npn npn 520 is to impel SCR 500 to open.The effect of n transistor npn npn 530 then is to control the voltage of keeping of SCR 500.
Thick oxide layer 540 is in order to electric insulation to be provided.P type diffusion region 506 as the anode of SCR 500 is connected to contact pins 550.510 of n type diffusion regions as the negative electrode of SCR 500 are connected to reference potential or ground connection position standard (GND).In one embodiment of this invention, a p type diffusion region 506 is connected to a power circuit, for example V Dd
Figure 20 B is the control circuit 600 of the embodiment of the invention.Control circuit 600 has a resistance 602, an electric capacity 604 and an output 606.Provide the time delay of about 1 microsecond (1 μ s) by resistance 602 and electric capacity 604 formed resistor capacitor circuits, than the time delays of 150 to 300 nanoseconds (ns) of general esd pulse for long.Control circuit 600 is connected in first power circuit such as V DdWith second source circuit such as V SsBetween.Output 606 is connected to the grid 522,532 shown in Figure 20 A.The ESD protective action that is provided by SCR 500 and control circuit 600 is similar to the ESD protection circuit 184 of the ESD protection circuit 82 of Fig. 5 or Fig. 9.
See also Figure 20 A and 20B, during normal running, grid 522,532 is biased in high voltage level V Dd, p transistor npn npn 520 is closed and 530 unlatchings of n transistor npn npn.Control circuit 600 is owing to the matrix resistance that the unlatching of n transistor npn npn 530 presents than SCR 500 is little resistance.The voltage of keeping of SCR500 is brought up to V DdOn, make SCR 500 unlikely bolt-locks.
During ESD, grid 522,532 is owing to the time delay that resistor capacitor circuit provided is biased in the accurate V in low-voltage position Ss, p transistor npn npn 520 is opened and n transistor npn npn 530 is closed.Control circuit 600 is owing to the matrix resistance that closing of n transistor npn npn 530 presents than SCR 500 is big resistance.The voltage drop of keeping of SCR 500 is low to moderate V DdFollowing, make SCR 500 keep the bolt-lock states with discharging ESD electric current.
Figure 21 is the ESD protection circuit 620 of another embodiment of the present invention.ESD protection circuit 620 has a SCR 500, PMOS transistor 520, a nmos pass transistor 530 and a control circuit 600.Control circuit 600 is connected in the first power circuit V DdWith second source circuit V SsBetween.SCR 500 is connected in contact pins 550 and second source circuit V Ss Between.PMOS transistor 520 is one-body molded with SCR 500 with nmos pass transistor 530.
During normal running, control circuit 600 provides one first voltage level V DdTo PMOS transistor 520 and nmos pass transistor 530, thereby provide one to be higher than V DdFirst keep voltage to SCR 500, make SCR 500 unlikely bolt-locks.
During ESD, for example there is the positive polarity esd pulse to appear at contact pins 550 and second source circuit V SsGround connection, control circuit 600 provide one second voltage level V SsTo PMOS transistor 520 and nmos pass transistor 530, thereby provide one to be lower than V DdSecond keep voltage to SCR 500, make SCR500 remain in the bolt-lock state, esd pulse is disposed to second source circuit V by contact pins 550 Ss
Figure 22 is the ESD protection circuit 640 of further embodiment of this invention.The structure of ESD protection circuit 640 is similar to ESD protection circuit 620, but SCR 500 is connected in the first power circuit V DdWith second source circuit V SsBetween.During ESD, for example there is the positive polarity esd pulse to appear at the first power circuit V DdAnd second source circuit V SsGround connection, control circuit 600 provide one second voltage level V SsTo PMOS transistor 520 and nmos pass transistor 530, thereby provide one to be lower than V DdSecond keep voltage to SCR 500, make SCR 500 remain in the bolt-lock state.Esd pulse is by the first power circuit V DdBe disposed to second source circuit V Ss
Figure 23 is the ESD protection circuit 660 of yet another embodiment of the invention.ESD protection circuit 660 has a plurality of SCR 500-1,500-2 ... 500-n and 500-p, and a control circuit 600.With SCR 500-n is representative, and it has a PMOS transistor 520-n and a nmos pass transistor 530-n, and is all one-body molded with SCR 500-n.Control circuit 600 has an output 606 and is connected to the PMOS of these SCR and the grid of nmos pass transistor (not label).SCR 500-p is connected in the first power circuit V DdWith second source circuit V SsBetween.Each SCR 500-1,500-2 ... 500-n be connected in corresponding contact pins 550-1, a 550-2 ... 550-n and second source circuit V SsBetween.
During normal running, control circuit 600 provides one first to keep voltage to SCR 500-1,500-2 via these PMOS and nmos pass transistor ... 500-n and 500-p make the unlikely bolt-lock of these SCR.
Appearing at a certain contact pins if any the positive polarity esd pulse, for example is contact pins 550-1, and the first power circuit V DdGround connection, control circuit 600 provides one second to keep voltage to SCR 500-1,500-2 via these PMOS and nmos pass transistor ... 500-n and 500-p make these SCR remain in the bolt-lock state.Esd pulse then by contact pins 550-1 through second source circuit V SsBe disposed to the first power circuit V Dd, this is the first path P1.
Appear at the first power circuit V if any the positive polarity esd pulse DdAnd a certain contact pins ground connection for example is contact pins 550-1, and control circuit 600 provides one second to keep voltage to SCR 500-1,500-2 via these PMOS and nmos pass transistor ... 500-n and 500-p make these SCR remain in the bolt-lock state.Esd pulse is then by the first power circuit V DdThrough second source circuit V SsBe disposed to contact pins 550-1, this is second path P 2.
Appear at a certain contact pins if any the positive polarity esd pulse, for example be contact pins 550-2, and another contact pins ground connection, for example be contact pins 550-n, control circuit 600 provides one second to keep voltage to SCR 500-1,500-2 via these PMOS and nmos pass transistor ... 500-n and 500-p make these SCR remain in the bolt-lock state.Esd pulse then by contact pins 550-2 through second source circuit V SsBe disposed to contact pins 550-n, this is Third Road footpath P3.
The present invention also provides a kind of means of defence of Electrostatic Discharge.Provide one to have the silicon controlled rectifier (SCR) of keeping voltage.A PMOS transistor and nmos pass transistor and SCR is one-body molded.The PMOS transistor has a first grid, and nmos pass transistor then has a second grid.During first situation, the voltage of keeping that provides one first signal to first and second grid to improve SCR makes the unlikely bolt-lock of SCR.During second situation, the voltage of keeping that provides a secondary signal to first and second grid to reduce SCR makes SCR remain in the bolt-lock state.
In another embodiment of the present invention, first power circuit and the second source circuit with second voltage level that provides to have first voltage level is provided the ESD means of defence, and second voltage level is different from first voltage level.A plurality of contact pins are provided.A plurality of silicon controlled rectifiers (SCR) are provided, and each SCR has nmos pass transistor of a PMOS transistor AND gate, and is all one-body molded with SCR.At least one SCR of these SCR is connected between first and second power circuit, and remaining SCR then is connected between a corresponding contact pins and the second source circuit.During normal running, provide one first to keep voltage via these PMOS and nmos pass transistor to these SCR, make the unlikely bolt-lock of these SCR.During ESD, provide one second to keep voltage via these PMOS and nmos pass transistor to these SCR, make these SCR remain in the bolt-lock state.
In one embodiment, esd pulse is disposed to first power circuit by one of contact pins via the second source circuit.In another embodiment, esd pulse is disposed to one of contact pins by first power circuit via the second source circuit.In another embodiment, esd pulse is disposed to another contact pins by one of contact pins via the second source circuit.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement, all should be encompassed in protection scope of the present invention in.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.

Claims (57)

1. electrostatic discharge protective integrated circuit is characterized in that comprising:
One silicon controlled rectifier;
One is connected to the control circuit of silicon controlled rectifier, during first situation, provide silicon controlled rectifier first to keep voltage so that its unlikely bolt-lock, and during second situation, provide silicon controlled rectifier second to keep voltage so that it remains in the bolt-lock state, wherein first keep voltage and be different from second and keep voltage.
2. electrostatic discharge protective integrated circuit as claimed in claim 1 is characterized in that: described silicon controlled rectifier comprises a parasitic two-carrier transistor and a dead resistance that is connected between transistorized base stage of this parasitism two-carrier and emitter-base bandgap grading.
3. electrostatic discharge protective integrated circuit as claimed in claim 2 is characterized in that: described control circuit presents the resistance less than this dead resistance during first situation.
4. electrostatic discharge protective integrated circuit as claimed in claim 3 is characterized in that: described control circuit presents the resistance greater than this dead resistance during second situation.
5. electrostatic discharge protective integrated circuit as claimed in claim 1 is characterized in that: described silicon controlled rectifier comprises a p mold base, and is formed at the p type diffusion region and that n well region, in the p mold base is formed in the n well region and is formed at the outer n type diffusion region of n well region.
6. electrostatic discharge protective integrated circuit as claimed in claim 1 is characterized in that: described control circuit comprises a MOS (metal-oxide-semiconductor) transistor that is connected to silicon controlled rectifier, and a resistor capacitor circuit that delay is provided.
7. electrostatic discharge protective integrated circuit as claimed in claim 4 is characterized in that: described control circuit comprises a nmos pass transistor, and it has a drain electrode and is connected to a part and is formed at diffusion region in this n well region.
8. electrostatic discharge protective integrated circuit as claimed in claim 4 is characterized in that: described control circuit comprises a PMOS transistor, and it has one source pole and is connected to the diffusion region that a part is formed at this n well region.
9. electrostatic discharge protective integrated circuit as claimed in claim 7, it is characterized in that: described control circuit comprises a resistance, one end of this resistance is connected to the grid of nmos pass transistor, and an electric capacity, and an end of this electric capacity is connected to the grid of this resistance and this nmos pass transistor.
10. electrostatic discharge protective integrated circuit as claimed in claim 9, it is characterized in that: described control circuit comprises an inverter, one resistance and an electric capacity, one output of this inverter is connected to the transistorized grid of PMOS, one end of this resistance is connected to an input of inverter, and an end of this electric capacity is connected to the input of resistance and inverter.
11. electrostatic discharge protective integrated circuit as claimed in claim 4, it is characterized in that: other comprises a PMOS transistor in order to trigger silicon controlled rectifier, this PMOS transistor has the p type diffusion region that one source pole is connected to silicon controlled rectifier, one drain electrode is connected to the p mold base of silicon controlled rectifier, and a matrix is connected to the n well region of silicon controlled rectifier.
12. electrostatic discharge protective integrated circuit as claimed in claim 4, it is characterized in that: other comprises a nmos pass transistor in order to trigger silicon controlled rectifier, this nmos pass transistor has the n type diffusion region that one source pole is connected to silicon controlled rectifier, one drain electrode is connected to the n well region of silicon controlled rectifier, and a matrix is connected to the p mold base of silicon controlled rectifier.
13. an electrostatic discharge protective integrated circuit is characterized in that comprising:
The silicon controlled rectifier that one MOS triggers, it comprises a silicon controlled rectifier and and is connected to silicon controlled rectifier to trigger the MOS (metal-oxide-semiconductor) transistor of this silicon controlled rectifier; And
One control circuit, it is connected to the silicon controlled rectifier that MOS triggers, during first situation, to provide one first to keep the silicon controlled rectifier that voltage triggers to MOS, so that the unlikely bolt-lock of silicon controlled rectifier that MOS triggers, and during second situation, provide one second to keep the silicon controlled rectifier that voltage triggers to MOS, so that the silicon controlled rectifier that MOS triggers remains in the bolt-lock state, wherein first keep voltage and be different from second and keep voltage.
14. electrostatic discharge protective integrated circuit as claimed in claim 13, it is characterized in that: the silicon controlled rectifier that described MOS triggers is that a MOS triggers silicon controlled rectifier, it comprises a PMOS transistor and one first silicon controlled rectifier, and wherein this integrated circuit comprises that in addition one the 2nd MOS triggers silicon controlled rectifier, and it comprises a nmos pass transistor and one second silicon controlled rectifier.
15. electrostatic discharge protective integrated circuit as claimed in claim 14, it is characterized in that: the described control circuit that is connected to MOS triggering silicon controlled rectifier is a first control circuit, and this integrated circuit comprises that in addition one is connected to the second control circuit that the 2nd MOS triggers silicon controlled rectifier.
16. electrostatic discharge protective integrated circuit as claimed in claim 14 is characterized in that: described first control circuit comprises a capacitor, the one end is connected to the partial electrostatic discharge voltage of a contact pins with this contact pins that is coupled.
17. electrostatic discharge protective integrated circuit as claimed in claim 15 is characterized in that: described second control circuit comprises a capacitor, the one end is connected to the partial electrostatic discharge voltage of a contact pins with this contact pins that is coupled.
18. electrostatic discharge protective integrated circuit as claimed in claim 15, it is characterized in that: described first control circuit comprises a nmos pass transistor and an inverter, and this inverter is connected to the grid of nmos pass transistor and the transistorized grid of PMOS that PMOS triggers silicon controlled rectifier.
19. electrostatic discharge protective integrated circuit as claimed in claim 16, it is characterized in that: described second control circuit comprises a PMOS transistor and an inverter, and this inverter is connected to the grid of the nmos pass transistor of transistorized grid of PMOS and NMOS triggering silicon controlled rectifier.
20. an electrostatic discharge protective integrated circuit is characterized in that comprising:
One silicon controlled rectifier, its matrix, one with one first doping type is formed in the matrix and is that the semiconductor well region, of second doping type is formed in the semiconductor well region is first diffusion region of first doping type, and one is formed at outside the semiconductor well region and is second diffusion region of second doping type;
One control circuit, its be connected to silicon controlled rectifier with during first situation, provide one first keep voltage to silicon controlled rectifier so that its unlikely bolt-lock, and during second situation, provide one second keep voltage to silicon controlled rectifier so that it keeps bolt-lock state, wherein first keep voltage and be different from second and keep voltage.
21. the means of defence of a static discharge comprises:
Provide one to have first silicon controlled rectifier of keeping voltage;
The voltage of keeping of control silicon controlled rectifier makes it be higher than a supply voltage so that the unlikely bolt-lock of silicon controlled rectifier during first situation, and the voltage of keeping of control silicon controlled rectifier makes it be lower than supply voltage so that silicon controlled rectifier remains in the bolt-lock state during second situation.
22. the means of defence of static discharge as claimed in claim 21 is characterized in that: other comprises provides one to be connected to the p type MOS (metal-oxide-semiconductor) transistor of silicon controlled rectifier to trigger this silicon controlled rectifier during second situation.
23. the means of defence of static discharge as claimed in claim 21 is characterized in that: other comprises provides one to be connected to the n type MOS (metal-oxide-semiconductor) transistor of silicon controlled rectifier to trigger this silicon controlled rectifier during second situation.
24. the means of defence of static discharge as claimed in claim 21 is characterized in that: other comprises silicon controlled rectifier is connected between one first power circuit and the second source circuit.
25. the means of defence of static discharge as claimed in claim 24 is characterized in that: other comprises with this first power circuit as V DdCircuit, and with this second source circuit as V SsCircuit.
26. an electrostatic discharge protective integrated circuit is characterized in that comprising:
A silicon controlled rectifier;
The first transistor of one first conductivity type, one-body molded with silicon controlled rectifier, have a first grid;
The transistor seconds of one second conductivity type, one-body molded with silicon controlled rectifier, have a second grid;
A control circuit, in response in first voltage that is applied to first and second grid, provide one first keep voltage to silicon controlled rectifier so that its unlikely bolt-lock, and in response in second voltage that is applied to first and second grid, provide one second keep voltage to silicon controlled rectifier so that it remains in the bolt-lock state.
27. electrostatic discharge protective integrated circuit as claimed in claim 26 is characterized in that: this control circuit comprises that in addition an output is connected to first and second grid.
28. electrostatic discharge protective integrated circuit as claimed in claim 26 is characterized in that: this control circuit comprises a resistance, an electric capacity and the output between resistance and electric capacity in addition.
29. electrostatic discharge protective integrated circuit as claimed in claim 26 is characterized in that: this control circuit comprises a resistance capacitance delay circuit in addition.
30. electrostatic discharge protective integrated circuit as claimed in claim 26 is characterized in that: this silicon controlled rectifier comprises a p mold base, in addition and is formed at the p type diffusion region and that n well region, in the p mold base is formed in the n well region and is formed at the outer n type diffusion region of n well region.
31. electrostatic discharge protective integrated circuit as claimed in claim 30 is characterized in that: this first transistor comprises that in addition one is formed at the channel region in the n well region.
32. electrostatic discharge protective integrated circuit as claimed in claim 30 is characterized in that: this transistor seconds comprises that in addition one is formed at the channel region in the p well region.
33. an electrostatic discharge protective integrated circuit is characterized in that comprising:
A silicon controlled rectifier;
One and the integrated p transistor npn npn of silicon controlled rectifier;
One and the integrated n transistor npn npn of silicon controlled rectifier;
A control circuit that is connected to p type and n transistor npn npn, its provide one first voltage to silicon controlled rectifier so that its unlikely bolt-lock, and provide one second voltage to silicon controlled rectifier so that it remains in the bolt-lock state.
34. electrostatic discharge protective integrated circuit as claimed in claim 33 is characterized in that: this control circuit comprises a resistance, an electric capacity and the output between resistance and electric capacity in addition.
35. electrostatic discharge protective integrated circuit as claimed in claim 33 is characterized in that: this control circuit comprises that in addition an output is connected to the grid of p transistor npn npn and the grid of n transistor npn npn.
36. electrostatic discharge protective integrated circuit as claimed in claim 33 is characterized in that: this silicon controlled rectifier comprises a p mold base, in addition and is formed at the p type diffusion region and that n well region, in the p mold base is formed in the n well region and is formed at the outer n type diffusion region of n well region.
37. electrostatic discharge protective integrated circuit as claimed in claim 36, it is characterized in that: this silicon controlled rectifier comprises the next drain electrode as the p transistor npn npn in another p type diffusion region that partly is formed at the n well region in addition, and p type diffusion region wherein is as the source electrode of p transistor npn npn.
38. electrostatic discharge protective integrated circuit as claimed in claim 36, it is characterized in that: this silicon controlled rectifier comprises that in addition being formed at another n type diffusion region in the p mold base comes drain electrode as the n transistor npn npn, and n type diffusion region wherein is as the source electrode of n transistor npn npn.
39. electrostatic discharge protective integrated circuit as claimed in claim 33 is characterized in that: this silicon controlled rectifier is connected between a contact pins and the power circuit.
40. electrostatic discharge protective integrated circuit as claimed in claim 33 is characterized in that: it is characterized in that: this silicon controlled rectifier is connected between the different power circuit.
41. an electrostatic discharge protective integrated circuit is characterized in that comprising:
First power circuit with first voltage level;
Second source circuit with second voltage level;
A plurality of contact pins;
A plurality of silicon controlled rectifiers, each silicon controlled rectifier all comprise a p transistor npn npn and a n transistor npn npn, and this p type and n transistor npn npn and silicon controlled rectifier are one-body molded;
A control circuit, via p type and n transistor npn npn provide one first keep voltage to these silicon controlled rectifiers so that the unlikely bolt-lock of these silicon controlled rectifiers, and via p type and n transistor npn npn provide one second keep voltage to these silicon controlled rectifiers so that these silicon controlled rectifiers remain in the bolt-lock state in during electrostatic discharge pulses appears at the static discharge of one of first power circuit or contact pins.
42. electrostatic discharge protective integrated circuit as claimed in claim 41, it is characterized in that comprising: these silicon controlled rectifiers comprise that in addition at least one is connected in the silicon controlled rectifier between first and second power circuit, and remaining silicon controlled rectifier then is connected between a corresponding contact pins and the second source circuit.
43. electrostatic discharge protective integrated circuit as claimed in claim 42 is characterized in that comprising: in during static discharge, electrostatic discharge pulses is disposed to first power circuit by one of these contact pins via the second source circuit.
44. electrostatic discharge protective integrated circuit as claimed in claim 42 is characterized in that comprising: in during static discharge, electrostatic discharge pulses is disposed to one of these contact pins by first power circuit via the second source circuit.
45. electrostatic discharge protective integrated circuit as claimed in claim 42 is characterized in that comprising: in during static discharge, electrostatic discharge pulses is disposed to another contact pins by one of these contact pins via the second source circuit.
46. electrostatic discharge protective integrated circuit as claimed in claim 41 is characterized in that comprising: this control circuit comprises a resistance capacitance delay circuit in addition.
47. electrostatic discharge protective integrated circuit as claimed in claim 41 is characterized in that comprising: this control circuit comprises that in addition an output is connected to the grid of each p type and n transistor npn npn.
48. the method for an electrostatic discharge protective comprises:
Provide one to have the silicon controlled rectifier of keeping voltage;
The first transistor and the silicon controlled rectifier of one first conductivity type is one-body molded, and the first transistor has first grid;
The transistor seconds and the silicon controlled rectifier of one second conductivity type is one-body molded, and transistor seconds has second grid;
What provide that one first signal to first and second grid improves silicon controlled rectifier keeps voltage so that its unlikely bolt-lock;
What provide that a secondary signal to first and second grid reduces silicon controlled rectifier keeps voltage so that it remains in the bolt-lock state.
49. the method for electrostatic discharge protective as claimed in claim 48 is characterized in that: other comprises that the voltage of keeping with silicon controlled rectifier is increased on the supply voltage.
50. the method for electrostatic discharge protective as claimed in claim 48 is characterized in that: other comprises that the voltage drop of keeping with silicon controlled rectifier is low to moderate under the supply voltage.
51. the method for electrostatic discharge protective as claimed in claim 48 is characterized in that: other comprises silicon controlled rectifier is connected between a contact pins and the power circuit.
52. the method for electrostatic discharge protective as claimed in claim 48 is characterized in that: other comprises silicon controlled rectifier is connected between the different power circuit.
53. one kind provides the method for electrostatic discharge protective to internal circuit, comprising:
First power circuit with first voltage level is provided;
Second source circuit with second voltage level is provided;
A plurality of contact pins are provided;
A plurality of silicon controlled rectifiers are provided, and each silicon controlled rectifier all comprises a p transistor npn npn and a n transistor npn npn, and this p type and n transistor npn npn and silicon controlled rectifier are one-body molded;
Via p type and n transistor npn npn provide one first keep voltage to these silicon controlled rectifiers so that the unlikely bolt-lock of these silicon controlled rectifiers; And
Via p type and n transistor npn npn provide one second keep voltage to these silicon controlled rectifiers so that these silicon controlled rectifiers remain in the bolt-lock state in during electrostatic discharge pulses appears at the static discharge of one of first power circuit or contact pins.
54. a kind of method that internal circuit is provided electrostatic discharge protective as claimed in claim 53, it is characterized in that: other comprises is connected between first and second power circuit at least one silicon controlled rectifier of these silicon controlled rectifiers, and remaining silicon controlled rectifier is connected between a corresponding contact pins and the second source circuit.
55. as claimed in claim 54ly a kind ofly provide the method for electrostatic discharge protective to internal circuit, it is characterized in that: other comprises electrostatic discharge pulses is disposed to first power circuit by one of contact pins via the second source circuit.
56. as claimed in claim 54ly a kind ofly provide the method for electrostatic discharge protective to internal circuit, it is characterized in that: other comprises electrostatic discharge pulses is disposed to one of contact pins by first power circuit via the second source circuit.
57. as claimed in claim 54ly a kind ofly provide the method for electrostatic discharge protective to internal circuit, it is characterized in that: other comprises electrostatic discharge pulses is disposed to another contact pins by one of contact pins via the second source circuit.
CN 200410039312 2004-01-19 2004-01-19 Static discharging protectire circuit and static discharging protective method Pending CN1649142A (en)

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Cited By (11)

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Publication number Priority date Publication date Assignee Title
CN101587890B (en) * 2008-05-23 2011-05-04 中芯国际集成电路制造(北京)有限公司 Layout method of static discharge protective structure
CN102254912A (en) * 2011-07-13 2011-11-23 浙江大学 Controlled silicon device under auxiliary trigger of embedded P-type MOS (Metal Oxide Semiconductor) transistor
CN101236967B (en) * 2008-03-05 2012-04-11 浙江大学 A built-in controllable silicon for reverse phase part
CN102903716A (en) * 2011-07-29 2013-01-30 飞思卡尔半导体公司 Combined output buffer and ESD diode device
CN104078460A (en) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 Electrostatic protection structure and electrostatic protection circuit
TWI484313B (en) * 2013-08-05 2015-05-11 Nuvoton Technology Corp Reference voltage generating circuit and voltage adjusting device having negative charge protection mechanism of the same
CN104078459B (en) * 2013-03-28 2016-12-28 中芯国际集成电路制造(上海)有限公司 Electrostatic preventing structure and electrostatic discharge protective circuit
WO2018053991A1 (en) * 2016-09-26 2018-03-29 深圳市汇顶科技股份有限公司 Electrostatic-discharge protection circuit applied to integrated circuit
US10134725B2 (en) 2016-09-26 2018-11-20 Shenzhen GOODIX Technology Co., Ltd. Electrostatic discharge protection circuit applied in integrated circuit
CN113921516A (en) * 2021-09-17 2022-01-11 杭州傲芯科技有限公司 Electrostatic discharge protection module and device using same
CN113921516B (en) * 2021-09-17 2024-09-27 杭州傲芯科技有限公司 Electrostatic discharge protection module and device using same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236967B (en) * 2008-03-05 2012-04-11 浙江大学 A built-in controllable silicon for reverse phase part
CN101587890B (en) * 2008-05-23 2011-05-04 中芯国际集成电路制造(北京)有限公司 Layout method of static discharge protective structure
CN102254912A (en) * 2011-07-13 2011-11-23 浙江大学 Controlled silicon device under auxiliary trigger of embedded P-type MOS (Metal Oxide Semiconductor) transistor
CN102254912B (en) * 2011-07-13 2012-10-24 浙江大学 Controlled silicon device under auxiliary trigger of embedded P-type MOS (Metal Oxide Semiconductor) transistor
CN102903716B (en) * 2011-07-29 2016-12-21 飞思卡尔半导体公司 The output buffer of combination and ESD diode device
CN102903716A (en) * 2011-07-29 2013-01-30 飞思卡尔半导体公司 Combined output buffer and ESD diode device
CN104078459B (en) * 2013-03-28 2016-12-28 中芯国际集成电路制造(上海)有限公司 Electrostatic preventing structure and electrostatic discharge protective circuit
CN104078460A (en) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 Electrostatic protection structure and electrostatic protection circuit
CN104078460B (en) * 2013-03-28 2017-02-08 中芯国际集成电路制造(上海)有限公司 Electrostatic protection structure and electrostatic protection circuit
TWI484313B (en) * 2013-08-05 2015-05-11 Nuvoton Technology Corp Reference voltage generating circuit and voltage adjusting device having negative charge protection mechanism of the same
WO2018053991A1 (en) * 2016-09-26 2018-03-29 深圳市汇顶科技股份有限公司 Electrostatic-discharge protection circuit applied to integrated circuit
US10134725B2 (en) 2016-09-26 2018-11-20 Shenzhen GOODIX Technology Co., Ltd. Electrostatic discharge protection circuit applied in integrated circuit
CN109478549A (en) * 2016-09-26 2019-03-15 深圳市汇顶科技股份有限公司 ESD protection circuit applied to integrated circuit
CN109478549B (en) * 2016-09-26 2021-05-11 深圳市汇顶科技股份有限公司 Electrostatic discharge protection circuit for integrated circuit
CN113921516A (en) * 2021-09-17 2022-01-11 杭州傲芯科技有限公司 Electrostatic discharge protection module and device using same
CN113921516B (en) * 2021-09-17 2024-09-27 杭州傲芯科技有限公司 Electrostatic discharge protection module and device using same

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