CN104078460B - Electrostatic protection structure and electrostatic protection circuit - Google Patents
Electrostatic protection structure and electrostatic protection circuit Download PDFInfo
- Publication number
- CN104078460B CN104078460B CN201310106740.9A CN201310106740A CN104078460B CN 104078460 B CN104078460 B CN 104078460B CN 201310106740 A CN201310106740 A CN 201310106740A CN 104078460 B CN104078460 B CN 104078460B
- Authority
- CN
- China
- Prior art keywords
- type
- region
- positive
- doping area
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention provides an electrostatic protection structure and an electrostatic protection circuit. The electrostatic protection structure comprises a PMOS transistor located in a first region of a first N-type trap, a first base doping region located in a second region of the first N-type trap, an NMOS transistor located in a third region of a first P-type trap, a plurality of independent second base doping regions located in a fourth region of the first P-type trap, a first N-type doping region surrounding the multiple independent second base doping regions, and a second N-type doping region surrounding the first N-type doping region and the multiple independent second base doping regions. The source region and grid electrode of the PMOS transistor are connected with a power supply end. The drain region of the PMOS transistor is connected with an input/output interface end. The first base doping region is connected with an external trigger voltage regulator circuit. The drain region of the NMOS transistor is connected with the input/output interface end. The grid electrode and source region of the NMOS transistor are connected with a grounding end. The second base doping regions are connected with the external trigger voltage regulator circuit. According to the electrostatic protection structure, paths of electrostatic discharge are increased, and electrostatic discharge efficiency is improved. According to the electrostatic protection structure and the electrostatic protection circuit, paths of electrostatic discharge of the electrostatic protection structure are increased, and electrostatic discharge efficiency is improved.
Description
Technical field
The present invention relates to electrostatic protection field, particularly to a kind of electrostatic preventing structure and electrostatic discharge protective circuit.
Background technology
In the making and application of IC chip, with the continuous improvement of super large-scale integration Technology,
Current CMOS production of integrated circuits technology comes into the deep-submicron stage, and the size of MOS device constantly reduces, gate oxide
Thickness more and more thinner, MOS device voltage endurance capability is remarkably decreased, static discharge（Electrostatic Discharge, ESD）
Harm to integrated circuit becomes more and more significant.Therefore, the protection that integrated circuit is carried out with ESD also becomes particularly important.
In order to strengthen the protective capacities to electrostatic, mostly at the input/output interface end of chip（I/O pad）Connect electrostatic
Protection circuit, electrostatic discharge protective circuit is the discharge path that internal circuit in chip provides electrostatic induced current, to avoid the electrostatic will be interior
Portion's circuit punctures.
In existing electrostatic discharge protective circuit, conventional device includes the nmos pass transistor of grounded-grid, grid connects power supply
PMOS transistor and silicon controlled rectifier (SCR)（SCR, Silicon Controlled Rectifier）Deng.Due to grounded-grid
Nmos pass transistor is compatible well with CMOS industry, and the nmos pass transistor of grid ground connection is widely used.
With reference to Fig. 1, Fig. 1 is the structural representation of existing electrostatic discharge protective circuit, and the drain electrode of nmos pass transistor 13 is defeated with input
Outgoing interface end 15 is connected, and the grid of nmos pass transistor 13 and source electrode are connected with earth terminal 16, when is produced from input/output interface end 15
When the big electrostatic potential of life or electrostatic induced current, electrostatic is discharged into earth terminal by the parasitic NPN audion in nmos pass transistor 13
16, specifically refer to Fig. 2, Fig. 2 is the cross-sectional view of nmos pass transistor in Fig. 1, including：Semiconductor substrate 100, described
There is in Semiconductor substrate 100 p-well 101, Semiconductor substrate 100 has the grid 103 of nmos pass transistor, grid 103 both sides
P-well 101 in there is drain region 102 and source region 104, the drain region 102 of nmos pass transistor and the input/output interface of nmos pass transistor
End 15 is connected, and the source region 104 of nmos pass transistor is connected with earth terminal 16 with grid 103, the p-well of described source region 104 side
Also there is in 101 p-type doped region 105, p-type doped region 105 is connected with earth terminal 16, p-type doped region 105 and source region 104 it
Between there is fleet plough groove isolation structure 106, the drain region 102 of nmos pass transistor constitutes the collecting zone of parasitic NPN audion 17, and NMOS is brilliant
The source region 104 of body pipe constitutes the launch site of parasitic NPN audion 17, and the p-well 101 of grid 103 bottom constitutes parasitic NPN audion
17 base, when electrostatic charge is gathered at input/output interface end 15, electric current flows to p-type from drain region 102 through well region resistance 18
Doped region 105 area so that between the p-well 101 of grid 103 bottom and earth terminal 16 produce electric potential difference, when electric potential difference be more than parasitism
During the threshold voltage of NPN triode 17, parasitic NPN audion 17 is in conducting state, and now electric current just flows to source region from drain region 102
104, discharge the electrostatic that input/output interface end 15 is gathered.
Existing esd protection circuit discharging efficiency when being discharged is relatively low.
Content of the invention
The problem that the present invention solves is to improve the efficiency of Electro-static Driven Comb.
For solving the above problems, technical solution of the present invention provides a kind of electrostatic preventing structure, including：Semiconductor substrate,
There is in described Semiconductor substrate the first N-type well region and the first P type trap zone, described first N-type well region includes first area and
Two regions, described first P type trap zone includes the 3rd region and the 4th region；In the first area of the first N-type well region
PMOS transistor, described PMOS transistor includes the grid in the first N-type well region and is located at grid both sides first N-type well region
Interior source/drain region, the source region of PMOS transistor is connected with power end with grid, and the drain region of PMOS transistor and input and output connect
Mouth end is connected；The first base doping area in the second area of the first N-type well region, the doping class in the first base doping area
Type is N-type, and the first base doping area is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electric potential difference
When, described external trigger voltage-regulating circuit drags down the current potential in the first base doping area；The 3rd region positioned at the first P type trap zone
Interior nmos pass transistor, described nmos pass transistor includes the grid in the first P type trap zone and is located at grid both sides first p-type
Source/drain region in well region, the drain region of nmos pass transistor is connected with input/output interface end, the grid of nmos pass transistor and source region
It is connected with earth terminal；The second some discrete base doping area in the 4th region of the first P type trap zone, described second
The doping type in base doping area is p-type, and the second base doping area is connected with external trigger voltage-regulating circuit, works as power end
When producing instantaneous electric potential difference, described external trigger voltage-regulating circuit draws high the current potential in the second base doping area；Positioned at the 4th area
The first n-type doping area in domain, described first n-type doping area surrounds described some the second discrete base doping areas, the first N-type
Doped region is connected with input/output interface end；The second n-type doping area in the 4th region, described second n-type doping area bag
Enclose described first n-type doping area, the second n-type doping area is connected with earth terminal.
Optionally, the first base doping area and the source region of PMOS and Semiconductor substrate constitute the first positive-negative-positive parasitism three poles
Pipe, the first base doping area constitutes the second positive-negative-positive parasitic triode with the drain region of PMOS and Semiconductor substrate.
Optionally, described some the second discrete base doping areas and the first n-type doping area and the second n-type doping area are constituted
Some NPN transistors in parallel.
Optionally, described first n-type doping area includes the sub- doped region of some N-types, and the quantity of the sub- doped region of N-type is equal to second
The quantity in base doping area, the sub- doped region of each N-type surrounds corresponding second base doping area.
Optionally, described external trigger voltage-regulating circuit includes RC coupling circuit and Nverter circuit, described RC coupling
Loop includes coupled capacitor and the coupling resistance connected, and the other end of coupling resistance connects to power end, coupled capacitor another
End connect to earth terminal, RC switching node connects to Nverter circuit, described Nverter circuit include connect the first phase inverter,
Second phase inverter and the 3rd phase inverter, the input of the first phase inverter is connected with RC switching node, the output of the first phase inverter
End is connected with the input of the second phase inverter, the input of the outfan of the second phase inverter and the 3rd phase inverter and the first base
Area's doped region is connected, and the outfan of the 3rd phase inverter is connected with the second base doping area.
Optionally, described first phase inverter, the second phase inverter and the 3rd phase inverter are CMOS inverter or TTL phase inverter.
Optionally, described electrostatic preventing structure also includes switch NMOS transistor, the drain electrode of switch NMOS transistor and electricity
Source is connected, and the source electrode of switch NMOS transistor is connected with earth terminal, and the grid of switch NMOS transistor is anti-phase with first
The outfan of device is connected.
Optionally, also there is in described first N-type well region the 3rd n-type doping area, the 3rd n-type doping area surrounds described PMOS
Transistor and the first base doping area, the 3rd n-type doping area is connected with power end.
Optionally, also there is in described first P type trap zone the first p-type doped region, the first p-type doped region surrounds described NMOS
Transistor and the second base doping area, the first n-type doping area and the second n-type doping area, the first p-type doped region is connected with earth terminal
Connect.
Optionally, also there is between described nmos pass transistor and the second n-type doping area the second p-type doped region, the second p-type is mixed
The two ends in miscellaneous area are contacted with the first p-type doped region.
Optionally, described PMOS transistor is to share source and drain PMOS transistor, and described shared source and drain PMOS transistor includes
Some first source regions of alternate intervals distribution and the first drain region in the first N-type well region, and it is located at the first adjacent source region
And first first grid in the first N-type well region between drain region, some first grids and the first source region be connected with power end,
Some first drain regions are connected with input/output interface end, the first base doping area and some first source regions and Semiconductor substrate
Constitute some first positive-negative-positive parasitic triodes in parallel, the first base doping area and some first drain regions and Semiconductor substrate
Constitute some second positive-negative-positive parasitic triodes in parallel.
Optionally, described second area on the bearing of trend that first grid extends to two ends, mix by described first base
Miscellaneous area is located in second area, and the first base doping area is equal to first along the length in the first source region and the first drain region distribution arrangement
Source region and the dispersion of distribution in the first drain region, the width in the first base doping area is 0.5～5 micron.
Optionally, in the first base doping area, dopant ion is phosphonium ion, arsenic ion or antimony ion.
Optionally, described nmos pass transistor is to share source and drain nmos pass transistor, and described shared source and drain nmos pass transistor includes
Some second source regions of alternate intervals distribution and the second drain region in the first P type trap zone, and it is located at the second adjacent source region
And second second grid in the first P type trap zone between drain region, some second source regions are connected with earth terminal with second grid,
Some second drain regions are connected with input/output interface end.
Optionally, the dopant ion in the second base doping area is boron ion, gallium ion or indium ion.
Optionally, also there is in described Semiconductor substrate the second N-type well region and the second P type trap zone, the second N-type well region and
Two P type trap zone are located between the first N-type well region and the first P type trap zone, the first N-type well region, the second P type trap zone, the second N-type well region
It is alternately distributed successively in Semiconductor substrate with the first P type trap zone.
Optionally, there is in described second P type trap zone the second p-type doped region, the second p-type doped region is connected with earth terminal
Connect.
Technical solution of the present invention provides a kind of electrostatic discharge protective circuit, including：PMOS transistor, the source region of PMOS transistor
It is connected with power end with grid, the drain region of PMOS transistor is connected with input/output interface end;Nmos pass transistor, NMOS is brilliant
The drain region of body pipe is connected with input/output interface end, and the grid of nmos pass transistor is connected with earth terminal with source region；First PNP
Type parasitic triode, the launch site of the first positive-negative-positive parasitic triode is connected with power end, the first positive-negative-positive parasitic triode
Collecting zone by being connected with earth terminal, the first base of positive-negative-positive parasitic triode and being connected of external trigger voltage-regulating circuit
Connect, when power end produces instantaneous electric potential difference, described external trigger voltage-regulating circuit drags down the first positive-negative-positive parasitic triode base
The current potential in area；Second positive-negative-positive parasitic triode, the launch site of the second positive-negative-positive parasitic triode is connected with input/output interface end
Connect, the connection of collecting zone earth terminal, the base of the second positive-negative-positive parasitic triode and the external trigger of the second positive-negative-positive parasitic triode
Being connected of voltage-regulating circuit, when power end produces instantaneous electric potential difference, described external trigger voltage-regulating circuit drags down the
The current potential of two positive-negative-positive parasitic triode bases；Some NPN type triode in parallel, the transmitting of some NPN type triode in parallel
Area is connected with earth terminal, and some collecting zones of NPN type triode in parallel are connected with input/output interface end, some parallel connections
The base of NPN type triode is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electric potential difference, described
External trigger voltage-regulating circuit draws high the current potential of the first NPN type parasitic triode base.
Optionally, described external trigger voltage-regulating circuit includes RC coupling circuit and Nverter circuit, described RC coupling
Loop includes coupled capacitor and the coupling resistance connected, and the other end of coupling resistance connects to power end, coupled capacitor another
End connect to earth terminal, RC switching node connects to Nverter circuit, described Nverter circuit include connect the first phase inverter,
Second phase inverter and the 3rd phase inverter, the input of the first phase inverter is connected with RC switching node, the output of the first phase inverter
End is connected with the input of the second phase inverter, the input of the outfan of the second phase inverter and the 3rd phase inverter, the first positive-negative-positive
The base of the base of parasitic triode and the second positive-negative-positive parasitic triode is connected, the outfan of the 3rd phase inverter with some
The base of NPN type triode in parallel is connected.
Compared with prior art, technical solution of the present invention has advantages below：
The source region of the electrostatic preventing structure of technical solution of the present invention, the first base doping area and PMOS and Semiconductor substrate
Constitute the first positive-negative-positive parasitic triode, the first base doping area constitutes the second positive-negative-positive with the drain region of PMOS and Semiconductor substrate
Parasitic triode, described some the second discrete base doping areas and the first n-type doping area and the second n-type doping area constitute some
NPN transistor in parallel, therefore when input/output interface and/or power end accumulation electrostatic, electrostatic is posted by the first positive-negative-positive
The Electro-static Driven Comb path that raw audion, the second positive-negative-positive parasitic triode or some NPN transistors in parallel are constituted is discharged into and connects
Ground terminal, increased the path of Electro-static Driven Comb, improves the efficiency of Electro-static Driven Comb, in addition, the second base doping area and the first base
Doped region is connected with external trigger voltage-regulating circuit respectively, thus controlling first by external trigger voltage-regulating circuit
The base current potential of positive-negative-positive parasitic triode, the second positive-negative-positive parasitic triode and some NPN transistors in parallel, makes first
Positive-negative-positive parasitic triode, the second positive-negative-positive parasitic triode are changed into circuit from passive triggering and conducting and control conducting, strengthen to posting
The control ability of raw audion, prevents the electrostatic gathering from can not timely and effectively discharge.
Further, described PMOS transistor is to share source and drain PMOS transistor, the first base doping area and some first sources
Area and Semiconductor substrate constitute some first positive-negative-positive parasitic triodes in parallel, the first base doping area and some first leakages
Area and Semiconductor substrate constitute some second positive-negative-positive parasitic triodes in parallel, when power end and input/output interface end collection
When having gathered electrostatic charge, electrostatic charge can be released by some first positive-negative-positive parasitic triodes and the second positive-negative-positive parasitic triode
It is put into earth terminal, increased the path of Electro-static Driven Comb, improve the efficiency of Electro-static Driven Comb.
Further, the second area of the first N-type well region is on the bearing of trend that first grid extends to two ends, and described
One base doping area is located in second area, and the first base doping area is along the length in the first source region and the first drain region distribution arrangement
Equal to the dispersion of distribution of the first source region and the first drain region, the width in the first base doping area is 0.5～5 micron, not only makes the
The layout area in one base doping area is less, and makes between the first base doping area and some first source regions and the first drain region
Distance equal, so that the first base doping area is to each when the first base doping area is connected with external trigger voltage-regulating circuit
The control ability of individual first positive-negative-positive parasitic triode and the second positive-negative-positive parasitic triode is identical, improves the uniform of Electro-static Driven Comb
Property and the stability of electrostatic discharge protective circuit.
Further, the external trigger voltage-regulating circuit of the composition of RC coupling circuit and Nverter circuit can drag down the first base
The current potential of area's doped region and the current potential that draws high the second base doping area are so that the triggering of parasitic transistor in electrostatic preventing structure
Conducting is not the passive triggering after build-up of electrostatic charges, but parasitic brilliant by the active control of external trigger voltage-regulating circuit
The conducting of body pipe, improves the susceptiveness of electrostatic preventing structure release electrostatic.
Further, described first n-type doping area includes the sub- doped region of some N-types, between the sub- doped region of adjacent N-type contact or
Do not contact, the quantity of the sub- doped region of N-type is equal to the quantity in the second base doping area, the sub- doped region of each N-type surrounds corresponding the
Two base doped regions so that the second base doping area, the sub- doped region of some N-types, the second base doping area and the second n-type doping area
Between composition some NPN transistor electrical parameters（Including threshold voltage etc.）Relatively, when the second base doping area with
It is easy to the control of some NPN transistors turns on the uniformity with Electro-static Driven Comb when external trigger voltage-regulating circuit is connected.
Brief description
Fig. 1～Fig. 2 is the structural representation of prior art electrostatic discharge protective circuit；
Fig. 3～5 are the structural representation of embodiment of the present invention electrostatic preventing structure；
Fig. 6 is the structural representation of embodiment of the present invention electrostatic discharge protective circuit.
Specific embodiment
Existing electrostatic discharge protective circuit passes through parasitic NPN audion 17（With reference to Fig. 2）Electric discharge, the path of its electric discharge only has one
Bar, and be passive triggering during the electric discharge of parasitic NPN triode ON, that is, want electrostatic charge to accumulate one at input/output interface end 15
During fixed electrostatic charge, electric current flows to p-type doped region 105 area so that grid 103 bottom from drain region 102 through well region resistance 18
P-well region and earth terminal 16 between produce electric potential difference, when electric potential difference be more than parasitic NPN audion 17 threshold voltage when, will be defeated
Enter output interface end 15 accumulation electrostatic charge release so that the efficiency of the Electro-static Driven Comb of existing electrostatic discharge protective circuit relatively
Low.
For solving the above problems, the invention provides a kind of electrostatic preventing structure, the first area of the first N-type well region has
PMOS transistor, in the second area of the first N-type well region, there is the first base doping area, the doping in the first base doping area
Type is N-type, and the source region of PMOS is connected with power end with grid, and the drain region of PMOS transistor is connected with input/output interface end
Connect, the first base doping area is connected with the outfan of external trigger voltage-regulating circuit；3rd region tool of the first P type trap zone
There is nmos pass transistor, the second some discrete base doping area in the 4th region of the first P type trap zone, described second base is mixed
The doping type in miscellaneous area is p-type, and the second base doping area is connected with external trigger voltage-regulating circuit, surrounds described some points
The described first n-type doping area in the second vertical base doping area, the first n-type doping area is connected with input/output interface end, surrounds
Described first n-type doping area and the second n-type doping area in some the second discrete base doping areas, the second n-type doping area with connect
Ground terminal is connected.In above-mentioned electrostatic preventing structure, the first base doping area constitutes first with the source region of PMOS and Semiconductor substrate
Positive-negative-positive parasitic triode, the first base doping area constitutes the second positive-negative-positive parasitism three poles with the drain region of PMOS and Semiconductor substrate
Pipe, described some the second discrete base doping areas are some in parallel with the first n-type doping area and the second n-type doping area composition
NPN transistor, therefore when input/output interface and/or power end accumulation electrostatic, electrostatic passes through the first positive-negative-positive parasitism three poles
The Electro-static Driven Comb path that pipe, the second positive-negative-positive parasitic triode or some NPN transistors in parallel are constituted is discharged into earth terminal,
Increased the path of Electro-static Driven Comb, improve the efficiency of Electro-static Driven Comb, in addition, the second base doping area and the first base doping area
It is connected with external trigger voltage-regulating circuit respectively, thus controlling the first positive-negative-positive to post by external trigger voltage-regulating circuit
The base current potential of raw audion, the second positive-negative-positive parasitic triode and some NPN transistors in parallel, makes the first positive-negative-positive parasitic
Audion, the second positive-negative-positive parasitic triode are changed into circuit from passive triggering and conducting and control conducting, strengthen to parasitic triode
Control ability, prevents the electrostatic gathering from can not timely and effectively discharge.
Below in conjunction with specific embodiments, the electrostatic preventing structure to the present invention and electrostatic discharge protective circuit are detailed Jie
Continue.Fig. 3 is the structural representation at the vertical view visual angle of embodiment of the present invention electrostatic preventing structure（Each port and external circuit in Fig. 3
All not shown）, Fig. 4 is the structural representation along line of cut AB direction for the Fig. 3, and Fig. 5 is the structural representation along line of cut CD direction for the Fig. 3
Figure, Fig. 6 is the structural representation of embodiment of the present invention electrostatic discharge protective circuit.
In conjunction with reference to Fig. 3 and Fig. 4, described electrostatic preventing structure, including：
Semiconductor substrate 300, has the first N-type well region 301 and the first P type trap zone 302 in described Semiconductor substrate 300,
Described first N-type well region 301 includes first area and second area, and described first P type trap zone 302 includes the 3rd region and the 4th
Region；PMOS transistor in the first area of the first N-type well region 301, described PMOS transistor is included positioned at the first N-type
Grid on well region 301 and the source region being located in grid both sides the first N-type well region 301 and drain region, the source region of PMOS transistor and
Grid is connected with power end Vdd, and the drain region of PMOS transistor is connected with input/output interface end I/O；Positioned at the first N-type trap
The first base doping area 308 in the second area in area 301, the doping type in the first base doping area 308 is N-type, the first base
Area's doped region 308 is connected with the second outfan c end of external trigger voltage-regulating circuit 325, when power end Vdd produces instantaneously
During electric potential difference, described external trigger voltage-regulating circuit 325 drags down the current potential in the first base doping area 308；Positioned at the first p-type trap
Nmos pass transistor in 3rd region in area 302, described nmos pass transistor includes the grid 311 in the first P type trap zone 302
With the source region in grid 311 both sides the first P type trap zone 302 and drain region, the drain region of nmos pass transistor and input/output interface
End I/O is connected, and the grid of nmos pass transistor is connected with earth terminal Vss with source region；Described electrostatic preventing structure（In conjunction with reference
Fig. 3 and Fig. 5）Also include：The second some discrete base doping area 314 in the 4th region of the first P type trap zone 302,
The doping type in described second base doping area 314 is p-type, the second base doping area 314 and external trigger voltage-regulating circuit
325 the 3rd outfan d end（With reference to Fig. 4 and Fig. 5）It is connected, when power end Vdd produces instantaneous electric potential difference, described outside is touched
Send out the current potential that voltage-regulating circuit 325 draws high the second base doping area 314；In the 4th region of the first P type trap zone 302
First n-type doping area 315, described first n-type doping area 315 surrounds described some the second discrete base doping areas 314, and first
N-type doping area 315 is connected with input/output interface end I/O；The second N-type in the 4th region of the first P type trap zone 302 is mixed
Miscellaneous area 316, described second n-type doping area 316 surrounds described first n-type doping area 315 and some the second discrete base dopings
Area 314, the second n-type doping area 316 is connected with earth terminal Vss.
Specifically, described Semiconductor substrate 300 is p-type doped substrate, and the material of described Semiconductor substrate 300 can be single
Crystal silicon（Si）, monocrystalline germanium（Ge）, or SiGe（GeSi）, carborundum（SiC）；It can also be silicon-on-insulator（SOI）, on insulator
Germanium（GOI）；Or can also be other materials, such as GaAs etc. III-V compounds of group.
Also there is between first N-type well region 301 and the first P type trap zone 302 the second adjacent N-type well region 304 and the second p-type
Well region 303, the first N-type well region 301, the second P type trap zone 303, the second N-type well region 304 and the first P type trap zone 302 are in quasiconductor
It is alternately distributed successively in substrate, in described second P type trap zone 303, there is the second p-type doped region 309（With reference to Fig. 4）, the second p-type
Doped region 309 is connected with earth terminal Vss, and described second p-type doped region 309 is as the end of PMOS transistor region Electro-static Driven Comb
Mouthful, in described second N-type well region 304, also there is the 4th type doped region 318, the 4th type doped region 318 is connected with power end Vdd
Connect so that the PN of the second N-type well region 304 and the second P type trap zone 303 composition is reverse-biased, prevent formation in the first N-type well region 301
There is latch-up, thus improving electrostatic protection between the nmos pass transistor being formed in PMOS transistor and the first P type trap zone 302
The stability of structure.In Fig. 3, described second P type trap zone 303, the second N-type well region 304 and the first P type trap zone 302 are located at a N
The right of type well region 301（X-axis positive direction）, in other embodiments of the invention, described second P type trap zone 303, the second N-type
Well region 304 and the first P type trap zone 302 may be located at the left side of the first N-type well region 301（X-axis negative direction）, top（Y-axis is square
To）Or it is following（Y-axis negative direction）.
Described first N-type well region 301 includes first area and second area, and second area is adjacent with first area, and first
There is in region PMOS transistor, there is in second area the first base doping area 308, the first base doping area 308 doping class
Type is N-type, and in the first base doping area 308, dopant ion is phosphonium ion, arsenic ion or antimony ion, the first base doping area 308
Formation process can with existing formed nmos pass transistor source-drain area technique mutually compatible, need not carry out extra photoetching and
Injection technology, to save manufacturing cost.
In described first N-type well region 301, also there is the 3rd n-type doping area 307, the 3rd n-type doping area 307 surrounds described
PMOS transistor and the first base doping area 308（With reference to Fig. 3）, the 3rd n-type doping area 307 is connected with power end Vdd, and the 3rd
N-type doping area 307 has isolation and the effect preventing breech lock when connecting Vdd.
Described PMOS transistor can be single PMOS transistor or the common source being made up of multiple PMOS transistor
Leakage PMOS transistor, in the present embodiment, with reference to Fig. 3 and Fig. 4, described PMOS transistor is to share source and drain PMOS transistor, described
Shared source and drain PMOS transistor includes some first sources of alternate intervals distribution in the first area of the first N-type well region 301
Area 305 and the first drain region 306, the doping type in the first source region 305 and the first drain region 306 is p-type, and is located at adjacent first
The first grid 304 in the first N-type well region 301 between source region 305 and the first drain region 306, some first grids 304 and first
Source region 305 is connected with power end Vdd, and some first drain regions 306 are connected with input/output interface end I/O, and the first base is mixed
Miscellaneous area 308 constitutes some first positive-negative-positive parasitic triode T1 in parallel with some first source regions 305 and Semiconductor substrate 300
（With reference to Fig. 4, in figure only illustrates a first positive-negative-positive parasitic triode）, wherein, the first base doping area 308 is as a PNP
The base of type parasitic triode T1, the first source region 305 is as the launch site of the first positive-negative-positive parasitic triode T1, Semiconductor substrate
300 as the first positive-negative-positive parasitic triode T1 collecting zone；First base doping area 308 and some first drain regions 306 and half
Conductor substrate 300 constitutes the second positive-negative-positive parasitic triode T2 of some parallel connections（One the second positive-negative-positive parasitism three is only shown in Fig. 4
Pole pipe）, wherein, as the base of the second positive-negative-positive parasitic triode T2, the first drain region 306 is as in the first base doping area 308
The launch site of two positive-negative-positive parasitic triode T2, Semiconductor substrate 300 is as the collecting zone of the second positive-negative-positive parasitic triode T2.This
In inventive embodiments, some first source regions 305 of shared source and drain PMOS transistor and the first drain region 306, the first base doping area
Some first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode can be formed between 308 and Semiconductor substrate 300
T2, when power end Vdd and/or input/output interface end I/O has gathered electrostatic charge, electrostatic charge can pass through some first
Positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2, through P-type semiconductor substrate 300, the second P type trap zone 303,
Second p-type doped region 309 is discharged into earth terminal Vss, increased the path of Electro-static Driven Comb, improves the efficiency of Electro-static Driven Comb.
In the present embodiment, the extension side that the second area of the first N-type well region 301 extends to two ends positioned at first grid 304
To（Y-axis negative direction）On（With reference to Fig. 3）, described first base doping area 308 is located in second area, the first base doping area
308 along in the first source region 305 and the first drain region 306 distribution arrangement（X-axis direction）Length be equal to the first source region 305 and the first leakage
The dispersion of distribution in area 306, the width in the first base doping area 308 is 0.5～5 micron, not only makes the first base doping area 308
Layout area less, and make between the first base doping area 308 and some first source regions 305 and the first drain region 306
Apart from equal, the electrical parameter of the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2 of formation（Including threshold
Threshold voltage etc.）Relatively, when the first base doping area 308 is connected with the second end c end of external trigger voltage-regulating circuit 325
When so that the first base doping area 308（Base as the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2
Area）Identical to the control ability of each first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2, improve quiet
The uniformity of electricity release and the stability of electrostatic discharge protective circuit.In other embodiments of the invention, first area and the secondth area
Domain can also be other arrangement modes, it should be noted that the arrangement mode of first area and second area should not limit this
The protection domain of invention.
Described first P type trap zone 302 includes the 3rd region and the 4th region, and the 3rd region and the 4th region are adjacent, and the 3rd
There is in region nmos pass transistor, there is in the 4th region some the second discrete base doping areas 314, the second base doping area
314 doping type is p-type, and in the second base doping area 314, dopant ion is boron ion, gallium ion or indium ion, the first base
The formation process of area's doped region 308 can be mutually compatible with the technique of the existing source-drain area forming PMOS transistor, need not carry out
Extra photoetching and injection technology, to save manufacturing cost.
In described first P type trap zone, 302 also have the first p-type doped region 310, and the first p-type doped region 310 surrounds described
Nmos pass transistor and the second base doping area 314, the first p-type doped region 310 is connected with earth terminal Vss, the first p-type doped region
310 have isolation and the effect preventing breech lock.
Described nmos pass transistor can be single nmos pass transistor or the common source being made up of multiple nmos pass transistors
Leakage nmos pass transistor, in the present embodiment, described nmos pass transistor is to share source and drain nmos pass transistor, and described shared source and drain NMOS is brilliant
Body pipe includes some second source regions 312 of alternate intervals distribution and the second drain region in the 3rd region of the first P type trap zone 302
313, and it is located at the second grid in the first P type trap zone 302 between the second adjacent source region 312 and the second drain region 313
311, some second source regions 312 are connected with earth terminal Vss with second grid 311, and some second drain regions 313 are connect with input and output
Mouth end I/O is connected, and the first p-type doped region 310 and some second source regions 312 and some second drain regions 313 constitute some first
NPN type parasitic triode T3, wherein, the first p-type doped region 310 is as the base of the first NPN type parasitic triode T3, the second source
As the launch site of the first NPN type parasitic triode T3, the second drain region 313 is as the first NPN type parasitic triode T3's in area 312
Collecting zone.When input/output interface end I/O has gathered electrostatic charge, some first NPN type parasitic triode T3 passively trigger
Conducting, electrostatic charge by some first NPN type parasitic triode T3, through the first P type trap zone 302, the first p-type doped region
310 are discharged into earth terminal Vss, increased the path of Electro-static Driven Comb, improve the efficiency of Electro-static Driven Comb.
In conjunction with reference to Fig. 3 and Fig. 5, originally it is in embodiment, the 4th region of the first P type trap zone 302 is located at second grid 311
The bearing of trend extending to two ends（Y-axis negative direction）On（With reference to Fig. 3）, in the 4th region, there are some the second discrete bases
Doped region 314, in the present embodiment with three the second base doping areas 314 as an example, the doping in described second base doping area
Type is p-type, and the second base doping area 314 is connected with the 3rd end d end of external trigger voltage-regulating circuit 325；First p-type
Also there is in 4th region of well region 302 first n-type doping area 315, described first n-type doping area 315 surrounds described some points
The second vertical base doping area 314, the first n-type doping area is connected with input/output interface end I/O；Described first P type trap zone 302
The 4th region in the second n-type doping area 316 of also having, described second n-type doping area 316 surrounds described first n-type doping
Area 315 and some the second discrete base doping areas 314, the second n-type doping area 316 is connected with earth terminal Vss.Some points
Vertical the second base doping area 314, the first n-type doping area 315 and the second base doping area 314 constitute some NPN transistors
T4（One NPN transistor is only shown in Fig. 5）, the wherein second base doping area 314 as the base of NPN transistor T4,
As the collecting zone of NPN transistor T4, the second n-type doping area 316 is as NPN transistor T4's in the first n-type doping area 315
Launch site, the electrostatic charge that input/output interface end I/O gathers can be discharged into earth terminal by some NPN transistor T4,
Thus improve the path of Electro-static Driven Comb, and, the layout structure of the NPN transistor in the embodiment of the present invention：First N-type is mixed
Miscellaneous area 315 surrounds some the second discrete base doping areas 314, and the second n-type doping area 316 surrounds described first n-type doping area
315 and some the second discrete base doping areas 314, both save the layout area of NPN transistor, make output interface end again
The charge that I/O gathers can pass through the second n-type doping area 316 of the first annular n-type doping area 315 annular to the periphery
Release, the active path of Electro-static Driven Comb increases.
Described first n-type doping area 315 includes the sub- doped region of some N-types, contact or do not connect between the sub- doped region of adjacent N-type
Touch, the quantity of the sub- doped region of N-type is equal to the quantity in the second base doping area, the sub- doped region of each N-type surrounds corresponding second base
Area's doped region, in the present embodiment, the quantity of the sub- doped region of described N-type is three, including the first N-type sub- doped region 315a, the 2nd N
The type doped region 315b and sub- doped region 315c of the 3rd N-type, the edge of the adjacent sub- doped region of N shape contacts with each other, to reduce cloth
Situation is amassed, and in the present embodiment, the sub- doped region of each N-type surrounds corresponding second base doping area 314 so that the second base doping
Area 314, some NPN of the composition between the sub- doped region of some N-types, the second base doping area 314 and the second n-type doping area 316
Transistor electricity parameter（Including threshold voltage etc.）Relatively, when the second base doping area 314 and external trigger Voltage Cortrol
It is easy to the control of some NPN transistors turns on the uniformity with Electro-static Driven Comb when circuit 325 is connected.
In other embodiments of the invention, the quantity in described first n-type doping area 315 is one, the first n-type doping area
The 315 all of second base doping areas 314 of encirclement.
In other embodiments of the invention, the quantity in described second n-type doping area is also multiple, the second n-type doping area
Quantity be equal to the quantity in the second base doping area, each second n-type doping area surrounds the sub- doped region of corresponding N-type and the second base
Area's doped region, if the NPN crystal of the composition between the sub- doped region of N-type and corresponding second base doping area and the second n-type doping area
Pipe electrical parameter（Including threshold voltage etc.）Essentially identical or closely, when the second base doping area is adjusted with external trigger voltage
It is easy to the control of some NPN transistors turns on the uniformity with Electro-static Driven Comb when whole circuit is connected.
First n-type doping area 315 and the second n-type doping area 316 dopant ion are phosphonium ion, arsenic ion or antimony ion, the
The formation process in one n-type doping area 315 and the second n-type doping area 316 can be with the existing source-drain area forming nmos pass transistor
Technique mutually compatible.
First p-type doped region 310 surrounds described second n-type doping area 316, described second n-type doping area 316 and a P
Type doped region 310 can contact or not contact.
Also there is between described nmos pass transistor and the second n-type doping area 316 second p-type doped region 317, the second p-type is mixed
The two ends in miscellaneous area 317 are contacted with the first p-type doped region 310, and described second p-type doped region 317 is used for isolating nmos pass transistor
And NPN triode.
Refer to Fig. 4, described external trigger voltage-regulating circuit 325 includes RC coupling circuit and Nverter circuit, described
RC coupling circuit includes coupled capacitor C and the coupling resistance R1 connecting, and the other end of coupling resistance R1 connects to power end Vdd,
The other end of coupled capacitor C connects to earth terminal Vss, and RC switching node a connects to Nverter circuit, described Nverter circuit bag
Include the first phase inverter Rv1, the second phase inverter Rv2 and the 3rd phase inverter Rv3, the input of the first phase inverter Rv1 and the RC of series connection
Switching node is connected, and the outfan of the first phase inverter Rv1 is connected with the input of the second phase inverter Rv2, the second phase inverter
The outfan of Rv2（Or the second outfan c end）It is connected with the input of the 3rd phase inverter Rv3 and the first base doping area 308
Connect, the outfan of the 3rd phase inverter Rv3（Or the 3rd outfan d end）With the second base doping area 314（With reference to Fig. 5）It is connected,
As power end Vdd because the accumulation of electrostatic produces instantaneous electric potential difference（Or transient pulse）When（Or input/output interface end I/O
The electrostatic of accumulation is transmitted to power end Vdd by the parasitic diode that the first drain region 306 and the 3rd n-type doping area 307 are constituted and makes
Power end Vdd produces instantaneous electric potential difference）, the external trigger voltage-regulating circuit of the composition of RC coupling circuit and Nverter circuit
325 current potentials that can drag down the first base doping area 308, triggering the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitism three poles
Pipe T2 conducting is so that the electrostatic charge that gathers of power end Vdd and input/output interface end I/O is parasitic through some first positive-negative-positives
Audion T1, some second positive-negative-positive parasitic triode T2, P-type semiconductor substrate 300, the second P type trap zone 303, the second p-type are mixed
Miscellaneous area 309 is discharged into earth terminal, and meanwhile, external trigger voltage-regulating circuit 325 can draw high the electricity in the second base doping area 314
Position, triggering NPN type triode T4 conducting so that the electrostatic charge that gathers of input/output interface end I/O, through by some NPN
Type audion T4, the first P type trap zone 302, the first p-type doped region 310 are discharged into earth terminal, in addition input/output interface end I/O
The electrostatic charge gathering may also pass through the first NPN type parasitic triode T3 and is discharged into ground connection by way of passive triggering and conducting
End Vss.Therefore, the first positive-negative-positive parasitic triode T1 in the electrostatic preventing structure of the embodiment of the present invention, the second positive-negative-positive are parasitic
The triggering and conducting of audion T2 and NPN type triode T4 is not the passive triggering after build-up of electrostatic charges, but is touched by outside
Send out the conducting of the active control parasitic transistor of voltage-regulating circuit 325, improve the sensitive of electrostatic preventing structure release electrostatic
Property, in addition the electrostatic preventing structure of the embodiment of the present invention can pass through some first positive-negative-positive parasitic triode T1, the second positive-negative-positive
The discharge path of parasitic triode T2, NPN type three pole T4 and the first NPN type parasitic triode T3 composition discharges simultaneously, increased
The path of electric discharge, improves the efficiency of Electro-static Driven Comb.
Described first phase inverter Rv1, the second phase inverter Rv2 and the 3rd phase inverter Rv3 are CMOS inverter or TTL is anti-phase
Device, in the present embodiment, described first phase inverter Rv1, the second phase inverter Rv2 and the 3rd phase inverter Rv3 are CMOS inverter.
Described electrostatic preventing structure also includes switch NMOS transistor N2, the drain electrode of switch NMOS transistor N2 and power end
Vdd is connected, and the source electrode of switch NMOS transistor N2 is connected with earth terminal Vss, the grid of switch NMOS transistor N2 and
The first outfan b end of one phase inverter Rv1 is connected, and switch NMOS transistor N2 increased one from power end Vdd to ground connection
The path of end Vss electric discharge.
The electrostatic discharge protective circuit that above-mentioned electrostatic preventing structure is constituted refer to Fig. 6, including：PMOS transistor P1, PMOS is brilliant
The source region of body pipe P1 is connected with power end Vdd with grid, and the drain region of PMOS transistor P1 is connected with input/output interface end I/O
Connect;Nmos pass transistor N1, the drain region of nmos pass transistor N1 is connected with input/output interface end I/O, the grid of nmos pass transistor N1
Pole is connected with earth terminal Vss with source region;First positive-negative-positive parasitic triode T1（Or some first positive-negative-positive parasitisms three in parallel
Pole pipe）, the base of the first positive-negative-positive parasitic triode T1 is connected with power end Vdd by the second dead resistance R2, a PNP
The launch site of type parasitic triode T1 is connected with power end Vdd, and the collecting zone of the first positive-negative-positive parasitic triode T1 passes through the 4th
Dead resistance R4 is connected with earth terminal Vss；Second positive-negative-positive parasitic triode T2（Or some second positive-negative-positive parasitisms three in parallel
Pole pipe）, the launch site of the second positive-negative-positive parasitic triode T2 is connected with input/output interface end I/O, the second positive-negative-positive parasitism three
The collecting zone of pole pipe T2 is connected with earth terminal Vss by trixenie resistance R3+4；First NPN type parasitic triode T3（Or
Some first NPN type parasitic triodes in parallel）, the base of the first NPN type parasitic triode T3 passes through the 5th dead resistance R5
It is connected with earth terminal Vss, the launch site of the first NPN type parasitic triode T3 is connected with earth terminal Vss, the first NPN type parasitism three
The collecting zone of pole pipe T3 is connected with input/output interface end I/O；NPN transistor T4（Some NPN transistors in parallel）, NPN
Transistor T4 collecting zone is connected with input/output interface end I/O, and the launch site of NPN transistor T4 is connected with earth terminal Vss；
Also include：External trigger voltage-regulating circuit, described external trigger voltage-regulating circuit includes RC coupling circuit and reverser electricity
Road, described RC coupling circuit includes coupled capacitor C and the coupling resistance R1 connecting, and the other end of coupling resistance R1 connects to power supply
End Vdd, the other end of coupled capacitor C connects to earth terminal Vss, and RC switching node a connects to Nverter circuit, described reverser
Circuit includes the first phase inverter Rv1, the second phase inverter Rv2 and the 3rd phase inverter Rv3 connecting, the input of the first phase inverter Rv1
End is connected with RC switching node a, the outfan of the first phase inverter Rv1（Or the first outfan b end）With the second phase inverter Rv2's
Input is connected, the outfan of the second phase inverter Rv2（Or the second outfan c end）With the input of the 3rd phase inverter Rv3,
The base of the base of one positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2 is connected, the 3rd phase inverter Rv3
Outfan（Or the 3rd outfan d end）It is connected with the base of NPN type triode T4；Also include switch NMOS transistor N2,
The drain electrode of switch NMOS transistor N2 is connected with power end Vdd, and the source electrode of switch NMOS transistor N2 is connected with earth terminal Vss
Connect, the grid of switch NMOS transistor N2 is connected with the outfan of the first phase inverter Rv1.
The operation principle of foregoing circuit is：When power end Vdd produces instantaneous electric potential difference due to the accumulation of electrostatic（Or it is defeated
The electrostatic entering output interface end I/O accumulation passes through the parasitic diode biography that the first drain region 306 and the 3rd n-type doping area 307 are constituted
Leading power end Vdd makes power end Vdd produce instantaneous electric potential difference）, the coupling in RC loop drags down the current potential of a point so that a point
For low level, b point anti-phase through the first phase inverter Rv1（Or first outfan）For high level, switch NMOS transistor N2 leads
Logical, power end Vdd passes through switch NMOS transistor N2 to earth terminal Vss release electrostatic；B point high level is through the second phase inverter
Rv2 anti-phase after, c point（Or second outfan）It is changed into low level, the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive are parasitic
Audion T2 turns on, and power end Vdd passes through the first positive-negative-positive parasitic triode T1 to earth terminal Vss release electrostatic, and input and output connect
Mouth end I/O passes through the second positive-negative-positive parasitic triode T2 to earth terminal Vss release electrostatic；It is anti-phase through the 3rd that c point is changed into low level
After device Rv2 is anti-phase, d point（Or the 3rd outfan）It is changed into high level, NPN type triode T4 turns on, input/output interface end I/O leads to
Cross NPN type triode T4 to earth terminal Vss release electrostatic, the first NPN type parasitic triode T3 can be with input/output interface simultaneously
Passive triggering and conducting in the presence of the electrostatic of end I/O accumulation, by the Electro-static Driven Comb of input/output interface end I/O accumulation to earth terminal
Vss.
To sum up, the source region of the electrostatic preventing structure of the embodiment of the present invention, the first base doping area and PMOS and quasiconductor
Substrate constitutes the first positive-negative-positive parasitic triode, and the first base doping area constitutes second with the drain region of PMOS and Semiconductor substrate
Positive-negative-positive parasitic triode, described some the second discrete base doping areas and the first n-type doping area and the second n-type doping area structure
Become some NPN transistors in parallel, therefore when input/output interface and/or power end accumulation electrostatic, electrostatic passes through first
The Electro-static Driven Comb path that positive-negative-positive parasitic triode, the second positive-negative-positive parasitic triode or some NPN transistors in parallel are constituted
Be discharged into earth terminal, increased the path of Electro-static Driven Comb, improve the efficiency of Electro-static Driven Comb, in addition, the second base doping area and
First base doping area is connected with external trigger voltage-regulating circuit respectively, thus passing through external trigger voltage-regulating circuit control
Make the base current potential of the first positive-negative-positive parasitic triode, the second positive-negative-positive parasitic triode and some NPN transistors in parallel, make
First positive-negative-positive parasitic triode, the second positive-negative-positive parasitic triode are changed into circuit from passive triggering and conducting and control conducting, strengthen
Control ability to parasitic triode, prevents the electrostatic gathering from can not timely and effectively discharge.
Although the present invention is open as above with preferred embodiment, it is not for limiting the present invention, any this area
Without departing from the spirit and scope of the present invention, the methods and techniques content that may be by the disclosure above is to this for technical staff
Bright technical scheme makes possible variation and modification, and therefore, every content without departing from technical solution of the present invention, according to the present invention
Technical spirit any simple modification, equivalent variations and modification that above example is made, belong to technical solution of the present invention
Protection domain.
Claims (19)
1. a kind of electrostatic preventing structure is it is characterised in that include：
Semiconductor substrate, has the first N-type well region and the first P type trap zone, described first N-type well region bag in described Semiconductor substrate
Include first area and second area, described first P type trap zone includes the 3rd region and the 4th region；
PMOS transistor in the first area of the first N-type well region, described PMOS transistor is included positioned at the first N-type well region
On grid and be located at grid both sides first N-type well region in source/drain region, the source region of PMOS transistor and grid and power end phase
Connect, the drain region of PMOS transistor is connected with input/output interface end；
The first base doping area in the second area of the first N-type well region, the doping type in the first base doping area is N
Type, the first base doping area is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electric potential difference, described outer
Portion's trigger voltage adjustment circuit drags down the current potential in the first base doping area；
Nmos pass transistor in the 3rd region of the first P type trap zone, described nmos pass transistor is included positioned at the first P type trap zone
On grid and the source/drain region being located in the P type trap zone of grid both sides first, the drain region of nmos pass transistor and input/output interface end
It is connected, the grid of nmos pass transistor is connected with earth terminal with source region；
The second some discrete base doping area in the 4th region of the first P type trap zone, described second base doping area
Doping type be p-type, the second base doping area is connected with external trigger voltage-regulating circuit, when power end produce instantaneously electric
During potential difference, described external trigger voltage-regulating circuit draws high the current potential in the second base doping area；
The first n-type doping area in the 4th region of the first P type trap zone, described first n-type doping area surrounds described some
The second discrete base doping area, the first n-type doping area is connected with input/output interface end；
The second n-type doping area in the 4th region of the first P type trap zone, described second n-type doping area surrounds a described N
Type doped region and some the second discrete base doping areas, the second n-type doping area is connected with earth terminal.
2. electrostatic preventing structure as claimed in claim 1 it is characterised in that the source region of the first base doping area and PMOS and
Semiconductor substrate constitutes the first positive-negative-positive parasitic triode, the drain region of the first base doping area and PMOS and Semiconductor substrate structure
Become the second positive-negative-positive parasitic triode.
3. electrostatic preventing structure as claimed in claim 1 it is characterised in that described some the second discrete base doping areas with
First n-type doping area and the second n-type doping area constitute some NPN transistors in parallel.
4. electrostatic preventing structure as claimed in claim 1 is it is characterised in that described first n-type doping area includes some N-type
Doped region, the quantity of the sub- doped region of N-type is equal to the quantity in the second base doping area, and the sub- doped region of each N-type surrounds corresponding the
Two base doped regions.
5. electrostatic preventing structure as claimed in claim 1 is it is characterised in that described external trigger voltage-regulating circuit includes RC
Coupling circuit and Nverter circuit, described RC coupling circuit include connect coupled capacitor and coupling resistance, coupling resistance another
One end connects to power end, and the other end of coupled capacitor connects to earth terminal, and RC switching node connects to Nverter circuit, described
Nverter circuit includes the first phase inverter, the second phase inverter and the 3rd phase inverter, the input of the first phase inverter and the RC connecting
Switching node is connected, and the outfan of the first phase inverter is connected with the input of the second phase inverter, the output of the second phase inverter
End is connected with the input of the 3rd phase inverter and the first base doping area, and the outfan of the 3rd phase inverter and the second base are mixed
Miscellaneous area is connected.
6. electrostatic preventing structure as claimed in claim 5 is it is characterised in that described first phase inverter, the second phase inverter and
Three phase inverters are CMOS inverter or TTL phase inverter.
7. electrostatic preventing structure as claimed in claim 5 is it is characterised in that described electrostatic preventing structure also includes switching NMOS
Transistor, the drain electrode of switch NMOS transistor is connected with power end, and the source electrode of switch NMOS transistor is connected with earth terminal,
The grid of switch NMOS transistor is connected with the outfan of the first phase inverter.
8. electrostatic preventing structure as claimed in claim 1 is it is characterised in that also have the 3rd N-type in described first N-type well region
Doped region, the 3rd n-type doping area surrounds described PMOS transistor and the first base doping area, the 3rd n-type doping area and power end
It is connected.
9. electrostatic preventing structure as claimed in claim 1 is it is characterised in that also have the first p-type in described first P type trap zone
Doped region, the first p-type doped region surrounds described nmos pass transistor and the second base doping area, the first n-type doping area and the second N-type
Doped region, the first p-type doped region is connected with earth terminal.
10. electrostatic preventing structure as claimed in claim 9 is it is characterised in that described nmos pass transistor and the second n-type doping area
Between also there is the second p-type doped region, the two ends of the second p-type doped region are contacted with the first p-type doped region.
11. electrostatic preventing structures as claimed in claim 1 are it is characterised in that described PMOS transistor is to share source and drain PMOS
Transistor, described shared source and drain PMOS transistor includes some first source regions of alternate intervals distribution in the first N-type well region
With the first drain region, and it is located at the first grid in the first N-type well region between the first adjacent source region and the first drain region, described
Some first grids and the first source region are connected with power end, and described some first drain regions are connected with input/output interface end,
Described first base doping area constitutes some first positive-negative-positive parasitism three poles in parallel with some first source regions and Semiconductor substrate
Pipe, described first base doping area constitutes some second positive-negative-positives parasitisms in parallel with some first drain regions and Semiconductor substrate
Audion.
12. electrostatic preventing structures as claimed in claim 11 are it is characterised in that described second area is located at first grid upwards
On the bearing of trend that lower two ends extend, described first base doping area is located in second area, and the first base doping area is along first
Length in source region and the first drain region distribution arrangement is equal to the first source region and the dispersion of distribution in the first drain region, the first base doping area
Width be 0.5～5 micron.
13. electrostatic preventing structures as claimed in claim 11 it is characterised in that in the first base doping area dopant ion be phosphorus
Ion, arsenic ion or antimony ion.
14. electrostatic preventing structures as claimed in claim 1 are it is characterised in that described nmos pass transistor is to share source and drain NMOS
Transistor, described shared source and drain nmos pass transistor includes some second source regions of alternate intervals distribution in the first P type trap zone
With the second drain region, and it is located at the second grid in the first P type trap zone between the second adjacent source region and the second drain region, described
Some second source regions are connected with earth terminal with second grid, and described some second drain regions are connected with input/output interface end.
15. electrostatic preventing structures as claimed in claim 1 are it is characterised in that the dopant ion in the second base doping area is boron
Ion, gallium ion or indium ion.
16. electrostatic preventing structures as claimed in claim 1 are it is characterised in that also have the second N-type in described Semiconductor substrate
Well region and the second P type trap zone, the second N-type well region and the second P type trap zone are located between the first N-type well region and the first P type trap zone, the
One N-type well region, the second P type trap zone, the second N-type well region and the first P type trap zone are alternately distributed in Semiconductor substrate successively.
17. electrostatic preventing structures as claimed in claim 16 are it is characterised in that have the second p-type in described second P type trap zone
Doped region, the second p-type doped region is connected with earth terminal.
A kind of 18. electrostatic discharge protective circuits are it is characterised in that include：PMOS transistor, the source region of PMOS transistor and grid and electricity
Source is connected, and the drain region of PMOS transistor is connected with input/output interface end；Nmos pass transistor, the drain region of nmos pass transistor
It is connected with input/output interface end, the grid of nmos pass transistor is connected with earth terminal with source region；First positive-negative-positive parasitism three poles
Pipe, the launch site of the first positive-negative-positive parasitic triode is connected with power end, the collecting zone of the first positive-negative-positive parasitic triode with connect
Ground terminal is connected, and the base of the first positive-negative-positive parasitic triode is connected with external trigger voltage-regulating circuit, when power end produces
During instantaneous electric potential difference, described external trigger voltage-regulating circuit drags down the current potential of the first positive-negative-positive parasitic triode base；Second
Positive-negative-positive parasitic triode, the launch site of the second positive-negative-positive parasitic triode is connected with input/output interface end, and the second positive-negative-positive is posted
The collecting zone of raw audion is connected with earth terminal, and the base of the second positive-negative-positive parasitic triode is electric with external trigger Voltage Cortrol
Road is connected, and when power end produces instantaneous electric potential difference, described external trigger voltage-regulating circuit drags down the second positive-negative-positive parasitism three
The current potential of pole pipe base；Some NPN type triode in parallel, described some launch sites of NPN type triode in parallel and ground connection
End connects, and described some collecting zones of NPN type triode in parallel are connected with input/output interface end, described some parallel connections
The base of NPN type triode is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electric potential difference, described outer
Portion's trigger voltage adjustment circuit draws high the current potential of the NPN type triode base of some parallel connections.
19. electrostatic discharge protective circuits as claimed in claim 18 are it is characterised in that described external trigger voltage-regulating circuit includes
RC coupling circuit and Nverter circuit, described RC coupling circuit includes coupled capacitor and the coupling resistance connected, coupling resistance
The other end connects to power end, and the other end of coupled capacitor connects to earth terminal, and RC switching node connects to Nverter circuit, institute
State the first phase inverter, the second phase inverter and the 3rd phase inverter that Nverter circuit includes connecting, the input of the first phase inverter with
RC switching node is connected, and the outfan of the first phase inverter is connected with the input of the second phase inverter, the second phase inverter defeated
Go out the base at end and the input, the base of the first positive-negative-positive parasitic triode and the second positive-negative-positive parasitic triode of the 3rd phase inverter
Area is connected, and the outfan of the 3rd phase inverter is connected with the base of described some NPN type triode in parallel.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310106740.9A CN104078460B (en) | 2013-03-28 | 2013-03-28 | Electrostatic protection structure and electrostatic protection circuit |
| US14/227,500 US9105477B2 (en) | 2013-03-28 | 2014-03-27 | ESD protection structure and ESD protection circuit |
| US14/227,405 US8981483B2 (en) | 2013-03-28 | 2014-03-27 | ESD protection structure and ESD protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310106740.9A CN104078460B (en) | 2013-03-28 | 2013-03-28 | Electrostatic protection structure and electrostatic protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104078460A CN104078460A (en) | 2014-10-01 |
| CN104078460B true CN104078460B (en) | 2017-02-08 |
Family
ID=51599635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310106740.9A Active CN104078460B (en) | 2013-03-28 | 2013-03-28 | Electrostatic protection structure and electrostatic protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104078460B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880502B (en) * | 2018-09-05 | 2022-10-14 | 无锡华润上华科技有限公司 | Semiconductor structure and motor driving device |
| CN111081703B (en) * | 2019-12-31 | 2023-12-26 | 广州新视界光电科技有限公司 | Electrostatic protection circuit and display device |
| CN114068518A (en) * | 2020-08-06 | 2022-02-18 | 长鑫存储技术有限公司 | Semiconductor electrostatic protection device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1649142A (en) * | 2004-01-19 | 2005-08-03 | 财团法人工业技术研究院 | Static discharging protectire circuit and static discharging protective method |
| CN102208408A (en) * | 2010-03-31 | 2011-10-05 | 上海宏力半导体制造有限公司 | Gate-drive thyristor and electrostatic protection circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7034364B2 (en) * | 2004-05-25 | 2006-04-25 | Texas Instruments Incorporated | Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection |
-
2013
- 2013-03-28 CN CN201310106740.9A patent/CN104078460B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1649142A (en) * | 2004-01-19 | 2005-08-03 | 财团法人工业技术研究院 | Static discharging protectire circuit and static discharging protective method |
| CN102208408A (en) * | 2010-03-31 | 2011-10-05 | 上海宏力半导体制造有限公司 | Gate-drive thyristor and electrostatic protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104078460A (en) | 2014-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104078459B (en) | Electrostatic preventing structure and electrostatic discharge protective circuit | |
| US9105477B2 (en) | ESD protection structure and ESD protection circuit | |
| CN103456731B (en) | Under-voltage protection equipment of accurate transceiver and forming method thereof | |
| CN104752417B (en) | Controllable silicon electrostatic protection device and forming method thereof | |
| CN101807598B (en) | PNPNP type triac | |
| CN103035638B (en) | Improve adjustable ESD protective device | |
| CN104241272B (en) | Static discharge transistor and its ESD protection circuit | |
| TWI523197B (en) | Electrostatic discharge protection device | |
| CN107527879A (en) | For the triggering of Active control and the apparatus and method of latch release IGCT | |
| US20130277745A1 (en) | Electrostatic discharge (esd) guard ring protective structure | |
| CN105655325A (en) | Electrostatic discharge protection circuit, and electrostatic discharge protection structure and manufacturing method thereof | |
| CN103811484A (en) | ESD Devices Comprising Semiconductor Fins | |
| CN103427408B (en) | ESD protection for high voltage applications | |
| CN104716132B (en) | The thyristor and its circuit of a kind of low trigger voltage and high maintenance voltage | |
| CN106328644A (en) | Semiconductor device and electronic device | |
| CN107799517A (en) | ESD devices for semiconductor structure | |
| CN104078460B (en) | Electrostatic protection structure and electrostatic protection circuit | |
| CN102315212B (en) | Grid drive thyristor circuit and electrostatic discharge protective circuit | |
| CN104835818B (en) | A kind of dual trigger LVTSCR structure and its circuit | |
| CN102315215B (en) | Gate driving thyristor circuit and electrostatic protection circuit | |
| CN104183596A (en) | Electrostatic discharge protection structure | |
| CN105489503B (en) | Semiconductor structure and forming method thereof, electrostatic discharge protective circuit | |
| US7892907B2 (en) | CMOS latch-up immunity | |
| CN102569292A (en) | ESD protection device with tunable design windows | |
| CN104319286B (en) | A kind of device architecture that can suppress parasitic latch-up suitable for Bulk CMOS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |