CN104078460A - Electrostatic protection structure and electrostatic protection circuit - Google Patents
Electrostatic protection structure and electrostatic protection circuit Download PDFInfo
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- CN104078460A CN104078460A CN201310106740.9A CN201310106740A CN104078460A CN 104078460 A CN104078460 A CN 104078460A CN 201310106740 A CN201310106740 A CN 201310106740A CN 104078460 A CN104078460 A CN 104078460A
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Abstract
The invention provides an electrostatic protection structure and an electrostatic protection circuit. The electrostatic protection structure comprises a PMOS transistor located in a first region of a first N-type trap, a first base doping region located in a second region of the first N-type trap, an NMOS transistor located in a third region of a first P-type trap, a plurality of independent second base doping regions located in a fourth region of the first P-type trap, a first N-type doping region surrounding the multiple independent second base doping regions, and a second N-type doping region surrounding the first N-type doping region and the multiple independent second base doping regions. The source region and grid electrode of the PMOS transistor are connected with a power supply end. The drain region of the PMOS transistor is connected with an input/output interface end. The first base doping region is connected with an external trigger voltage regulator circuit. The drain region of the NMOS transistor is connected with the input/output interface end. The grid electrode and source region of the NMOS transistor are connected with a grounding end. The second base doping regions are connected with the external trigger voltage regulator circuit. According to the electrostatic protection structure, paths of electrostatic discharge are increased, and electrostatic discharge efficiency is improved. According to the electrostatic protection structure and the electrostatic protection circuit, paths of electrostatic discharge of the electrostatic protection structure are increased, and electrostatic discharge efficiency is improved.
Description
Technical field
The present invention relates to electrostatic protection field, particularly a kind of electrostatic preventing structure and electrostatic discharge protective circuit.
Background technology
In the Production and application of integrated circuit (IC) chip, along with improving constantly of very lagre scale integrated circuit (VLSIC) technology, current CMOS production of integrated circuits technology has entered the deep-submicron stage, the size of MOS device is constantly dwindled, the thickness of gate oxide is more and more thinner, MOS device withstand voltage ability significantly declines, and static discharge (Electrostatic Discharge, ESD) becomes more and more significant to the harm of integrated circuit.Therefore the protection of, integrated circuit being carried out to ESD also becomes particularly important.
In order to strengthen the protective capacities to static, mostly the input/output interface end (I/O pad) at chip connects electrostatic discharge protective circuit, and electrostatic discharge protective circuit is the discharge path that the internal circuit in chip provides electrostatic induced current, to avoid static that internal circuit is punctured.
In existing electrostatic discharge protective circuit, conventional device comprises the nmos pass transistor of grounded-grid, PMOS transistor that grid connects power supply and silicon controlled rectifier (SCR, Silicon Controlled Rectifier) etc.Because nmos pass transistor and the CMOS industry of grounded-grid are well compatible, the nmos pass transistor of grid ground connection is widely used.
With reference to figure 1, Fig. 1 is the structural representation of existing electrostatic discharge protective circuit, the drain electrode of nmos pass transistor 13 is connected with input/output interface end 15, the grid of nmos pass transistor 13 is connected with earth terminal 16 with source electrode, when input/output interface end 15 produces large electrostatic potential or electrostatic induced current, static is discharged into earth terminal 16 by the parasitic NPN triode in nmos pass transistor 13, specifically please refer to Fig. 2, Fig. 2 is the cross-sectional view of nmos pass transistor in Fig. 1, comprise: Semiconductor substrate 100, in described Semiconductor substrate 100, there is P trap 101, the grid 103 in Semiconductor substrate 100 with nmos pass transistor, the 102He source region, drain region 104 in the P trap 101 of grid 103 both sides with nmos pass transistor, the drain region 102 of nmos pass transistor is connected with input/output interface end 15, the source region 104 of nmos pass transistor is connected with earth terminal 16 with grid 103, in the P trap 101 of described source region 104 1 sides, also there is P type doped region 105, P type doped region 105 is connected with earth terminal 16, between 105Yu source region, P type doped region 104, there is fleet plough groove isolation structure 106, the drain region 102 of nmos pass transistor forms the collector region of parasitic NPN triode 17, the source region 104 of nmos pass transistor forms the emitter region of parasitic NPN triode 17, the P trap 101 of grid 103 bottoms forms the base of parasitic NPN triode 17, when input/output interface end 15 gathers electrostatic charge, from drain region, 102 process well region resistance 18 flow to 105th district, P type doped region to electric current, make to produce electrical potential difference between the P trap 101 of grid 103 bottoms and earth terminal 16, when electrical potential difference is greater than the threshold voltage of parasitic NPN triode 17, parasitic NPN triode 17 is conducting state, now electric current just 102 flows to source region 104 from drain region, discharge the static that input/output interface end 15 gathers.
Existing esd protection circuit discharging efficiency when discharging is lower.
Summary of the invention
The problem that the present invention solves is to improve the efficiency that static discharges.
For addressing the above problem, technical solution of the present invention provides a kind of electrostatic preventing structure, comprise: Semiconductor substrate, in described Semiconductor substrate, there is the first N-type well region and a P type well region, described the first N-type well region comprises first area and second area, and a described P type well region comprises the 3rd region and the 4th region; Be positioned at the PMOS transistor of the first area of the first N-type well region, described PMOS transistor comprises the grid being positioned on the first N-type well region and is positioned at the source/drain region of grid both sides the first N-type well region, the transistorized source region of PMOS is connected with power end with grid, and the transistorized drain region of PMOS is connected with input/output interface end; Be positioned at the first base doping district of the second area of the first N-type well region, the doping type in the first base doping district is N-type, the first base doping district is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit drags down the current potential in the first base doping district; Be positioned at the nmos pass transistor in the 3rd region of a P type well region, described nmos pass transistor comprises the grid being positioned on a P type well region and is positioned at the source/drain region of grid both sides the one P type well region, the drain region of nmos pass transistor is connected with input/output interface end, and the grid of nmos pass transistor is connected with earth terminal with source region; Be positioned at the second some discrete base doping district in the 4th region of a P type well region, the doping type in described the second base doping district is P type, the second base doping district is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit is drawn high the current potential in the second base doping district; Be positioned at the first N-type doped region in the 4th region, described the first N-type doped region surrounds described some the second discrete base doping districts, and the first N-type doped region is connected with input/output interface end; Be positioned at the second N-type doped region in the 4th region, described the second N-type doped region surrounds described the first N-type doped region, and the second N-type doped region is connected with earth terminal.
Optionally, the source region of the first base doping district and PMOS and Semiconductor substrate form the first positive-negative-positive parasitic triode, and the drain region of the first base doping district and PMOS and Semiconductor substrate form the second positive-negative-positive parasitic triode.
Optionally, described some the second discrete base doping districts form some NPN transistor in parallel with the first N-type doped region and the second N-type doped region.
Optionally, described the first N-type doped region comprises the sub-doped region of some N-types, and the quantity of the sub-doped region of N-type equals the quantity in the second base doping district, and the sub-doped region of each N-type surrounds the second corresponding base doping district.
Optionally, described external trigger voltage-regulating circuit comprises RC coupling circuit and Nverter circuit, described RC coupling circuit comprises coupling capacitance and the coupling resistance of series connection, the other end of coupling resistance is connected to power end, the other end of coupling capacitance is connected to earth terminal, RC switching node is connected to Nverter circuit, described Nverter circuit comprises the first inverter of series connection, the second inverter and the 3rd inverter, the input of the first inverter is connected with RC switching node, the output of the first inverter is connected with the input of the second inverter, the output of the second inverter is connected with input and the first base doping district of the 3rd inverter, the output of the 3rd inverter is connected with the second base doping district.
Optionally, described the first inverter, the second inverter and the 3rd inverter are CMOS inverter or TTL inverter.
Optionally; described electrostatic preventing structure also comprises switch nmos pass transistor; the drain electrode of switch nmos pass transistor is connected with power end, and the source electrode of switch nmos pass transistor is connected with earth terminal, and the grid of switch nmos pass transistor is connected with the output of the first inverter.
Optionally, in described the first N-type well region, also have the 3rd N-type doped region, the 3rd N-type doped region surrounds described PMOS transistor and the first base doping district, and the 3rd N-type doped region is connected with power end.
Optionally, in a described P type well region, also have a P type doped region, a P type doped region surrounds described nmos pass transistor and the second base doping district, the first N-type doped region and the second N-type doped region, and a P type doped region is connected with earth terminal.
Optionally, also have the 2nd P type doped region between described nmos pass transistor and the second N-type doped region, the two ends of the 2nd P type doped region contact with a P type doped region.
Optionally, described PMOS transistor is that common source leaks PMOS transistor, described common source leaks PMOS transistor and comprises some the first source regions and the first drain region that is positioned at the first N-type well region alternate intervals distribution, and the first grid on the first N-type well region between the first adjacent source region and the first drain region, some first grids are connected with power end with the first source region, some the first drain regions are connected with input/output interface end, the first base doping district forms some the first positive-negative-positive parasitic triodes in parallel with some the first source regions and Semiconductor substrate, the first base doping district forms some the second positive-negative-positive parasitic triodes in parallel with some the first drain regions and Semiconductor substrate.
Optionally, described second area is positioned at first grid on the bearing of trend of two ends extension, described the first base doping district is positioned at second area, the first base doping district equals the dispersion of distribution in the first source region and the first drain region along the length on the first source region and the first drain region distribution arrangement, the width in the first base doping district is 0.5～5 micron.
Optionally, the ion that adulterates in the first base doping district is phosphonium ion, arsenic ion or antimony ion.
Optionally, described nmos pass transistor is that common source leaks nmos pass transistor, described common source leaks nmos pass transistor and comprises some the second source regions and the second drain region that is positioned at a P type well region alternate intervals distribution, and the second grid on the P type well region between the second adjacent source region and the second drain region, some the second source regions are connected with earth terminal with second grid, and some the second drain regions are connected with input/output interface end.
Optionally, the doping ion in the second base doping district is boron ion, gallium ion or indium ion.
Optionally, in described Semiconductor substrate, also there is the second N-type well region and the 2nd P type well region, the second N-type well region and the 2nd P type well region are between the first N-type well region and a P type well region, and the first N-type well region, the 2nd P type well region, the second N-type well region and a P type well region are alternately distributed successively in Semiconductor substrate.
Optionally, in described the 2nd P type well region, have the 2nd P type doped region, the 2nd P type doped region is connected with earth terminal.
Technical solution of the present invention provides a kind of electrostatic discharge protective circuit, comprising: PMOS transistor, and the transistorized source region of PMOS is connected with power end with grid, and the transistorized drain region of PMOS is connected with input/output interface end; Nmos pass transistor, the drain region of nmos pass transistor is connected with input/output interface end, and the grid of nmos pass transistor is connected with earth terminal with source region; The first positive-negative-positive parasitic triode, the emitter region of the first positive-negative-positive parasitic triode is connected with power end, the collector region of the first positive-negative-positive parasitic triode is by being connected with earth terminal, the base of the first positive-negative-positive parasitic triode is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit drags down the current potential of the first positive-negative-positive parasitic triode base; The second positive-negative-positive parasitic triode, the emitter region of the second positive-negative-positive parasitic triode is connected with input/output interface end, the collector region earth terminal of the second positive-negative-positive parasitic triode connects, the base of the second positive-negative-positive parasitic triode is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit drags down the current potential of the second positive-negative-positive parasitic triode base; The NPN type triode of some parallel connections, the emitter region of the NPN type triode of some parallel connections is connected with earth terminal, the collector region of the NPN type triode of some parallel connections is connected with input/output interface end, the base of NPN type triode of some parallel connections and being connected of external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit is drawn high the current potential of a NPN type parasitic triode base.
Optionally, described external trigger voltage-regulating circuit comprises RC coupling circuit and Nverter circuit, described RC coupling circuit comprises coupling capacitance and the coupling resistance of series connection, the other end of coupling resistance is connected to power end, the other end of coupling capacitance is connected to earth terminal, RC switching node is connected to Nverter circuit, described Nverter circuit comprises the first inverter of series connection, the second inverter and the 3rd inverter, the input of the first inverter is connected with RC switching node, the output of the first inverter is connected with the input of the second inverter, the input of the output of the second inverter and the 3rd inverter, the base of the base of the first positive-negative-positive parasitic triode and the second positive-negative-positive parasitic triode is connected, the output of the 3rd inverter is connected with the base of the NPN type triode of some parallel connections.
Compared with prior art, technical solution of the present invention has the following advantages:
The electrostatic preventing structure of technical solution of the present invention, the source region of the first base doping district and PMOS and Semiconductor substrate form the first positive-negative-positive parasitic triode, the drain region of the first base doping district and PMOS and Semiconductor substrate form the second positive-negative-positive parasitic triode, described some the second discrete base doping districts form some NPN transistor in parallel with the first N-type doped region and the second N-type doped region, therefore when input/output interface and/or power end accumulation static, static is by the first positive-negative-positive parasitic triode, the static that the NPN transistor of the second positive-negative-positive parasitic triode or some parallel connections forms discharges path and is discharged into earth terminal, increased the path that static discharges, improved the efficiency that static discharges, in addition, the second base doping district is connected with external trigger voltage-regulating circuit respectively with the first base doping district, thereby control the first positive-negative-positive parasitic triode by external trigger voltage-regulating circuit, the base current potential of the NPN transistor of the second positive-negative-positive parasitic triode and some parallel connections, make the first positive-negative-positive parasitic triode, the second positive-negative-positive parasitic triode becomes circuit from passive triggering and conducting and controls conducting, strengthened the control ability to parasitic triode, prevent that the static gathering from can not discharge timely and effectively.
Further, described PMOS transistor is that common source leaks PMOS transistor, the first base doping district forms some the first positive-negative-positive parasitic triodes in parallel with some the first source regions and Semiconductor substrate, the first base doping district forms some the second positive-negative-positive parasitic triodes in parallel with some the first drain regions and Semiconductor substrate, when power end and input/output interface end have gathered electrostatic charge, electrostatic charge can be discharged into earth terminal by some the first positive-negative-positive parasitic triodes and the second positive-negative-positive parasitic triode, increased the path that static discharges, improve the efficiency that static discharges.
Further, the second area of the first N-type well region is positioned at first grid on the bearing of trend of two ends extension, described the first base doping district is positioned at second area, the first base doping district equals the dispersion of distribution in the first source region and the first drain region along the length on the first source region and the first drain region distribution arrangement, the width in the first base doping district is 0.5～5 micron, not only make the layout area in the first base doping district less, and the first base doping district is equated with the distance between some the first source regions and the first drain region, when the first base doping district is connected with external trigger voltage-regulating circuit, make the first base doping district identical with the control ability of the second positive-negative-positive parasitic triode to each the first positive-negative-positive parasitic triode, the uniformity of static release and the stability of electrostatic discharge protective circuit have been improved.
Further; the external trigger voltage-regulating circuit of the formation of RC coupling circuit and Nverter circuit can drag down the current potential in the first base doping district and draw high the current potential in the second base doping district; the triggering and conducting that makes the parasitic transistor in electrostatic preventing structure is not the passive triggering after build-up of electrostatic charges; but the conducting of ACTIVE CONTROL parasitic transistor by external trigger voltage-regulating circuit has improved the sensitivity of electrostatic preventing structure release electrostatic.
Further, described the first N-type doped region comprises the sub-doped region of some N-types, between the sub-doped region of adjacent N-type, contact or do not contact, the quantity of the sub-doped region of N-type equals the quantity in the second base doping district, the sub-doped region of each N-type surrounds the second corresponding base doping district, make the second base doping district, the sub-doped region of some N-types, some NPN transistor electrical parameters (comprising threshold voltage etc.) of the formation between the second base doping district and the second N-type doped region are more approaching, when the second base doping district is connected with external trigger voltage-regulating circuit, be easy to the control conducting of some NPN transistor and the uniformity that static discharges.
Accompanying drawing explanation
Fig. 1～Fig. 2 is the structural representation of prior art electrostatic discharge protective circuit;
Fig. 3～5 are the structural representation of embodiment of the present invention electrostatic preventing structure;
Fig. 6 is the structural representation of embodiment of the present invention electrostatic discharge protective circuit.
Embodiment
Existing electrostatic discharge protective circuit passes through parasitic NPN triode 17(with reference to figure 2) electric discharge, the path of its electric discharge only has one, and be passive triggering during parasitic NPN triode conducting electric discharge, want electrostatic charge when input/output interface end 15 accumulates certain electrostatic charge, from drain region, 102 process well region resistance 18 flow to 105th district, P type doped region to electric current, make to produce electrical potential difference between the P well region of grid 103 bottoms and earth terminal 16, when electrical potential difference is greater than the threshold voltage of parasitic NPN triode 17, the electrostatic charge of input/output interface end 15 accumulation is discharged, the efficiency that the static of existing electrostatic discharge protective circuit is discharged is relatively low.
For addressing the above problem, the invention provides a kind of electrostatic preventing structure, the PMOS transistor that the first area of the first N-type well region has, in the second area of the first N-type well region, there is the first base doping district, the doping type in the first base doping district is N-type, the source region of PMOS is connected with power end with grid, and the transistorized drain region of PMOS is connected with input/output interface end, and the first base doping district is connected with the output of external trigger voltage-regulating circuit; The 3rd region of the one P type well region has nmos pass transistor, the second some discrete base doping district in the 4th region of the one P type well region, the doping type in described the second base doping district is P type, the second base doping district is connected with external trigger voltage-regulating circuit, surround the described first N-type doped region in described some the second discrete base doping districts, the first N-type doped region is connected with input/output interface end, the the second N-type doped region that surrounds described the first N-type doped region and some the second discrete base doping districts, the second N-type doped region is connected with earth terminal.In above-mentioned electrostatic preventing structure, the source region of the first base doping district and PMOS and Semiconductor substrate form the first positive-negative-positive parasitic triode, the drain region of the first base doping district and PMOS and Semiconductor substrate form the second positive-negative-positive parasitic triode, described some the second discrete base doping districts form some NPN transistor in parallel with the first N-type doped region and the second N-type doped region, therefore when input/output interface and/or power end accumulation static, static is by the first positive-negative-positive parasitic triode, the static that the NPN transistor of the second positive-negative-positive parasitic triode or some parallel connections forms discharges path and is discharged into earth terminal, increased the path that static discharges, improved the efficiency that static discharges, in addition, the second base doping district is connected with external trigger voltage-regulating circuit respectively with the first base doping district, thereby control the first positive-negative-positive parasitic triode by external trigger voltage-regulating circuit, the base current potential of the NPN transistor of the second positive-negative-positive parasitic triode and some parallel connections, make the first positive-negative-positive parasitic triode, the second positive-negative-positive parasitic triode becomes circuit from passive triggering and conducting and controls conducting, strengthened the control ability to parasitic triode, prevent that the static gathering from can not discharge timely and effectively.
Below in conjunction with specific embodiments, electrostatic preventing structure of the present invention and electrostatic discharge protective circuit are done to detailed introduction.Fig. 3 is the structural representation of overlooking visual angle (in Fig. 3, each port and external circuit are all not shown) of embodiment of the present invention electrostatic preventing structure; Fig. 4 is that Fig. 3 is along the structural representation of line of cut AB direction; Fig. 5 be Fig. 3 along the structural representation of line of cut CD direction, Fig. 6 is the structural representation of embodiment of the present invention electrostatic discharge protective circuit.
In conjunction with reference to figure 3 and Fig. 4, described electrostatic preventing structure, comprising:
Semiconductor substrate 300, has the first N-type well region 301 and a P type well region 302 in described Semiconductor substrate 300, described the first N-type well region 301 comprises first area and second area, and a described P type well region 302 comprises the 3rd region and the 4th region; Be positioned at the PMOS transistor of the first area of the first N-type well region 301, described PMOS transistor comprises the grid being positioned on the first N-type well region 301 and is positioned at source region and the drain region of grid both sides the first N-type well region 301, the transistorized source region of PMOS is connected with power end Vdd with grid, and the transistorized drain region of PMOS is connected with input/output interface end I/O; Be positioned at the first base doping district 308 of the second area of the first N-type well region 301, the doping type in the first base doping district 308 is N-type, the first base doping district 308 is connected with the second output c end of external trigger voltage-regulating circuit 325, when power end Vdd produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit 325 drags down the current potential in the first base doping district 308; Be positioned at the nmos pass transistor in the 3rd region of a P type well region 302, described nmos pass transistor comprises the grid 311 being positioned on a P type well region 302 and source region and the drain region that is positioned at grid 311 both sides the one P type well region 302, the drain region of nmos pass transistor is connected with input/output interface end I/O, and the grid of nmos pass transistor is connected with earth terminal Vss with source region; Described electrostatic preventing structure (in conjunction with reference to figure 3 and Fig. 5) also comprises: the second some discrete base doping district 314 that is positioned at the 4th region of a P type well region 302, the doping type in described the second base doping district 314 is P type, the second base doping district 314 is connected with the 3rd output d end (with reference to figure 4 and Fig. 5) of external trigger voltage-regulating circuit 325, when power end Vdd produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit 325 is drawn high the current potential in the second base doping district 314; Be positioned at the first N-type doped region 315 in the 4th region of a P type well region 302, described the first N-type doped region 315 surrounds described some discrete 314, the first N-type doped regions 315, the second base doping district and is connected with input/output interface end I/O; Be positioned at the second N-type doped region 316 in the 4th region of a P type well region 302, described the second N-type doped region 316 surrounds described the first N-type doped region 315 and some discrete 314, the second N-type doped regions 316, the second base doping district are connected with earth terminal Vss.
Concrete, described Semiconductor substrate 300 is P type doped substrate, the material of described Semiconductor substrate 300 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be for other material, such as III-V compounds of group such as GaAs.
Between the first N-type well region 301 and a P type well region 302, also there is the second adjacent N-type well region 304 and the 2nd P type well region 303, the first N-type well region 301, the 2nd P type well region 303, the second N-type well region 304 and a P type well region 302 are alternately distributed successively in Semiconductor substrate, in described the 2nd P type well region 303, there is the 2nd P type doped region 309(with reference to figure 4), the 2nd P type doped region 309 is connected with earth terminal Vss, the port that described the 2nd P type doped region 309 discharges as PMOS transistor area static, in described the second N-type well region 304, also there is the 4th type doped region 318, the 4th type doped region 318 is connected with power end Vdd, the PN that the second N-type well region 304 and the 2nd P type well region 303 are formed is anti-inclined to one side, prevent from, between the PMOS transistor of the first N-type well region 301 interior formation and the nmos pass transistor of P type well region 302 interior formation, latch-up occurs, thereby improve the stability of electrostatic preventing structure.In Fig. 3, described the 2nd P type well region 303, the second N-type well region 304 and a P type well region 302 are positioned at the right (x axle positive direction) of the first N-type well region 301, in other embodiments of the invention, described the 2nd P type well region 303, the second N-type well region 304 and a P type well region 302 can be positioned at the left side (x axle negative direction), top (the y axle positive direction) or following (y axle negative direction) of the first N-type well region 301.
Described the first N-type well region 301 comprises first area and second area, second area and first area are adjacent, in first area, there is PMOS transistor, in second area, there is the first base doping district 308, the first base doping district 308 doping types are N-type, the ion that adulterates in the first base doping district 308 is phosphonium ion, arsenic ion or antimony ion, the formation technique in the first base doping district 308 can be compatible mutually with the technique of the source-drain area of existing formation nmos pass transistor, without carrying out extra photoetching and injection technology, to save manufacturing cost.
In described the first N-type well region 301, also there is the 3rd N-type doped region 307, the 3rd N-type doped region 307 described PMOS transistors of encirclement and the first base doping district 308(are with reference to figure 3), the 3rd N-type doped region 307 is connected with power end Vdd, and the 3rd N-type doped region 307 has isolation while connecting Vdd and prevents the effect of breech lock.
Described PMOS transistor can be single PMOS transistor or the common source consisting of a plurality of PMOS transistors leakage PMOS transistor, in the present embodiment, with reference to figure 3 and Fig. 4, described PMOS transistor is that common source leaks PMOS transistor, described common source leaks some the first source regions 305 and the first drain region 306 that PMOS transistor comprises the first area alternate intervals distribution that is positioned at the first N-type well region 301, the doping type in the first source region 305 and the first drain region 306 is P type, and at the first adjacent source region 305 and the first grid 304 on the first N-type well region 301 between the first drain region 306, some first grids 304 are connected with power end Vdd with the first source region 305, some the first drain regions 306 are connected with input/output interface end I/O, the first base doping district 308 forms some the first positive-negative-positive parasitic triode T1(in parallel with reference to figure 4 with some the first source regions 305 and Semiconductor substrate 300, a first positive-negative-positive parasitic triode is only shown) in figure, wherein, the first base doping district 308 is as the base of the first positive-negative-positive parasitic triode T1, the first source region 305 is as the emitter region of the first positive-negative-positive parasitic triode T1, Semiconductor substrate 300 is as the collector region of the first positive-negative-positive parasitic triode T1, the first base doping district 308 forms in some second positive-negative-positive parasitic triode T2(Fig. 4 in parallel a second positive-negative-positive parasitic triode is only shown with some the first drain regions 306 and Semiconductor substrate 300), wherein, the first base doping district 308 is as the base of the second positive-negative-positive parasitic triode T2, the first drain region 306 is as the emitter region of the second positive-negative-positive parasitic triode T2, and Semiconductor substrate 300 is as the collector region of the second positive-negative-positive parasitic triode T2.In the embodiment of the present invention, common source leaks transistorized some the first source regions 305 of PMOS and the first drain region 306, between the first base doping district 308 and Semiconductor substrate 300, can form some the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2, when power end Vdd and/or input/output interface end I/O have gathered electrostatic charge, electrostatic charge can pass through some the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2, through P type semiconductor substrate 300, the 2nd P type well region 303, the 2nd P type doped region 309 is discharged into earth terminal Vss, increased the path that static discharges, improve the efficiency that static discharges.
In the present embodiment, the second area of the first N-type well region 301 is positioned at the bearing of trend (y axle negative direction) upper (with reference to figure 3) that first grid 304 extends to two ends, described the first base doping district 308 is positioned at second area, the first base doping district 308 equals the dispersion of distribution in the first source region 305 and the first drain region 306 along the length of (x direction of principal axis) on the first source region 305 and the first drain region 306 distribution arrangements, the width in the first base doping district 308 is 0.5～5 micron, not only make the layout area in the first base doping district 308 less, and the first base doping district 308 is equated with the distance between some the first source regions 305 and the first drain region 306, the the first positive-negative-positive parasitic triode T1 forming and the electrical parameter (comprising threshold voltage etc.) of the second positive-negative-positive parasitic triode T2 are more approaching, when the first base doping district 308 is connected with the second end c end of external trigger voltage-regulating circuit 325, make the first base doping district 308(as the base of the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2) identical with the control ability of the second positive-negative-positive parasitic triode T2 to each the first positive-negative-positive parasitic triode T1, the uniformity of static release and the stability of electrostatic discharge protective circuit have been improved.In other embodiments of the invention, first area and second area can also be other arrangement modes, it should be noted that, the arrangement mode of first area and second area should not limit the scope of the invention.
A described P type well region 302 comprises the 3rd region and the 4th region, the 3rd region is adjacent with the 4th region, in the 3rd region, there is nmos pass transistor, in the 4th region, there are some the second discrete base doping districts 314, the doping type in the second base doping district 314 is P type, the ion that adulterates in the second base doping district 314 is boron ion, gallium ion or indium ion, the formation technique in the first base doping district 308 can be compatible mutually with the technique of the transistorized source-drain area of existing formation PMOS, without carrying out extra photoetching and injection technology, to save manufacturing cost.
In a described P type well region, 302 also have a P type doped region 310, the one P type doped region 310 surrounds described nmos pass transistor and the second base doping district 314, the one P type doped region 310 is connected with earth terminal Vss, and a P type doped region 310 has isolation and prevents the effect of breech lock.
Described nmos pass transistor can be single nmos pass transistor or the common source consisting of a plurality of nmos pass transistors leakage nmos pass transistor, in the present embodiment, described nmos pass transistor is that common source leaks nmos pass transistor, described common source leaks some the second source regions 312 and the second drain region 313 that nmos pass transistor comprises the 3rd region alternate intervals distribution that is positioned at a P type well region 302, and the second grid 311 on the P type well region 302 between the second adjacent source region 312 and the second drain region 313, some the second source regions 312 are connected with earth terminal Vss with second grid 311, some the second drain regions 313 are connected with input/output interface end I/O, the one P type doped region 310 forms some NPN type parasitic triode T3 with some the second source regions 312 and some the second drain regions 313, wherein, the one P type doped region 310 is as the base of a NPN type parasitic triode T3, the second source region 312 is as the emitter region of a NPN type parasitic triode T3, the second drain region 313 is as the collector region of a NPN type parasitic triode T3.When input/output interface end I/O has gathered electrostatic charge, the passive triggering and conducting of some NPN type parasitic triode T3, electrostatic charge is by some NPN type parasitic triode T3, through a P type well region 302, a P type doped region 310, be discharged into earth terminal Vss, increase the path that static discharges, improved the efficiency that static discharges.
In conjunction with reference to figure 3 and Fig. 5, originally be in embodiment, the 4th region of the one P type well region 302 is positioned at the bearing of trend (y axle negative direction) upper (with reference to figure 3) that second grid 311 extends to two ends, in the 4th region, there are some the second discrete base doping districts 314, in the present embodiment, using three the second base doping districts 314 as example, the doping type in described the second base doping district is P type, and the second base doping district 314 is connected with the 3rd end d end of external trigger voltage-regulating circuit 325; In the 4th region of the one P type well region 302, also have the first N-type doped region 315, described the first N-type doped region 315 surrounds described some discrete 314, the first N-type doped regions, the second base doping district and is connected with input/output interface end I/O; The the second N-type doped region 316 also having in the 4th region of a described P type well region 302, described the second N-type doped region 316 surrounds described the first N-type doped region 315 and some discrete 314, the second N-type doped regions 316, the second base doping district are connected with earth terminal Vss.Some the second discrete base doping districts 314, in the first N-type doped region 315 and the some NPN transistor T4(Fig. 5 of the second base doping district 314 formation, a NPN transistor is only shown), wherein the second base doping district 314 is as the base of NPN transistor T4, the first N-type doped region 315 is as the collector region of NPN transistor T4, the second N-type doped region 316 is as the emitter region of NPN transistor T4, the electrostatic charge that input/output interface end I/O gathers can be discharged into earth terminal by some NPN transistor T4, thereby improved the path that static discharges, and, the layout structure of the NPN transistor in the embodiment of the present invention: the first N-type doped region 315 surrounds some the second discrete base doping districts 314, the second N-type doped region 316 surrounds described the first N-type doped region 315 and some the second discrete base doping districts 314, both saved the layout area of NPN transistor, make again the electric charge electric charge that output interface end I/O gathers to discharge by the second annular N-type doped region 316 to the periphery, the first annular N-type doped region 315, the active path that static discharges increases.
Described the first N-type doped region 315 comprises the sub-doped region of some N-types, between the sub-doped region of adjacent N-type, contact or do not contact, the quantity of the sub-doped region of N-type equals the quantity in the second base doping district, the sub-doped region of each N-type surrounds the second corresponding base doping district, in the present embodiment, the quantity of the sub-doped region of described N-type is three, comprise the sub-doped region 315a of the first N-type, the sub-doped region 315b of the second N-type and the sub-doped region 315c of the 3rd N-type, the edge of the adjacent sub-doped region of N shape is in contact with one another, to reduce layout area, in the present embodiment, the sub-doped region of each N-type surrounds the second corresponding base doping district 314, make the second base doping district 314, the sub-doped region of some N-types, some NPN transistor electrical parameters (comprising threshold voltage etc.) of the formation between the second base doping district 314 and the second N-type doped region 316 are more approaching, when the second base doping district 314 is connected with external trigger voltage-regulating circuit 325, be easy to the control conducting of some NPN transistor and the uniformity that static discharges.
In other embodiments of the invention, the quantity of described the first N-type doped region 315 is one, and the first N-type doped region 315 surrounds the second all base doping districts 314.
In other embodiments of the invention, the quantity of described the second N-type doped region is also a plurality of, the quantity of the second N-type doped region equals the quantity in the second base doping district, each second N-type doped region surrounds the sub-doped region of corresponding N-type and the second base doping district, if the NPN transistor electrical parameter (comprising threshold voltage etc.) of the formation between the sub-doped region of N-type and corresponding the second base doping district and the second N-type doped region is basic identical or very approaching, when the second base doping district is connected with external trigger voltage-regulating circuit, be easy to the control conducting of some NPN transistor and the uniformity that static discharges.
The first N-type doped region 315 and the second N-type doped region 316 doping ions are phosphonium ion, arsenic ion or antimony ion, and the formation technique of the first N-type doped region 315 and the second N-type doped region 316 can be compatible mutually with the technique of the source-drain area of existing formation nmos pass transistor.
The one P type doped region 310 surrounds described the second N-type doped region 316, and described the second N-type doped region 316 can contact or not contact with a P type doped region 310.
The two ends also between described nmos pass transistor and the second N-type doped region 316 with 317, the two P type doped regions 317, the 2nd P type doped region contact with a P type doped region 310, and described the 2nd P type doped region 317 is for isolating nmos pass transistor and NPN triode.
Please refer to Fig. 4, described external trigger voltage-regulating circuit 325 comprises RC coupling circuit and Nverter circuit, described RC coupling circuit comprises coupling capacitance C and the coupling resistance R1 of series connection, the other end of coupling resistance R1 is connected to power end Vdd, the other end of coupling capacitance C is connected to earth terminal Vss, RC switching node a is connected to Nverter circuit, described Nverter circuit comprises the first inverter Rv1 of series connection, the second inverter Rv2 and the 3rd inverter Rv3, the input of the first inverter Rv1 is connected with RC switching node, the output of the first inverter Rv1 is connected with the input of the second inverter Rv2, the output of the second inverter Rv2 (or the second output c end) is connected with input and the first base doping district 308 of the 3rd inverter Rv3, the output of the 3rd inverter Rv3 (or the 3rd output d end) with the second base doping district 314(with reference to figure 5) be connected, when power end Vdd produces instantaneous electrical potential difference (or transient pulse) due to gathering of static (or the parasitic diode that forms by the first drain region 306 and the 3rd N-type doped region 307 of the static of input/output interface end I/O accumulation be transmitted to power end Vdd make power end Vdd produce instantaneous electrical potential difference), the external trigger voltage-regulating circuit 325 of the formation of RC coupling circuit and Nverter circuit can drag down the current potential in the first base doping district 308, trigger the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2 conducting, some the first positive-negative-positive parasitic triode T1 of electrostatic charge process that power end Vdd and input/output interface end I/O are gathered, some the second positive-negative-positive parasitic triode T2, P type semiconductor substrate 300, the 2nd P type well region 303, the 2nd P type doped region 309 is discharged into earth terminal, simultaneously, external trigger voltage-regulating circuit 325 can draw high the current potential in the second base doping district 314, trigger NPN type triode T4 conducting, the electrostatic charge that input/output interface end I/O is gathered, process is by some NPN type triode T4, the one P type well region 302, the one P type doped region 310 is discharged into earth terminal, the electrostatic charge that input/output interface end I/O gathers in addition can also the mode by passive triggering and conducting be discharged into earth terminal Vss through a NPN type parasitic triode T3.Therefore, the first positive-negative-positive parasitic triode T1 in the electrostatic preventing structure of the embodiment of the present invention, the triggering and conducting of the second positive-negative-positive parasitic triode T2 and NPN type triode T4 is not the passive triggering after build-up of electrostatic charges, but the conducting of ACTIVE CONTROL parasitic transistor by external trigger voltage-regulating circuit 325, improved the sensitivity of electrostatic preventing structure release electrostatic, the electrostatic preventing structure of the embodiment of the present invention can pass through some the first positive-negative-positive parasitic triode T1 in addition, the second positive-negative-positive parasitic triode T2, the discharge path that NPN type three utmost point T4 and a NPN type parasitic triode T3 form discharges simultaneously, increased the path of electric discharge, improved the efficiency that static discharges.
Described the first inverter Rv1, the second inverter Rv2 and the 3rd inverter Rv3 are CMOS inverter or TTL inverter, and in the present embodiment, described the first inverter Rv1, the second inverter Rv2 and the 3rd inverter Rv3 are CMOS inverter.
Described electrostatic preventing structure also comprises switch nmos pass transistor N2; the drain electrode of switch nmos pass transistor N2 is connected with power end Vdd; the source electrode of switch nmos pass transistor N2 is connected with earth terminal Vss; the grid of switch nmos pass transistor N2 is connected with the first output b end of the first inverter Rv1, and switch nmos pass transistor N2 has increased the path of an electric discharge from power end Vdd to earth terminal Vss.
The electrostatic discharge protective circuit that above-mentioned electrostatic preventing structure forms please refer to Fig. 6, comprising: PMOS transistor P1, and the source region of PMOS transistor P1 is connected with power end Vdd with grid, and the drain region of PMOS transistor P1 is connected with input/output interface end I/O, nmos pass transistor N1, the drain region of nmos pass transistor N1 is connected with input/output interface end I/O, and the grid of nmos pass transistor N1 is connected with earth terminal Vss with source region, the first positive-negative-positive parasitic triode of the first positive-negative-positive parasitic triode T1(or some parallel connections), the base of the first positive-negative-positive parasitic triode T1 is connected with power end Vdd by the second dead resistance R2, the emitter region of the first positive-negative-positive parasitic triode T1 is connected with power end Vdd, and the collector region of the first positive-negative-positive parasitic triode T1 is connected with earth terminal Vss by the 4th dead resistance R4, the second positive-negative-positive parasitic triode of the second positive-negative-positive parasitic triode T2(or some parallel connections), the emitter region of the second positive-negative-positive parasitic triode T2 is connected with input/output interface end I/O, and the collector region of the second positive-negative-positive parasitic triode T2 is connected with earth terminal Vss by trixenie resistance R 3+4, the one NPN type parasitic triode of the one NPN type parasitic triode T3(or some parallel connections), the base of the one NPN type parasitic triode T3 is connected with earth terminal Vss by the 5th dead resistance R5, the emitter region of the one NPN type parasitic triode T3 is connected with earth terminal Vss, and the collector region of a NPN type parasitic triode T3 is connected with input/output interface end I/O, the NPN transistor of the some parallel connections of NPN transistor T4(), NPN transistor T4 collector region is connected with input/output interface end I/O, and the emitter region of NPN transistor T4 is connected with earth terminal Vss, also comprise: external trigger voltage-regulating circuit, described external trigger voltage-regulating circuit comprises RC coupling circuit and Nverter circuit, described RC coupling circuit comprises coupling capacitance C and the coupling resistance R1 of series connection, the other end of coupling resistance R1 is connected to power end Vdd, the other end of coupling capacitance C is connected to earth terminal Vss, RC switching node a is connected to Nverter circuit, described Nverter circuit comprises the first inverter Rv1 of series connection, the second inverter Rv2 and the 3rd inverter Rv3, the input of the first inverter Rv1 is connected with RC switching node a, the output of the first inverter Rv1 (or the first output b end) is connected with the input of the second inverter Rv2, the input of the output of the second inverter Rv2 (or the second output c end) and the 3rd inverter Rv3, the base of the base of the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2 is connected, the output of the 3rd inverter Rv3 (or the 3rd output d end) is connected with the base of NPN type triode T4, also comprise switch nmos pass transistor N2, the drain electrode of switch nmos pass transistor N2 is connected with power end Vdd, and the source electrode of switch nmos pass transistor N2 is connected with earth terminal Vss, and the grid of switch nmos pass transistor N2 is connected with the output of the first inverter Rv1.
The operation principle of foregoing circuit is: when power end Vdd produces instantaneous electrical potential difference due to gathering of static (or the parasitic diode that consists of the first drain region 306 and the 3rd N-type doped region 307 of the static of input/output interface end I/O accumulation be transmitted to power end Vdd make power end Vdd produce instantaneous electrical potential difference), the coupling in RC loop drags down the current potential that a is ordered, make a point for low level, anti-phase through the first inverter Rv1, b point (or first output) is high level, switch nmos pass transistor N2 conducting, power end Vdd passes through switch nmos pass transistor N2 to earth terminal Vss release electrostatic, b point high level is through after the second inverter Rv2 anti-phase, c point (or second output) becomes low level, the first positive-negative-positive parasitic triode T1 and the second positive-negative-positive parasitic triode T2 conducting, power end Vdd is by the first positive-negative-positive parasitic triode T1 to earth terminal Vss release electrostatic, and input/output interface end I/O passes through the second positive-negative-positive parasitic triode T2 to earth terminal Vss release electrostatic, c point becomes low level after the 3rd inverter Rv2 is anti-phase, d point (or the 3rd output) becomes high level, NPN type triode T4 conducting, input/output interface end I/O passes through NPN type triode T4 to earth terminal Vss release electrostatic, passive triggering and conducting under the effect of the static that simultaneously a NPN type parasitic triode T3 can input/output interface end I/O accumulation, is discharged into earth terminal Vss by the static of input/output interface end I/O accumulation.
To sum up, the electrostatic preventing structure of the embodiment of the present invention, the source region of the first base doping district and PMOS and Semiconductor substrate form the first positive-negative-positive parasitic triode, the drain region of the first base doping district and PMOS and Semiconductor substrate form the second positive-negative-positive parasitic triode, described some the second discrete base doping districts form some NPN transistor in parallel with the first N-type doped region and the second N-type doped region, therefore when input/output interface and/or power end accumulation static, static is by the first positive-negative-positive parasitic triode, the static that the NPN transistor of the second positive-negative-positive parasitic triode or some parallel connections forms discharges path and is discharged into earth terminal, increased the path that static discharges, improved the efficiency that static discharges, in addition, the second base doping district is connected with external trigger voltage-regulating circuit respectively with the first base doping district, thereby control the first positive-negative-positive parasitic triode by external trigger voltage-regulating circuit, the base current potential of the NPN transistor of the second positive-negative-positive parasitic triode and some parallel connections, make the first positive-negative-positive parasitic triode, the second positive-negative-positive parasitic triode becomes circuit from passive triggering and conducting and controls conducting, strengthened the control ability to parasitic triode, prevent that the static gathering from can not discharge timely and effectively.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. an electrostatic preventing structure, is characterized in that, comprising:
Semiconductor substrate, has the first N-type well region and a P type well region in described Semiconductor substrate, described the first N-type well region comprises first area and second area, and a described P type well region comprises the 3rd region and the 4th region;
Be positioned at the PMOS transistor of the first area of the first N-type well region, described PMOS transistor comprises the grid being positioned on the first N-type well region and is positioned at the source/drain region of grid both sides the first N-type well region, the transistorized source region of PMOS is connected with power end with grid, and the transistorized drain region of PMOS is connected with input/output interface end;
Be positioned at the first base doping district of the second area of the first N-type well region, the doping type in the first base doping district is N-type, the first base doping district is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit drags down the current potential in the first base doping district;
Be positioned at the nmos pass transistor in the 3rd region of a P type well region, described nmos pass transistor comprises the grid being positioned on a P type well region and is positioned at the source/drain region of grid both sides the one P type well region, the drain region of nmos pass transistor is connected with input/output interface end, and the grid of nmos pass transistor is connected with earth terminal with source region;
Be positioned at the second some discrete base doping district in the 4th region of a P type well region, the doping type in described the second base doping district is P type, the second base doping district is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit is drawn high the current potential in the second base doping district;
Be positioned at the first N-type doped region in the 4th region of a P type well region, described the first N-type doped region surrounds described some the second discrete base doping districts, and the first N-type doped region is connected with input/output interface end;
Be positioned at the second N-type doped region in the 4th region of a P type well region, described the second N-type doped region surrounds described the first N-type doped region and some the second discrete base doping districts, and the second N-type doped region is connected with earth terminal.
2. electrostatic preventing structure as claimed in claim 1; it is characterized in that; the source region of the first base doping district and PMOS and Semiconductor substrate form the first positive-negative-positive parasitic triode, and the drain region of the first base doping district and PMOS and Semiconductor substrate form the second positive-negative-positive parasitic triode.
3. electrostatic preventing structure as claimed in claim 1, is characterized in that, described some the second discrete base doping districts form some NPN transistor in parallel with the first N-type doped region and the second N-type doped region.
4. electrostatic preventing structure as claimed in claim 1; it is characterized in that; described the first N-type doped region comprises the sub-doped region of some N-types, and the quantity of the sub-doped region of N-type equals the quantity in the second base doping district, and the sub-doped region of each N-type surrounds the second corresponding base doping district.
5. electrostatic preventing structure as claimed in claim 1, it is characterized in that, described external trigger voltage-regulating circuit comprises RC coupling circuit and Nverter circuit, described RC coupling circuit comprises coupling capacitance and the coupling resistance of series connection, the other end of coupling resistance is connected to power end, the other end of coupling capacitance is connected to earth terminal, RC switching node is connected to Nverter circuit, described Nverter circuit comprises the first inverter of series connection, the second inverter and the 3rd inverter, the input of the first inverter is connected with RC switching node, the output of the first inverter is connected with the input of the second inverter, the output of the second inverter is connected with input and the first base doping district of the 3rd inverter, the output of the 3rd inverter is connected with the second base doping district.
6. electrostatic preventing structure as claimed in claim 5, is characterized in that, described the first inverter, the second inverter and the 3rd inverter are CMOS inverter or TTL inverter.
7. electrostatic preventing structure as claimed in claim 5; it is characterized in that; described electrostatic preventing structure also comprises switch nmos pass transistor; the drain electrode of switch nmos pass transistor is connected with power end; the source electrode of switch nmos pass transistor is connected with earth terminal, and the grid of switch nmos pass transistor is connected with the output of the first inverter.
8. electrostatic preventing structure as claimed in claim 1, is characterized in that, in described the first N-type well region, also has the 3rd N-type doped region, and the 3rd N-type doped region surrounds described PMOS transistor and the first base doping district, and the 3rd N-type doped region is connected with power end.
9. electrostatic preventing structure as claimed in claim 1; it is characterized in that; in a described P type well region, also there is a P type doped region; the one P type doped region surrounds described nmos pass transistor and the second base doping district, the first N-type doped region and the second N-type doped region, and a P type doped region is connected with earth terminal.
10. electrostatic preventing structure as claimed in claim 9, is characterized in that, also has the 2nd P type doped region between described nmos pass transistor and the second N-type doped region, and the two ends of the 2nd P type doped region contact with a P type doped region.
11. electrostatic preventing structures as claimed in claim 1, it is characterized in that, described PMOS transistor is that common source leaks PMOS transistor, described common source leaks PMOS transistor and comprises some the first source regions and the first drain region that is positioned at the first N-type well region alternate intervals distribution, and the first grid on the first N-type well region between the first adjacent source region and the first drain region, some first grids are connected with power end with the first source region, some the first drain regions are connected with input/output interface end, the first base doping district forms some the first positive-negative-positive parasitic triodes in parallel with some the first source regions and Semiconductor substrate, the first base doping district forms some the second positive-negative-positive parasitic triodes in parallel with some the first drain regions and Semiconductor substrate.
12. electrostatic preventing structures as claimed in claim 11; it is characterized in that; described second area is positioned at first grid on the bearing of trend of two ends extension; described the first base doping district is positioned at second area; the first base doping district equals the dispersion of distribution in the first source region and the first drain region along the length on the first source region and the first drain region distribution arrangement, the width in the first base doping district is 0.5～5 micron.
13. electrostatic preventing structures as claimed in claim 11, is characterized in that, the ion that adulterates in the first base doping district is phosphonium ion, arsenic ion or antimony ion.
14. electrostatic preventing structures as claimed in claim 1; it is characterized in that; described nmos pass transistor is that common source leaks nmos pass transistor; described common source leaks nmos pass transistor and comprises some the second source regions and the second drain region that is positioned at a P type well region alternate intervals distribution; and the second grid on the P type well region between the second adjacent source region and the second drain region; some the second source regions are connected with earth terminal with second grid, and some the second drain regions are connected with input/output interface end.
15. electrostatic preventing structures as claimed in claim 1, is characterized in that, the doping ion in the second base doping district is boron ion, gallium ion or indium ion.
16. electrostatic preventing structures as claimed in claim 1; it is characterized in that; in described Semiconductor substrate, also there is the second N-type well region and the 2nd P type well region; the second N-type well region and the 2nd P type well region are between the first N-type well region and a P type well region, and the first N-type well region, the 2nd P type well region, the second N-type well region and a P type well region are alternately distributed successively in Semiconductor substrate.
17. electrostatic preventing structures as claimed in claim 16, is characterized in that, in described the 2nd P type well region, have the 2nd P type doped region, and the 2nd P type doped region is connected with earth terminal.
18. 1 kinds of electrostatic discharge protective circuits, is characterized in that, comprising: PMOS transistor, and the transistorized source region of PMOS is connected with power end with grid, and the transistorized drain region of PMOS is connected with input/output interface end; Nmos pass transistor, the drain region of nmos pass transistor is connected with input/output interface end, and the grid of nmos pass transistor is connected with earth terminal with source region; The first positive-negative-positive parasitic triode, the emitter region of the first positive-negative-positive parasitic triode is connected with power end, the collector region of the first positive-negative-positive parasitic triode is by being connected with earth terminal, the base of the first positive-negative-positive parasitic triode is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit drags down the current potential of the first positive-negative-positive parasitic triode base; The second positive-negative-positive parasitic triode, the emitter region of the second positive-negative-positive parasitic triode is connected with input/output interface end, the collector region earth terminal of the second positive-negative-positive parasitic triode connects, the base of the second positive-negative-positive parasitic triode is connected with external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit drags down the current potential of the second positive-negative-positive parasitic triode base; The NPN type triode of some parallel connections, the emitter region of the NPN type triode of some parallel connections is connected with earth terminal, the collector region of the NPN type triode of some parallel connections is connected with input/output interface end, the base of NPN type triode of some parallel connections and being connected of external trigger voltage-regulating circuit, when power end produces instantaneous electrical potential difference, described external trigger voltage-regulating circuit is drawn high the current potential of a NPN type parasitic triode base.
19. electrostatic discharge protective circuits as claimed in claim 18, it is characterized in that, described external trigger voltage-regulating circuit comprises RC coupling circuit and Nverter circuit, described RC coupling circuit comprises coupling capacitance and the coupling resistance of series connection, the other end of coupling resistance is connected to power end, the other end of coupling capacitance is connected to earth terminal, RC switching node is connected to Nverter circuit, described Nverter circuit comprises the first inverter of series connection, the second inverter and the 3rd inverter, the input of the first inverter is connected with RC switching node, the output of the first inverter is connected with the input of the second inverter, the input of the output of the second inverter and the 3rd inverter, the base of the base of the first positive-negative-positive parasitic triode and the second positive-negative-positive parasitic triode is connected, the output of the 3rd inverter is connected with the base of the NPN type triode of some parallel connections.
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| US14/227,405 US8981483B2 (en) | 2013-03-28 | 2014-03-27 | ESD protection structure and ESD protection circuit |
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| CN110880502A (en) * | 2018-09-05 | 2020-03-13 | 无锡华润上华科技有限公司 | Semiconductor structure and motor driving device |
| CN110880502B (en) * | 2018-09-05 | 2022-10-14 | 无锡华润上华科技有限公司 | Semiconductor structure and motor driving device |
| CN111081703A (en) * | 2019-12-31 | 2020-04-28 | 广州新视界光电科技有限公司 | Electrostatic protection circuit and display device |
| CN111081703B (en) * | 2019-12-31 | 2023-12-26 | 广州新视界光电科技有限公司 | Electrostatic protection circuit and display device |
| WO2022027952A1 (en) * | 2020-08-06 | 2022-02-10 | 长鑫存储技术有限公司 | Electrostatic protection device for semiconductor |
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