CN1627532A

CN1627532A - I/O NMOS parts for reducing hot carrier's effect

Info

Publication number: CN1627532A
Application number: CN 200310109226
Authority: CN
Inventors: 钱文生; 那炜; 郭永芳; 肖胜安; 姚泽强
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2003-12-10
Filing date: 2003-12-10
Publication date: 2005-06-15

Abstract

The disclosed I/O NMOS device includes silicon substrate, source region and drain region on two sides of upper part of substrate, and grid oxide layer at upper part in middle of silicon substrate. Polysilicon layer is on grid oxide layer, and there are sidewalls on two sides of polysilicon layer and grid oxide layer. Position at middle part of substrate is higher than height of source region and drain region. In the said above structure, peak point of transverse electric field of channel caused by leakage voltage is far from surface of channel so as to reduce injection of hot carrier to grid oxide layer as well as reduce the said peak value of transverse electric field. Thus, effect of hot carrier is improved, service life and reliability of the disclosed I/O NMOS device is raised.

Description

A kind of I/O nmos device that reduces hot carrier's effect

Technical field

The present invention relates to the device of a kind of I/O NMOS, especially relate to a kind of device that reduces the I/O NMOS of hot carrier's effect.

Background technology

In present integrated circuit, I/O (I/O) device is important part.Compare with core devices, the I/O device has the characteristics of high working voltage and high driving ability.Though the channel length of I/O device is usually all greater than core devices, but under high working voltage, transverse electric field intensity in the device channel is much larger than core devices, so hot carrier's effect (HCE) is the problem that often runs in the I/O designs, also be the principal element that influences device reliability, especially nmos device.Solving conventional I/O device HCE is by adjusting the ion implanting conditions of its low doping source/leakage (LDD) and source/leakage (SD), reducing the method for channel laterally electric field.But the subject matter of this method is that Devices Characteristics also can be drifted about thereupon when adjusting ion and injecting, and all can change such as the threshold voltage and the saturation current of device, and the various parasitic capacitances of device also can change because of the dark change of source/drain junction.For the HCE problem that tackles the problem at its root, need be optimized the traditional devices structure, make device guarantee to increase substantially device lifetime under the constant prerequisite of characteristic, thereby guarantee the high reliability of device.The present invention has done tiny but very crucial optimization to the conventional device structure, proposes a kind of new device technology, can increase substantially device lifetime, changes the fundamental characteristics of device simultaneously hardly.

Summary of the invention

The objective of the invention is fundamentally to solve hot carrier's effect, guarantee the high reliability of device by conventional I/O device architecture is optimized.

The I/O nmos device that the present invention reduces hot carrier's effect comprises that the pars intermedia that the both sides, top of silicon substrate, substrate have source region and drain region, a silicon substrate has polysilicon layer, the both sides of polysilicon form side wall, it is characterized in that: the pars intermedia position of substrate is slightly higher than source region and drain region.

Another feature of the present invention is: have gate oxide between silicon substrate and the polysilicon layer, side wall is positioned at the both sides of gate oxide and polysilicon layer.

Owing to adopt said structure, the peak point of the channel laterally electric field that the I/ONMOS device that the present invention reduces hot carrier's effect is caused by drain voltage is just away from channel surface, effectively reduce the injection of hot carrier to gate oxide, reduce the peak value electric field value in the raceway groove simultaneously, significantly improve HCE (hot carrier's effect), thereby guarantee the high reliability of device.

Description of drawings

Fig. 1 is that the present invention reduces the preflood device of I/O NMOS of hot carrier's effect and the comparison diagram of existing device architecture.

Fig. 2 is that the present invention reduces the I/O nmos device of hot carrier's effect and the structure comparison diagram of existing device.

Fig. 3 is to use crystalline silicon to make the comparison diagram of the flow process of the old process of I/O NMOS and the I/O nmos device that the present invention reduces hot carrier's effect.

Fig. 4 is the device of the I/O NMOS that reduces hot carrier's effect of the present invention with TCAD simulation and the difference schematic diagram of existing device channel surface transverse electric field distribution.

Fig. 5 is the difference schematic diagram of the relation of the substrate current of the device of the present invention of TCAD simulation 0.35 μ m I/O NMOS of reducing hot carrier's effect and existing device and gate voltage.

Wherein:

1 silicon substrate, 2 polysilicons

3 oxide layers, 4 side walls

Embodiment

Below in conjunction with drawings and Examples the present invention is further described.

See also shown in the accompanying drawing 3, when prior art is made at I/O NMOS, at first on original silicon chip, forming gate oxide as silicon substrate; Second step i.e. deposit polysilicon above gate oxide; The 3rd step was to carry out polysilicon gate etching, carved the polysilicon that goes to I/O nmos device source/drain region, formed polysilicon gate; The 4th step promptly was the etching gate oxide, kept the oxide layer of above-mentioned polysilicon gate below; The 5th step reoxidized, and formed new oxide layer at the upper surface of device; The 6th step, carry out ion and inject, form low doping source/leakage (LDD); In the 7th step, carry out a deposited oxide layer again and carry out nitrogenize; In the 8th step, the etching nitration case forms side wall; Then carry out the making of other technical process.And in the I/O nmos device manufacturing process that reduces hot carrier's effect of the present invention, its making step is: at first form gate oxide 3 on as the original silicon chip of silicon substrate 1; Second step i.e. deposit polysilicon 2 above gate oxide 3; The 3rd step was to carry out polysilicon gate etching, carved the polysilicon 2 that goes to I/O nmos device source/drain region, formed polysilicon gate; The 4th step promptly was an etching oxidation layer 3, kept the oxide layer 3 at above-mentioned polysilicon 2 places; The 5th step, further adopt the selectivity dry etching, remove the silicon membrane layer of 200 , make process source/drain region a little less than the pipe grid region; The 6th step reoxidized, and formed new oxide layer at the upper surface of device; In the 7th step, ion injects, and forms low doping source/leakage (LDD); In the 8th step, carry out a deposited oxide layer again and carry out nitrogenize; In the 9th step, the etching nitration case forms side wall 4; Then carry out the making of other technical process.

By said process as can be known, the present invention's manufacture method of reducing the I/O nmos device of hot carrier's effect is compared the technology that only has a little change promptly to increase the silicon membrane layer of etching 200 later at traditional handicraft etching gate oxide with manufacture method of the prior art.The silicon membrane layer of etching 200 in the time of equally, also can the etching gate oxide.

See also Figure 1 and Figure 2, I/O nmos device by the invention described above fabrication techniques comprises the silicon substrate that monocrystalline silicon forms, the both sides, top of silicon substrate have through ion injects source region and the drain region that the back forms, and forms LDD knot and drain junction between the edge in source region and drain region and silicon substrate.The place, pars intermedia top of above-mentioned silicon substrate has gate oxide, the polysilicon layer that the gate oxide top has accumulation, and the both sides of polysilicon and gate oxide have silicon nitride and form side wall.Through the selectivity dry etching, the pars intermedia raceway groove position of substrate exceeds 200 than source region and drain region.

See also Fig. 4 and shown in Figure 5, because the present invention does not change the condition that any ion injects, therefore the threshold voltage and the saturation current of device can not change, and the various parasitic capacitances of device can not change yet, so the various characteristics of device can not change yet.Because the peak point of the channel laterally electric field that is caused by drain voltage of the present invention effectively reduces the injection of hot carrier to gate oxide just away from channel surface, reduce the interior peak value electric field value of raceway groove simultaneously, significantly improve HCE.The present invention has done tiny but very crucial optimization to the conventional device structure, proposes a kind of new device technology, and TCAD simplation verification new device can increase substantially device lifetime, changes the fundamental characteristics of device simultaneously hardly.

Claims

1. I/O nmos device that is used to reduce hot carrier's effect, the place, pars intermedia top that the both sides, top that comprise silicon substrate, silicon substrate have source region and drain region, silicon substrate has gate oxide, has polysilicon layer on the gate oxide, the both sides of polysilicon and gate oxide have side wall, it is characterized in that: silicon substrate is slightly higher than source region and drain region in the part of the corresponding polysilicon layer in centre.

2. the I/O nmos device that is used to reduce hot carrier's effect as claimed in claim 1 is characterized in that: described silicon substrate in the part of the corresponding polysilicon layer in centre than source region and high 200 in drain region.

3. the I/O nmos device that is used for the reduction of heat carrier effect as claimed in claim 1 is characterized in that: the composition of described side wall is a silicon nitride.