CN106033716A - Manufacturing method of LTPS assembly - Google Patents
Manufacturing method of LTPS assembly Download PDFInfo
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- CN106033716A CN106033716A CN201510116897.9A CN201510116897A CN106033716A CN 106033716 A CN106033716 A CN 106033716A CN 201510116897 A CN201510116897 A CN 201510116897A CN 106033716 A CN106033716 A CN 106033716A
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- assembly
- polysilicon layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 61
- 150000002500 ions Chemical class 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 71
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 52
- 229920005591 polysilicon Polymers 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000002347 injection Methods 0.000 claims abstract description 7
- 239000007924 injection Substances 0.000 claims abstract description 7
- 239000002019 doping agent Substances 0.000 claims description 24
- 238000002513 implantation Methods 0.000 claims description 21
- 238000002360 preparation method Methods 0.000 claims description 14
- 239000011521 glass Substances 0.000 claims description 11
- 238000000429 assembly Methods 0.000 claims description 9
- 230000000712 assembly Effects 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229920003023 plastic Polymers 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000001771 vacuum deposition Methods 0.000 claims description 3
- -1 boron ion Chemical class 0.000 claims description 2
- 239000007792 gaseous phase Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract 3
- 230000006872 improvement Effects 0.000 description 17
- 229920001621 AMOLED Polymers 0.000 description 10
- 230000005611 electricity Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Geometry (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a LTPS assembly. The method comprises the following steps of providing a substrate and manufacturing and forming a polysilicon layer on the substrate; manufacturing and forming a grid metal layer on the polysilicon layer; for the polysilicon layer, carrying out first ion implantation as a first injection dosage so as to form a source electrode area, a drain electrode area and a channel area located between the source electrode area and the drain electrode area in the polysilicon layer; carrying out heating processing on the polysilicon layer so that doped ions of the first ion implantation are diffused towards the direction of the channel area; and for the polysilicon layer, carrying out second ion implantation as a second injection dosage so as to form lightly-doped drain structures between the channel area and the source electrode area, and the channel area and the drain electrode area, wherein the second injection dosage is greater than the first injection dosage. The formed lightly-doped drain structures can reduce an electric quantity difference value between the source electrode area and the drain electrode area of two sides of the channel area, and then a leakage current phenomenon of the LTPS assembly is improved, a condition that the leakage current is too large so that an assembly operation is unstable and even loses efficacy and image quality of a display is influenced is avoided.
Description
Technical field
The present invention designs AMOLED Display Technique, refers in particular to the manufacturer of a kind of LTPS assembly
Method.
Background technology
In flat panel display, active matrix organic light-emitting diode (Active Matrix Organic
Light Emitting Diode, AMOLED) display is frivolous with it, active illuminating, fast-response speed
The many merits such as degree, wide viewing angle, rich color and high brightness, low-power consumption, high-low temperature resistant and by industry
Being known as is the third generation Display Technique after liquid crystal display (LCD).AMOLED is new
Display technology from generation to generation, it has self-luminous, wide viewing angle, contrast, low power consumption, high response speed
The advantages such as degree, high-resolution, full-color slimming, having challenge becomes the display technology of following main flow.
In prior art, the LTPS components of AMOLED device mainly uses LTPS (Low
Temperature Poly Silicon, low temperature polycrystalline silicon) processing procedure, Fig. 1 is existing LTPS assembly
Structural representation after gate metal layer completes, shown in Figure 1, due to existing
The LTPS components of AMOLED device, including substrate 90, the polycrystalline that is prepared on substrate 90
Silicon layer (P-Si) 91, gate metal layer 92 and preparation are formed at substrate 90 and polysilicon layer 91
Between, and the insulating barrier 93 between polysilicon layer 91 and gate metal layer 92.Wherein, polycrystalline
It is formed with channel region 911 on silicon layer 91 and is formed at the source area of channel region 911 both sides
(Source) 912 and drain region (Drain) 913.
Due between source area 912 and the drain region 913 of channel region 911 both sides of polysilicon layer 91
Electric field energy differ greatly, therefore LTPS assembly electrical performance goes out to have relatively large leakage phenomenon,
The quality of image (such as display bright spot) of display can be affected when this leakage current is excessive.Therefore, AMOLED
The good corrupt of the LTPS components of device will determine the final display quality of AMOLED device.Cause
This, it is necessary to the LTPS assembly of existing AMOLED device is improved.
Summary of the invention
Because the problem of leakage current easily occurs in the LTPS assembly of above-mentioned prior art, the present invention carries
Supply the manufacture method of a kind of LTPS assembly, including:
Substrate is provided, and prepares formation polysilicon layer on the substrate；
On described polysilicon layer, preparation forms gate metal layer；
Ion implanting for the first time is carried out with the first implantation dosage, thereby described for described polysilicon layer
Form source area, drain region and between described source area and described drain region in polysilicon layer
Channel region；
Described polysilicon layer is carried out heat treated, and the dopant ion making described first time ion implanting is past
The direction of described channel region is diffused；And
Second time ion implanting is carried out with the second implantation dosage, at described raceway groove for described polysilicon layer
Formed respectively between district and described source area and between described channel region and described drain region and be lightly doped
Drain structure, wherein, described second implantation dosage is more than described first implantation dosage.
The manufacture method of LTPS assembly of the present invention, first carrying out ion implanting for the first time is low dosage, then
Carry out heat treated, make the dopant ion of low dosage be diffused toward the direction of channel region, then carry out
Secondary ion is injected to high dose, between channel region and source area, and channel region and drain region it
Between form lightly doped drain structure respectively, can reduce between source area and the drain region of channel region both sides
Electricity difference, and then improve the leakage phenomenon of LTPS assembly, it is to avoid due to leakage current is excessive causes group
Part fluctuation of service even lost efficacy, and then affected the quality of image of display.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described first time ion is noted
The dopant ion entered is p-type dopant ion with the dopant ion of described second time ion implanting.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described p-type dopant ion
For boron ion.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described first implantation dosage
For 1E14, described second implantation dosage is 1E15.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, carry out described first time from
Implantation Energy when son injects is with Implantation Energy when carrying out described second time ion implanting
30KeV。
Further improvement is that of the manufacture method of LTPS assembly of the present invention, enters described polysilicon layer
Heating-up temperature during row heat treated is between 580 DEG C to 600 DEG C.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described heating-up temperature is
590℃。
Further improvement is that of the manufacture method of LTPS assembly of the present invention, enters described polysilicon layer
Heat time heating time during row heat treated is between 10 minutes to 30 minutes.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described heat time heating time is 15
Minute.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described lightly doped drain structure
Width be between 0.15 micron to 0.45 micron.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described lightly doped drain structure
Width be 0.3 micron.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, on described polysilicon layer
After preparation forms described gate metal layer, in described gate metal layer, form one layer of light resistance glass；With
And before carrying out first time ion implanting in described polysilicon layer, first described gate metal layer is carried out
The removal of described smooth resistance glass.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described substrate is by with glass
Glass, plastics or the transparency carrier that quartz is material.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, in described polysilicon layer
Before carrying out first time ion implanting, further comprise the steps of: between described substrate and described polysilicon layer,
And preparation forms insulating barrier between described polysilicon layer and described gate metal layer.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described insulating barrier is oxidation
Silicon layer, silicon nitride layer or silicon oxide layer and the combination layer of silicon nitride layer.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described insulating barrier is to pass through
Plasma enhanced chemical vapor deposition method or the preparation of low-pressure chemical vapour deposition technique are formed.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described gate metal layer
Material is molybdenum.
Further improvement is that of the manufacture method of LTPS assembly of the present invention, described gate metal layer is
Formed by sputtering or vacuum deposition method preparation.
Accompanying drawing explanation
Fig. 1 is existing LTPS assembly structural representation after gate metal layer completes.
Fig. 2 is the flow chart of the manufacture method of LTPS assembly of the present invention.
Fig. 3 be LTPS assembly of the present invention manufacture method in LTPS assembly gate metal layer make
Structural representation after completing.
Fig. 4 be LTPS assembly of the present invention manufacture method in LTPS assembly in first time ion implanting
After structural representation.
Fig. 5 be LTPS assembly of the present invention manufacture method in LTPS assembly knot after a heating treatment
Structure schematic diagram.
Fig. 6 be LTPS assembly of the present invention manufacture method in LTPS assembly in second time ion implanting
After structural representation.
Fig. 7 be LTPS assembly of the present invention manufacture method in LTPS assembly formed lightly doped drain structure
After structural representation.
Fig. 8 is the LTPS assembly of the manufacture method using LTPS assembly of the present invention and existing LTPS
Electricity contrast difference figure between the source-drain electrode of assembly.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing
And embodiment, the present invention is further elaborated.Should be appreciated that described herein specifically
Embodiment only in order to explain the present invention, is not intended to limit the present invention.
Fig. 2 is the flow chart of the manufacture method of LTPS assembly of the present invention, coordinates referring to shown in Fig. 2,
The manufacture method of the LTPS assembly of the present invention, including:
S101 provides substrate, and prepares formation polysilicon layer on the substrate；
S102 prepares formation gate metal layer on described polysilicon layer；
Fig. 3 be LTPS assembly of the present invention manufacture method in LTPS assembly gate metal layer make
Structural representation after completing.Specifically, in conjunction with shown in Fig. 3, it is provided that substrate 10, at substrate 10
Upper preparation forms polysilicon layer 20.Wherein, substrate 10 is by with glass, plastics or quartz as material
Transparency carrier.
On polysilicon layer 20, formation gate metal layer 30, grid are prepared by sputtering or vacuum deposition method
The material of pole metal level 30 preferably uses molybdenum (Mo).
Sunk by plasma enhanced chemical vapor deposition method (PECVD) or low-pressure chemical gaseous phase
Area method (LPCVD) is between substrate 10 and polysilicon layer 20, and polysilicon layer 20 and grid
Between metal level 30, preparation forms insulating barrier 40.Insulating barrier 40 preferably silicon oxide layer (SiO),
Silicon nitride layer (SiN) or silicon oxide layer and the combination layer of silicon nitride layer.
S103 carries out ion implanting for the first time for described polysilicon layer with the first implantation dosage, thereby
In described polysilicon layer, form source area, drain region and be positioned at described source area and described drain electrode
Channel region between district；
Specifically, after on polysilicon layer 20, preparation forms gate metal layer 30, gate metal layer
One layer of light resistance glass can be formed on 30, before carrying out first time ion implanting in polysilicon layer 20,
First gate metal layer 30 is carried out the removal of light resistance glass.
Fig. 4 be LTPS assembly of the present invention manufacture method in LTPS assembly in first time ion implanting
After structural representation.Shown in Fig. 4, after light resistance glass is removed, with 1E14/cm2Injection
Dosage and the Implantation Energy of 30KeV, carry out ion implanting for the first time in polysilicon layer 20.First
After secondary ion injects, in polysilicon layer 20, form source area 220, drain region 230 and be positioned at
Channel region 210 between source area 220 and drain region 230.Wherein, channel region 210 is positioned at grid
The underface of metal level 30.
Preferably, the dopant ion of ion implanting is p-type dopant ion for the first time, more preferably
Boron (B) ion.As shown in Figure 4, for the first time after ion implanting, source area 220 and drain region 230
Interior doped with P-dopant ion.
S104 carries out heat treated to described polysilicon layer, makes the doping of described first time ion implanting
Ion is diffused toward the direction of described channel region；
Fig. 5 be LTPS assembly of the present invention manufacture method in LTPS assembly knot after a heating treatment
Structure schematic diagram.Specifically, shown in Fig. 5, with the heating-up temperatures of 580～600 DEG C to polysilicon
Layer 20 carries out heat treated, and heat time heating time, control was between 10～30 minutes, makes ion note for the first time
The dopant ion entered is diffused toward the direction of channel region 210.Preferably, heating-up temperature is set to
590 DEG C, will be set to heat time heating time 15 minutes.
When the distance of the diffusion of the dopant ion of first time ion implanting is less than 0.15 micron, finally
Lightly doped drain (LDD) structure formed may be too small, may deteriorate film characteristics.When
When the distance of the diffusion of the dopant ion of ion implanting is more than 0.45 micron for the first time, ditch can be caused again
The width in road district 210 is too small, causes electronics and the hole can not smooth flow.Therefore, will for the first time from
The distance controlling of the diffusion of the dopant ion that son injects is between 0.15～0.45 micron.Preferably, will
The distance controlling of the diffusion of the dopant ion of ion implanting is at 0.3 micron for the first time.
S105 carries out second time ion implanting for described polysilicon layer with the second implantation dosage, in institute
State between channel region and described source area and formed respectively between described channel region and described drain region
Lightly doped drain structure, wherein, described second implantation dosage is more than described first implantation dosage.
Fig. 6 be LTPS assembly of the present invention manufacture method in LTPS assembly in second time ion implanting
After structural representation, Fig. 7 be LTPS assembly of the present invention manufacture method in LTPS assembly formed
Structural representation after lightly doped drain structure.
Specifically, shown in Fig. 6, with 1E15/cm2Implantation dosage and the injection energy of 30KeV
Amount, carries out second time ion implanting in polysilicon layer 20.Preferably, ion implanting for the second time
Dopant ion is p-type dopant ion, more preferably boron (B) ion.As shown in Figure 6, second
After secondary ion injects, doped with P+ dopant ion in source area 220 and drain region 230, but,
The part blocked by gate metal layer 30 is still doped with P-dopant ion.Therefore, shown in Fig. 7,
For the second time after ion implanting, between channel region 210 and source area 220, and channel region 210
And between drain region 230, just form respectively lightly doped drain structure 240, lightly doped drain structure 240
Width is equal to the distance that the dopant ion of above-mentioned first time ion implanting spreads after heat treated.
The manufacture method of LTPS assembly of the present invention, first carrying out ion implanting for the first time is low dosage, then
Carry out heat treated, make the dopant ion of low dosage be diffused toward the direction of channel region, then carry out
Secondary ion is injected to high dose, between channel region and source area, and channel region and drain region it
Between form lightly doped drain structure respectively, can reduce between source area and the drain region of channel region both sides
Electricity difference, and then improve the leakage phenomenon of LTPS assembly, it is to avoid due to leakage current is excessive causes group
Part fluctuation of service even lost efficacy, and then affected the quality of image of display.
Fig. 8 is the LTPS assembly of the manufacture method using LTPS assembly of the present invention and existing LTPS
Electricity contrast difference figure between the source-drain electrode of assembly, wherein curve A represents employing LTPS of the present invention
Electricity difference between the source-drain electrode of the LTPS assembly after the manufacture method of assembly, curve B represents existing
Electricity difference between the source-drain electrode of some LTPS assemblies.
As can be seen from Figure 8, the LTPS assembly of the manufacture method of LTPS assembly of the present invention is used
Source-drain electrode between electricity difference be substantially less than the electricity between the source-drain electrode of existing LTPS assembly
Amount difference.Therefore, use the manufacture method of LTPS assembly of the present invention, channel region both sides can be reduced
Source area and drain region between electricity difference, and then improve the leakage phenomenon of LTPS assembly,
Avoid that due to leakage current is excessive causes assembly fluctuation of service even to lose efficacy, and then affect the image of display
Quality.
The above is only presently preferred embodiments of the present invention, not the present invention is done any in form
Restriction, although the present invention is disclosed above with preferred embodiment, but is not limited to the present invention,
Any those skilled in the art, in the range of without departing from technical solution of the present invention, when can profit
Make a little change with the technology contents of the disclosure above or be modified to the Equivalent embodiments of equivalent variations, but
Every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention is to above example
Any simple modification, equivalent variations and the modification made, all still falls within the scope of technical solution of the present invention
In.
Claims (18)
1. the manufacture method of a LTPS assembly, it is characterised in that including:
Substrate is provided, and prepares formation polysilicon layer on the substrate；
On described polysilicon layer, preparation forms gate metal layer；
Ion implanting for the first time is carried out with the first implantation dosage, thereby described for described polysilicon layer
Form source area, drain region and between described source area and described drain region in polysilicon layer
Channel region；
Described polysilicon layer is carried out heat treated, and the dopant ion making described first time ion implanting is past
The direction of described channel region is diffused；And
Second time ion implanting is carried out with the second implantation dosage, at described raceway groove for described polysilicon layer
Formed respectively between district and described source area and between described channel region and described drain region and be lightly doped
Drain structure, wherein, described second implantation dosage is more than described first implantation dosage.
2. the manufacture method of LTPS assembly as claimed in claim 1, it is characterised in that described the
The dopant ion that primary ions is injected is p-type doping with the dopant ion of described second time ion implanting
Ion.
3. the manufacture method of LTPS assembly as claimed in claim 2, it is characterised in that described P
Type dopant ion is boron ion.
4. the manufacture method of LTPS assembly as claimed in claim 1, it is characterised in that described the
One implantation dosage is 1E14, and described second implantation dosage is 1E15.
5. the manufacture method of LTPS assembly as claimed in claim 1, it is characterised in that carry out institute
Implantation Energy when stating for the first time ion implanting and injection energy when carrying out described second time ion implanting
Amount is 30KeV.
6. the manufacture method of LTPS assembly as claimed in claim 1, it is characterised in that to described
Heating-up temperature when polysilicon layer carries out heat treated is between 580 DEG C to 600 DEG C.
7. the manufacture method of LTPS assembly as claimed in claim 6, it is characterised in that described in add
Hot temperature is 590 DEG C.
8. the manufacture method of LTPS assembly as claimed in claim 1, it is characterised in that to described
Heat time heating time when polysilicon layer carries out heat treated is between 10 minutes to 30 minutes.
9. the manufacture method of LTPS assembly as claimed in claim 8, it is characterised in that described in add
The heat time is 15 minutes.
10. the manufacture method of LTPS assembly as claimed in claim 1, it is characterised in that described gently
The width of doped drain structure is between 0.15 micron to 0.45 micron.
The manufacture method of 11. LTPS assemblies as claimed in claim 10, it is characterised in that described
The width of lightly doped drain structure is 0.3 micron.
The manufacture method of 12. LTPS assemblies as claimed in claim 1, it is characterised in that described
After preparation forms described gate metal layer on polysilicon layer, in described gate metal layer, form one layer of light
Resistance glass；And before carrying out first time ion implanting in described polysilicon layer, first to described grid
Metal level carries out the removal of described smooth resistance glass.
The manufacture method of 13. LTPS assemblies as claimed in claim 1, it is characterised in that described base
Plate is by the transparency carrier with glass, plastics or quartz as material.
The manufacture method of 14. LTPS assemblies as claimed in claim 1, it is characterised in that described
Carry out for the first time before ion implanting in polysilicon layer, further comprise the steps of: at described substrate and described many
Between crystal silicon layer, and between described polysilicon layer and described gate metal layer, preparation forms insulating barrier.
The manufacture method of 15. LTPS assemblies as claimed in claim 14, it is characterised in that described
Insulating barrier is the combination layer of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer.
The manufacture method of the 16. LTPS assemblies as described in claims 14 or 15, it is characterised in that
Described insulating barrier is to be deposited by plasma enhanced chemical vapor deposition method or low-pressure chemical gaseous phase
Method preparation is formed.
The manufacture method of 17. LTPS assemblies as claimed in claim 1, it is characterised in that described grid
The material of pole metal level is molybdenum.
The manufacture method of 18. LTPS assemblies as claimed in claim 17, it is characterised in that described
Gate metal layer is formed by sputtering or vacuum deposition method preparation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510116897.9A CN106033716A (en) | 2015-03-17 | 2015-03-17 | Manufacturing method of LTPS assembly |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510116897.9A CN106033716A (en) | 2015-03-17 | 2015-03-17 | Manufacturing method of LTPS assembly |
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| CN106033716A true CN106033716A (en) | 2016-10-19 |
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| CN201510116897.9A Pending CN106033716A (en) | 2015-03-17 | 2015-03-17 | Manufacturing method of LTPS assembly |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6479350B1 (en) * | 1999-08-18 | 2002-11-12 | Advanced Micro Devices, Inc. | Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers |
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