CN1625811A - Enhnced cut-off frequency silicon germanium transistor - Google Patents
Enhnced cut-off frequency silicon germanium transistor Download PDFInfo
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- CN1625811A CN1625811A CNA028287622A CN02828762A CN1625811A CN 1625811 A CN1625811 A CN 1625811A CN A028287622 A CNA028287622 A CN A028287622A CN 02828762 A CN02828762 A CN 02828762A CN 1625811 A CN1625811 A CN 1625811A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 123
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 2
- 238000003032 molecular docking Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013213 extrapolation Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
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Abstract
A bipolar transistor for a small signal amplifier that has improved Early voltages, and hence enhanced cutoff frequency. The SiGe layer has a thickness (t) and a Ge content that is greater than the stability limit. The misfit dislocations do not create appreciable charge trapping sites, and do not extend into the overlying base/collector junction such that performance is improved without yield degradation.
Description
Technical field
The present invention relates to SiGe (SiGe) heterojunction bipolar transistor (HBT).
Background technology
Usually known by using the wafer that on silicon substrate, comprises one or more layers SiGe (SiGe) to form HBT.On this substrate, because lattice constant different between SiGe film and the silicon substrate, germanium atom produces mechanical strain in composite membrane.In the plane of silicon substrate, the SiGe lattice that lattice constant is bigger is pressed on the less silicon substrate of lattice constant.In the plane perpendicular to silicon substrate, the lattice constant of SiGe layer is greater than the lattice constant of silicon substrate, and is under the tensile stress thus.Strain with Ge atom itself the SiGe film and below natural Si substrate between produce bandgap offset.This bandgap offset has strengthened the charge carrier diffusion on the base and has improved transistor speed thus by produced stepped zone in the base, and the distinct advantages of SiGe HBT is provided thus.SiGe HBT be used for small signal amplifier (that is, and change about 5 volts or littler) transistor, with the switching speed (more than the 1GHz) that provides present radio communication device to need.
During SiGe HBT was used for small signal amplifier, one of them difficulty that the inventor runs into was that the output characteristic (that is, collector current and collector emitter voltage) that is used for the common emitter of this amplifier demonstrates relatively poor early voltage usually." early voltage " (V
A) be the slope characteristics of these output characteristic, the voltage when being IC=0A as curve extrapolation is indicated.The curve water crossing is flat, and the voltage of IC=0 extrapolation place is big more, so early voltage is high more.Fig. 1 a (prior art) shows the early voltage that does not use SiGe HBT when of the present invention.Each curve shows for the different output characteristic that applies base current; Curve is high more, and the base current that applies is high more.Should notice that it is more vertical that slope of a curve becomes along with the base current that applies increases.
The inventor has been noted that V
ACurrent gain cutoff frequencies (f for SiGe HBT
T) key indication.Have now found that and have low V
AThe NPN device have low f
TThe device that current gain cutoff frequencies reduces provides the suboptimum switching speed.
Therefore, need to develop SiGe HBTs in this area, and then improved current gain cutoff frequencies with enhancing early voltage.
Summary of the invention
An object of the present invention is to increase the current gain cutoff frequencies of SiGe HBTs thus.
In first scheme, the present invention is a kind of SiGe HBT, comprises the thickness that has and the Ge concentration SiGe layer greater than the SiGe limit of stability, and a plurality of misfit dislocations wherein do not produce significant charge-trapping position.
In another program, the present invention is a kind of SiGe HBT, have on a plurality of isolation structures thickness at least about 70nm, Ge concentration is at least 10% SiGe layer, the collector on the isolation structure and a plurality of misfit dislocations of significantly not extending on collector.
In another program, the present invention is the bipolar transistor that is used to have at least about the small signal amplifier of the cut-off frequency of 19GHz, has thickness and Ge concentration SiGe layer greater than the SiGe limit of stability, a plurality of isolated areas of docking with described collector area, and be formed on base on the described collector area, a plurality of misfit dislocations in the described SiGe layer are adjacent with described a plurality of isolated area and extend in the described collector area, and the while does not extend in the described base basically.
In another program, the present invention is a kind of method that forms bipolar transistor, may further comprise the steps: form a plurality of isolated areas in silicon substrate; Form the SiGe layer on described substrate and described isolated area, thickness that described SiGe layer has and Ge concentration are greater than the SiGe limit of stability; And mixing described SiGe layer and substrate to form collector area with first dopant, wherein said collector area comprises a plurality of misfit dislocations, does not extend to basically in the other parts that described collector area enters bipolar transistor outward.
Description of drawings
By the detailed description of the present invention shown in following, above and other structure of the present invention and characteristics will become more obvious.In the following description, with reference to accompanying drawing, wherein:
Fig. 1 a is the IC of the SiGe HBT of experiment and the curve chart of VCE;
Fig. 1 b is the IC of SiGe HBT of the present invention and the curve chart of VCE;
Fig. 2 shows the Collector Current Density of NPN and the curve chart of cut-off frequency, and NPN has the early voltage that is presented at respectively among Fig. 1 a and the 1b;
Fig. 3 is the curve chart of SiGe concentration and thickness, shows a plurality of experimental data points that superpose on the SiGe stability curve that comprises of the present invention and prior art article report;
Fig. 4 is the profile according to the SiGe HBT of the instruction formation of the first embodiment of the present invention;
Fig. 5 shows the Gummel curve chart (IC, IB and VCE) of NPN, and NPN has the early voltage that is presented at respectively among Fig. 1 a and the 1b;
Fig. 6 is the standard finished products rate data of the thickness of the SiGe HBT that data point shows among Fig. 3; And
Fig. 7 is the curve chart of three embodiment of the Ge concentration of SiGe layer of the present invention and layer thickness.
Embodiment
The inventor finds can significantly improve early voltage (so cut-off frequency) by the thickness that increases the SiGe layer.Though the known in the prior art purpose for other increases the thickness of SiGe layer, yet, owing to worry to produce misfit dislocation, avoid thicker SiGe layer usually.As below introducing in detail, the inventor finds that misfit dislocation can not influence performance or the rate of finished products of gained SiGeHBT negatively when suitably controlling.
Because intrinsic lattice mismatch in the Si-Ge compound, by introducing mechanical strain, SiGe has improved charge mobility.Yet if there is too many Ge, if perhaps the SiGe layer is too thick, acceptable understanding is that the gained crystal dislocation will reduce performance and rate of finished products in this area so.Cause mis-behave because the bandgap offset that mechanical stress produced SiGe and provide has been provided dislocation.Since defective effect the crystal of substrate cause rate of finished products to worsen.In fact, this general understanding becomes very universal, usually be recognized as " Matthews-Blakesley limit of stability " or " the Stiffler limit ", at first report these interactional researchers (people such as Stiffler with approval, Journal of Applied Physics, Vol.71, No.10,4820-4825 page or leaf; Matthews and Blakeslee " Defects in EpitaxialMultilayer ", 118-125 page or leaf (1974) among the Journal of Crystal Growth 27).For ease of later reference, these results will be referred to as " SiGe limit of stability ".Be plotted among Fig. 3 with the different SiGe limit of stability of Stiffler report by Matthews-Blakesley, show the best relation between SiGe thickness and the Ge concentration.
More research concentrates on by eliminating the whole bag of tricks that these misfit dislocations surmount the SiGe limit of stability.Referring to people's such as Laderman U.S. patent 5,256,550, use low-temperature epitaxy deposition techniques the one SiGe layer has been discussed, cap Si layer then connects suitable thermal cycle afterwards and forms the thicker SiGe layer that does not have misfit dislocation.In this structure, need to cover the Si layer, to keep the strain of SiGe layer, do not produce misfit dislocation simultaneously.People's such as K.Schonenberg paper, exercise question is " TheStability of SiGe Strained Layers on Small Area Trench Isolated SiliconIslands ", Electrochemical Society Proceedings, Vol.96-4, Proceedings of the4
ThInternational Symposium on Process Physics and Modeling inSemiconductor Technology.Los Angeles, the CA 5-10 month in 1996, the 296-308 page or leaf, reported reducing of the SiGe district size of surrounding along with isolated area, observed defect concentration reduces, revised shallow trench isolation from technology reducing stress.The content relevant with this zone also is reported in Vescan, " Selective Epitaxial Growth of Strained SiGe/Si forOptoelectronic Devices; " Materials Science and Engineering B, Solid-StateMaterials for Advanced Technology, Vol.51, No.1-3,166-69 page or leaf (1998).
Another reason that will avoid misfit dislocation in the active area of bipolar transistor is to prevent to produce the charge-trapping position.If these charge-trapping positions exist enough quantity will reduce the life-span of minority carrier.In typical bipolar transistor, this causes current gain to reduce, and this is undesirable in small-signal applications.Yet, in power amplifier is used, can tolerate the current gain that reduces.Thus, taught the dislocation of having a mind in the U.S. patent 5,097,308,, reduced the life-span of the minority carrier in the bipolar power rectifier thus so that the trap that makes minority carrier how compound to be provided by SiGe-Si interface introducing 9-20 μ m.In bipolar rectifier, need low minority carrier lifetime to increase switching speed.Determine switching speed in the bipolar transistor by the degree of removing the electric charge in the base fast.A kind of charge removal process is compound, and compound so that transistor ends in the charge-trapping position electronics and hole thus.Yet, amplify application for the SiGe bipolar transistor small signal of standard, do not wish to follow the current gain that reduces of this minority carrier lifetime (can avoid in fact usually; As mentioned above, the described minimizing of switching speed is incompatible with the target that increases the cut-off current gain frequency).
The inventor has now found that by being compounded to form the SiGe layer in the thickness/concentration greater than the SiGe stability curve, significantly improved early voltage, increased cut-off frequency, do not produce misfit dislocation and significantly discharged mechanical stress and produced the bandgap offset that SiGe provides, have no significant effect the crystal of substrate.Fig. 3 shows and is used to provide the SiGe thickness and the concentration of the data of report here.For comparison purpose, the Ge concentration fixed is 10%, and increase thickness.Should notice that preceding two data points are positioned at or are lower than the SiGe stability curve; These devices provide the early voltage result shown in Fig. 1 a.SiGe thickness of the present invention originates in about 70nm.
As shown in Figure 4, SiGe HBT of the present invention forms and has within it on the monocrystalline substrate 10 of shallow channel isolation area (STI) 12.Use conventional technology extension ground growth SiGe layer 14 on substrate 10 to arrive the thickness of 40nm at least, Ge concentration is at least about 10%.Suitably mixing forms after the collector area 14C, growing period with the in-situ doped SiGe layer of boron with formation base 14B (laterally not being shown to scale).Should notice in fact that boron from the base can spread during multiple processing thermal cycle is deep in the SiGe layer, is deep into degree of depth Y by the degree of depth X of SiGe layer 14.So, can produce substrate/collector junction at JA or JB.Thus, use technique known to form the emitter electrode (not shown) subsequently to finish the formation of HBT.HBT of the present invention then is connected to other HBT that is formed on the substrate, to form integrated circuit.
Fig. 1 b shows collector circuit and the collector emitter voltage of SiGe HBT of the present invention.Should note significantly improving early voltage (for all base voltages that applies, curve is level very, and meaning for collector emitter voltage increases, and collector current is constant).
Fig. 2 shows for the Collector Current Density under a and the b situation and the curve chart of cut-off frequency: the NPN (shown in the dotted line) that (a) has early voltage shown in Fig. 1 a; And the NPN (shown in the solid line) that early voltage shown in Fig. 1 b (b) is arranged.Should notice that having the transistor that improves early voltage for the present invention has increased cut-off frequency.The about 19GHz of peak F t.Should note scope upper cut off frequency increase equally at the collector current of broad.
A scheme of the present invention is that these gains and the cut-off frequency in the early voltage is not cost to reduce performance (passing through charge-trapping) or rate of finished products (passing through crystal dislocation).
At first consider charge-trapping, should note at first observing the cut-off frequency shown in Fig. 4 increases; If introduced suitable charge-trapping by misfit dislocation, the gained charge carrier is compound will to reduce cut-off frequency, not increase it.And Fig. 5 shows the Gummel curve (IC, IB and VCE) of NPN, has the early voltage shown in Fig. 1 a and the 1b respectively.(n under the room temperature～1 (n is desirable measurement) or 60mV/decade) shows the remarkable charge-trapping that does not exist by the misfit dislocation introducing that forms as a thicker SiGe part should to note IB in the Gummel curve and IC having desirable slope.One of them result who avoids increasing charge-trapping has obtained the puncture voltage (BVCEO) that these higher cut-off frequencies responsively do not reduce device simultaneously shown in Fig. 1 a and 1b; Perhaps, change kind of a mode, along with the increase of SiGe thickness, the device cut-off frequency Ft with given puncture voltage BVCEO increases.For the designs that needs the high-breakdown-voltage device, this particular importance that becomes (for example aspect power amplifier or reading magnetic head).
Consider rate of finished products now, Fig. 6 shows the standard finished products rate curve for different SiGe thickness SiGeHBT of the present invention.The upper limit (see figure 2) of the approximate SiGe stability curve in first district that illustrates (thickness of 300 dusts, 10% Ge concentration).On the SiGe stability curve in the time of should noting being increased to 10% Ge concentration along with thickness, rate of finished products does not significantly change.This shows that the misfit dislocation in the SiGe layer of the present invention has no significant effect the crystal of substrate, and this is that because if so rate of finished products will increase with SiGe thickness and descend.
Fig. 7 shows the curve for the thick SiGe layer depth of three embodiment Ge percentage of the present invention and 70nm.In first embodiment, shown in curve A, the Ge concentration in the SiGe layer of the present invention is similar to 10% in the whole thickness of the thick SiGe film of 40nm.This embodiment has produced the collector emitter voltage curve of the present invention shown in the solid line of collector current and Fig. 3.In a second embodiment, shown in curve B, the Ge concentration in the SiGe layer of the present invention is similar to 10% in the whole thickness of the thick SiGe film of 70nm.First and second embodiment have produced yield data shown in Figure 6.In the 3rd embodiment, shown in curve C, Ge concentration in the SiGe layer of the present invention is at the upper surface of SiGe layer and 1/3rd (for the thick about 23nm of SiGe film of 70nm) about 25% of its thickness, then at 2/3rds places of the thickness of SiGe film, the percentage of Ge drops to 10% with significant linear mode by 25%, for all the other thickness of SiGe film, concentration is 10% then.Be reduced to 10% by the content with the lower surface place, the result of misfit dislocation, rate of finished products and performance is observed identical with preceding two embodiment of the present invention.
In the fourth embodiment of the present invention (not shown among Fig. 7), 150nm is thick for the SiGe layer, and has approximate 10% Ge concentration in its whole thickness.Even the inventor finds this thickness and Ge concentration, misfit dislocation has the overall characteristic of report here.According to these results, the inventor believes the SiGe layer even may be thicker than 150nm, and the characteristic of report still is provided.
Here results reported shows the fundamental cause that does not exist SiGe concentration and thickness need be subjected to dislocation generation effects limit.
Thus, obviously the character restriction that only has to the Ge percentage is to have introduced very little or too many stress in below the Si layer, the inventor believes that being lower than about 5% concentration falls the stress that can not provide enough and improve with the charge mobility of introducing a great deal of, about concentration more than 35% can provide the stress forbidden in the thickness range (about 70nm and more than), obviously owing on the upper surface of SiGe layer, formed hillock, optimized early voltage or reduced rate of finished products.
The inventor finds that the misfit dislocation in the SiGe layer of the present invention is positioned at STI edge 12A shown in Figure 3, in most of zone of 12B.Dislocation is tending towards extending along the SiGe/Si interfacial water level land shown in the dotted line 10A.Obviously do not observe basically and extend in collector JA or the JB, at this moment, we do not observe and extend in the emitter region.And as previously mentioned, desirable Gummel curve shows that the gained dislocation do not set up suitable charge-trapping position.
Thus, opposite with the instruction in this area, the SiGe layer that the inventor finds to have misfit dislocation can improve performance and not reduce rate of finished products simultaneously.Opposite with the instruction in this area, the inventor find they self or inner a large amount of misfit dislocations do not determine performance or rate of finished products.On the contrary, key is that dislocation does not produce significant charge-trapping, and does not pass collector in a large number.
Though above the present invention with reference to the certain embodiments introduction the invention is not restricted to this.Can make amendment to the embodiment that introduces and not break away from the spirit and scope of requirement of the present invention simultaneously.For example, though instructed specific Ge concentration, concentration gradient and/or thickness,, also can use other concentration, gradient and/or thickness as long as the identical total result of report here can be provided.
Industrial applicibility
The present invention can be applicable to circuit and device, particularly is used in circuit and device in the communication system.
Claims (23)
1. a SiGe (SiGe) heterojunction bipolar transistor (HBT) comprise the thickness (t) that has and the Ge concentration SiGe layer (14) greater than the SiGe limit of stability, and a plurality of misfit dislocations in it does not produce significant charge-trapping position.
2. according to the HBT of claim 1, wherein said SiGe layer (14) has collector, and wherein said a plurality of misfit dislocation does not significantly extend on the collector.
3. according to the HBT of claim 1, have a plurality of isolation structures (12) go up thickness (t) be at least about 70nm and Ge concentration be at least 10% SiGe layer (14), on the isolation structure (12) collector and a plurality ofly not have a remarkable misfit dislocation of on collector, extending.
4. according to the HBT of claim 3, wherein said a plurality of misfit dislocations do not produce significant charge-trapping position.
5. according to the HBT of claim 1, wherein said HBT has the cut-off frequency at least about 19GHz, a plurality of isolated areas (12) of docking with described collector area, and be formed on base on the described collector area, described a plurality of misfit dislocations in the wherein said SiGe layer are adjacent with described a plurality of isolated area (12) and extend in the described collector area, and the while does not extend in the described base basically.
6. according to the transistor of claim 5, wherein said SiGe layer (14) has and is at least 10% Ge concentration.
7. according to the transistor of claim 6, wherein said SiGe layer (14) has the thickness (t) that is at least about 70nm.
8. according to the transistor of claim 6, wherein said SiGe layer (14) has the thickness (t) that is at least about 150nm.
9. according to the transistor of claim 6, wherein said SiGe layer (14) has the Ge concentration that changes in described SiGe layer (14).
10. according to the transistor of claim 9, the Ge concentration of wherein said SiGe layer (14) is higher and lower in its value at lower surface place in the value at its upper surface place.
11. transistor according to claim 10, wherein said Ge concentration has first value on the top of described SiGe layer (14), in the bottom of described SiGe film, have second value, and the value in described SiGe layer (14) mid portion is changed into described second value by described first value less than described first value.
12. according to the transistor of claim 11, wherein said high value is about 25%, described low value is about 10%.
13. according to the transistor of claim 11, wherein at 1/3rd places, top of described SiGe layer (14) thickness (t), described Ge concentration is about 25%.
14. according to the transistor of claim 13, wherein at 1/3rd places, centre of described SiGe layer (14) thickness (t), described Ge concentration is reduced to 10% in the overall linear mode by 25%.
15. according to the transistor of claim 14, wherein at 1/3rd places, bottom of described SiGe layer (14) thickness (t), described Ge concentration is about 10%.
16. a manufacturing according to any one bipolar transistor among the claim 1-15 with Ft with have given BV with increase
CEOMethod, may further comprise the steps:
In silicon substrate (10), form a plurality of isolated areas (12);
Go up formation SiGe layer (14) at described substrate (10) and described isolated area (12), thickness (t) that described SiGe layer (14) has and Ge concentration are greater than the SiGe limit of stability; And
Mix described SiGe layer (14) and substrate (10) to form collector area with first dopant, and wherein said collector area comprises a plurality of misfit dislocations, does not extend to basically in the other parts that described collector area enters bipolar transistor outward.
17. according to the method for claim 16, wherein said SiGe layer (14) has the Ge concentration between 5% and 35%.
18. according to the method for claim 16, wherein said SiGe layer (14) has and is at least about 10% Ge concentration.
19. according to the method for claim 16, wherein said SiGe layer (14) has the thickness (t) that is at least about 70nm.
20. according to the method for claim 19, wherein said SiGe layer (14) has the thickness (t) that is at least about 150nm.
21. according to the method for claim 17, wherein said SiGe layer (14) has the Ge concentration that changes in described SiGe layer (14).
22. according to the method for claim 21, the Ge concentration of wherein said SiGe layer (14) is higher and lower in its value at lower surface place in the value at its upper surface place.
23. method according to claim 21, wherein said Ge concentration has first value on the top of described SiGe layer (14), in the bottom of described SiGe film, have second value, and the value in described SiGe layer (14) mid portion is changed into described second value by described first value less than described first value.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2002/013315 WO2003092079A1 (en) | 2002-04-26 | 2002-04-26 | Enhanced cutoff frequency silicon germanium transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1625811A true CN1625811A (en) | 2005-06-08 |
Family
ID=29268423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA028287622A Pending CN1625811A (en) | 2002-04-26 | 2002-04-26 | Enhnced cut-off frequency silicon germanium transistor |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1502308A4 (en) |
| JP (1) | JP4223002B2 (en) |
| KR (1) | KR100754561B1 (en) |
| CN (1) | CN1625811A (en) |
| AU (1) | AU2002305254A1 (en) |
| WO (1) | WO2003092079A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7544577B2 (en) * | 2005-08-26 | 2009-06-09 | International Business Machines Corporation | Mobility enhancement in SiGe heterojunction bipolar transistors |
| JP4829566B2 (en) * | 2005-08-30 | 2011-12-07 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198689A (en) * | 1988-11-30 | 1993-03-30 | Fujitsu Limited | Heterojunction bipolar transistor |
| US5250448A (en) * | 1990-01-31 | 1993-10-05 | Kabushiki Kaisha Toshiba | Method of fabricating a miniaturized heterojunction bipolar transistor |
| US5225371A (en) * | 1992-03-17 | 1993-07-06 | The United States Of America As Represented By The Secretary Of The Navy | Laser formation of graded junction devices |
| US5266504A (en) * | 1992-03-26 | 1993-11-30 | International Business Machines Corporation | Low temperature emitter process for high performance bipolar devices |
| US5461243A (en) * | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
| EP1070341A1 (en) * | 1998-04-10 | 2001-01-24 | Massachusetts Institute Of Technology | Silicon-germanium etch stop layer system |
| JP3658745B2 (en) * | 1998-08-19 | 2005-06-08 | 株式会社ルネサステクノロジ | Bipolar transistor |
| US6492711B1 (en) * | 1999-06-22 | 2002-12-10 | Matsushita Electric Industrial Co., Ltd. | Heterojunction bipolar transistor and method for fabricating the same |
| US6346453B1 (en) * | 2000-01-27 | 2002-02-12 | Sige Microsystems Inc. | Method of producing a SI-GE base heterojunction bipolar device |
| FR2806831B1 (en) * | 2000-03-27 | 2003-09-19 | St Microelectronics Sa | METHOD FOR MANUFACTURING A BIPOLAR SELF-ALIGNED DOUBLE-POLYSILICIUM TYPE BIPOLAR TRANSISTOR AND CORRESPONDING TRANSISTOR |
| JP2002110690A (en) * | 2000-09-29 | 2002-04-12 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| US6552406B1 (en) * | 2000-10-03 | 2003-04-22 | International Business Machines Corporation | SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks |
-
2002
- 2002-04-26 JP JP2004500339A patent/JP4223002B2/en not_active Expired - Fee Related
- 2002-04-26 CN CNA028287622A patent/CN1625811A/en active Pending
- 2002-04-26 KR KR1020047016720A patent/KR100754561B1/en not_active IP Right Cessation
- 2002-04-26 WO PCT/US2002/013315 patent/WO2003092079A1/en active Application Filing
- 2002-04-26 AU AU2002305254A patent/AU2002305254A1/en not_active Abandoned
- 2002-04-26 EP EP02734064A patent/EP1502308A4/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040103974A (en) | 2004-12-09 |
| EP1502308A4 (en) | 2009-03-18 |
| WO2003092079A1 (en) | 2003-11-06 |
| AU2002305254A1 (en) | 2003-11-10 |
| EP1502308A1 (en) | 2005-02-02 |
| KR100754561B1 (en) | 2007-09-05 |
| JP4223002B2 (en) | 2009-02-12 |
| JP2005524233A (en) | 2005-08-11 |
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