CN1427463A - Method for mfg. polycrystal-polycrystalline capacitor by SIGE BICMOS integrated scheme - Google Patents
Method for mfg. polycrystal-polycrystalline capacitor by SIGE BICMOS integrated scheme Download PDFInfo
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- CN1427463A CN1427463A CN 01143340 CN01143340A CN1427463A CN 1427463 A CN1427463 A CN 1427463A CN 01143340 CN01143340 CN 01143340 CN 01143340 A CN01143340 A CN 01143340A CN 1427463 A CN1427463 A CN 1427463A
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Abstract
A process for preparing polycrystal-polycrystal capacitor by BiCMOS technology features that the lower plate electrode of said capacitor is prepared during depositing the grid of CMOS transistor, and the upper SiGe plate electrode is prepared during growing the SiGe base area of heterobipolar transistor.
Description
Technical field
The present invention relates to BiCMOS (that is bipolar complementary metal oxide semiconductor (CMOS)) technology, relate to more precisely and the integrated polysilicon-polysilicon silicon of SiGe heterojunction bipolar transistor that is the manufacture method of polycrystal-polycrystalline capacitor.
Background technology
In field of manufacturing semiconductor devices, CMOS and BiCMOS technology have been widely used for very complicated analog to digital subsystem is integrated on the single chip.In this subsystem, need high-precision capacitor usually.
Several capacitors be can obtain at present, diffusion-polycrystalline capacitor, polycrystal-polycrystalline capacitor and metal-metal capacitor device comprised.In order to satisfy the needs of current this generation integrated device, adopted polycrystal-polycrystalline capacitor more and more to high precision capacitor.
Although its precision is very high, polycrystal-polycrystalline capacitor is owing to be better than spreading-polycrystalline capacitor but be inferior to the electrology characteristic of metal-metal capacitor device than being easier to make and having, thereby is a kind of compromise between high cost and the desirable capacitor specific characteristics.Yet it is more much more difficult than making polycrystal-polycrystalline capacitor to make the metal-metal capacitor device.
And known polycrystal-polycrystalline capacitor has the relation than the linear better V-C of MOS (that is diffusion-polycrystalline) capacitor.The medium of mos capacitance device comes self-heating to be grown in oxide on the heavy doping diffusion region.On the contrary, the medium of polycrystal-polycrystalline capacitor is the chemical vapor deposition of deposit (CVD) oxide normally, and reliability requirement makes the oxide that obtains can realize thicklyer than thermal oxide.Therefore, the capacitance of mos capacitance device is generally higher than polycrystal-polycrystalline capacitor.
Though the method for known various making polycrystal-polycrystalline capacitors, most prior art method are not suitable for coming integrated with the BiCMOS process program.Consider problem with art methods integrated BiCMOS, for a kind of new improvement of adopting the masking steps that uses in existing polysilicon layer and the conventional BiCMOS technology of exploitation the method for manufacturing polycrystal-polycrystalline capacitor, exist demand always.Specifically, form by the grid of MOS transistor if can develop a kind of capacitor base platform, and the manufacture method of the polycrystal-polycrystalline capacitor that forms by the base of heterojunction bipolar transistor of the head slab of capacitor wherein, then be useful especially.
Summary of the invention
An object of the present invention is to provide the method for the polycrystal-polycrystalline capacitor that a kind of uncomplicated also not expensive manufacturing CMOS or BiCMOS integrated circuit use.
Another object of the present invention provides the existing polysilicon of a kind of utilization and masking steps is made polycrystal-polycrystalline capacitor, thereby with low cost polycrystal-polycrystalline capacitor is integrated into method in the BiCMOS device.
A further object of the present invention provides a kind of step of the SiGe based structures that is used for making MOS transistor and bipolar transistor in the common BiCMOS technology and method that structure is made polycrystal-polycrystalline capacitor utilized.
Utilize method of the present invention, these and other purpose and advantage have been reached, wherein, the following polysilicon layer of capacitor is made in the process of deposit CMOS gate electrode, and the last SiGe polysilicon layer of capacitor is made in the base process of growth SiGe heterojunction bipolar transistor.In a broad sense, method of the present invention is made the lower plate electrode of polycrystal-polycrystalline capacitor in the process that is included in the transistorized gate electrode of deposit CMOS; And SiGe plate electrode in the process of SiGe base of growth heterojunction bipolar transistor, making.
Specifically, in first embodiment of the invention, method of the present invention comprises the following step:
(a) on the part isolated area in treating to make the device region of polycrystal-polycrystalline capacitor, make first polysilicon layer;
(b) around described first polysilicon layer, make first nitride spacers;
(c) on described first polysilicon layer and described first nitride spacers, the deposition of nitride layer;
(d) ion with first conduction type is injected in described first polysilicon layer, so that form the bottom electrode of described polycrystal-polycrystalline capacitor;
(e) remove the described nitride layer of part, so that form second nitride spacers and the described bottom electrode of expose portion;
(f) on the described at least expose portion of described bottom electrode, make stack membrane, described stack membrane comprises oxide layer, second polysilicon layer and SiGe layer;
(g) second conductive type ion that will be different from described first conduction type is injected in described SiGe layer and described second polysilicon layer;
(h) described at least SiGe layer and described second polysilicon layer are corroded, so that form the top electrode of described polycrystal-polycrystalline capacitor; And
(i) the autoregistration silication is carried out on the surface of all exposures of described top electrode.
It is to be noted that above-mentioned processing step is used to make the polycrystal-polycrystalline capacitor of big electric capacity.As an alternative, before structure is carried out the autoregistration silication, can on the top electrode that part exposes, make patterned protectiveness nitride layer.
According to second embodiment of the present invention of making high tension apparatus, method of the present invention comprises the following step:
(a) on the part isolated area in treating to make the device region of polycrystal-polycrystalline capacitor, make first polysilicon layer;
(b) around described first polysilicon layer, make first nitride spacers;
(c) on described first polysilicon layer and described first nitride spacers, the deposition of nitride layer;
(d) ion with first conduction type is injected in described first polysilicon layer, so that form the bottom electrode of described polycrystal-polycrystalline capacitor;
(e) make stack membrane on described at least nitride layer, described stack membrane comprises oxide skin(coating), second polysilicon layer and SiGe layer;
(f) second conductive type ion that will be different from described first conduction type is injected in described SiGe layer and described second polysilicon layer;
(g) described at least SiGe layer and described second polysilicon layer are corroded, so that form the top electrode of described polycrystal-polycrystalline capacitor; And
(h) the autoregistration silication is carried out on the surface of all exposures of described top electrode.
As the situation of first embodiment, before the autoregistration silication, can on the top electrode that exposes to small part, make patterned protectiveness nitride layer.
Be stressed that herein first polysilicon layer of doping is as the bottom electrode of polycrystal-polycrystalline capacitor of the present invention, and the SiGe layer that mixes is with second polysilicon layer of the doping top electrode as polycrystal-polycrystalline capacitor.
Description of drawings
Fig. 1-the 9th, the profile of polycrystal-polycrystalline capacitor in used each processing step of first embodiment of the invention.
Figure 10-11 shows optional processing step, and wherein patterned protectiveness nitride layer is used in first embodiment of the present invention.
Figure 12-the 19th, the profile of polycrystal-polycrystalline capacitor in used each processing step of second embodiment of the invention.
Figure 20-21 shows optional processing step, and wherein patterned protectiveness nitride layer is used in second embodiment of the present invention.
Embodiment
Describe the present invention in more detail below with reference to the accompanying drawing that is attached in the application's book, the invention provides a kind of manufacture method with the integrated polycrystal-polycrystalline capacitor of SiGe BiCMOS technology.Should be noted that, identical and corresponding element with identical and accordingly reference number represent.And, in accompanying drawing of the present invention, only show the capacitor devices district of BiCMOS device.Not shown CMOS and bipolar device region are fabricated in the zone in the district of capacitor devices shown in the neighborhood graph.
At first, show making by big electric capacity polycrystal-polycrystalline capacitor in each used processing step of first embodiment of the invention with reference to Fig. 1-9.Specifically, Fig. 1 shows and makes first polysilicon layer 14 on the part isolated area 12 in being made in Semiconductor substrate 10.Semiconductor substrate 10 is by forming including, but not limited to the conventional semi-conducting material of Si, Ge, SiGe, GaAs, InAs, InP and all other III/V compound semiconductors.Also considered the laminate substrate such as Si/Si or Si/SiGe herein.In these semi-conducting materials, Semiconductor substrate preferably is made up of Si.Semiconductor substrate can be p type substrate or n type substrate, depends on the type for the treatment of to appear at the MOS device in the final BiCMOS structure.
Isolated area can be LOCOS (local oxidation of silicon) district or trench isolation regions, trench isolation regions preferably shown in Figure 1.When adopting LOCOS to isolate, conventional oxidation technology known to one skilled in the art is used to form zone 12.On the other hand, when isolated area 12 is trench isolation regions shown in Figure 1, then utilize conventional photoetching, burn into and raceway groove fill method to form the isolation channel district.Because the making of isolation channel comprises common process known to one skilled in the art, so locate not provide its detailed description.
To become first polysilicon layer 14 of polycrystal-polycrystalline capacitor bottom electrode after a while, also be fabricated in the cmos device district, and will be used in the cmos device district gate electrode as cmos device.In the present invention, use, make first polysilicon layer 14 including, but not limited to chemical vapor deposition (CVD), plasma assisted CVD, sputter, chemical solution deposit and other similar conventional depositing technics such as depositing technics.The thickness of first polysilicon layer can change, but the thickness of first polysilicon layer is typically about 500-5000 , preferably is about 1000-2000 .
Then, as shown in Figure 2, around first polysilicon layer, make first nitride spacers 16.Specifically, first nitride spacers 16 is fabricated on the vertical boundary that first polysilicon layer of previous making is exposed.Use the conventional depositing technics such as CVD, the plasma assisted CVD depositing technics similar, make by Si with other
3N
4And so on first nitride spacers formed of conventional nitride material, thereupon with photoetching and corrosion.The etching process that is used for making first nitride spacers 16 is than removing polysilicon high optionally conventional etching process to be arranged for removing nitride.
Fig. 3 shows polycrystal-polycrystalline capacitor structure after making second nitride layer 18 on structure shown in Figure 2.Specifically, utilization is same as or is different from the conventional depositing technics that is used for making first nitride spacers, and second nitride layer is fabricated on first polysilicon layer 14 and first nitride spacers 16.And second nitride layer can be made up of the material that contains nitride that is same as or be different from first nitride spacers.It is to be noted that second nitride layer is used for protecting adjacent device region in the process of making polycrystal-polycrystalline capacitor.
In place along with second nitride layer, the ion 20 of first conduction type (P type or N type) is injected in first polysilicon layer, so that form the bottom electrode 22 of polycrystal-polycrystalline capacitor, sees Fig. 4.The ion that is used for forming the bottom electrode of polycrystal-polycrystalline capacitor injects, and is to carry out in the conventional ion injection device that can work under conventional injectant energy.The concentration of the foreign ion that uses in this implantation step can change, and its numerical value is in the normally used scope of one skilled in the art.And the type of the foreign ion that adopts in this step of the present invention only depends on the type of device to be made.
According to the first embodiment of the invention that is used for making big electric capacity polycrystal-polycrystalline capacitor, utilize conventional photoetching that second nitride layer is carried out graphically, and adopt subsequently for removing nitride and than removing the polysilicon that mixes, high optionally etching process is arranged, so that form second nitride spacers 24, see Fig. 5.Specifically, second nitride layer 18 is corroded, so that form the window 21 of bottom electrode below the expose portion in second nitride layer.
Then, as shown in Figure 6, on structure shown in Figure 5, make stack membrane 30.According to the present invention, stack membrane 30 is made up of oxide skin(coating) 32, second polysilicon layer 34 and SiGe layer 36.In the present invention, oxide skin(coating) 32 is to make of the conventional depositing technics of CVD and so on, or as an alternative, can make oxide skin(coating) 32 with the hot growth technique of routine.The thickness of oxide skin(coating) can change, but the thickness of the oxide skin(coating) 32 of stack membrane 30 is about 50-200 usually.
With being same as or being different from the depositing technics that is used for making first polysilicon layer 14, make the polysilicon layer 34 of stack membrane 30.The thickness of polysilicon layer 34 can change, but the thickness of second polysilicon layer 34 of stack membrane 30 is about 100-1000 usually.
Use including, but not limited to the conventional depositing technics of high vacuum chemical vapour deposition (UHVCVD), molecular beam epitaxy (MBE), rapid heat chemical vapour deposition (RTCVD) and plasma reinforced chemical vapor deposition (PECVD), make the SiGe layer 36 of the stack membrane 30 of the SiGe base that also is used to form bipolar transistor area under control (not shown).It is to be noted that the thickness of SiGe can change, thereby be not limited to concrete thickness range.Above-mentioned each depositing technics that is used for making the SiGe layer comprises and adopts normal condition known to one skilled in the art.These conditions can change according to the type of the depositing technics that is used for making the SiGe layer.
After on the bottom electrode that exposes, having made stack membrane 30, the SiGe layer 36 and second polysilicon layer 34 are carried out the ion injection, wherein be different from second conductive type ion 38 of first conduction type, be injected in the layer 36 and 34.Specifically, in the conventional ion injection device that can under conventional injectant energy, work, carry out the above-mentioned second ion implantation step.The concentration of the impurity that uses in the doping step of this implantation step that is layer 36 and 34 can change, and depends on the type that is injected into the impurity in first polysilicon layer.Fig. 7 shows and forms this step of the present invention that is doped layer 40.It is to be noted that being doped layer 40 is combinations of the SiGe layer 36 and second polysilicon layer 34.And, be doped the top electrode of layer 40 as polycrystal-polycrystalline capacitor of the present invention.
After SiGe layer and second polysilicon layer being mixed, the layer 40 that is doped (that is the SiGe layers that are doped and second polysilicon layer of being doped) carried out the conventional photoetching and the corrosion process that the SiGe layer that is doped and second polysilicon layer can be patterned into the top electrode 40 that forms structure shown in Figure 8 with second conductive type ion.Should be noted that in the process of the SiGe layer that corrosion is doped and second polysilicon layer, some oxide layer of below also may be corroded.
After this step of the present invention, can be alternatively top electrode that is the layer 40 that is doped be carried out another ion injecting process, wherein Fu Jia second ion is injected in the top electrode.It is to be noted that this optionally additional implantation step has formed source region and the drain region (not shown) in the cmos device district.Fig. 9 shows the top electrode exposed surface and has experienced conventional autoregistration silication operation structure afterwards, has wherein formed self-aligned silicide district 42.This autoregistration silication operation is to utilize conventional annealing temperature and time known to one skilled in the art to carry out.
Figure 10-11 shows the additional processing step that can be used in the present invention's first method before carrying out autoregistration silication operation.Specifically, Figure 10 shows the structure of Fig. 9, and it comprises the graphical protectiveness nitride layer 44 that is produced on the polycrystal-polycrystalline capacitor horizontal surface.Utilize conventional depositing technics,, make this graphical protective layer thereupon with photoetching and corrosion.Figure 11 shows and carries out above-mentioned autoregistration silication operation structure afterwards.
Figure 12-19 shows second embodiment of the present invention, and wherein second nitride layer 18 is retained in the structure in all each processing steps.This has just obtained high voltage polycrystal-polycrystalline capacitor device.Specifically, be used for identical shown in the processing step of structure shown in the construction drawing 12-15 and above-mentioned Fig. 1-4.Replace as shown in Figure 5 nitride layer being corroded, in this embodiment of the present invention, nitride layer is not corroded, and makes stack membrane 30 thereon with above-mentioned processing step, so that structure shown in Figure 16 is provided.Figure 17-19 is except polycrystal-polycrystalline capacitor comprises second nitride layer 18, and is identical with Fig. 7-9.
Figure 20-21 shows an optional step of second embodiment of the invention, has wherein used graphical protectiveness nitride layer.
Though according to the preferred embodiments of the invention the present invention has been carried out concrete description, the one skilled in the art is understandable that, can make the above-mentioned of form and details aspect and other change and do not surmount design of the present invention and scope.Therefore think that the present invention is not limited to described accurate form and details, and be included in the scope of claims.
Claims (18)
1. make the method for integrated polycrystal-polycrystalline capacitor with BiCMOS technology for one kind, it is included in the lower plate electrode of making polycrystal-polycrystalline capacitor in the process of the transistorized gate electrode of deposit CMOS; And SiGe plate electrode in the process of SiGe base of growth heterojunction bipolar transistor, making.
2. the process of claim 1 wherein and make described lower plate electrode: on the part isolated area in treating to make the device region of polycrystal-polycrystalline capacitor, make first polysilicon layer with the following step; Around described first polysilicon layer, make first nitride spacers; On described first polysilicon layer and described first nitride spacers, the deposition of nitride layer; And the ion of first conduction type is injected in described first polysilicon layer, so that form the described lower plate electrode of described polycrystal-polycrystalline capacitor.
3. the method for claim 2 is wherein made the described SiGe plate electrode of going up with the following step: remove the described nitride layer of part, so that form second nitride spacers and the described lower plate electrode of expose portion; On the described at least expose portion of described lower plate electrode, make stack membrane, described stack membrane comprises oxide skin(coating), second polysilicon layer and SiGe layer; Second conductive type ion that will be different from described first conduction type is injected in described SiGe layer and described second polysilicon layer; At least described SiGe layer and described second polysilicon layer are corroded, so that form the described upper flat plate electrode of described polycrystal-polycrystalline capacitor; And described all exposed surfaces of going up the SiGe plate electrode are carried out the autoregistration silication.
4. the method for claim 3 wherein before the autoregistration silication, is made graphical protectiveness nitride layer on the SiGe plate electrode on part is described.
5. the method for claim 2, wherein make the described SiGe plate electrode of going up with the following step: on described at least nitride layer, make stack membrane, described stack membrane comprises oxide skin(coating), second polysilicon layer and SiGe layer; Second conductive type ion that will be different from described first conduction type is injected in described SiGe layer and described second polysilicon layer; At least described SiGe layer and described second polysilicon layer are corroded, so that form the described SiGe plate electrode of going up of described polycrystal-polycrystalline capacitor; And described all exposed surfaces of going up the SiGe plate electrode are carried out the autoregistration silication.
6. the method for claim 5 wherein before the autoregistration silication, is made graphical protectiveness nitride layer on the SiGe plate electrode on part is described.
7. make the method for integrated polycrystal-polycrystalline capacitor with BiCMOS technology for one kind, it comprises the following step:
(a) on the part isolated area in treating to make the device region of polycrystal-polycrystalline capacitor, make first polysilicon layer;
(b) around described first polysilicon layer, make first nitride spacers;
(c) on described first polysilicon layer and described first nitride spacers, the deposition of nitride layer;
(d) ion with first conduction type is injected in described first polysilicon layer, so that form the bottom electrode of described polycrystal-polycrystalline capacitor;
(e) remove the described nitride layer of part, so that form second nitride spacers and the described bottom electrode of expose portion;
(f) on the described at least expose portion of described bottom electrode, make stack membrane, described stack membrane comprises oxide layer, second polysilicon layer and SiGe layer;
(g) second conductive type ion that will be different from described first conduction type is injected in described SiGe layer and described second polysilicon layer;
(h) described at least SiGe layer and described second polysilicon layer are corroded, so that form the top electrode of described polycrystal-polycrystalline capacitor; And
(i) the autoregistration silication is carried out on the surface of all exposures of described top electrode.
8. the method for claim 7 wherein before the autoregistration silication, is made graphical protectiveness nitride layer on the top electrode that part exposes.
9. the method for claim 7 is wherein made described first polysilicon layer with the depositing technics that is selected from chemical vapor deposition (CVD), plasma assisted CVD, sputter and the chemical solution deposit.
10. the method for claim 7 is wherein made described first nitride spacers with deposit and caustic solution.
11. the method for claim 7 is wherein made described nitride layer with the depositing technics that is selected from CVD, plasma assisted CVD, sputter and the chemical solution deposit.
12. the process of claim 1 wherein and use the depositing technics that is selected from high vacuum chemical vapour deposition (UHVCVD), molecular beam epitaxy (MBE), rapid heat chemical vapour deposition (RTCVD) and the plasma reinforced chemical vapor deposition (PECVD) that the described SiGe layer that provides in the making step (f) is provided.
13. make the method for integrated polycrystal-polycrystalline capacitor with BiCMOS technology for one kind, it comprises the following step:
(a) on the part isolated area in treating to make the device region of polycrystal-polycrystalline capacitor, make first polysilicon layer;
(b) around described first polysilicon layer, make first nitride spacers;
(c) on described first polysilicon layer and described first nitride spacers, the deposition of nitride layer;
(d) ion with first conduction type is injected in described first polysilicon layer, so that form the bottom electrode of described polycrystal-polycrystalline capacitor;
(e) make stack membrane on described at least nitride layer, described stack membrane comprises oxide skin(coating), second polysilicon layer and SiGe layer;
(f) second conductive type ion that will be different from described first conduction type is injected in described SiGe layer and described second polysilicon layer;
(g) described at least SiGe layer and described second polysilicon layer are corroded, so that form the top electrode of described polycrystal-polycrystalline capacitor; And
(h) the autoregistration silication is carried out on the surface of all exposures of described top electrode.
14. the method for claim 13 wherein before the autoregistration silication, is made graphical protectiveness nitride layer on the top electrode that part exposes.
15. the method for claim 13 is wherein made described first polysilicon layer with the depositing technics that is selected from chemical vapor deposition (CVD), plasma assisted CVD, sputter and the chemical solution deposit.
16. the method for claim 13 is wherein made described first nitride spacers with deposit and caustic solution.
17. the method for claim 13 is wherein made described nitride layer with the depositing technics that is selected from CVD, plasma assisted CVD, sputter and the chemical solution deposit.
18. the method for claim 13 wherein uses the depositing technics that is selected from high vacuum chemical vapour deposition (UHVCVD), molecular beam epitaxy (MBE), rapid heat chemical vapour deposition (RTCVD) and the plasma reinforced chemical vapor deposition (PECVD) that the described SiGe layer that provides in the making step (e) is provided.
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| CN 01143340 CN1204616C (en) | 2001-12-20 | 2001-12-20 | Method for mfg. polycrystal-polycrystalline capacitor by SIGE BICMOS integrated scheme |
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| CN 01143340 CN1204616C (en) | 2001-12-20 | 2001-12-20 | Method for mfg. polycrystal-polycrystalline capacitor by SIGE BICMOS integrated scheme |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7781296B2 (en) | 2004-06-18 | 2010-08-24 | Stmicroelectronics Sas | Integrated circuit comprising a capacitor with metal electrodes and process for fabricating such a capacitor |
| CN101589460B (en) * | 2005-08-26 | 2011-07-20 | 国际商业机器公司 | Mobility enhancement in sige heterojunction bipolar transistors |
| CN103094361A (en) * | 2011-11-03 | 2013-05-08 | 上海华虹Nec电子有限公司 | PIS capacitor in a silicon germanium heterojunction bipolar transistor (HBT) process and manufacturing method thereof |
| CN115132662A (en) * | 2022-07-06 | 2022-09-30 | 重庆中科渝芯电子有限公司 | Optimization integration method for simulating high-stress edge effect in BiCMOS (bipolar complementary metal oxide semiconductor) process and high-linearity double-polycrystal capacitor |
-
2001
- 2001-12-20 CN CN 01143340 patent/CN1204616C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7781296B2 (en) | 2004-06-18 | 2010-08-24 | Stmicroelectronics Sas | Integrated circuit comprising a capacitor with metal electrodes and process for fabricating such a capacitor |
| US8975682B2 (en) | 2004-06-18 | 2015-03-10 | Stmicroelectronics (Crolles 2) Sas | Integrated circuit comprising a capacitor with HSG metal electrodes |
| CN101589460B (en) * | 2005-08-26 | 2011-07-20 | 国际商业机器公司 | Mobility enhancement in sige heterojunction bipolar transistors |
| CN103094361A (en) * | 2011-11-03 | 2013-05-08 | 上海华虹Nec电子有限公司 | PIS capacitor in a silicon germanium heterojunction bipolar transistor (HBT) process and manufacturing method thereof |
| CN103094361B (en) * | 2011-11-03 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | PIS capacitor in a kind of SiGe HBT technique and manufacture method thereof |
| CN115132662A (en) * | 2022-07-06 | 2022-09-30 | 重庆中科渝芯电子有限公司 | Optimization integration method for simulating high-stress edge effect in BiCMOS (bipolar complementary metal oxide semiconductor) process and high-linearity double-polycrystal capacitor |
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| CN1204616C (en) | 2005-06-01 |
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