CN1618122A - An oxide layer on a GAAS-based semiconductor structure and method of forming same - Google Patents

An oxide layer on a GAAS-based semiconductor structure and method of forming same Download PDF

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CN1618122A
CN1618122A CNA028276825A CN02827682A CN1618122A CN 1618122 A CN1618122 A CN 1618122A CN A028276825 A CNA028276825 A CN A028276825A CN 02827682 A CN02827682 A CN 02827682A CN 1618122 A CN1618122 A CN 1618122A
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layer
semiconductor structure
oxide
gaas
gaas base
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CN1333445C (en
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马提亚斯·帕斯莱克
小尼古拉斯·威廉·梅登多普
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

A compound semiconductor structure comprises a first layer (8) of gallium oxide located on a supporting semiconductor structure (7) to form an interface therewith. A second layer (9) of a Ga-Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor (430), a heterojunction bipolar transistor (310), or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga-Gd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the Ga-Gd-oxide provides a low oxide leakage current density.

Description

Oxide layer on the GAAS based semiconductor structure and forming method thereof
Technical field
The present invention relates generally to be included in the goods of the dielectric oxide layer that forms on the GaAs based semiconductor structure.
Background technology
In semiconductor technology, often need on various supporting constructions, form dielectric layer or film, as the gate insulator in the field-effect transistor, cover the insulating barrier or the passivation layer in the various zones (for example extrinsic base region) of the transistor of other type such as HBT etc., around vertical cavity surface emitting laser or the table top of edge emitter laser or the insulating barrier or the passivation layer of wall, or the like.Use howsoever, all requiring dielectric layer or film usually is the good insulator of fabricating low-defect-density, so that device performance can be worked and strengthen/kept to device.Equally, the thickness of this layer must be enough to the semiconductor device characteristic that provides required, for example leakage current, reliability or the like.
Because lack the insulating barrier with the low interface density of states and stable device work on GaAs (GaAs) base semiconductor, performance, integrated level and the merchantability of numeral and simulation GaAs base device and circuit are very restricted.As known in the art, the oxide-film by oxidation GaAs sill growth causes high interface state density and at the pinned Fermi level in GaAs oxide interface place.
For example, at people's such as M.Passlack Journal of Vacuum Science﹠amp; Technology, vol.17,49 (1999) and United States Patent (USP) 6,030,453 and 6,094,295 in formation Ga is disclosed 2O 3The method of film.As being discussed in these lists of references, employing in-situ deposition gallium oxide molecule on GaAs base epitaxial loayer keeps ultra high vacuum (UHV) simultaneously, makes high-quality Ga 2O 3/ GaAs interface.The Ga of Zhi Zaoing like this 2O 3/ GaAs interface has 5,000-30, the interface recombination rate S of 000cm/s and be low to moderate 3.5 * 10 10Cm -2EV -1Interface state density D ItYet because high oxidation object bulk trap densities and too big leakage current, adopting the performance of the gallium oxide of this technology manufacturing is not enough for many application.As a result, the performance of one pole and bipolar device is affected, and makes mos field effect transistor (MOSFET) stable and reliable, based compound semiconductor and exists problem.
As at United States Patent (USP) 6,159, discuss in 834 like that, determined that aforesaid technology can not make high-quality Ga 2O 3Layer is because the oxygen room in this layer produces the defective that causes unacceptable oxide bulk trap densities.The molecular beam of patent ' 834 by introducing gallium oxide on the surface of chip architecture is to start oxidate and at the Ga that finishes a 1-2 individual layer 2O 3The time the second bundle elemental oxygen and overcome this problem is provided.By from crystal Ga 2O 3Or gallic acid Yanyuan thermal evaporation and the molecular beam of gallium oxide is provided, being excited in the desorb atomic source (neutral electron stimulated desorptionatom source) any by RF or microwave plasma discharge, thermal decomposition or neutral electronics provides the oxygen atom bundle.This manufacturing technology is kept the Ga of excellent quality simultaneously by reducing the oxygen density relevant with oxygen defect 2O 3-GaAs interface and improved Ga 2O 3The quality of layer.Yet oxide bulk trap densities is still too high, and observes very big leakage current.
As Ga 2O 3Replacement, gadolinium gallium oxide (Ga 2O 3(Gd 2O 3)) be used as the dielectric layer on the GaAs base device.Although this oxide layer has acceptable low-leakage current density, Ga 2O 3(Gd 2O 3)-GaAs interface state density is higher, causes unacceptable device performance.
Therefore, need provide the dielectric layer structure on a kind of GaAs base device, this device has the oxide-GaAs interface and the protoxide leakage current density of fabricating low-defect-density simultaneously.
Summary of the invention
In conjunction with others, the invention provides a kind of new, improved manufacturing grid quality Ga 2O 3The method of compound semiconductor structure.The present invention also provides wherein relevant with the oxygen room defect concentration of a kind of manufacturing to use suitable grid quality Ga for MOSFET 2O 3New, the improved method of compound semiconductor structure.
According to an embodiment of the invention, a kind of compound semiconductor structure is provided, this semiconductor structure comprises GaAs base supports semiconductor structure.The ground floor gallium oxide is positioned on the surface of this supports semiconductor structure, thereby forms the interface with it.Second layer Ga-Gd oxide is set on the ground floor.
In a specific implementations of the present invention, this Ga-Gd oxide is Gd 3Ga 5O 12
In yet another embodiment of the present invention, GaAs base supports semiconductor structure is a GaAs base heterojunction structure, as the semiconductor device of finishing to small part.In some embodiments of the present invention, the semiconductor device that part is finished for example can be MOS (metal-oxide-semiconductor) memory, heterojunction bipolar transistor or semiconductor laser.
According to another embodiment of the invention, provide a kind of method that on supports semiconductor structure, forms dielectric layer structure.This method begins to provide and has dielectric layer structure with the GaAs on surface thereon, position base supports semiconductor structure.Deposition ground floor Ga on the surface of this supporting construction 2O 3Deposition second layer Ga-Gd oxide on this ground floor.In such a way, provide the dielectric layer structure that has simultaneously fabricating low-defect-density and protoxide leakage current density at the interface, because this dielectric structure is by the Ga of Ga-Gd oxide skin(coating) and then at oxide-GaAs 2O 3Layer forms.This Ga 2O 3Layer be used to form and GaAs base supports semiconductor structure between high quality interface, the Ga-Gd oxide provides the protoxide leakage current density simultaneously.
Description of drawings
Fig. 1 is the simplification sectional view that deposits the part semiconductor structure of composite dielectric layer structure on it according to of the present invention;
Ultra high vacuum (UHV) molecular beam epitaxy system that Fig. 2 explanation is used in the structure according to one embodiment of the present invention shop drawings 1;
Fig. 3 is the simplification cross-sectional view in conjunction with HBT of the present invention;
Fig. 4 is the simplification cross-sectional view in conjunction with metal-oxide semiconductor (MOS) FET of the present invention.
Embodiment
The inventor has determined to be formed by the gallium oxide of Ga-Gd oxide layer/GaAs interface and then the dielectric layer structure of high-quality, low defective surprisingly.On the contrary, the dielectric layer of prior art or form by gallium oxide/GaAs interface or by Ga-Gd oxide/GaAs interface.
Specifically with reference to Fig. 1, the simplification sectional view that deposits the part semiconductor structure of dielectric layer structure according to the present invention on it is described.The part semiconductor structure comprises GaAs base supports semiconductor structure 7, for simplification with the individual layer explanation.Basically, structure 7 comprises any Semiconductor substrate, epitaxial loayer, heterostructure or its combination, has the surface by the dielectric layer structure coating.Usually, this substrate is GaAs or GaAs sill (III-V material), and epitaxial loayer is to take over what known technology epitaxially grown GaAs sill on substrate.
Composite dielectric structure 5 comprises the lip-deep ground floor 8 that is formed on supports semiconductor structure 7 and the second layer 9 that is formed on the layer 8.Such just as will be explained, layer 8 is by deposition one deck Ga on the surface of supports semiconductor structure 7 2O 3And form.Layer 8 provides the low interface density of states on the GaAs base supports semiconductor structure 7.Second layer material (layer 9) is deposited on the layer 8 then, thereby forms composite dielectric structure 5, and this layer has the Ga of ratio 2O 3Low body bulk trap densities.
Can be in process for making any time easily of composite dielectric structure 5 forms, for example in structure 7 after the epitaxial growth of included arbitrary or all layers in the growth room original position form.Ga 2O 3Layer 8 can adopt the obtainable any technology of those of ordinary skill in the art to form.For example, Ga 2O 3Layer 8 can be by for example at United States Patent (USP) 6,030, the thermal evaporation crystal Ga under the UHV condition that discusses in 453,6,094,295 and 6,159,834 2O 3Or gallate forms.Perhaps, Ga 2O 3Layer 8 can form by other suitable technique known in the art, as the high-purity single crystal source by specific selection material is provided and adopt this source of a kind of evaporation in thermal evaporation, electron beam evaporation and the laser ablation.As above-mentioned, only comprise Ga when on the GaAs sill, forming 2O 3Dielectric layer the time, oxide bulk trap densities is high to unacceptable.In order to overcome this problem, Ga in the present invention 2O 3Layer 8 just thickness is enough to cover the GaAs surface basically, and prevents to be diffused into GaAs-Ga from the Gd of the layer 9 that forms subsequently 2O 3The interface.Usually, the minimum thickness of layer 8 need be decided by the thermodynamic stability of total.Layer 8 the maximum ga(u)ge that is allowed decided by body trap distribution and density and semiconductor device performance requirements.For example, in some embodiments of the present invention, the Ga of formation 2O 3Layer 8 thickness usually at 0.5nm in the scope of 10nm, and more preferably in the scope of 2-5nm.
As above-mentioned, in case Ga 2O 3Layer 8 has formed, at Ga 2O 3Sedimentary deposit 9 is to finish composite dielectric structure 5 on the layer 8.Layer 9 compares Ga by the body bulk trap densities 2O 3Low material forms.Especially, according to the present invention, layer 9 is Ga-Gd oxides, and this oxide is the mixed oxide that comprises Ga, Gd and oxygen.In specific implementations more of the present invention, the Ga-Gd oxide is Gd 3Ga 5O 12Although be not limited to the present invention, believe that at present Gd is the stabilizer element that is used for Ga is stabilized in the 3+ oxidation state.Should be appreciated that in the mixed oxide film Ga basically the requirement of complete oxidation do not represent that all Ga ion 100% ground must be in the 3+ ionic state.For example, if in all Ga ions 80% or more many places just can obtain acceptable result in the 3+ attitude.The minimum thickness of layer 9 is required to decide by performance of semiconductor device.Usually, layer 9 thickness at about 2nm in the scope of 1000nm, and more preferably in the scope of 5-20nm.
The present invention has advantageously realized having at oxide-GaAs interface simultaneously fabricating low-defect-density and because the Ga-Gd oxide is deposited over Ga 2O 3On the layer 8 and have a dielectric layer structure of protoxide leakage current density, this be used to form for the first time and GaAs base supports semiconductor structure between high quality interface.Also promptly, the present invention adopts by the Ga of Ga-Gd oxide skin(coating) and then 2O 3The composite dielectric structure that layer forms.
Ultra high vacuum (UHV) molecular beam epitaxy (MBE) system that Fig. 2 explanation is used in according to the composite dielectric structure in an embodiment of the invention shop drawings 15.System 20 comprises that UHV chamber 21, high temp jet unit 22 and 29, atomic oxygen source 23, cell shutter 24,31 and 28, substrate holder 25 are as platen.Certainly, be to be understood that system 20 can allow to make simultaneously a plurality of wafers and/or comprises and being used in routinely among the MBE but not other standard source, for example jet units such as Ga, As, Al, In, Ge shown in figure 2.
Adopting Ga-Gd oxide such as Gd 3Ga 5O 12In the specific implementations as the composite dielectric structure second layer 9, the GaAs base supports semiconductor structure 7 with upper surface 15 of atomic ordered and chemically cleaning is installed on the substrate holder 25 and is loaded in the UHV chamber 21.Subsequently, semiconductor structure 7 is heated to the temperature of suitable rising according to the known principle of those skilled in the art.Adopt high temp jet unit 22 to make crystal Ga 2O 3Or gallic acid Yanyuan thermal evaporation.By opening cell shutter 24 and the molecular beam of gallium oxide 26 of guiding upper surface 15 being provided, start Ga 2O 3The deposition of molecule on the upper surface 15 of the atomic ordered of semiconductor structure 7 and chemically cleaning, thus initial gallium oxide layer on substrate, formed.
The quality of initial gallium oxide layer can be by improving with gallium oxide deposition and atomic oxygen, to reduce the oxygen room that produces defective.Especially, after opening cell shutter 24, by the baffle plate 28 of opening atomic oxygen source 23, with the upper surface 15 of a branch of elemental oxygen 27 guiding semiconductor structures 7.This baffle plate can be at initial Ga 2O 3Any time in the deposition process opens, and is preferably depositing the Ga of 1-2 individual layer 2O 3Afterwards, because for Ga 2O 3The low interface density of states at-GaAs interface, the surface oxidation of GaAs will be eliminated fully.
Then, continue to deposit Ga simultaneously by deposition Gd 2O 3And formation Ga-Gd oxide layer.As Gd 3Ga 5O 12The Gd source material, preferably, adopt high temp jet unit 29 thermal evaporations by the form of high-purity, monocrystalline.By at Ga 2O 3 Opening cell shutter 31 sometime and start the deposition of Gd after the deposition beginning.Yet the Gd deposition can or begin before semiconductor structure 7 is exposed to atomic oxygen beam subsequently.The performance such as the stoichiometric proportion that person of skill in the art will appreciate that the composite dielectric structure 5 that forms on semiconductor structure 7 can be by regulating Ga 2O 3The flux of jet units 22, Gd jet units 29 and elemental oxygen unit 23 is controlled,
In conjunction with the specific examples of the semiconductor device of preceding art dielectric layer structure as shown in Figure 3-4.Particularly, with reference to Fig. 3, the simplification cross-sectional view of the heterojunction bipolar transistor (HBT) 310 that forms according to the present invention is described.According to the form of this simplification, HBT310 comprises substrate 311, be formed on collector layer 312 (growth or different depositions) on substrate 311 upper surfaces, be formed on the base layer 313 on collector layer 312 upper surfaces and be formed on emitter layer 314 on base layer 313 upper surfaces.On collector layer 312 upper surfaces, form the collector electrode contact or contact 315.On base layer 313 upper surfaces, form the base stage contact or contact 316.On emitter layer 314 upper surfaces, form emitter contact 317.The different layer of all these forms with contacting according to known mode, and can be according to forming for any easily order of the manufacturing technology of certain device or employing.Usually, substrate 311 is GaAs sills, and all material that uses in the layer 312,313 and 314 is the materials similar system, makes them be coupled on crystallography.As well known in the art, this can by in order in the growth room of standard each layer of epitaxial growth realize.
On the exposed portions serve of emitter layer 314 and base layer 313, form composite dielectric layer structure 320, with passivation and enhance device performance and stability.As explained above, can any time easily in the manufacturing step process after UHV condition is gone down the removing natural oxidizing thing form dielectric layer structure 320.Composite dielectric layer structure 320 comprises the ground floor 321 and the second layer 322.Ground floor 321 is Ga 2O 3Thin layer and corresponding among Fig. 1 the layer 8.The second layer 322 be the Ga-Gd oxide skin(coating) and corresponding among Fig. 1 the layer 9.First and second layer 321 and 322 according to aforesaid step formation, typically after forming contact 315 and 316.The thickness of the composite dielectric layer structure 320 that forms is greater than about 50 dusts, and preferably at about 70 dusts in the scope of 250 dusts.
Fig. 4 explanation is simplified cross-sectional view according to the semiconductor field effect transistor FET 430 of the present invention's structure.FET 430 comprises the substrate 431 that has heavily doped source and drain region 432 and 433 respectively, and form therein the two between channel region 434.Substrate 431 is GaAs sills.According to the present invention, on channel region 434, form composite dielectric layer structure 435 (being often referred to gate oxide).Dielectric layer structure 435 comprises Ga 2O 3The ground floor 440 and the Ga-Gd oxide second layer 442.Grid Metal Contact 436 is formed on the dielectric layer structure 435 by common operation, and source and drain contact 437 and 438 are respectively formed on source and drain region 432 and 433.
Should be appreciated that the described semiconductor device of Fig. 3-4 just provides with the example form illustrated, the present invention more generally may be used on the composite dielectric structure that forms, for example semiconductor laser and light-sensitive device on various semiconductor device.
Although this paper specifically describes and has described various execution modes, should be appreciated that modification of the present invention and change also in above-mentioned professor's scope, and within the scope of the claims, and the scope that does not deviate from spirit of the present invention and want to comprise.

Claims (13)

1. compound semiconductor structure comprises:
GaAs base supports semiconductor structure;
The gallium oxide ground floor forms the interface with it thereby be positioned on the surface of supports semiconductor structure; And
The Ga-Gd oxide second layer is arranged on the ground floor.
2. according to the compound semiconductor structure of claim 1, wherein said Ga-Gd oxide is Gd 3Ga 5O 12
3. according to the compound semiconductor structure of claim 1, wherein said GaAs base supports semiconductor structure is a GaAs base heterojunction structure.
4. according to the compound semiconductor structure of claim 3, wherein said GaAs base supports semiconductor structure is the MOS (metal-oxide-semiconductor) memory of finishing to small part.
5. according to the compound semiconductor structure of claim 3, wherein said GaAs base supports semiconductor structure is the heterojunction bipolar transistor of finishing to small part.
6. method that forms dielectric layer structure on supports semiconductor structure may further comprise the steps:
GaAs base supports semiconductor structure is provided;
Deposition gallium oxide ground floor on the surface of supporting construction; And
The deposition Ga-Gd oxide second layer on ground floor.
7. according to the method for claim 6, the step of wherein said deposition gallium oxide layer comprises by the hydatogenesis gallium oxide layer.
8. according to the method for claim 7, wherein the step by evaporation deposition gallium oxide layer on the surface of supports semiconductor structure comprises a kind of in thermal evaporation, electron beam evaporation and the laser ablation.
9. method according to Claim 8 also is included in the step of evaporation atom oxygen during the step of the described deposition gallium oxide layer of small part.
10. according to the method for claim 9, the step of wherein said evaporation atom oxygen is beginning after the gallium oxide at least one individual layer of surface deposition of supports semiconductor structure.
11. according to the method for claim 6, wherein said GaAs base supports semiconductor structure is a GaAs base heterojunction structure.
12. according to the method for claim 11, wherein said GaAs base supports semiconductor structure is the MOS (metal-oxide-semiconductor) memory of finishing to small part.
13. according to the method for claim 11, wherein said GaAs base supports semiconductor structure is the heterojunction bipolar transistor of finishing to small part.
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