KR101345390B1 - Interface layer reduction method, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film - Google Patents

Interface layer reduction method, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film Download PDF

Info

Publication number
KR101345390B1
KR101345390B1 KR1020127015820A KR20127015820A KR101345390B1 KR 101345390 B1 KR101345390 B1 KR 101345390B1 KR 1020127015820 A KR1020127015820 A KR 1020127015820A KR 20127015820 A KR20127015820 A KR 20127015820A KR 101345390 B1 KR101345390 B1 KR 101345390B1
Authority
KR
South Korea
Prior art keywords
metal
oxide film
dielectric constant
film
high dielectric
Prior art date
Application number
KR1020127015820A
Other languages
Korean (ko)
Other versions
KR20120095999A (en
Inventor
나오토 우메자와
토요히로 치쿄
토시히데 나바타메
Original Assignee
도쿠리츠교세이호징 붓시쯔 자이료 겐큐키코
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 도쿠리츠교세이호징 붓시쯔 자이료 겐큐키코 filed Critical 도쿠리츠교세이호징 붓시쯔 자이료 겐큐키코
Publication of KR20120095999A publication Critical patent/KR20120095999A/en
Application granted granted Critical
Publication of KR101345390B1 publication Critical patent/KR101345390B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

고유전율막이 게이트 절연막으로서 기판위에 형성되면, SiOX 등의 계면층이 게이트 절연막과 기판사이에 형성됨에 따라, 게이트 절연막의 실효 유전율이 감소된다. 이에 따라 본 발명은 계면층의 두께를 감소시키는 계면층 감소 방법을 개시한다. 상기 계면층 감소 방법은, (a) 반도체층 위에, 계면층으로서의 상기 반도체의 산화막을 개재하여 제1 금속의 산화물막을 형성하는 단계; 및, (b) 상기 제1 금속 산화물막위에, 상기 제1 금속보다 원자가가 큰 제2 금속의 산화물막을 형성하는 단계;를 구비한다. When the high dielectric constant film is formed on the substrate as the gate insulating film, SiO X As the interfacial layer such as is formed between the gate insulating film and the substrate, the effective dielectric constant of the gate insulating film is reduced. Accordingly, the present invention discloses an interface layer reduction method for reducing the thickness of an interface layer. The method for reducing an interfacial layer comprises the steps of: (a) forming an oxide film of a first metal on the semiconductor layer via an oxide film of the semiconductor as an interfacial layer; And (b) forming an oxide film of a second metal having a greater valency than the first metal on the first metal oxide film.

Description

계면층 삭감 방법, 고유전율 게이트 절연막의 형성 방법, 고유전율 게이트 절연막, 고유전율 게이트 산화막,및 고유전율 게이트 산화막을 구비하는 트랜지스터{INTERFACE LAYER REDUCTION METHOD, METHOD FOR FORMING HIGH DIELECTRIC CONSTANT GATE INSULATING FILM, HIGH DIELECTRIC CONSTANT GATE INSULATING FILM, HIGH DIELECTRIC CONSTANT GATE OXIDE FILM, AND TRANSISTOR HAVING HIGH DIELECTRIC CONSTANT GATE OXIDE FILM}A transistor comprising an interfacial layer reduction method, a method of forming a high dielectric constant gate insulating film, a high dielectric constant gate insulating film, a high dielectric constant gate oxide film, and a high dielectric constant gate oxide film. CONSTANT GATE INSULATING FILM, HIGH DIELECTRIC CONSTANT GATE OXIDE FILM, AND TRANSISTOR HAVING HIGH DIELECTRIC CONSTANT GATE OXIDE FILM}

본 발명은 계면층 삭감 방법, 고유전율 게이트 절연막의 형성 방법, 고유전율 게이트 절연막, 고유전율 게이트 산화막, 및 고유전율 게이트 산화막을 구비하는 트랜지스터에 관한 것으로서, 특히 고체계면의 구조를 제어하는 방법 및 게이트 스택 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor comprising an interfacial layer reduction method, a method of forming a high dielectric constant gate insulating film, a high dielectric constant gate insulating film, a high dielectric constant gate oxide film, and a high dielectric constant gate oxide film. The stack structure is concerned.

집적회로상의 소자가 미세화됨에 따라, 게이트 절연막으로서 종래 사용된 실리콘 산화물을 대신하여, HfO2이나 La2O3등의 고유전율의 산화막이 사용되고 있다. As elements on integrated circuits become finer, high dielectric constant oxide films such as HfO 2 and La 2 O 3 are used in place of silicon oxides conventionally used as gate insulating films.

그러한 고유전율의 산화막을 Si나 Ge등의 기판위에 형성하면, 양자의 계면에 SiOX나 GeOX 등의 계면층이 형성되어 실효적인 유전율이 낮아지는 문제가 있다. 계면층은, 고온에서 막 형성 프로세스를 수행하는 성막(成膜)중에 형성되거나, 또는 저온에서 고유전율막을 퇴적시켜도 그 후의 열처리(anneal) 과정에서 고유전율막을 통해서 공급되는 산소에 의해서도 계면층이 생긴다.When such a high dielectric constant oxide film is formed on a substrate such as Si or Ge, SiO X or GeO X is formed at both interfaces. There is a problem that an effective dielectric constant is lowered because an interfacial layer such as is formed. The interfacial layer is formed during the film formation process at a high temperature, or even when the high dielectric constant film is deposited at a low temperature, the interfacial layer is also formed by oxygen supplied through the high dielectric constant film in the subsequent annealing process. .

이러한 고유전율막으로서는 예를들어 HfO2가 사용된다. HfO2에 Ti를 첨가함으로써 그 유전율을 더욱 높게 하려는 시도가 행해졌지만(예를 들면 비특허문헌 1), 이는 계면층에 의한 전술한 문제를 본질적으로 해결하는 것이 아니다.As such a high dielectric constant film, for example, HfO 2 is used. Attempts have been made to further increase the dielectric constant by adding Ti to HfO 2 (for example, Non Patent Literature 1), but this does not essentially solve the above-described problems caused by the interface layer.

La2O3을 캐핑층으로서 HfO2 위에 적재하는 연구도 과거에 행해졌다(예를 들면 비특허문헌 2). 그러나 이러한 종래 기술은 전극의 실효적인 일 함수를 변화시켜서 임계값 전압을 제어하는 것으로, 계면층에 의한 상기한 문제를 해결하기 위한 것은 아니다. The La 2 O 3 was done in the past, it studies cache placed on the HfO 2 as a layer (for example, Non-Patent Document 2). However, this conventional technique controls the threshold voltage by changing the effective work function of the electrode, and is not intended to solve the above problems caused by the interface layer.

게다가, Al2O3을 HfO2 위에 캐핑해서 산소의 침입을 억제하는 시도도 행해졌다 (예를 들면 비특허문헌 3). 이 종래 기술은 산화막의 외부에서 내부로의 산소 확산을 막는 것이기 때문에, 일단 계면층이 형성되면(상술한 것 같이, 계면층은 간단하게 형성된다.), 이러한 캐핑을 하더라도 전술한 문제점들은 해결되지 않는다.In addition, attempts have been made to suppress the invasion of oxygen by capping Al 2 O 3 on HfO 2 (eg, Non-Patent Document 3). Since this prior art prevents oxygen diffusion from the outside to the inside of the oxide film, once the interface layer is formed (as described above, the interface layer is simply formed), the above-mentioned problems are not solved even with such capping. Do not.

게다가, Ti, AlN을 HfO2등의 고유전율 막위에 캐핑함으로써, 고유전율막을 통해 하층의 계면층으로부터 산소를 흡수하는 것도 시도하였다(예를 들면 비특허문헌 4, 5). 그렇지만, 이렇게 계면층으로부터 산소를 뽑으면, 고유전율막으로부터도 산소를 뽑게 되면, 이에 의해 고유전율막내의 산소 구멍이 늘어나버린다. 고유전율막내의 산소 구멍은 디바이스의 신뢰성을 열화시키는 요인이 되므로, 계면층의 문제를 이 방법에 의해 해결하는 것은 바람직하지 못하다.In addition, by capturing Ti and AlN on a high dielectric constant film such as HfO 2 , attempts have also been made to absorb oxygen from the lower interface layer through the high dielectric constant film (eg, Non-Patent Documents 4 and 5). However, when oxygen is extracted from the interfacial layer in this way, oxygen is also extracted from the high dielectric constant film, thereby increasing the oxygen holes in the high dielectric constant film. Since the oxygen holes in the high dielectric constant film cause deterioration of the reliability of the device, it is not preferable to solve the problem of the interface layer by this method.

또 GaAs등의 Ⅲ-V계 화합물반도체의 경우에는 고유전율막과 GaAs등과의 계면에 다수의 계면결함이 형성되는 문제가 있으며, 그러한 계면결함을 제거하기 위해 Si/SiNX, Ge, Ga2O3등의 층을 의도적으로 삽입한다(예를 들면 비특허문헌 6~8). 이 삽입된 층이 산화되는 경우(당초부터 산화물층을 삽입할 경우에는 그러한 층 자체)에도 상술한 바와 같은 문제점이 발생하고, 이 반도체로 제작되는 디바이스의 성능 향상에 방해가 되었다.
In addition, in the case of III-V compound semiconductors such as GaAs, a large number of interfacial defects are formed at the interface between the high-k film and GaAs. In order to remove such interfacial defects, Si / SiN X , Ge, Ga 2 O Layers 3 and the like are intentionally inserted (for example, non-patent documents 6 to 8). When the inserted layer is oxidized (the layer itself when the oxide layer is inserted from the beginning), the same problem as described above occurs, which hinders the performance improvement of the device fabricated from this semiconductor.

1: JOURNAL OF APPLIED PHYSICS 101, 044509(2007), Min Li, Zhihong Zhang, Stephen A. Campbella, Hong-Jyh Li and Jeff J. Peterson, "Hafnium titanate as a high permittivity gate insulator: Electrical and physical characteristics and thermodynamic stability 1: JOURNAL OF APPLIED PHYSICS 101, 044509 (2007), Min Li, Zhihong Zhang, Stephen A. Campbella, Hong-Jyh Li and Jeff J. Peterson, "Hafnium titanate as a high permittivity gate insulator: Electrical and physical characteristics and thermodynamic stability 2: APPLIED PHYSICS LETTERS 89, 232103(2006), H. N. Alshareef, M. Quevedo-Lopez, H. C. Wen, R. Harris, P. Kirsch, P. Majhi, B. H. Lee, R. Jammy, D. J. Lichtenwalner, J. S. Jur, and A. I. Kingon, "Work function engineering using lanthanum oxide interfacial layers 2: APPLIED PHYSICS LETTERS 89, 232103 (2006), HN Alshareef, M. Quevedo-Lopez, HC Wen, R. Harris, P. Kirsch, P. Majhi, BH Lee, R. Jammy, DJ Lichtenwalner, JS Jur, and AI Kingon, "Work function engineering using lanthanum oxide interfacial layers 3: APPLIED PHYSICS LETTERS VOLUME 82, NUMBER 20, 19 MAY 2003, Manisha Kundua, Noriyuki Miyata, Toshihide Nabatame, Tsuyoshi Horikawa, Masakazu Ichikawa and Akira Toriumi, "Effect of Al2O3 capping layer on suppression of interfacial SiO2 growth in HfO2/ultrathin SiO2/Si(001) structure" 3: APPLIED PHYSICS LETTERS VOLUME 82, NUMBER 20, 19 MAY 2003, Manisha Kundua, Noriyuki Miyata, Toshihide Nabatame, Tsuyoshi Horikawa, Masakazu Ichikawa and Akira Toriumi, "Effect of Al2O3 capping layer on suppression of interfacial SiO2 growth in HfO2 / ultrathin SiO2 / Si (001) structure " 4: JOURNAL OF APPLIED PHYSICS 96, 3467(2004), H. Kim, et al., "Engineering Chemically Abrupt High-k Metal Oxide/Silicon Interfaces Using an Oxygen-Gettering Metal Overlayer 4: JOURNAL OF APPLIED PHYSICS 96, 3467 (2004), H. Kim, et al., "Engineering Chemically Abrupt High-k Metal Oxide / Silicon Interfaces Using an Oxygen-Gettering Metal Overlayer 5: APPLIED PHYSICS LETTERS 89, 041906(2006), M. P. 　Austin et al., "Influence of AlN layers on the interface stability of HfO2 gate dielectric stacks" 5: APPLIED PHYSICS LETTERS 89, 041906 (2006), M. P., Austin et al., "Influence of AlN layers on the interface stability of HfO2 gate dielectric stacks" 6: JOURNAL OF VACUUM SCIENCE & TECHNOLOGY, B17(1), Jan/Feb 1999, M. 　Passlack, et al., "Interface charge and nonradiative carrier recombination in Ga2O3-GaAs interface structures"6: JOURNAL OF VACUUM SCIENCE & TECHNOLOGY, B17 (1), Jan / Feb 1999, M. Passlack, et al., "Interface charge and nonradiative carrier recombination in Ga2O3-GaAs interface structures" 7: APPLIED PHYSICS LETTERS 89, 043501(2006), Davood Shahrjerdi, et al., "Unpinned metal gate/high-k GaAs capacitors: Fabrication and characterization" 7: APPLIED PHYSICS LETTERS 89, 043501 (2006), Davood Shahrjerdi, et al., "Unpinned metal gate / high-k GaAs capacitors: Fabrication and characterization" 8: JOURNAL OF VACUUM SCIENCE & TECHNOLOGY, B27(4), Jul/Aug 2009, Masamichi Akazawa, et al., "Capacitance-voltage and photoluminescence study of high-k/ GaAs interfaces controlled by Si interface control layer 8: JOURNAL OF VACUUM SCIENCE & TECHNOLOGY, B27 (4), Jul / Aug 2009, Masamichi Akazawa, et al., "Capacitance-voltage and photoluminescence study of high-k / GaAs interfaces controlled by Si interface control layer 9: O. Kubaschewski, C. B. Alcock, and P. J. Spencer, in Materials Thermochemistry 6th edition(Pergamon Press, April 1993)9: O. Kubaschewski, C. B. Alcock, and P. J. Spencer, in Materials Thermochemistry 6th edition (Pergamon Press, April 1993)

본 발명은 고유전율 막의 특성을 열화시키지 않으면서 그 아래에 형성되어 있는 계면층을 얇게 함으로써 계면층에 의한 전술한 문제점들을 해결하는 것을 그 과제로 한다.
An object of the present invention is to solve the above-mentioned problems caused by the interface layer by thinning the interface layer formed thereunder without deteriorating the characteristics of the high dielectric constant film.

본 발명은 다가 금속산화물을 고유전체 산화막위에 적재함으로써, 전술한 과제를 달성한다.The present invention achieves the above-described problems by loading a polyvalent metal oxide on a high dielectric oxide film.

본발명의 1측면에 따르면 아래의 계면층 삭감 방법이 주어진다. According to one aspect of the present invention, the following interface layer reduction method is given.

다시 말해, (a) 반도체층 위에, 계면층으로서의 상기 반도체의 산화막을 개재하여 제1 금속의 산화물막을 형성하는 단계와, (b) 상기 제1금속 산화물막위에, 상기 제1 금속보다 큰 원자가를 갖는 제2금속의 산화물막을 형성하는 단계;를 구비하여, 상기 계면층의 두께를 삭감하는 계면층 삭감 방법이다.In other words, (a) forming an oxide film of a first metal on the semiconductor layer via an oxide film of the semiconductor as an interface layer, and (b) having a valence greater than that of the first metal on the first metal oxide film. Forming an oxide film of a second metal having the same; and reducing the thickness of the interface layer.

상기 제2 금속 산화물은 화학량론적 조성보다도 산소가 결손되는 것이 바람직하다.It is preferable that oxygen is lacking in the said 2nd metal oxide rather than a stoichiometric composition.

상기 제2 금속 산화물막을 형성하는 단계는, 상기 제1 금속 산화물막 위에 상기 제2 금속 산화물을 증착하는 단계를 구비하는 것이 바람직하다.The forming of the second metal oxide film preferably includes depositing the second metal oxide on the first metal oxide film.

상기 제2 금속 산화물막을 형성하는 단계는, 아래의 단계 (b-1) 및 (b-2)를 구비하는 것이 바람직하다. (b-1) 상기 제1 금속 산화물막 위에 상기 제2 금속막을 형성하는 단계이며, (b-2) 상기 제2 금속막을 산화하는 단계이다.The step of forming the second metal oxide film preferably includes the following steps (b-1) and (b-2). (b-1) forming the second metal film on the first metal oxide film, and (b-2) oxidizing the second metal film.

상기 반도체층의 형성 재료는 실리콘이며, 상기 계면층은 산화 실리콘인 것이 바람직하다.It is preferable that the formation material of the said semiconductor layer is silicon, and the said interface layer is silicon oxide.

상기 제1 금속 산화물은 산화 실리콘보다도 큰 유전율을 갖는 것이 바람직하다.It is preferable that the said 1st metal oxide has a dielectric constant larger than silicon oxide.

상기 반도체층의 형성 재료는 Ⅲ-V계 화합물반도체인 것이 바람직하다.It is preferable that the formation material of the said semiconductor layer is a III-V type compound semiconductor.

상기 제1금속은 하프늄(Hf), 지르코늄(Zr) 및 티탄(Ti) 중에서 선택된 적어도 1종류의 금속이며, 상기 제2금속은 탄탈(Ta), 니오브(Nb) 및 바나듐(V)중에서 선택된 적어도 1종류의 금속인 것이 바람직하다.The first metal is at least one metal selected from hafnium (Hf), zirconium (Zr), and titanium (Ti), and the second metal is at least one selected from tantalum (Ta), niobium (Nb), and vanadium (V). It is preferable that it is one type of metal.

(c) 상기 제1금속산화물막 위에 형성된 상기 제2 금속산화물막의 적어도 일부를 제거하는 단계를 구비하는 것이 바람직하다.(c) preferably removing at least a portion of the second metal oxide film formed on the first metal oxide film.

본 발명의 또 다른 측면에 의하면, 전술한 방법 중 하나의 계면층 삭감 방법을 사용해서 고유전율 게이트 절연막을 형성하는 고유전율 게이트 절연막의 형성 방법이 제공된다. According to still another aspect of the present invention, there is provided a method of forming a high dielectric constant gate insulating film that forms a high dielectric constant gate insulating film by using the interface layer reduction method of one of the above-described methods.

본 발명의 또 다른 측면에 의하면, 전술한 방법 중 하나의 계면층 삭감 방법에 의해 제작된 고유전율 게이트 절연막이 제공된다. According to another aspect of the present invention, there is provided a high dielectric constant gate insulating film produced by the interface layer reduction method of one of the above-described methods.

본 발명의 또 다른 측면에 의하면, 제1금속 산화물과, 상기 제1금속 산화물로 확산되며 상기 제1금속보다도 큰 원자가를 갖는 적어도 1종류의 금속인 제2 금속을 포함하는 고유전율 게이트 산화막이며, 상기 제1 금속 산화물은, 상기 고유전율 게이트 산화막의 아래에 있는 반도체층 또는 상기 반도체층과 상기 고유전율 게이트산화막과의 사이에 설계된 층의 산화물보다도 큰 유전율을 갖는 적어도 1종류의 금속의 산화물로 이루어지는 고유전율 게이트 산화막이 제공된다.According to still another aspect of the present invention, there is provided a high-k gate oxide film including a first metal oxide and a second metal which is diffused into the first metal oxide and is at least one kind of metal having a valence greater than that of the first metal. The first metal oxide is composed of an oxide of at least one metal having a dielectric constant greater than that of the semiconductor layer under the high dielectric constant gate oxide film or a layer designed between the semiconductor layer and the high dielectric constant gate oxide film. A high dielectric constant gate oxide film is provided.

상기 반도체층의 형성 재료는 실리콘이며, 제1 금속 산화물은 산화 실리콘보다도 큰 유전율을 갖는 적어도 1종류의 금속의 산화물인 것이 바람직하다.It is preferable that the formation material of the said semiconductor layer is silicon, and a 1st metal oxide is an oxide of at least 1 type of metal which has a dielectric constant larger than silicon oxide.

상기 제1 금속은 하프늄(Hf), 지르코늄(Zr) 및 티탄(Ti)으로부터 선택된 적어도 1종류의 금속이며, 상기 제2 금속은 탄탈(Ta), 니오브(Nb) 및 바나듐(V)으로부터 선택된 적어도 1종류의 금속인 것이 바람직하다.The first metal is at least one metal selected from hafnium (Hf), zirconium (Zr) and titanium (Ti), and the second metal is at least selected from tantalum (Ta), niobium (Nb) and vanadium (V). It is preferable that it is one type of metal.

상기 제1 금속 산화물은 산화 하프늄이며, 상기 제2 금속은 탄탈인 것이 바람직하다.Preferably, the first metal oxide is hafnium oxide, and the second metal is tantalum.

상기 탄탈의 농도는 1020~1022개/cm3인 것이 바람직하다.The concentration of tantalum is preferably 10 20 to 10 22 pieces / cm 3 .

본 발명의 또 다른 측면에 의하면, 전술한 어느 하나의 고유전율 게이트 산화막을 구비하는 트랜지스터가 제공된다.
According to still another aspect of the present invention, there is provided a transistor having any one of the above-described high-k gate oxide films.

본 발명에 의하면, 상기 과제를 해결할 수 있고 계면층의 두께를 삭감할 수 있으므로, 고유전체 산화막을 게이트 절연막으로서 사용한 디바이스에 있어서, 게이트 절연막의 실효 유전율을 높은 값으로 유지할 수 있다.According to the present invention, the above problems can be solved and the thickness of the interface layer can be reduced, so that in the device using the high dielectric oxide film as the gate insulating film, the effective dielectric constant of the gate insulating film can be maintained at a high value.

도 1은 본 발명의 실시예와 비교예의 층구조를 비교한 TEM사진.
도 2(a)는 본 발명의 실시예 1의 층구조의 구성 원소를 보여주는 SIMS측정 결과의 그림.
도 2(b)는 비교예의 층구조의 구성 원소를 보여주는 SIMS측정 결과의 그림.
도 3은 HfO2위에의 Ta2O5-x적재 효과를 이론적으로 설명하는 그림(1).
도 4는HfO2위에의 Ta2O5-x적재 효과를 이론적으로 설명하는 그림(2).
도 5는 HfO2안의 결함밀도를 페르미(Fermi) 에너지의 함수로서 플롯한 그림.
도 6은 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 7은 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 8은 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 9는 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 10은 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 11은 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 12는 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 13은 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 14는 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.
도 15는 본 발명의 실시예에 의한 CMOS구조의 제작 방법을 설명하는 그림.1 is a TEM photograph comparing the layer structure of the Examples and Comparative Examples of the present invention.
Figure 2 (a) is a diagram of the SIMS measurement results showing the constituent elements of the layer structure of Example 1 of the present invention.
Figure 2 (b) is a diagram of the SIMS measurement results showing the constituent elements of the layer structure of the comparative example.
FIG. 3 is a diagram (1) for explaining theoretically the effect of Ta2O5-x loading on HfO2. FIG.
4 is a diagram (2) illustrating the theoretical effect of Ta2O5-x loading on HfO2.
FIG. 5 is a plot of defect density in HfO 2 as a function of Fermi energy. FIG.
6 is a view for explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.
7 is a view for explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.
8 is a view for explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.
9 is a view for explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.
10 is a view for explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.
Fig. 11 is a diagram explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.
12 is a diagram for explaining a method for manufacturing a CMOS structure according to the embodiment of the present invention.
Fig. 13 is a diagram explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.
Fig. 14 is a diagram explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.
Fig. 15 is a diagram explaining a method of manufacturing a CMOS structure according to the embodiment of the present invention.

이하, 도면에 근거해서 본 발명의 실시예를 상세하게 설명한다. 이하의 실시예에서는 이해하기 쉽게 하기 위해 구체적인 예를 들어 설명을 하지만, 이 예는 단순한 예시이며, 본 발명의 기술적 범위는 특허청구의 범위의 각 청구항을 가장 넓게 해석하는 것으로 이해되어야만 한다.EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described in detail based on drawing. In the following embodiments, specific examples will be described for ease of understanding, but the examples are merely illustrative, and the technical scope of the present invention should be understood as the broadest interpretation of each claim in the claims.

[실시예1] [Example 1]

여기에서는, 본 발명에 의한 계면층 두께의 저감 효과를 도모하는 실시예를 종래 기술에 근거하는 비교예와 대비하면서 설명한다.Here, the Example which aims at the effect of reducing the thickness of an interface layer by this invention is demonstrated, comparing with the comparative example based on a prior art.

도 1의 사진의 오른쪽은, 본 발명의 1실시예에 따라 제작된 층구조의 단면에 대한 TEM(투과형 전자현미경) 사진이다. 이러한 층 구조를 제작할 때에는, Si기판 위에 얇은 산화실리콘(SiO2) 막을 제작하고 그 위에 산화 하프늄(HfO2)막을 제작했다. 그 후, HfO2막 위에 산화 탄탈(Ta2O5-X)막을 제작했다(Ta2O5이 아니고 Ta2O5 -X로 한 이유는 후술한다).The right side of the photograph of FIG. 1 is a TEM (transmission electron microscope) photograph of a cross section of a layer structure produced according to an embodiment of the present invention. In producing such a layer structure, a thin silicon oxide (SiO 2 ) film was produced on a Si substrate, and a hafnium oxide (HfO 2 ) film was produced thereon. Then, HfO 2 film was produced tantalum (Ta 2 O 5-X) over the oxide film (Ta 2 O 5 is not a reason for a Ta 2 O 5 -X will be described later).

위에 전술한 층 구조의 보다 구체적인 작성 방법은 아래와 같다.
More specific preparation method of the above-described layer structure is as follows.

(1) 얇은 산화 실리콘막(1) thin silicon oxide film

희석된 불화수소산용액으로 상기 Si기판표면의 자연산화막을 제거한 후에, 950 ℃ 이상의 고온 열처리 산화 방법으로 처리하여, 상기 얇은 산화 실리콘막을 제작했다. 한편, 실리콘(Si기판)을 사전에 미리 산화하여 상기 얇은 산화 실리콘층을 제작하는 것은, 상기 산화 하프늄막(제1 금속 산화물막)과의 사이에 결함이 적은 양호한 계면을 형성하기 위해서이며, 본 발명에 의하면, 후공정의 PDA(Post Deposition Annealing) 처리에 있어서 막이 증가되는 계면층으로서의 상기 산화 실리콘막의 두께를 삭감할 수 있다.
After removing the native oxide film on the surface of the Si substrate with a diluted hydrofluoric acid solution, the thin silicon oxide film was prepared by a high temperature heat treatment oxidation method of 950 ° C or higher. On the other hand, the thin silicon oxide layer is fabricated in advance by oxidizing silicon (Si substrate) in advance in order to form a good interface with few defects between the hafnium oxide film (first metal oxide film). According to the present invention, it is possible to reduce the thickness of the silicon oxide film as an interfacial layer in which the film is increased in a post-deposition annealing (PDA) process in a later step.

(2) 산화 하프늄막 (제1 금속 산화물막)(2) Hafnium oxide film (first metal oxide film)

산소원료로서 H2O를, 하프늄원료로서 TEMAHf(Tetrakis-Ethylmethylamido-Hafnium:Hf(NEtMe)4)을 이용하여, 원자층 제어 증착(ALD:Atomic Layer Deposition)법에 의해, 상기 산화 실리콘 막위에 산화 하프늄막을 퇴적했다. 그 후, 퇴적된 막의 결함 등을 저감시키기 위해 1,050℃에서 PDA(Post Deposition Annealing) 처리를 실시했다.
Oxidation on the silicon oxide film by atomic layer controlled deposition (ALD) using H 2 O as an oxygen source and TEMAHf (Tetrakis-Ethylmethylamido-Hafnium: Hf (NEtMe) 4 ) as a hafnium source. A hafnium film was deposited. After that, a PDA (Post Deposition Annealing) treatment was performed at 1,050 ° C. in order to reduce defects and the like of the deposited film.

(3) 산화 탄탈막 (제2 금속 산화물막) (3) tantalum oxide film (second metal oxide film)

산화 탄탈 타겟을 채용한 저산소분압화의 펄스 레이저 증착(Pulsed Laser deposition)법으로, 상기 산화 하프늄막 위에 산소결손형의 상기 산화 탄탈(Ta2O5-X)막을 약 5nm퇴적했다. About 5 nm of the oxygen-deficient tantalum oxide (Ta 2 O 5-X ) film was deposited on the hafnium oxide film by a low oxygen partial pressure pulsed laser deposition method employing a tantalum oxide target.

　한편, 상기 산화 탄탈막에서의 탄탈의 농도는, 1020~1022개/cm3인 것이 바람직하다. On the other hand, the concentration of tantalum in the tantalum oxide film is preferably 10 20 to 10 22 pieces / cm 3 .

　상기 탄탈의 농도가, 1020개/cm3미만이면 상기 산화 하프늄막(제1금속 산화물막)으로의 탄탈의 확산이 불충분하게 될 것이며, 1022개/cm3을 초과하면 상기 산화 하프늄막으로부터 산소를 흡수하도록 하기 때문에 상기 산화 하프늄막에 결함이 늘어나서 막질이 열화할 것이다.If the concentration of tantalum is less than 10 20 pieces / cm 3 , diffusion of tantalum into the hafnium oxide film (first metal oxide film) will be insufficient, and if it exceeds 10 22 pieces / cm 3 from the hafnium oxide film, Because it absorbs oxygen, defects will increase in the hafnium oxide film and the film quality will deteriorate.

한편, 도 2 (a) 및 (b)에 도시된 바와 같이, 상기 산화 탄탈막 위에는 또한 산화 실리콘막이 배치되고 있다. 이 산화 실리콘막은, 도 2 (a) 및 (b)에 그 결과를 나타내는 백 사이드SIMS 분석할 때의 시료제작에 견딜수 있는 강도를 갖는 보호막으로서 퇴적된 것이다. 따라서, 이 산화 실리콘막은 단지 측정의 형편상 마련되어진 것이며, 본 발명 그 자체에는 관계없다. 또 이하에 서술되는 비교예에 있어서도, 동일한 목적에서 산화 하프늄막 위에 산화 실리콘막이 퇴적되어 있다.On the other hand, as shown in Figs. 2A and 2B, a silicon oxide film is further disposed on the tantalum oxide film. This silicon oxide film is deposited as a protective film having a strength that can withstand the fabrication of the back side SIMS analysis shown in Figs. 2 (a) and 2 (b). Therefore, this silicon oxide film is provided only for the convenience of a measurement, and is not related to this invention itself. Also in the comparative examples described below, a silicon oxide film is deposited on the hafnium oxide film for the same purpose.

[비교예][Comparative Example]

Ta2O5 -X막을 마련하지 않는 것이외는, 실시예 1의 층구조와 같은 방법에 의해 비교예에 관련되는 층구조를 제작했다. 실시예 1의 사진과 동일한 조건으로 제작한 TEM사진을 도 1의 왼쪽에 도시하였다.
By a method such as that of the layer structure except in Example 1 Ta 2 O 5 does not include a film -X to prepare a layered structure according to the comparative example. A TEM photograph produced under the same conditions as the photograph of Example 1 is shown on the left side of FIG. 1.

[실시예 1과 비교예의 대비][Comparison of Example 1 and Comparative Example]

도 2(a) 및 도 2(b)는, 실시예 1의 층구조(도2(a))과 비교예의 층구조(도2(b))의 SIMS(2차 이온 질량분석)측정 결과의 그래프를 도시하고 있다. 이 그래프들로부터, 오른쪽의 실시예 1의 층구조의 그래프에서는, HfO2막 위에 적재(퇴적)된 Ta2O5-x막으로부터 Ta가 HfO2안으로 확산하고 있는 모양을 알 수 있다. 반대로 Hf도 Ta2O5-x막측으로 확산하고 있기 때문에, Ta2O5 -x막중에서는 그 오른쪽 끝(도1의 TEM사진에서는 위)에서도 상당한 양의 Hf가 존재하고 있다. 도 1의 오른쪽에 있어서 HfO2 의 위층이 모두 TaHfOx로 표기되고 있는 것은 이러한 상황을 나타내기 위해서다.2 (a) and 2 (b) show the results of SIMS (secondary ion mass spectrometry) measurement of the layer structure (FIG. 2 (a)) of Example 1 and the layer structure (FIG. 2 (b)) of the comparative example. The graph is shown. From these graphs, it can be seen from the graph of the layer structure of Example 1 on the right that Ta is diffused into HfO 2 from the Ta 2 O 5-x film loaded (deposited) on the HfO 2 film. In contrast, because Hf also be spread toward the Ta 2 O 5-x film, Ta 2 O 5 -x the film has a significant amount of Hf in the presence (upper in the TEM photograph of FIG. 1) that the right edge. In the right side of FIG. 1, all of the upper layers of HfO 2 are denoted by TaHfO x to indicate such a situation.

도 1의 2개의 TEM사진을 비교하면 알수 있는 바와 같이, 계면층(SiOx로 표기되어 있는 영역임. 계면층을 구성하는 산화 실리콘중의 산소가 화학량론 조성인 SiO2보다도 적은 것이 있기 때문에, 이와 같이 표기하고 있다)의 두께가, 비교예의 1.6nm에 대하여, 실시예 1에서는 Ta2O5 -x를 적재한 것으로서 1.2~1.4nm로 얇아져 있다.As can be seen by comparing the two TEM photographs of Fig. 1, the interface layer (area denoted by SiO x .) Since there is less oxygen in the silicon oxide constituting the interface layer than SiO 2 which is a stoichiometric composition, In this way, the thickness of the layer (described above) is thinned at 1.2 to 1.4 nm as in Example 1 where Ta 2 O 5 -x is loaded with respect to 1.6 nm of the comparative example.

이 작용은, Ta2O5 -x막을 적재하는 과정에서 계면층의 산소가 HfO2막측으로 빠져나감으로써 일어나는 것이다.This action occurs when oxygen in the interfacial layer escapes to the HfO 2 film side in the process of loading the Ta 2 O 5 -x film.

이를 도 3 내지 도 5를 참조해서 이론에 근거해서 설명한다.This will be described based on the theory with reference to FIGS. 3 to 5.

도 3에 있어서, Ta가 HfO2안으로 확산되어 Hf사이트를 치환하면, 전자가 밴드갭의 높은 준위로 유기된다. 이것은 Ta의 원자가가 Hf의 원자가보다도 크기 때문이다. 이러한 높은 준위를 점유한 전자는 에너지적으로 불안정하기 때문에 낮은 준위로 이동하려고 하지만 도 3의 상부에 도시된 바와 같이 가전자대는 이미 점유되고 있으므로, 이대로는 이동할 수 없다. 다시 말해, Ta가 Hf사이트를 치환(TaHf) 하면, 전자는 밴드갭의 높은 준위로 유기되므로 불안정하다. 그런데 격자간 산소가 형성되면, 도 4의 상부에 도시된 바와 같이, 가전자대 근방에 비점유 준위가 형성되므로, 전자의 이동이 일어나고, 시스템의 전체가 안정화된다. 다시 말해, 격자간 산소(Oi)가 형성됨으로써, 전자는 낮은 준위로 이동할 수 있게 되어 안정화된다.In Fig. 3, when Ta diffuses into HfO 2 to replace the Hf site, electrons are induced to a high level of the band gap. This is because the valence of Ta is larger than that of Hf. The electrons occupying this high level attempt to move to a lower level because they are energetically unstable, but as the valence band is already occupied, as shown in the upper part of FIG. In other words, when Ta substitutes the Hf site (Ta Hf ), the electrons are unstable because they are induced to a high level of the band gap. However, when the interstitial oxygen is formed, as shown in the upper portion of FIG. 4, since a non-occupying level is formed near the valence band, electrons move and the entire system is stabilized. In other words, by forming interstitial oxygen (O i ), electrons can move to a lower level and stabilize.

Ta가 HfO2안으로 확산됨으로써 격자간 산소의 형성(산소의 흡수)이 촉진되기 때문에, 근접한 SiOx층으로부터 산소가 빠져나가 HfO2안으로 확산된다. 이것이 SiOx계면층의 막두께감소에 공헌하고 있다고 판단된다. 도 3 및 도 4의 하부에, 상부의 전자상태에 대응하는 계면구조와 원자의 확산을 나타낸 개념도를 도시하고 있다.Since Ta diffuses into HfO 2 to promote the formation of interstitial oxygen (absorption of oxygen), oxygen escapes from the adjacent SiO x layer and diffuses into HfO 2 . It is thought that this contributes to the reduction in the film thickness of the SiO x interface layer. 3 and 4, conceptual diagrams showing the interfacial structure and the diffusion of atoms corresponding to the upper electronic state are shown.

아래에 결함밀도의 계산 방법을 나타낸다. 예로서 HfO2 단사정(單斜晶;monoclinic crystal) 96원자중 1개의 Hf를 Ta로 치환한 결함(치환Ta)의 밀도의 계산 순서를 나타낸다. 제1원리계산에 의해, 결함을 도입한 결정의 구조를 완화하고, 그 전체 에너지를 어림잡아 계산하고, 결함이 없을 경우와의 전체 에너지의 차이를 구한다. 그 다음에, Hf와 Ta의 화학 포텐셜을 각각 HfO2과 Ta2O5의 생성 엔탈피의 실험 값(비특허문헌9참조)으로부터 어림잡아 계산한다. 산소의 화학 포텐셜은 SiO2과 Si의 벌크의 전체 에너지의 차이로부터 구한다. The calculation method of the defect density is shown below. As an example HfO 2 The calculation procedure of the density of the defect (substitution Ta) which substituted one Hf with Ta among the monoclinic 96 atoms is shown. By the first principle calculation, the structure of the crystal incorporating the defect is relaxed, the total energy is estimated and calculated, and the difference in total energy from the case where there is no defect is obtained. Next, the chemical potentials of Hf and Ta are estimated from the experimental values (see Non-Patent Document 9) of the production enthalpy of HfO 2 and Ta 2 O 5 , respectively. The chemical potential of oxygen is obtained from the difference in the total energy of the bulk of SiO 2 and Si.

이것은 HfO2의 막이 Si기판위에 형성된 것을 고려하기 위해서다. 따라서 형성 에너지는 페르미(Fermi) 에너지만의 함수로서 나타낼 수 있다. 이 형성 에너지를 사용해서 다음의 수식 가운데 아래범위내의 식으로부터 결함밀도를 계산한다. 온도는 1,000℃로 설정했다.This is to consider that a film of HfO 2 is formed on the Si substrate. The formation energy can thus be expressed as a function of Fermi energy only. Using this formation energy, the defect density is calculated from the equation within the following range. The temperature was set to 1,000 ° C.

Figure 112012048540390-pct00001
Figure 112012048540390-pct00001

도 5은, 상기 결함밀도의 계산 방법에 의해, HfO2내부 결함밀도를 페르미(Fermi) 에너지의 함수로서 도시한 결과다. 한편, 도 5에 있어서는, 페르미 준위의 상승과 격자간 산소의 증가의 관계가 도시되어 있다. Ta가 첨가되지 않은 때에는, 양(+)으로 대전된 산소 구멍(VO 2 +)과 음(-)으로 대전된 격자간 산소(Oi 2 -)의 밀도가 일치하는 점에서 전하중성이 유지된다. 이 점이 HfO2고유의 페르미 준위로 판단된다(εF intrinsic). 한편, Ta가 첨가되었을 경우에는, VO 2 +의 농도보다도 Ta1 +의 농도가 커지므로, Ta1 +의 농도가 Oi 2 -의 농도의 2배가 된 점에서 전하중성이 만족된다. 이 조건에 의해 결정되는 페르미 준위(εF extrinsic)는 εF intrinsic보다도 고에너지측에 위치하고 있으므로, Ta첨가에 의해 페르미 준위가 윗쪽으로 이동하게 된다. 그 결과, 격자간 산소의 밀도가 상승하고, 산소 구멍의 밀도가 감소하고 있는 것을 알 수 있다. 즉, Ta첨가에 의해 HfO2안의 산소밀도가 상승하는 것을 의미한다. 이 계산 결과는 도 3 및 도 4를 참조해서 설명한 본 발명의 작용의 이론적 해석을 뒷받침하는 것이다.FIG. 5 shows the results of the HfO 2 internal defect density as a function of Fermi energy by the above-described method for calculating the defect density. In FIG. 5, the relationship between the increase in the Fermi level and the increase in the interstitial oxygen is shown. If Ta is not added, positive oxygen hole (V O 2 +) charged with negative (-) as the oxygen between the charged grid (O i 2 -), the charge neutrality maintained at a point at which a density of the match do. This point is judged to be the Fermi level inherent in HfO 2 (ε F intrinsic ). On the other hand, if Ta is added, so larger than the concentration of the Ta 1 + concentration of V + O 2, the concentration of Ta 1 + O i 2 - the charge neutrality is satisfied at the two times that of the concentration. The Fermi level (ε F extrinsic ) determined by this condition is located on the higher energy side than the ε F intrinsic , so the Fermi level moves upward by adding Ta. As a result, it turns out that the density of interstitial oxygen rises and the density of oxygen pores decreases. That is, it means that the oxygen density in the HfO 2 raised by the addition of Ta. This calculation result supports the theoretical analysis of the operation of the present invention described with reference to FIGS. 3 and 4.

여기서 비특허문헌 4, 5과의 차이를 설명한다. 이 종래 기술에 있어서는 고유전체막에 캐핑한 막이 고유전체막으로부터도 산소를 뽑아내기 때문에, 이미 설명한 것과 같이 디바이스의 신뢰성 열화라고 하는 문제점을 일으킨다. 이에 대하여, 본 발명에 있어서는 상술한 설명으로부터도 명확한 것 같이, 고유전체 막 자신이 산소를 흡수하므로 고유전체막에 산소 구멍은 생기지 않고, 신뢰성의 저하를 초래할 일은 없어진다.Here, the difference from the nonpatent literatures 4 and 5 is demonstrated. In this prior art, since the film capped on the high dielectric film also extracts oxygen from the high dielectric film, this causes a problem of deterioration of the reliability of the device as described above. On the other hand, in the present invention, as is clear from the above description, since the high dielectric film itself absorbs oxygen, oxygen pores are not formed in the high dielectric film and there is no cause of deterioration in reliability.

한편, HfO2안으로 Ta가 확산하는 것으로서 산소를 주위로부터 뽑아낼 때, 이러한 인출이 Ta2O5측에서는 될 수 있는 한 일어나지 않도록 하는 것이 바람직하다. Ta산화물의 막 형성시 산소가 과잉한 상태의 산화물 막이 가능한 한 산소의 공급원으로서 기능하여, SiOx측으로부터 산소 뽑는 양을 감소시킨다. 이러한 현상을 억제하기 위해서, 막 형성시 Ta산화물의 화학량론적인 조성 Ta2O5에서 산소가 결손된 Ta2O5-x의 막이 되게 해야 한다.On the other hand, when Ta is extracted from the surroundings as Ta diffuses into HfO 2 , it is preferable that such extraction does not occur as much as possible on the Ta 2 O 5 side. When the Ta oxide film is formed, the oxide film in the state of excess oxygen functions as a source of oxygen as much as possible, thereby reducing the amount of oxygen extracted from the SiO x side. In order to suppress this phenomenon, it is necessary to make the film of Ta 2 O 5-x having oxygen deficiency in the stoichiometric composition Ta 2 O 5 of Ta oxide during film formation.

또, 초기부터 Ta와 Hf를 섞으면서 막을 형성하면, 분위기중의 산소와 열평형을 만족해버리므로, SiOx로부터 산소를 뽑는 효과가 상실되어 버린다. 따라서 이번과 같이 환원한, 다시 말해 산소결손이 있는 Ta2O5 -x를 HfO2 위에 막형성할 필요가 있다.In addition, when a film is formed by mixing Ta and Hf from the beginning, the oxygen and thermal equilibrium in the atmosphere are satisfied, so the effect of extracting oxygen from SiO x is lost. Therefore, it is necessary to form Ta 2 O 5 -x reduced in this manner, that is, oxygen deficiency, on HfO 2 .

본 발명에 의해 게이트 절연막을 제작할 경우에는, HfO2층 위에 적재된 Ta2O5 -x층도 게이트 절연막으로서 기능하기 때문에, 이대로는 게이트 절연막의 두께가 증대한다. 이 두께가 게이트 절연막으로서 요구되는 두께를 초과할 경우에는, Ta2O5 -x층 (실제로는 상술한 바와 같이 Ta와 Hf가 서로 섞인 TaHfOx층이 되고 있다)측의 적어도 일부를 습식 에칭 등에 의해 제거한다. 상술한 바와 같이 해서 제작된 층구조에 있어서는, Ta2O5층 측은 비정질인 것에 대해 HfO2층 측은 결정화되어 있기 때문에, HfO2층 자체가 에칭의 스톱퍼의 역할을 수행하므로 상기 에칭의 제어는 용이하다.When producing a gate insulating film by the present invention, because it functions as a HfO 2 layer of Ta 2 O 5 -x layer is also placed on the gate insulating film, this rate is increased the thickness of the gate insulating film. When this thickness exceeds the thickness required as the gate insulating film, at least a part of the Ta 2 O 5 -x layer (actually, the TaHfO x layer in which Ta and Hf are mixed with each other as described above) is wet-etched or the like. By removing. In the layer structure fabricated as described above, since the HfO 2 layer side is crystallized while the Ta 2 O 5 layer side is amorphous, the HfO 2 layer itself acts as a stopper for etching, so the control of the etching is easy. Do.

본 발명에 의해 얻을 수 있는 효과는, 적재 산화물의 금속 원소인 Ta의 원자가가 Hf의 원자가인 4가보다도 큰 것에 기인하고 있다. 따라서, 본 발명은 HfO2과 Ta2O5-x의 조합에 한정되는 것이 아니고, HfO2, ZrO2, TiO2등의 4가의 금속산화물과 Ta2O(5-x), Nb2O5 -x, V2O5 -x등의 5가의 금속산화물의 조합이라면 같은 효과를 얻을 수 있는 것으로 예상된다. 또, 각각의 막이 1종류의 금속의 산화물일 필요는 없고, 각각 상기 조건을 충족하는 복수의 금속의 산화물로 구성되어 있어도 같은 효과를 얻을 수 있다. 예를 들면, HfO2단독이 아니고 HfO2과 TiO2의 고용체로 고유전체막을 제작할 수도 있다. 적재 산화물도 동일하다.The effect which can be obtained by this invention is attributable to the valence of Ta which is a metal element of a loading oxide being larger than tetravalent which is the valence of Hf. Therefore, the present invention is not limited to the combination of HfO 2 and Ta 2 O 5-x , and tetravalent metal oxides such as HfO 2 , ZrO 2 , TiO 2 , and Ta 2 O (5-x) , Nb 2 O 5 A combination of pentavalent metal oxides such as -x and V 2 O 5 -x is expected to achieve the same effect. Moreover, each film does not need to be an oxide of one type of metal, and the same effect can be obtained even if it is comprised from the oxide of the some metal which respectively satisfy | fills the said conditions. For example, a high dielectric film can also be produced from a solid solution of HfO 2 and TiO 2 instead of HfO 2 alone. The same applies to the loading oxide.

또한, 실시예 1에서는 반도체로서 실리콘을 예시해서 설명하고 있지만, 실리콘이외의 반도체, 예를 들면 게르마늄(Ge)이나 갈륨 비소(GaAs)등의 각종의 화합물 반도체에 대하여도, 본 발명은 고유전체와 이들 반도체의 사이에 형성되는 이 반도체의 산화물 혹은 유전체와 이들 반도체의 사이에 삽입되는, 예를 들면 Si/SiNx, Ge, Ga2O3등의 다른 층(계면결함 삭감층)이 산화됨에 의해 형성되는 계면층의 삭감에 효과를 발휘한다. In Example 1, silicon is exemplified and described. However, the present invention also applies to semiconductors other than silicon, for example, various compound semiconductors such as germanium (Ge) and gallium arsenide (GaAs). The oxide or dielectric of the semiconductor formed between these semiconductors and another layer (interface defect reducing layer) interposed between these semiconductors, for example, Si / SiN x , Ge, Ga 2 O 3, etc., are oxidized. It is effective in reducing the interface layer formed.

[ 실시예 2]Example 2

이하에, 본 발명을 n채널형 및 p채널형 MOS트랜지스터로 구성되는 CMOS(Complementary Metal Oxide Semiconductor) 집적 회로의 제조 방법에 적용한 실시예를, 도 6~도 15을 참조해서 설명한다. 실제로는 반도체 기판위에는 다수의 트랜지스터가 작성되지만, 설명을 이해하기 쉽게 하기 위해서, 이하의 실시예에서는 n채널형 MOS트랜지스터와 p채널 형MOS트랜지스터를 각기 1개씩 제작하는 것으로서 설명한다.An embodiment to which the present invention is applied to a method of manufacturing a Complementary Metal Oxide Semiconductor (CMOS) integrated circuit composed of n-channel and p-channel MOS transistors will be described below with reference to FIGS. 6 to 15. Although a large number of transistors are actually formed on the semiconductor substrate, in order to make the description easy to understand, the following embodiments will be described as manufacturing one n-channel MOS transistor and one p-channel MOS transistor, respectively.

우선, 도 6에 따르면, 예를 들면 p형의 단결정 실리콘으로 이루어지는 반도체기판 (이하, 기판이라고 한다) (601)의 주면(主面)에 널리 알려진 STI(Shallow Trench Isolation)기술을 채용해서 소자분리홈(602)을 형성한다.First, according to FIG. 6, for example, a device is separated by employing a well-known shallow trench isolation (STI) technique on the main surface of a semiconductor substrate (hereinafter, referred to as a substrate) 601 made of p-type single crystal silicon. The groove 602 is formed.

계속해서, 기판(601)의 n채널형 MOS트랜지스터 형성 영역(도면의 좌측. 이후의 도면에서도 동일함)에 붕소를 이온 주입하고, p채널형 MOS트랜지스터 형성 영역(도면의 우측. 이후의 도면에서도 동일함)에 인(燐)을 이온 주입한다. 그 다음에, 기판(601)의 nMOS 형성 영역과 pMOS 형성 영역에, MOS트랜지스터의 문턱 전압값을 조정하기 위한 불순물을 이온 주입한다. 다음, 기판(601)을 열처리하여 상기 불순물을 기판(601)안으로 확산시키는 것에 의해, 기판(601)의 주면에 p형 웰(603) 및 n형 웰(604)을 형성한다. Subsequently, boron is ion-implanted into the n-channel MOS transistor formation region (the left side of the figure. Is the same). Then, impurities are implanted into the nMOS formation region and the pMOS formation region of the substrate 601 to adjust the threshold voltage value of the MOS transistor. Subsequently, the substrate 601 is heat-treated to diffuse the impurities into the substrate 601 to form the p-type well 603 and the n-type well 604 on the main surface of the substrate 601.

계속해서, 도 7에 도시된 바와 같이, nMOS 형성 영역의 p형웰(603)과 pMOS 형성영역의 n형웰(604)의 각각의 표면에, 산화 실리콘(SiO2)로부터 이루어지는 계면층을 형성한 뒤, 산화 하프늄(HfO2)으로 이루어지는 게이트 절연막(701)을 형성한다. 한편, 트랜지스터 특성 향상을 위하여, 결함저감용의 매우 얇은(예를 들면 0.3~0.5nm정도) 산화 실리콘의 계면층이 산화 하프늄과 실리콘의 계면에 마련됨으로써, 여기에서도 실시예 1과 동일한 층구조를 제작했다.Subsequently, as shown in FIG. 7, an interface layer made of silicon oxide (SiO 2 ) is formed on the surfaces of the p-type wells 603 in the nMOS formation region and the n-type wells 604 in the pMOS formation region. A gate insulating film 701 made of hafnium oxide (HfO 2 ) is formed. On the other hand, in order to improve transistor characteristics, a very thin (for example, about 0.3 to 0.5 nm) silicon oxide interface layer for reducing defects is provided at the interface between hafnium oxide and silicon, whereby the same layer structure as in Example 1 can be obtained. Made.

상기 산화 실리콘 막은, 예를 들면, 희석된 불화수소산용액으로 Si기판표면의 자연산화막을 제거한 후에, 950 ℃이상의 고온 열처리 산화 방법으로 제작한다. 계속해서, 상기 산화 하프늄막은, 예를 들면, H2O의 O(산소)원료와 TEMAHf(Tetrakis-Ethylmethylamido-Hafnium:Hf(NEtMe)4)의 Hf(하프늄)원료를 이용한 원자층제어증착(ALD:Atomic Layer Deposition)법에 의해 퇴적시킨 후, 그 막의 결함등을 저감시키기 위해 700℃ 이상의 PDA(Post Deposition Annealing)를 실시한다.The silicon oxide film is produced by, for example, a high temperature heat treatment oxidation method of 950 ° C. or higher after removing the native oxide film on the surface of the Si substrate with a diluted hydrofluoric acid solution. Subsequently, the hafnium oxide film is, for example, atomic layer controlled deposition (ALD) using an O (oxygen) material of H 2 O and a Hf (hafnium) material of TEMAHf (Tetrakis-Ethylmethylamido-Hafnium: Hf (NEtMe) 4 ). After deposition by the atomic layer deposition method, PDA (Post Deposition Annealing) at 700 ° C or higher is performed to reduce defects of the film.

도 1의 단면TEM상에 도시된 바와 같이, 1,050℃의 PDA처리에 있어서, 상기 산화 하프늄막으로부터 산소가 방출됨에 따라 실리콘 기판에서의 산화 반응이 진행되고, 그 결과로서 막 두께 1.6nm의 산화 실리콘막이 형성된다.As shown on the cross-sectional TEM of FIG. 1, in the PDA treatment at 1,050 ° C, an oxidation reaction proceeds on a silicon substrate as oxygen is released from the hafnium oxide film, and as a result, silicon oxide having a thickness of 1.6 nm. A film is formed.

여기에 있어서, 전술한 산화 하프늄/산화 실리콘막의 적층구조위에 산화 탄탈 타겟을 채용한 저산소분압화의 펄스 레이저 증착(Pulsed Laser deposition)법으로, 산소결손형의 산화 탄탈(Ta2O5-x)막을 약 5nm퇴적시킨다. 상기 산화 탄탈막의 퇴적중에, 마이그레이션에 의해 Ta원자가 상기 산화 하프늄막 안으로 확산되어 TaHfOx구조를 형성한다. HfO2막으로 Ta원자가 들어감에 의해 화학량론비와의 차이가 생겨 산소가 부족해지기 때문에, SiO2막으로부터 산소가 방출된다. 그 결과, SiO2막이 실리콘 서브 산화막(SiO2-x)이 되어서 증발 등이 발생하므로 상기 산화 실리콘막의 막 두께를 감소시키게 된다.Here, the oxygen-depleted tantalum oxide (Ta 2 O 5-x ) by a low oxygen partial pressure pulsed laser deposition method employing a tantalum oxide target on the laminated structure of the hafnium oxide / silicon oxide film described above. The film is deposited to about 5 nm. During deposition of the tantalum oxide film, Ta atoms diffuse into the hafnium oxide film by migration to form a TaHfO x structure. As Ta atoms enter the HfO 2 film, a difference with the stoichiometric ratio occurs and oxygen is deficient, and oxygen is released from the SiO 2 film. As a result, since the SiO 2 film becomes a silicon sub oxide film (SiO 2-x ) and evaporation occurs, the thickness of the silicon oxide film is reduced.

도 2 (a) 및 (b)에 도시된 바와 같이, 백 사이드SIMS분석에 의해도, 상기 산화 하프늄막중에 Ta원자가 존재하는 것을 확인할 수 있다. 산소결손형 산화 탄탈막은, 이밖에 탄탈 금속을 타겟으로 이용한 스퍼터링(sputtering)법 및 전자빔증착법으로 금속 탄탈막을 퇴적한 후 저온 산화 처리에 의해도 제작할 수 있다. 상기 산화 탄탈막의 두께는, 상기 산화 하프늄막의 두께에 대해 10%이상인 것이 바람직하다.As shown in Fig. 2 (a) and (b), it is confirmed by the back side SIMS analysis that Ta atoms exist in the hafnium oxide film. In addition, the oxygen-deficient tantalum oxide film can also be produced by a low temperature oxidation treatment after depositing a metal tantalum film by sputtering and electron beam deposition using a tantalum metal as a target. It is preferable that the thickness of the said tantalum oxide film is 10% or more with respect to the thickness of the said hafnium oxide film.

그 다음에, TaHfOX구조의 형성에 관여하지 않는 여분의 산화 탄탈막은, 산성 습식(wet) 에칭이나 건식(dry) 에칭 공정을 이용하여 제거한다. 어느쪽의 에칭 프로세스에 있어서도 산화 탄탈막과 TaHfOX막의 선택성을 이용해서 산화 탄탈막의 제거를 하는 것이 가능하다. 이 여분의 산화 탄탈막을 제거함에 의해 게이트 절연막의 두께를 저감시킬 수 있다.Then, the excess tantalum oxide film not involved in the formation of the TaHfO X structure is removed using an acidic wet etching or dry etching process. In either etching process, it is possible to remove the tantalum oxide film using the selectivity of the tantalum oxide film and the TaHfO X film. By removing this extra tantalum oxide film, the thickness of the gate insulating film can be reduced.

그 다음에, TaHfOX막을 치밀화하기 위해서 열처리를 하지만, 이러한 처리는 TaHfOX막으로부터의 산소의 재방출을 억제하기 위하여 수소 가스의 환원 분위기 및/또는 질소 가스 분위기에서 한다. 이밖에, 유기금속화학기상증착(MOCVD:Metalorganic Chemical Vapor Deposition)법, 스퍼터링법 및 전자빔증착방법등을 이용하여 산화 하프늄막을 퇴적시키는 것이 바람직하다.Then, heat treatment is performed to densify the TaHfO X film, but this treatment is carried out in a reducing atmosphere of hydrogen gas and / or a nitrogen gas atmosphere in order to suppress the re-emission of oxygen from the TaHfO X film. In addition, it is preferable to deposit a hafnium oxide film using an organometallic chemical vapor deposition (MOCVD) method, a sputtering method, an electron beam deposition method, or the like.

이러한 산화 하프늄은 상기 산화 실리콘보다 비유전율이 높은 하프늄계 산화물이다. 상기 산화 하프늄으로 구성되는 게이트 절연막(701)의 비유전율이 16이라면, 상기 산화 하프늄의 막 두께를 예를 들면 2nm으로 했을 경우, 산화 실리콘 환산 막 두께(EOT;Equivalent Oxide Thickness)은, 예를 들면 0.5nm이 된다. 이 경우, MOS트랜지스터의 ON상태의 누설(leak) 전류는, 동일한 두께의 산화 실리콘으로 구성되는 게이트 절연막의 MOS트랜지스터와 비교해서 저감할 수 있다.Such hafnium oxide is a hafnium oxide having a higher dielectric constant than the silicon oxide. If the relative dielectric constant of the gate insulating film 701 made of hafnium oxide is 16, when the film thickness of the hafnium oxide is 2 nm, for example, the equivalent oxide thickness (EOT) is, for example, 0.5 nm. In this case, the leakage current in the ON state of the MOS transistor can be reduced in comparison with the MOS transistor of the gate insulating film made of silicon oxide of the same thickness.

계속해서, 도 8에 도시된 바와 같이, 게이트 절연막(701)위에 스퍼터링법을 채용해서 질화 티탄(TiN)으로 구성되는 금속질화물막(801)을 퇴적(형성)하고, 그 금속질화물막(801)위에 CVD법을 채용해서 질화 실리콘 막을 퇴적한 후, 포토레지스트막(도시되지 않음)을 마스크로 한 건식식각으로 질화 실리콘막을 패터닝함으로써, pMOS형성 영역에 하드 마스크(802)를 형성한다. 본 실시예에서는, 질화 티탄으로 구성되는 금속질화물막(801)의 두께는 예를 들면 20nm이다.Subsequently, as shown in FIG. 8, the metal nitride film 801 made of titanium nitride (TiN) is deposited (formed) by employing a sputtering method on the gate insulating film 701, and the metal nitride film 801. After the silicon nitride film is deposited by employing the CVD method, the hard mask 802 is formed in the pMOS formation region by patterning the silicon nitride film by dry etching using a photoresist film (not shown) as a mask. In the present embodiment, the thickness of the metal nitride film 801 made of titanium nitride is 20 nm, for example.

계속해서, 도 9에 도시된 바와 같이, nMOS형성 영역의 금속질화물막(801)을 식각시켜 제거하여 nMOS형성 영역의 게이트 절연막(701)을 노출시킨 후, 그 게이트 절연막(701)위에 스퍼터링법을 채용해서 질화 티탄 알루미늄(TiAlN)으로 구성되는 금속질화물막(901)을 퇴적(형성)한다.Subsequently, as shown in FIG. 9, the metal nitride film 801 of the nMOS forming region is etched away to expose the gate insulating film 701 of the nMOS forming region, and then sputtering is performed on the gate insulating film 701. A metal nitride film 901 made of titanium aluminum nitride (TiAlN) is deposited to form (form).

계속해서, 금속질화물막(901)위에 CVD법을 채용해서 질화 실리콘막을 퇴적하고, 포토레지스트 막(도시되지 않음)을 마스크로 하여 건식 식각하여 질화 실리콘막을 패터닝하는 것에 의해, nMOS형성 영역에 하드 마스크(도시되지 않음)을 형성한 후, pMOS형성 영역의 금속질화물막(901)을 식각하여 제거한다.Subsequently, a silicon nitride film is deposited on the metal nitride film 901 by using a CVD method, followed by dry etching using a photoresist film (not shown) as a mask to pattern the silicon nitride film, thereby hard masking the nMOS formation region. After forming (not shown), the metal nitride film 901 in the pMOS formation region is etched and removed.

계속해서, 도 10에 도시된 바와 같이, pMOS형성 영역의 하드 마스크(802)를 제거한다.Subsequently, as shown in FIG. 10, the hard mask 802 of the pMOS formation region is removed.

계속해서, 도 11에 도시된 바와 같이, pMOS형성 영역의 금속질화물막(801) 및 nMOS형성 영역의 금속질화물막(901)위에 질화 탄탈(배리어 메탈)로 구성되는 캡층(1101)을 퇴적(형성)한 후, photoresist 막(도시되지 않음)을 마스크로 한 건식 식각하여 캡층(1101) 및 금속질화물막(801, 901)을 패터닝한다. 이것에 의해, n형 웰(604)의 게이트 절연막(701)위 및 p형 웰(603)의 게이트 절연막(701)위에, 각각 금속질화물막(801)으로 구성되는 게이트 전극(1102) 및 금속질화물막(901)으로 구성되는 게이트 전극(1103)이 형성된다.Subsequently, as shown in FIG. 11, a cap layer 1101 made of tantalum nitride (barrier metal) is deposited (formed) on the metal nitride film 801 in the pMOS formation region and the metal nitride film 901 in the nMOS formation region. After that, the cap layer 1101 and the metal nitride films 801 and 901 are patterned by dry etching using a photoresist film (not shown) as a mask. As a result, the gate electrode 1102 and the metal nitride formed of the metal nitride film 801 on the gate insulating film 701 of the n-type well 604 and the gate insulating film 701 of the p-type well 603, respectively. A gate electrode 1103 composed of a film 901 is formed.

캡층(1101)은, 기판(601)이 산소를 포함하는 분위기중에 노출되더라도, 금속질화물막(801, 901)에 산소가 도달하지 않도록 하기 위해서 마련되어지는 배리어 메탈로 구성되며, 본 실시예에서는 질화 탄탈을 적용하고 있다. 한편, pMOS형성 영역에는 캡층(1101)이 없어도 좋다.The cap layer 1101 is made of a barrier metal provided so that oxygen does not reach the metal nitride films 801 and 901 even when the substrate 601 is exposed to an atmosphere containing oxygen. In this embodiment, tantalum nitride is used. Is applying. On the other hand, the cap layer 1101 may not be present in the pMOS formation region.

계속해서, 도 12에 도시된 바와 같이, p형 웰(603)에 인(燐) 또는 비소를 이온 주입해서 n-형 반도체영역 (1201)을 형성하고, n형 웰(604)에 붕소를 이온 주입해서 p-형 반도체영역(1202)을 형성한 후, 게이트 전극(1102) 및 게이트 전극(1103)의 측벽에 측벽 스페이서(1203)을 형성한다. n-형 반도체영역(1201)은 n채널형 MOS트랜지스터를 LDD(Lightly Doped Drain)구조로 하기 위해서 형성하고, p-형 반도체영역(1202)은 p채널형 MOS트랜지스터를 LDD구조로 하기 위해서 형성한다. 측벽 스페이서(1203)는, 기판(601)위에 CVD법에서 산화 실리콘막을 퇴적한 후, 이 산화 실리콘막을 이방성 식각함으로써 형성된다.Subsequently, as shown in FIG. 12, phosphorus or arsenic is ion-implanted into the p-type well 603 to form the n-type semiconductor region 1201, and boron is ionized in the n-type well 604. After implantation to form the p-type semiconductor region 1202, sidewall spacers 1203 are formed on the sidewalls of the gate electrode 1102 and the gate electrode 1103. The n-type semiconductor region 1201 is formed to form an n-channel MOS transistor in a lightly doped drain (LDD) structure, and the p-type semiconductor region 1202 is formed to make a p-channel MOS transistor in an LDD structure. . The sidewall spacers 1203 are formed by depositing a silicon oxide film on the substrate 601 by CVD and then anisotropically etching the silicon oxide film.

계속해서, 도 13에 도시된 바와 같이, p형 웰(603)에 인(燐) 또는 비소를 이온 주입하고, n형 웰(604)에 붕소를 이온 주입한 후, 기판(601)을 열처리해서 이 불순물을 확산시키는 것에 의해, p형 웰(603)에 n+형 반도체영역(소스·드레인) (1301)을 형성하고, n형 웰(604)에 p+형 반도체영역(소스·드레인)(1302)을 형성한다.Subsequently, as shown in FIG. 13, phosphorus or arsenic is ion-implanted into the p-type well 603, boron is ion-implanted into the n-type well 604, and then the substrate 601 is heat treated. By diffusing the impurities, an n + type semiconductor region (source and drain) 1301 is formed in the p type well 603, and a p + type semiconductor region (source and drain) 1302 is formed in the n type well 604. To form.

계속해서, 도 14에 도시된 바와 같이, 기판(601)위에 CVD법에 의해 산화 실리콘으로 구성된 층간 절연막 (1401)을 형성하고, 화학적 기계연마법으로 그 표면을 평탄화한 후, 포토레지스트 막을 마스크로 하여 층간 절연막(1401)을 건식식각하여, n+형 반도체영역(소스·드레인)(1301)의 상부와 p+형 반도체영역(소스·드레인)(1302)의 상부에 컨택트 홀(1402)을 형성한다.Subsequently, as shown in FIG. 14, an interlayer insulating film 1401 made of silicon oxide is formed on the substrate 601 by CVD, and the surface thereof is planarized by chemical mechanical polishing, and then the photoresist film is used as a mask. The interlayer insulating film 1401 is dry etched to form contact holes 1402 on the n + type semiconductor region (source and drain) 1301 and on the p + type semiconductor region (source and drain) 1302.

계속해서, 도 15에 도시된 바와 같이, 컨택트 홀(1402)의 내부에 플러그(1501)을 형성하고, 계속해서 층간 절연막(1401)의 상부에 금속배선(1502)을 형성한다. 플러그(1501)을 형성하기 위해서는, 컨택트 홀(1402)의 내부를 포함하는 층간 절연막(1401)위에 스퍼터링법으로 질화 티탄(TiN)막과 텅스텐(W)막을 퇴적한 후, 층간 절연막(1401)위의 TiN막과 W막을 화학적 기계연마법으로 제거한다. 또, 금속 배선(1502)을 형성하기 위해서는, 층간 절연막(1401)위에 스퍼터링법으로 W막이나 Al합금막등의 금속막을 퇴적한 후, 포토레지스트막(도시되지 않음)을 마스크로 한 건식식각하여 이 금속막을 패터닝한다.Subsequently, as shown in FIG. 15, a plug 1501 is formed inside the contact hole 1402, and a metal wiring 1502 is formed over the interlayer insulating film 1401. To form the plug 1501, a titanium nitride (TiN) film and a tungsten (W) film are deposited on the interlayer insulating film 1401 including the inside of the contact hole 1402 by sputtering, and then on the interlayer insulating film 1401. TiN film and W film were removed by chemical mechanical polishing. In order to form the metal wiring 1502, a metal film such as a W film or an Al alloy film is deposited on the interlayer insulating film 1401 by sputtering, followed by dry etching using a photoresist film (not shown) as a mask. This metal film is patterned.

여기까지의 공정에 의해, 산화 실리콘막의 두께를 감소시킨 게이트 절연막을 구비하는 n채널형MOS트랜지스터(1303) 및 p채널형MOS트랜지스터(1304)가 완성된다.By the steps up to this point, the n-channel MOS transistor 1303 and the p-channel MOS transistor 1304 including the gate insulating film having reduced thickness of the silicon oxide film are completed.

이상, 상세하게 설명한 것 같이, 본 발명은 계면층의 형성후에 이 계면층과는 직접 접촉하지 않는 곳에서 계면층의 두께를 얇게 할 수 있는 신규한 것이기 때문, 실효 유전율이 높은 게이트 산화막을 얻기 위한 프로세스에 새로운 선택사항과 자유도를 주는 것이며, 실용에 제공해서 매우 유효하다.As described in detail above, the present invention is a novel one capable of making the thickness of the interface layer thin in a place where it is not in direct contact with the interface layer after the formation of the interface layer. It gives new options and degrees of freedom to the process and is very useful for practical use.

601: 반도체기판
602: 소자분리홈
603 : p형 웰
604 : n형 웰
701: 게이트 절연막
801: 금속질화물막
802: 하드 마스크
901: 금속질화물막
1101: 캡층
1102: 게이트 전극
1103:게이트 전극
1201 : n-형 반도체영역
1202 : p-형 반도체영역
1203 : 측벽스페이서
1301 : n+형 반도체영역
1302 : p+형 반도체영역
1303 : n채널형MOS트랜지스터
1304 : p채널형MOS트랜지스터
1401: 층간 절연막
1402: 컨택트 홀
1501: 플러그
1502: 금속 배선601: semiconductor substrate
602: device isolation groove
603: p-type well
604 n-type well
701: gate insulating film
801: metal nitride film
802: hard mask
901: metal nitride film
1101: cap layer
1102: gate electrode
1103: gate electrode
1201: n-type semiconductor region
1202: p-type semiconductor region
1203: sidewall spacer
1301: n + type semiconductor region
1302: p + type semiconductor region
1303 n-channel MOS transistor
1304: p-channel MOS transistor
1401: interlayer insulating film
1402: contact hole
1501: plug
1502: metal wiring

Claims (18)

(a) 반도체 위에, 계면층으로서의 반도체 산화막을 형성하는 단계;
(b) 상기 계면층위에, 제1 금속의 산화물막을 형성하는 단계;
(c) 어닐링(annealing)에 의해, 상기 계면층의 두께를 증가시키는 단계; 및
(d) 제1 금속 산화물막위에, 상기 제1 금속보다 원자가가 큰 제2 금속의 산화물막을 형성하는 단계;
를 구비하여 상기 계면층의 두께를 삭감하는 계면층 삭감 방법.(a) forming a semiconductor oxide film as an interface layer on the semiconductor;
(b) forming an oxide film of a first metal on the interface layer;
(c) increasing the thickness of the interfacial layer by annealing; And
(d) forming an oxide film of a second metal having a greater valence than the first metal on the first metal oxide film;
And an interface layer reduction method for reducing the thickness of the interface layer. 제1항에 있어서, 제2 금속 산화물은, 화학량론적 조성보다도 산소가 결손되어 있는 것을 특징으로 하는 계면층 삭감 방법.The method of reducing an interfacial layer according to claim 1, wherein the second metal oxide is deficient in oxygen than in a stoichiometric composition. 제1항 또는 제2항에 있어서, 제2 금속 산화물막을 형성하는 단계는, 상기 제1 금속 산화물막위에 상기 제2 금속의 산화물을 증착하는 단계를 구비하는 것을 특징으로 하는 계면층 삭감 방법.3. The method of claim 1 or 2, wherein forming the second metal oxide film comprises depositing an oxide of the second metal on the first metal oxide film. 제1항 또는 제2항에 있어서, 제2 금속 산화물막을 형성하는 단계는,
(d-1) 상기 제1 금속 산화물막위에 제2 금속막을 형성하는 단계; 및
(d-2) 상기 제2 금속막을 산화시키는 단계; 를
구비하는 것을 특징으로 하는 계면층 삭감 방법.The method of claim 1, wherein the forming of the second metal oxide film comprises:
(d-1) forming a second metal film on the first metal oxide film; And
(d-2) oxidizing the second metal film; To
The interface layer reduction method characterized by the above-mentioned. 제1항 내지 제2항 중 어느 한 항에 있어서, 상기 반도체의 형성 재료는 실리콘이며, 상기 계면층은 산화 실리콘인 것을 특징으로 하는 계면층 삭감 방법.The interface layer reduction method according to any one of claims 1 to 2, wherein the semiconductor forming material is silicon, and the interface layer is silicon oxide. 제5항에 있어서, 상기 제1 금속의 산화물은 산화 실리콘보다 큰 유전율을 갖는 것을 특징으로 하는 계면층 삭감 방법.6. The method of claim 5 wherein the oxide of the first metal has a higher dielectric constant than silicon oxide. 제1항 내지 제2항 중 어느 한 항에 있어서, 상기 반도체의 형성 재료는 Ⅲ-V계 화합물반도체이며, 상기 반도체와 상기 제1 금속 산화물막의 사이에 계면결함 경감층을 더 구비하는 것을 특징으로 하는 계면층 삭감 방법. The semiconductor material according to any one of claims 1 to 2, wherein the semiconductor forming material is a III-V-based compound semiconductor, and further comprising an interface defect alleviation layer between the semiconductor and the first metal oxide film. Interface layer reduction method to do. 제1항 내지 제2항 중 어느 한 항에 있어서, 상기 제1 금속은 하프늄(Hf), 지르코늄(Zr) 및 티탄(Ti)으로부터 선택된 적어도 1종류의 금속이며, 상기 제2 금속은 탄탈(Ta), 니오브(Nb) 및 바나듐(V)으로부터 선택된 적어도 1종류의 금속인 것을 특징으로 하는 계면층 삭감 방법.The method of claim 1, wherein the first metal is at least one metal selected from hafnium (Hf), zirconium (Zr), and titanium (Ti), and the second metal is tantalum (Ta). ), At least one metal selected from niobium (Nb) and vanadium (V). 제1항 내지 제2항 중 어느 한 항에 있어서, (e) 상기 제1 금속 산화물막 위에 형성된 상기 제2 금속 산화물막의 적어도 일부를 제거하는 단계를 더 구비하는 것을 특징으로 하는 계면층 삭감 방법.The method according to any one of claims 1 to 2, further comprising (e) removing at least a portion of the second metal oxide film formed on the first metal oxide film. (a) 반도체위에, 계면층으로서의 반도체 산화막을 형성하는 단계;
(b) 상기 계면층위에, 제1 금속의 산화물막을 형성하는 단계;
(c) 어닐링(annealing)에 의해, 상기 계면층의 두께를 증가시키는 단계; 및
(d) 상기 제1 금속의 산화물막위에, 상기 제1 금속보다 원자가가 큰 제2 금속의 산화물막을 형성하는 단계;
를 구비하여, 상기 계면층의 두께를 감소시키는 계면층 삭감 방법을 사용하여 고유전율 게이트 절연막을 형성하는 고유전율 게이트 절연막의 형성 방법.(a) forming a semiconductor oxide film as an interface layer on the semiconductor;
(b) forming an oxide film of a first metal on the interface layer;
(c) increasing the thickness of the interfacial layer by annealing; And
(d) forming an oxide film of a second metal having a greater valence than the first metal on the oxide film of the first metal;
And forming a high dielectric constant gate insulating film using an interface layer reduction method for reducing the thickness of the interface layer. (a) 반도체위에, 계면층으로서의 반도체 산화막을 형성하는 단계;
(b) 상기 계면층위에, 제1 금속의 산화물막을 형성하는 단계;
(c) 어닐링(annealing)에 의해, 상기 계면층의 두께를 증가시키는 단계; 및
(d) 상기 제1 금속의 산화물막위에, 상기 제1 금속보다 원자가가 큰 제2 금속의 산화물막을 형성하는 단계;
를 구비하여, 상기 계면층의 두께를 감소시키는 계면층 삭감 방법에 의해 제작된 고유전율 게이트 절연막.(a) forming a semiconductor oxide film as an interface layer on the semiconductor;
(b) forming an oxide film of a first metal on the interface layer;
(c) increasing the thickness of the interfacial layer by annealing; And
(d) forming an oxide film of a second metal having a greater valence than the first metal on the oxide film of the first metal;
And a high dielectric constant gate insulating film prepared by an interface layer reduction method for reducing the thickness of the interface layer. 제1 금속 산화물과, 상기 제1 금속 산화물로 확산된 제1 금속보다 큰 원자가를 갖는 적어도 1종류의 금속인 제2 금속을 포함하는 고유전율 게이트 산화막에 있어서,
상기 제1 금속 산화물은, 상기 고유전율 게이트 산화막의 아래에 있는 반도체층 또는 상기 반도체층과 상기 고유전율 게이트 산화막의 사이에 마련되어진 층의 산화물보다 큰 유전율을 갖는 적어도 1종류의 금속의 산화물인 것을 특징으로 하는 고유전율 게이트 산화막.A high dielectric constant gate oxide film comprising a first metal oxide and a second metal which is at least one kind of metal having a valence greater than that of the first metal diffused into the first metal oxide,
The first metal oxide is an oxide of at least one type of metal having a dielectric constant greater than that of a semiconductor layer under the high dielectric constant gate oxide film or a layer provided between the semiconductor layer and the high dielectric constant gate oxide film. A high dielectric constant gate oxide film. 제12항에 있어서, 상기 반도체층의 형성 재료는 실리콘이며, 제1 금속 산화물은 산화 실리콘보다 큰 유전율을 갖는 적어도 1종류의 금속의 산화물인 것을 특징으로 하는 고유전율 게이트 산화막.The high dielectric constant gate oxide film according to claim 12, wherein the semiconductor material is formed of silicon, and the first metal oxide is an oxide of at least one metal having a dielectric constant greater than that of silicon oxide. 제12항 또는 제13항에 있어서, 상기 제1 금속은 하프늄(Hf), 지르코늄(Zr) 및 티탄(Ti)으로부터 선택된 적어도 1종류의 금속이며, 상기 제2 금속은 탄탈(Ta), 니오브(Nb) 및 바나듐(V)으로부터 선택된 적어도 1종류의 금속인 것을 특징으로 하는 고유전율 게이트 산화막.The method of claim 12 or 13, wherein the first metal is at least one metal selected from hafnium (Hf), zirconium (Zr) and titanium (Ti), and the second metal is tantalum (Ta), niobium ( At least one metal selected from Nb) and vanadium (V). 제14항에 있어서, 상기 제1 금속 산화물은 산화 하프늄이며, 상기 제2 금속은 탄탈인 것을 특징으로 하는 고유전율 게이트 산화막. 15. The high-k gate oxide film of claim 14, wherein the first metal oxide is hafnium oxide, and the second metal is tantalum. 제15항에 있어서, 상기 탄탈의 농도는 1020~1022개/cm3인 것을 특징으로 하는 고유전율 게이트 산화막.The high dielectric constant gate oxide film of claim 15, wherein the concentration of tantalum is 10 20 to 10 22 atoms / cm 3 . (a) 반도체위에, 계면층으로서의 반도체 산화막을 형성하는 단계;
(b) 상기 계면층위에, 제1 금속의 산화물막을 형성하는 단계;
(c) 어닐링(annealing)에 의해, 상기 계면층의 두께를 증가시키는 단계; 및
(d) 상기 제1 금속의 산화물막위에, 상기 제1 금속보다 원자가가 큰 제2 금속의 산화물막을 형성하는 단계;
를 구비하여 상기 계면층의 두께를 감소시키는 계면층 삭감 방법에 의해 제작된 고유전율 게이트 절연막을 갖는 트랜지스터.(a) forming a semiconductor oxide film as an interface layer on the semiconductor;
(b) forming an oxide film of a first metal on the interface layer;
(c) increasing the thickness of the interfacial layer by annealing; And
(d) forming an oxide film of a second metal having a greater valence than the first metal on the oxide film of the first metal;
And a high dielectric constant gate insulating film fabricated by an interface layer reduction method for reducing the thickness of the interface layer. 제1 금속 산화물, 상기 제1 금속 산화물로 확산된 제1 금속보다 큰 원자가를 갖는 적어도 1 종류의 금속인 제2 금속을 포함하는 고유전율 게이트 산화막에 있어서,
상기 제1 금속 산화물은 상기 고유전율 게이트 산화막의 아래에 있는 반도체층 또는 반도체층과 상기 고유전율 게이트 산화막의 사이에 설계된 층의 산화물보다 큰 유전율을 갖는 적어도 1종류의 금속의 산화물인 것을 특징으로 하는 고유전율 게이트 산화막.




A high dielectric constant gate oxide film comprising a first metal oxide and a second metal which is at least one kind of metal having a valence greater than that of the first metal diffused into the first metal oxide,
Wherein the first metal oxide is an oxide of at least one type of metal having a dielectric constant greater than that of the semiconductor layer under the high dielectric constant gate oxide film or a layer designed between the semiconductor layer and the high dielectric constant gate oxide film. High dielectric constant gate oxide film.




KR1020127015820A 2009-12-01 2010-11-30 Interface layer reduction method, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film KR101345390B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009273000 2009-12-01
JPJP-P-2009-273000 2009-12-01
PCT/JP2010/071353 WO2011068096A1 (en) 2009-12-01 2010-11-30 Interface layer reduction method, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film

Publications (2)

Publication Number Publication Date
KR20120095999A KR20120095999A (en) 2012-08-29
KR101345390B1 true KR101345390B1 (en) 2013-12-24

Family

ID=44114943

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020127015820A KR101345390B1 (en) 2009-12-01 2010-11-30 Interface layer reduction method, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film

Country Status (4)

Country Link
US (2) US8575038B2 (en)
JP (1) JP5757628B2 (en)
KR (1) KR101345390B1 (en)
WO (1) WO2011068096A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101345390B1 (en) * 2009-12-01 2013-12-24 도쿠리츠교세이호징 붓시쯔 자이료 겐큐키코 Interface layer reduction method, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film
KR102099881B1 (en) 2013-09-03 2020-05-15 삼성전자 주식회사 Semiconductor device and method of fabricating the same
US9515186B2 (en) 2014-01-23 2016-12-06 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR102295641B1 (en) 2015-03-02 2021-08-27 삼성전자주식회사 Semiconductor device and manufacturing the same
KR102342850B1 (en) 2015-04-17 2021-12-23 삼성전자주식회사 Curing method of dielectric layer for manufacturing semiconductor device
KR102238444B1 (en) 2017-03-13 2021-04-09 삼성전자주식회사 Semiconductor device and method for fabricating the same
JP2024051448A (en) * 2022-09-30 2024-04-11 東京エレクトロン株式会社 Manufacturing method for semiconductor device, and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003204058A (en) 2002-01-10 2003-07-18 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2007173796A (en) * 2005-12-19 2007-07-05 Internatl Business Mach Corp <Ibm> SEMICONDUCTOR STRUCTURE USING METAL OXYNITRIDE ACTING AS pFET MATERIAL AND ITS MANUFACTURING METHOD

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6057584A (en) * 1997-12-19 2000-05-02 Advanced Micro Devices, Inc. Semiconductor device having a tri-layer gate insulating dielectric
US6727148B1 (en) * 1998-06-30 2004-04-27 Lam Research Corporation ULSI MOS with high dielectric constant gate insulator
US6756320B2 (en) * 2002-01-18 2004-06-29 Freescale Semiconductor, Inc. Method of forming article comprising an oxide layer on a GaAs-based semiconductor structure
US6617209B1 (en) * 2002-02-22 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6696327B1 (en) * 2003-03-18 2004-02-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
KR100568448B1 (en) * 2004-04-19 2006-04-07 삼성전자주식회사 method of fabricating high-k dielectric layer having reduced impurity
KR101345390B1 (en) * 2009-12-01 2013-12-24 도쿠리츠교세이호징 붓시쯔 자이료 겐큐키코 Interface layer reduction method, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003204058A (en) 2002-01-10 2003-07-18 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2007173796A (en) * 2005-12-19 2007-07-05 Internatl Business Mach Corp <Ibm> SEMICONDUCTOR STRUCTURE USING METAL OXYNITRIDE ACTING AS pFET MATERIAL AND ITS MANUFACTURING METHOD

Also Published As

Publication number Publication date
US20120280372A1 (en) 2012-11-08
US20140061872A1 (en) 2014-03-06
US8759925B2 (en) 2014-06-24
JPWO2011068096A1 (en) 2013-04-18
WO2011068096A1 (en) 2011-06-09
JP5757628B2 (en) 2015-07-29
KR20120095999A (en) 2012-08-29
US8575038B2 (en) 2013-11-05

Similar Documents

Publication Publication Date Title
KR101345390B1 (en) Interface layer reduction method, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film
KR102402105B1 (en) Semiconductor device
TWI278039B (en) Semiconductor device for high-k gate dielectrics and fabrication method thereof
US7824990B2 (en) Multi-metal-oxide high-K gate dielectrics
US20090108294A1 (en) Scalable high-k dielectric gate stack
TWI453820B (en) Semiconductor device and the fabrication method thereof
TWI553906B (en) Hybrid gate last integration scheme for multi-layer high-k gate stacks
US7700438B2 (en) MOS device with nano-crystal gate structure
US9023708B2 (en) Method of forming semiconductor device
US8802527B1 (en) Gate electrode optimized for low voltage operation
US9029959B2 (en) Composite high-k gate dielectric stack for reducing gate leakage
JP4181195B2 (en) Insulating film and semiconductor device using the same
US20100320520A1 (en) Dielectric, capacitor using dielectric, semiconductor device using dielectric, and manufacturing method of dielectric
JP2004214673A (en) Using of indium for fixing work function of p-type doped polysilicon or polysilicon germanium
JP2005079512A (en) Mos type semiconductor device and its manufacturing method
JP4309320B2 (en) Semiconductor device and manufacturing method thereof
US9786762B2 (en) Gate electrode of a semiconductor device, and method for producing same
Choi et al. Aggressively scaled ultra thin undoped HfO/sub 2/gate dielectric (EOT< 0.7 nm) with TaN gate electrode using engineered interface layer
KR100843223B1 (en) Semiconductor device having different gate structures according to its channel type and method for manufacturing the same
US9159779B2 (en) Method of fabricating semiconductor device
US11043573B2 (en) Method of fabricating tantalum nitride barrier layer and semiconductor device thereof
TW201546906A (en) Semiconductor device and method for fabricating the same
JP5057957B2 (en) Semiconductor device and manufacturing method thereof
TWI580045B (en) Semiconductor structure and method for forming the same
JP2000243961A (en) Method of forming gate oxide film of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee