JP5057957B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a high dielectric constant insulating layer and a manufacturing method thereof.

Miniaturization of a scaled CMOS LSI element requires a thin gate insulating layer. The gate insulating layer in the next generation MOS field effect transistor of the generation below 0.1 μm is required to have a film thickness of 1.5 nm or less in terms of SiO ₂ . However, in this film thickness region, the leakage current due to the direct tunnel current cannot be suppressed, and this leads to an increase in power consumption. Therefore, SiO ₂ can no longer be applied as the gate insulating layer. Therefore, as a substitute material, research and development of a material having a high dielectric constant and capable of suppressing a leak current by increasing the film thickness, that is, a high-k material, is being actively conducted all over the world.

Many high-k materials have been proposed so far, but in recent years, for example, HfO ₂ , HfSiO layers, or HfSiON layers to which nitrogen is added are practically used because of their high dielectric constant and thermal stability. It is promising for the realization. In particular, with respect to the HfSiON layer, crystallization which causes leakage current or impurity diffusion is not induced even after a heat treatment process for activation annealing of polycrystalline silicon used as a gate electrode, and the equivalent SiO ₂ thickness is obtained. 0.6 nm is achieved. (See Non-Patent Document 1)

However, in the structure in the case where an Hf-based material such as HfO ₂ , HfSiO, or HfSiON layer is used as the gate insulating layer, the gate is formed at the interface between the silicon substrate and the gate insulating layer by heat treatment in the semiconductor device manufacturing process. A low dielectric constant layer is formed which is considered to be SiO ₂ produced by the reaction between the insulating layer and the silicon of the substrate.

  Further, silicon in the silicon substrate diffuses in the gate insulating layer through heat treatment in the manufacturing process of the semiconductor device and precipitates on the surface of the insulating layer to form silicide, thereby forming a low dielectric constant layer.

The existence of these low dielectric constant layers is no longer critical in the generation where a further thinning of the gate insulating layer is required, such as 0.5 nm or less in terms of SiO ₂ .

  In addition, the problem is not only the presence of the low dielectric constant interface layer, but the MISFET using such a gate insulating layer has a problem that the threshold voltage to turn on is shifted from an ideal value. There is a problem that the on-current cannot be secured in a low power supply voltage state. As a factor of this threshold shift, hafnium is bonded to silicon constituting the polycrystalline silicon or Si diffused in the substrate at the interface of the polycrystalline silicon electrode / insulating layer, and this Hf-Si bond level is Fermi pinning. The model that brings

These low dielectric constant layer formation and threshold shift problems are not limited to gate insulating layers using Hf-based materials, but can react with the metal on which the silicon of the substrate can diffuse or with polycrystalline silicon as the electrode. The same occurs when a high dielectric constant gate insulating layer using a metal, such as an oxide of Zr, Ti, or Ta, is applied.
IEDM Tech. Dig. (2003) 107.

  The present invention has been made to solve the above problems, and in a high dielectric constant insulating layer applied to a semiconductor device, a reaction between the insulating layer constituent components and silicon is suppressed, and a low dielectric constant layer is formed on the surface of the insulating layer. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the formation of the substrate and suppress the threshold shift.

  As a result of intensive studies to overcome the above problems, the present inventors have focused on the point that each of the above problems is caused by a reaction between an element constituting an insulating layer and silicon constituting a silicon substrate or an electrode. The present inventors have found that a structure provided with a barrier layer made of a material that suppresses interface reaction at the interface above or below the insulating layer and diffusion of silicon from the substrate is effective.

In other words, at the interface above the high dielectric constant insulating layer, there is no silicon diffusion and silicide formation reaction with silicon, and no low dielectric constant interface layer is generated, and the dielectric constant is sufficiently higher than that of SiO _2. A structure in which an insulating layer is provided as a barrier layer is provided.

The present invention (Claim 1) includes a silicon substrate,
An insulating layer of an oxide of at least one element selected from at least Hf, Zr, Ti, Ta formed on the silicon substrate;
A polysilicon electrode formed on the insulating layer;
A semiconductor device comprising: a LaAlO ₃ layer having a thickness of 0.5 nm to 2 nm formed at an interface between the insulating layer and the electrode.

The present invention (Claim 2) is the semiconductor device according to Claim 1, wherein the LaAlO ₃ layer is an amorphous layer.

The present invention (Claim 3 ) is characterized in that the LaAlO ₃ layer is provided at the interface between the insulating layer and the polysilicon electrode in contact with the insulating layer and the polysilicon electrode. A semiconductor device according to claim 1 .

The present invention (claim 4), wherein the insulating layer is a gate insulating layer, to an item to any one of claims 1 to claim 3, characterized in that it comprises a MISFET the polysilicon electrode is a gate electrode It is a semiconductor device of description.

Further, the present invention (Claim 5 ) includes an insulating layer forming step of forming an insulating layer of an oxide of at least one element selected from Hf, Zr, Ti, and Ta on a silicon substrate;
An electrode forming step of forming a polysilicon electrode on the insulating layer;
Performing a metal oxide forming step of forming a LaAlO ₃ layer having a thickness of 0.5 nm to 2 nm on the surface of the insulating layer after the insulating layer forming step and before the polysilicon electrode forming step. A method for manufacturing a semiconductor device.

The present invention (Claim 6 ) includes an insulating layer forming step of forming an insulating layer of an oxide of at least one element selected from Hf, Zr, Ti, and Ta on a silicon substrate;
An electrode forming step of forming a polysilicon electrode on the insulating layer, and a thickness of one atomic layer or less of metal La and metal Al on the surface of the insulating layer after the insulating layer forming step and before the polysilicon electrode forming step. A metal oxide forming step of depositing a LaAlO ₃ layer having a thickness of 0.5 nm to 2 nm and oxidizing the metal layer in an oxidizing atmosphere on the metal layer after forming the metal layer deposited in A method for manufacturing a semiconductor device is provided.

  According to the present invention, in a high dielectric constant insulating layer applied to a semiconductor device, the reaction between the insulating layer constituents and silicon is suppressed, the formation of a low dielectric constant layer on the surface of the insulating layer is suppressed, and the threshold is reduced. A semiconductor device capable of suppressing a value shift and a manufacturing method thereof can be provided.

  The present invention is described in detail below.

  First, the characteristics of a metal oxide layer containing La and Al formed on a silicon substrate (hereinafter, the metal oxide layer containing La and Al is referred to as “LaAlO layer”), interface reaction and silicon diffusion suppressing effect The results of evaluation with a focus on are described.

FIG. 1 shows that a LaAlO layer is deposited on a n-type silicon substrate from which a natural oxide film has been removed by HF treatment by a laser ablation method using a LaAlO ₃ single crystal substrate as a target, and then introduced into a rapid thermal annealing (RTA) apparatus. 2 is a cross-sectional TEM image of a sample subjected to RTA treatment at 1000 ° C. for 30 seconds in a nitrogen atmosphere at normal pressure. As seen in FIG. 1, the interface between the silicon substrate and the LaAlO layer is in direct contact, no transition layer is present, and no low dielectric constant interface layer is generated. The LaAlO layer was an amorphous layer.

  FIG. 2 shows Si2s, Al2p and La4d XPS spectra of the LaAlO layer. Regarding the Si2s spectrum, the peak of silicon is only due to the metal of the substrate, and no peak due to the oxide state is observed. This result is consistent with the result that the interface layer was not generated in the TEM image. Furthermore, in the Al2p and La4d XPS spectra, both peaks due to oxides are not observed, and no peaks due to the formation of silicide are observed.

These results indicate that even when heat treatment at 1000 ° C. is performed, the LaAlO layer does not generate oxide or silicide due to reaction of the substrate with silicon.
These results are similarly obtained at the interface between the LaAlO layer and the electrode when the LaAlO layer is laminated on the polycrystalline silicon electrode.

  Next, the results of evaluating the characteristics of the LaAlO layer when this LaAlO layer is formed at the interface between the silicon substrate and the gate insulating layer of Hf oxide will be described.

After a 2 nm LaAlO layer is deposited on a silicon substrate by the similar method, which in the HfO ₂ deposited by laser ablation in which the HfO ₂ as a target continuously, 1000 ° C., the RTA process for 30 seconds gave.

FIG. 3 shows the result of analyzing the depth direction of oxygen and silicon by secondary ion mass spectrometry (SIMS) of this sample (FIG. 3B), and the same conditions except that no LaAlO layer is formed for comparison. FIG. 3A shows the result of SIMS analysis of the HfO ₂ single layer film produced in the same manner.

As is clear from FIG. 3, when the LaAlO layer is present at the interface between the silicon substrate and the HfO ₂ layer (FIG. 3B), the diffusion of silicon from the silicon substrate into the HfO ₂ layer or on the surface, In addition, the generation of the interface layer at the interface between the silicon substrate and the LaAlO layer is not observed, but in the case of the HfO ₂ single layer without providing the LaAlO layer (FIG. 3A), the silicon from the silicon substrate diffuses in the layer. It can be seen that it is deposited on the surface of the HfO ₂ layer and that an interface layer is formed at the interface between the silicon substrate and the HfO ₂ layer.

The result of the comparison between FIG. 3A and FIG. 3B shows that the barrier property of the LaAlO layer against the diffusion of silicon in the HfO ₂ insulating layer and the generation of the interface layer is tremendous.

  Next, in order to evaluate the film thickness suitable for expressing the barrier property against the silicon diffusion of the LaAlO layer, the film thickness of LaAlO was changed to 0.3 nm, 0.5 nm, 0.7 nm, and 0.9 nm, FIG. 4 shows the results of evaluating the peak intensity of silicon deposited on the surface by X-ray photoelectron spectroscopy after performing RTA treatment at 1000 ° C. for 30 seconds.

  As is apparent from FIG. 4, the Si peak intensity is remarkably reduced with a film thickness of 0.5 nm as a boundary, and is hardly detected at 0.5 nm or more. That is, it can be seen that a film thickness of 0.5 nm or more is desirable in order to obtain a sufficient barrier property for silicon diffusion in the LaAlO layer.

Next, in order to evaluate the heat resistance against crystallization of the LaAlO layer (amorphous layer), the thickness of LaAlO was changed to 1.5 nm, 2.0 nm, and 2.5 nm, and RTA treatment at 1000 ° C. for 30 seconds was performed. FIG. 5 shows the results of In-plane X-ray diffraction measurement, focusing on the LaAlO ₃ (600) peak.

From FIG. 5, the diffraction peak of LaAlO ₃ (600) is not observed at the film thicknesses of 1.5 nm and 2.0 nm, whereas a very weak peak is observed at the film thickness of 2.5 nm. This is because LaAlO does not crystallize even when RTA treatment is performed at 1000 ° C. for 30 seconds at a film thickness of 2.0 nm or less, whereas crystallization is induced by the same process at 2.5 nm. Show. For example, in the crystallization in the gate insulating layer, the crystal grain boundary becomes a diffusion path of impurities such as boron and arsenic introduced to activate the polycrystalline silicon as an electrode, and these impurities diffuse to the channel. This is a phenomenon to be suppressed because it causes threshold fluctuations and a crystal grain boundary can form a trap level. Considering this, it can be said that the LaAlO layer as the barrier layer of the gate insulating layer is desirably used with a film thickness of 2 nm or less so that crystallization is not induced even when the RTA treatment is performed at 1000 ° C. for 30 seconds.

  In consideration of the above-described barrier property against silicon diffusion and heat resistance against crystallization, the LaAlO barrier layer is preferably an amorphous layer having a thickness of 0.5 nm to 2 nm.

  The phenomenon that silicon in the silicon substrate diffuses and precipitates on the surface of the insulating layer, as observed in FIG. 3B, is the same when an oxide of Zr, Ti, Ta is applied as the high dielectric constant insulating layer. Observed at. That is, when these insulating layers are simply used as the gate insulating layer, silicon oxide or the like is used at the interface between the silicon substrate and the insulating layer, and at the interface between the insulating layer and the electrode, silicon oxide is used on the surface in addition to silicon oxide. May form a low dielectric constant interface layer or shift the threshold value. However, even in these insulating layers, the presence of the LaAlO layer suppresses the reaction between the silicon substrate and the constituent components of the insulating layer and the diffusion of silicon in the insulating layer, which in turn reduces the occurrence of low dielectric constant interface layers and threshold shifts. Can be suppressed.

  Since oxides of Hf, Zr, Ti, and Ta have a high dielectric constant and excellent heat resistance, they are less deteriorated even after a high temperature process, and are suitable as an insulating layer of a semiconductor device such as a gate insulating layer of MISFET. . On the other hand, metal oxides containing La and Al not only have the characteristics suitable as a barrier material as described above, but also have a high dielectric constant, so that the silicon oxide in the high dielectric constant gate insulating film is made thinner. Very suitable for use as a barrier material at the interface. Therefore, a highly reliable semiconductor device can be obtained by laminating both.

Specifically, for example, a composite oxide containing La and Al represented by LaAlO ₃ is used for the LaAlO layer, but a material that hardly generates a low dielectric constant reaction layer at the interface with the substrate or the electrode, for example, La ₂ O ₃ and Al ₂ O ₃ may be partially included.

  In the above example, a series of film formation is performed by the laser ablation method, but the present invention is not limited to film formation by this method, and a method such as a CVD method, an MBE method, a vapor deposition method, or an ALD method is used. Also good.

In the above example, the LaAlO layer is an amorphous layer. However, on the silicon (100) substrate, the mismatch between silicon (100) and LaAlO ₃ is as small as 1.1%. LaAlO ₃ crystal layer, also LaAlO ₃ formed on, since it is possible to epitaxially grow on a silicon substrate, and more preferably, grain boundaries may be used epitaxial single crystal layers of hard LaAlO ₃ occurs . Since this LaAlO ₃ crystal has a perovskite structure and a very dense and stable layer is formed, it is also effective as a barrier material.

  The semiconductor device according to the present invention can be applied to a gate insulating layer and gate electrode structure in a MISFET, a gate electrode and insulating layer structure of a nonvolatile memory element, a capacitor electrode and insulating layer structure of a capacitor element, etc. It is not limited.

  FIG. 6 is a cross-sectional view showing an embodiment of a semiconductor device having a MISFET. An element isolation layer 102 made of a silicon oxide layer is formed on the surface of the n-type silicon substrate 101. A source / drain diffusion layer 105 is formed in the element region defined by the element isolation layer 102. On the n-type silicon substrate 101 between the source / drain diffusion layers 105, a gate insulating layer 103 having a thickness of about 2 nm to 5 nm and a gate electrode 104 which is a polysilicon layer provided on the gate insulating layer 103 are formed. Has been.

  A substrate-gate insulating layer interface barrier layer 1011 having a thickness of about 0.5 nm to 2 nm is formed at the interface between the gate insulating layer 103 and the silicon substrate 101, and a thickness of about 0.03 nm is formed at the interface between the gate insulating layer 103 and the gate electrode 104. A gate insulating layer-gate electrode interface barrier layer 1012 having a thickness of 5 nm to 2 nm is formed. The metal oxide layer containing La and Al according to the present invention is applied to the substrate-gate insulating layer interface barrier layer 1011 and the gate insulating layer-gate electrode interface barrier layer 1012.

  A gate sidewall 107 of a silicon nitride layer is formed on the sidewalls of the substrate-gate insulating layer interface barrier layer 1011, the gate insulating layer 103, the gate electrode 104, and the gate insulating layer-gate electrode interface barrier layer 1012. Thus, a MISFET having the gate electrode 104 and the source / drain diffusion layer 105 is configured.

  On the n-type silicon substrate 101 on which such a MISFET is formed, an interlayer insulating layer 108 made of a silicon oxide layer is formed. A contact hole reaching the source / drain diffusion layer 105 is opened in the interlayer insulating layer 108. An aluminum metal wiring 109 that is electrically connected to the source / drain diffusion layer 105 is buried in the contact hole.

  FIG. 6 shows an example in which a substrate-gate insulating layer interface barrier layer 1011 and a gate insulating layer-gate electrode interface barrier layer 1012 are provided on both upper and lower interfaces of the gate insulating layer 103. Even if at least one of the gate insulating layer interface barrier layer 1011 and the gate insulating layer-gate electrode interface barrier layer 1012 is present, the effect of the present invention is exhibited. Desirably, at least the substrate-gate insulating layer interface barrier layer 1011 is provided, and more desirably both the substrate-gate insulating layer interface barrier layer 1011 and the gate insulating layer-gate electrode interface barrier layer 1012 are provided. This is desirable for enhancing the effect of the present invention.

_HfO as a gate insulating layer _{103, HfO 2, HfSiO 4,} HfSiON, ZrO 2, ZrSiO 4, TiO 2, TaO 5, Ta 2 O 5, Sr 2 Ta 2 O 7, SrTiO 3, BaTiO 3, CaTiO 3, Ba _{x Sr 1-x TiO 3,} PbTiO 3, PbZr x Ti 1-x O 3, SrBi 2 Ta 2 O 9, SrBi 2 (Ta x Nb 1-x) 2 O 9, CeO 2, HfAlO, HfAlON or Bi ₂ Examples include (Ta _x Nb _1-x ) O ₆ .

  The gate electrode 106 may be a metal gate electrode such as polycrystalline SiGe, TiN, Mo, Au, Al, Pt, Ag, or W.

  Next, an embodiment of a method for manufacturing a semiconductor device having a MISFET shown in FIG. 6 will be described with reference to FIGS. 7 and 8 are schematic cross-sectional views showing an embodiment of a manufacturing process of a MISFET.

Here, a manufacturing method will be described by taking, as an example, a MISFET in which a LaAlO layer is applied to upper and lower interface barrier layers with respect to an HfO ₂ gate insulating layer.

  First, as shown in FIG. 7A, an element isolation region 102 is formed on a p-type silicon substrate 101 by a silicon thermal oxide film. In the figure, the element isolation region 102 protrudes above the substrate surface, but the upper surface of the element separation region 102 may be the same height as the substrate surface.

Next, as shown in FIG. 7B, a metal oxide forming step (A) in which a barrier layer 1011 of a LaAlO layer is formed to 1.5 nm on the silicon substrate surface, and an insulation in which a HfO ₂ layer to be a gate insulating layer is formed to 2 nm. A layer formation step, and further a metal oxide formation step (B) in which a barrier layer 1012 of a LaAlO layer is again formed to 1.5 nm are performed. Details of the metal oxide forming steps (A) and (B) will be described later. Only one or both of the metal oxide formation steps (A) and (B) may be performed depending on the desired formation position of the barrier layer.

  Next, as shown in FIG. 7C, a polysilicon film 104 is deposited on the entire surface by chemical vapor deposition, and then the polysilicon film is patterned to form the gate electrode 104 as shown in FIG. An electrode forming step of forming is performed.

  Next, as shown in FIG. 8E, a sidewall insulating film 107 made of, for example, a silicon nitride film is formed on the sidewall of the gate portion.

  Next, as shown in FIG. 8F, for example, P is ion-implanted on the entire surface, and then heat treatment is performed, and P is diffused into the silicon substrate 101 to be activated, thereby forming a source region and a drain region 105.

  The subsequent steps are in accordance with a normal MIS type transistor manufacturing process. A silicon oxide film serving as an interlayer insulating film is deposited on the entire surface by chemical vapor deposition, and a contact hole is opened in the interlayer insulating film 108. Subsequently, an Al film is deposited on the entire surface by sputtering, and this Al film is patterned by reactive ion etching to form an aluminum wiring 109, whereby a MIS transistor having the structure shown in FIG. 6 is completed. To do.

  The MISFET formed in this way shows a satisfactory operation even when a high temperature process of about 1000 ° C. or higher is performed, the leakage current of the gate insulating layer is suppressed to be extremely low, and no threshold shift is observed.

  Hereinafter, the metal oxide forming steps (A) and (B) will be described in more detail.

One example of the metal oxide forming process applicable as the metal oxide forming process (A) or (B) is a laser ablation method, a CVD method, an MBE, or a silicon substrate surface or an insulating film surface. An oxide containing La and Al is formed by a method such as a method, a vapor deposition method, or an ALD method. For example, in the laser ablation method, it can be formed by film formation using a LaAlO ₃ single crystal as a target.

  As another example of the metal oxide forming step applicable as the metal oxide forming step (A) or (B), one atomic layer of metal La and metal Al is formed on the silicon substrate surface or the insulating film surface or both. There is a method in which after forming a metal layer deposited with the following thickness, an oxide layer containing La and Al is deposited on the metal layer in an oxidizing atmosphere and the metal layer is oxidized. At this time, for example, a molecular beam epitaxy method (MBE method) can be applied. Specific examples thereof will be described below.

First, an n-type silicon substrate from which a natural oxide layer has been removed by HF treatment is introduced into an MBE chamber, the substrate temperature is set to 300 ° C., and La and Al are used as evaporation sources to form La and Al on the silicon substrate. Monolayer deposition is performed at a composition ratio of 1: 1. Thereafter, the substrate temperature is raised to 600 ° C., and while introducing 1 × 10 ⁻⁴ Pa of oxygen into the MBE apparatus, a 1 nm LaAlO layer is deposited using metal La and metal Al as an evaporation source.

  The XPS spectrum of the layer deposited in this way is similar to that shown in FIG. 2, and the peak of the oxide state of Si and the peak due to the metal of La and Al are not observed. Only the peak of the substrate and only the peak due to the oxide of La and Al were observed. This result shows that La and Al initially deposited in a monolayer are oxidized by subsequent processes, and there is a LaAlO layer directly on the silicon substrate and no transition layer at the interface. Yes. Further, the barrier layer produced by such a method exhibits good barrier characteristics against silicon diffusion similar to that shown in FIG. 3, and does not cause a silicide formation reaction with silicon and a low dielectric constant interface layer.

Cross-sectional TEM image of LaAlO layer. XPS spectrum of the LaAlO layer. The figure which shows the analysis result by LaIMS of a LaAlO layer and a comparative example. The figure which shows the result of having evaluated the peak intensity of the silicon deposited on the surface of a LaAlO layer by X-ray photoelectron spectroscopy. The figure which shows the result of having performed the In-plane X-ray-diffraction measurement of the LaAlO layer. Sectional drawing which shows one Embodiment of MISFET. Sectional drawing which shows one Embodiment of the manufacturing method of MISFET. Sectional drawing which shows one Embodiment of the manufacturing method of MISFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Silicon substrate 1011 ... Substrate-gate insulating layer interface barrier layer 1012 ... Gate insulating layer-gate electrode interface barrier layer 102 ... Element isolation layer 103 ... Gate insulating layer 104 ... Gate Electrode 105 ... Source / drain diffusion layer 106 ... Gate electrode 107 ... Gate side wall 108 ... Interlayer insulating layer 109 ... Aluminum wiring

Claims (6)

A silicon substrate;
An insulating layer of an oxide of at least one element selected from at least Hf, Zr, Ti, Ta formed on the silicon substrate;
A polysilicon electrode formed on the insulating layer;
A semiconductor device comprising: a LaAlO ₃ layer having a thickness of 0.5 nm or more and 2 nm or less formed at an interface between the insulating layer and the electrode. The semiconductor device according to claim 1, wherein the LaAlO ₃ layer is an amorphous layer. The LaAlO ₃ layer, said the interface between the insulating layer and the polysilicon electrode, the insulating layer and a semiconductor device according to claim 1 or claim 2 wherein, characterized in that provided in contact with the polysilicon electrode . Wherein the insulating layer is a gate insulating layer, a semiconductor device according to any one claims 1 to 3, characterized in that it comprises a MISFET the polysilicon electrode is a gate electrode. Forming an insulating layer of an oxide of at least one element selected from Hf, Zr, Ti, and Ta on a silicon substrate;
An electrode forming step of forming a polysilicon electrode on the insulating layer;
Performing a metal oxide forming step of forming a LaAlO ₃ layer having a thickness of 0.5 nm or more and 2 nm or less on the surface of the insulating layer after the insulating layer forming step and before the polysilicon electrode forming step. A method for manufacturing a semiconductor device. Forming an insulating layer of an oxide of at least one element selected from Hf, Zr, Ti, and Ta on a silicon substrate;
An electrode forming step of forming a polysilicon electrode on the insulating layer, and a thickness of one atomic layer or less of metal La and metal Al on the surface of the insulating layer after the insulating layer forming step and before the polysilicon electrode forming step. A metal oxide forming step of depositing a LaAlO ₃ layer having a thickness of 0.5 nm to 2 nm and oxidizing the metal layer in an oxidizing atmosphere on the metal layer after forming the metal layer deposited in A method for manufacturing a semiconductor device, comprising: