JPH05243252A - Maufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To stably supply an element having excellent high speed and high frequency characteristics with high yield by removing instability of growing and improving selectivity. CONSTITUTION:In order to manufacture a bipolar transistor, a base contact layer or an external base layer is formed by gradually or stepwisely varying a growing temperature by a molecular beam epitaxy method including at least organic group III material as one of material gases. Or, it is formed by gradually or stepwisely varying a molecular beam intensity of group V material. Or, a surface of a substrate during crystalline growing is irradiated with an ultraviolet ray and an intensity of the ray is gradually or stepwisely varied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor.

[0002]

2. Description of the Related Art A bipolar transistor has an excellent feature that it has a larger current driving capability than a field effect transistor. Therefore, in recent years, not only Si but also Ga
Research and development of bipolar transistors using compound semiconductors such as As have been actively conducted. In particular, a bipolar transistor using a compound semiconductor has a great advantage in that the emitter / base junction can be configured as a heterojunction and the emitter injection efficiency can be largely maintained even if the base has a high concentration.

In a compound semiconductor bipolar transistor, in order to reduce the base contact resistance, II
A method of forming a p-type high impurity concentration layer in an external base region by a molecular beam epitaxy method using an organic metal as a group I source material (hereinafter referred to as MONBE method) is disclosed in Japanese Patent Application No. 2-1.
No. 97102 and Japanese Patent Application No. 2-197103.

FIGS. 6 (a) and 6 (b) show Japanese Patent Application No. 2-197102 and Japanese Patent Application No. 2-1971, respectively.
FIG. 23 is a schematic cross-sectional view of the bipolar transistor described in No. 03 specification. P-GaA formed by MOMBE method
The s layer 11 is disposed on the surface of the external base region in FIG. 6A and functions as a base contact layer.
In FIG. 6B, the entire external base region is occupied. This reduces the base contact resistance between the base electrode and the intrinsic base layer.

In FIGS. 6A and 6B, 1 is G
a semi-insulating substrate made of aAs, 2 a collector contact layer made of n-GaAs, 3 a collector layer made of n-GaAs, 4 a base layer made of p-GaAs, 5 n
-Al _0.25 Ga _0.75 As emitter layer, 6 is n-
A graded layer made of Al _x Ga _1-x As (x: 0.25 → 0), 7 is an emitter contact layer made of n-GaAs, 11 is a base contact layer or an external base layer made of p-GaAs, and 18 is An emitter electrode made of AuGeNi, 14 a base electrode made of TiPtAu, 17 a collector electrode made of AuGeNi, 8 and 10 SiO ₂ films, and 12 an insulating region.

In manufacturing the above bipolar transistor, the p-GaAs layer 11 is formed by forming the SiO ₂ film 8
And 10 are selectively used as masks. In that case, the growth temperature and the molecular beam intensity of the group V raw material are kept constant. Moreover, the surface of the growth substrate is not irradiated with ultraviolet light.

[0007]

[Problems to be Solved by the Invention] N. Furuhata et al., Journal of Crystal Grouse (Journal of
(Crystal Growth), Volume 107, 199
On the 1st year, page 1049, the relationship between the carrier concentration of the growth layer and the growth conditions obtained when trimethylgallium (Ga (CH ₃ ) ₃ : hereinafter referred to as TMG) and solid arsenic are used as growth raw materials is reported. ing. According to it, TMG flow rate: 1 cc / min, arsenic partial pressure: 1.5 × 10 ⁻⁵ Tor
By setting the growth temperature to 530 ° C. or lower under r, the TMG flow rate: 1 cc / min, and the arsenic partial pressure below 9 × 10 ⁻⁶ Torr under the growth temperature of 550 ° C., 1
P-GaA having a carrier concentration of × 10 ²⁰ cm ^-3 or more
An s layer is obtained.

In order to reduce the base contact resistance, it is desirable to increase the carrier concentration in the external base region. For that purpose, it is necessary to set the growth temperature at the time of forming the p-GaAs layer low and set the molecular beam intensity of the group V raw material small. In addition, since a compound semiconductor bipolar transistor generally has a highly doped semiconductor layer in the intrinsic region of the transistor, a lower growth temperature is preferable in order to maintain the steepness of the impurity profile of the intrinsic region. desirable.

However, when the growth temperature is set to 500 ° C. or lower or the arsenic partial pressure is set to 1 × 10 ⁻⁷ Torr or lower to form the p-GaAs layer, the substrate temperature becomes unstable. In addition, the degree of vacuum of the background in the growth chamber decreases, which makes it difficult to control the arsenic partial pressure, and the growth itself often becomes unstable. As a result, not only the growth rate and the reproducibility of the impurity concentration are lowered, but also the surface may be severely roughened, and in some cases, the growth layer may be polycrystallized. Further, when the selective growth is performed, it becomes a factor that the selectivity with respect to the mask such as SiO ₂ is deteriorated. Moreover, under the above-mentioned growth conditions, it is very difficult to precisely control the growth parameters such as the substrate temperature and the arsenic partial pressure, so that there are large variations among the wafers. Conventionally, this step of forming a high-concentration p-GaAs layer on the whole or a part of the external base region has been a major obstacle to improving the yield of transistors.

The present invention solves such a problem and solves the problem of 1 ×
When forming a p-type high impurity concentration layer of 10 ²⁰ cm ^-3 or more in the external base region, the growth instability is removed and the selectivity is improved, whereby the base contact resistance is reduced and the high speed and high frequency characteristics are excellent. Another object of the present invention is to provide a method of manufacturing a bipolar transistor capable of stably supplying a stable device with good yield.

[0011]

A method of manufacturing a bipolar transistor according to a first aspect of the present invention comprises a step of forming a laminated structure including at least a collector layer, a base layer and an emitter layer on a semi-insulating substrate, and at least a raw material gas. One of them is to form at least a part of the extrinsic base region by gradually or stepwise changing the growth temperature by a molecular beam epitaxy method containing an organic group III raw material.

A method of manufacturing a bipolar transistor according to a second aspect of the present invention comprises a step of forming a laminated structure including at least a collector layer, a base layer and an emitter layer on a semi-insulating substrate, and an organic group III gas containing at least one source gas. A step of gradually or stepwise changing the molecular beam intensity of the group V raw material by a molecular beam epitaxy method containing the raw material to form at least a part of the external base region.

A method of manufacturing a bipolar transistor according to a third aspect of the present invention comprises a step of forming a laminated structure including at least a collector layer, a base layer and an emitter layer on a semi-insulating substrate, and an organic group III gas as at least one of source gases. A step of forming at least a part of the external base region by irradiating the surface of the substrate during crystal growth with ultraviolet rays and gradually or stepwise changing the light intensity of the ultraviolet rays by a molecular beam epitaxy method containing raw materials. It is characterized by including and.

[0014]

When a highly doped semiconductor layer is formed by the MOMBE method or the like, it is important to obtain a good single crystal thin film, especially to suppress three-dimensional growth and polycrystallization in the initial stage of crystal growth. That's the point. For that purpose, it is necessary to supply the group V raw material and the group III raw material to the surface of the substrate in a well-balanced manner and sufficiently activate the surface migration of the adsorbed molecules / particles so that the crystal growth proceeds in the two-dimensional growth mode. Is. There are two methods of activation, thermal excitation and photoexcitation. The former is achieved by raising the substrate temperature, and the latter is achieved by irradiating the substrate surface with ultraviolet rays. The effect of the ultraviolet irradiation is, for example, M. Kumagawa et al.
wa et al. ), Japanese Journal of Applied Physics
urnal of Applied Physic
s), Vol. 7, 1968, pp. 1332, and Earl.
G. Freezer et al. (RG Frieser et
al. ), Journal of Electrochemical Society
chemical Society), Volume 115, 196
8 years, reported on page 401.

Further, in order to prevent three-dimensional growth due to multi-layer adsorption of group III raw materials, and a large deviation from the stoichiometric composition and surface roughness caused by lack of group V raw materials, V
It is effective to make the / III ratio higher than a predetermined value, that is, increase the arsenic partial pressure to some extent.

That is, as described above, in order to stably form a high impurity concentration by the MOMBE method, (1) the growth temperature is increased, (2) the molecular beam intensity of the group V raw material is increased, ( 3) Three methods of irradiating the surface of the growth substrate with ultraviolet rays are effective. However, the methods (1) and (2) both cause a decrease in carrier concentration in the growth layer, and are therefore not desirable from the viewpoint of further increasing the concentration of the external base region and further reducing the base contact resistance. .. Similarly, the method (3) is also
The action of decreasing the carrier density of the growth layer is caused by Jun-ichi Nishiwa.
hizawa et al. ), Journal of Electrochemical Society (Journal o
f Electrochemical Societ
y), 132, 1985, p. 1197.

In the present invention, when the high impurity concentration layer is formed in the external base region, the growth condition is changed midway to solve the above-mentioned problems. As concrete measures, three methods of (1) changing the growth temperature, (2) changing the molecular beam intensity of the group V raw material, and (3) changing the light intensity of ultraviolet rays are used. Regarding the way of changing, it is necessary to obtain stable two-dimensional growth in the initial stage of growth and to obtain a high concentration layer in the final stage of growth, so in (1), high → low, It is general that (2) is large → small, and (3) is large → small. In that case, the same effect can be obtained by gradually changing the steps between the initial process and the terminal process or stepwise. Further, it is not always necessary to make the change in one direction as described above, and it is possible to make various changes on the way. However, from the viewpoint of further reducing the sheet resistance of the external base region, it is desirable to make the above change while considering that the high impurity concentration layer occupies as much of the growth layer as possible.

In the base resistance of the bipolar transistor of the compound semiconductor, the proportion of the base contact resistance is usually very large. Therefore, by using the method of the present invention, the high concentration external base region can be selected with good selectivity.
It is possible to stably form a bipolar transistor having a small base resistance and to manufacture it with high yield.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

4A to 4C and 5D to 5E.
FIG. 6A is a cross-sectional view of the semiconductor chip in process order, for explaining the method of manufacturing the bipolar transistor according to the first embodiment of the present invention.

First, as shown in FIG.
On the semi-insulating substrate 1 made of n-GaAs collector contact layer (3 × 10 ¹⁸ cm ⁻³ , 400 nm)
2, collector layer composed of n-GaAs layer (5 × 10 ¹⁶ c
m ⁻³ , 500 nm) 3, a base layer (2 × 10 ¹⁹ cm ⁻³ , 60 nm) made of a p-GaAs layer 4, n-Al _0.25 G
a emitter layer composed of a _0.75 As layer (3 × 10 ¹⁷ cm ⁻³ ,
_{200nm) 5, n-Al x} Ga 1-x As layer (x: 0.
25 → 0) graded layer (3 × 10 ¹⁷ c
m ⁻³ , 50 nm) 6, and an emitter contact layer (3 × 10 ¹⁸ cm ⁻³ , 100 nm) 7 made of an n-GaAs layer 7
By the BE method, the layers are sequentially formed at a growth temperature of 600 ° C. Subsequently, after sequentially forming a photoresist film 9 having a predetermined pattern and the SiO ₂ film 8 on the n-GaAs layer 7, the photoresist film 9 as a mask, the SiO ₂ film 8 is removed by reactive ion beam etching ..

Next, as shown in FIG. 4B, the n-GaAs layer 7 and the n-Al layer are formed using the photoresist film 9 as a mask.
_{The x} Ga _1-x As layer 6 is removed by reactive ion beam etching using Cl ₂ as an etching gas, and n-Al _0.25 Ga _0.75 A is similarly formed until a predetermined thickness is obtained.
The s layer 5 is etched. Then, after washing with an organic solvent to remove the photoresist film 9, SiO _{2 is formed on the} entire surface.
The film 10 is formed. Then, the unnecessary portion of the SiO ₂ film 10 is removed by reactive ion beam etching using CF ₄ as an etching gas, so that the n-GaAs layer 7, the n-Al _x Ga _{1 -x} As layer 6 and the n-GaAs layer 7 are formed. Al _0.25 G
A side wall made of the SiO ₂ film 10 is formed on the side surface of the a _0.75 As layer 5. Further, using the SiO ₂ films 8 and 10 as a mask, n-
Al _0.25 Ga _0.75 As layer 5 is removed by etching,
-Exposing the surface of the GaAs layer 4. At this time, the SiO ₂ film 1
Under 0, a protective layer made of n-Al _0.25 Ga _0.75 As layer 5 is formed.

Next, as shown in FIG. 4 (c), by the MOMBE method using TMG and solid arsenic as growth materials,
Using the SiO ₂ films 8 and 10 as a mask, p-GaAs
A p-GaAs layer 11 is selectively formed on the layer 4.

FIG. 1 shows the change over time in the substrate temperature after the start of growth in this step. Prior to the growth of the p-GaAs layer 11, the substrate temperature is adjusted to 600 while irradiating the arsenic molecular beam.
After the temperature was raised to ℃ to remove the oxide film on the surface of the p-GaAs layer 4, the TMG flow rate was 1 cc / min and the arsenic partial pressure was 1.5 ×.
Hold at 10 ^-5 Torr and increase the substrate temperature from 550 ° C to 500
Growth is performed by changing the temperature from 450 ° C to 450 ° C. The growth time at each substrate temperature is 550 ° C .: 2 minutes, 500 ° C .:
3 minutes and 450 ° C .: 6 minutes, but it took about 30 seconds for each transition after the substrate temperature change. This gives about 25
A 0 nm p-GaAs layer 11 is formed.

Subsequently, H ⁺ is injected into the other portion except the portion where the bipolar transistor is formed to form an insulating region 12, and then a photoresist film 13 having a predetermined pattern is formed, and a TiPtAu layer 14 is formed from above. Vapor deposition.

Next, as shown in FIG. 5 (d), the TiPtAu layer 14 is lifted off by cleaning with an organic solvent and removing the photoresist film 13, so that the width of the base electrode becomes a predetermined value. Then, a photoresist film having a predetermined pattern is formed. Then, the TiPtAu layer 14 is etched and removed by ion milling using the photoresist film as a mask, and the p-GaAs layers 11 and 4 are sequentially etched and removed by a mixed solution of phosphoric acid, hydrogen peroxide and water. .. Then, after cleaning with an organic solvent to remove the photoresist film, a photoresist film 16 having a predetermined pattern for forming a collector opening is formed, and using this as a mask, a mixture of phosphoric acid, hydrogen peroxide and water is used to n-. By etching and removing the GaAs layer 3, the surface of the n-GaAs layer 2 is exposed. Further, AuG which is an ohmic metal of the n-GaAs layer 2 is arranged from above.
The eNi layer 17 is deposited.

Next, as shown in FIG. 5 (e), after the photoresist film 16 is dissolved in an organic solvent and lift-off is performed, a photoresist film having a predetermined pattern for forming an emitter opening is formed, and SiO 2 is formed by buffered hydrofluoric acid. _{2 The} film 8 is removed by etching. Then, after depositing an AuGeNi layer 19 which is an ohmic metal of the n-GaAs layer 7 from above,
The photoresist film is dissolved in an organic solvent and lift-off is performed to complete a compound semiconductor bipolar transistor.

In the embodiment of the second invention, as in the embodiment of the first invention described above, FIGS. 4 (a) to 4 (c) and 5 (d) are used.
Through the steps (e) to (e), a compound semiconductor bipolar transistor is obtained. However, in this embodiment, when the p-GaAs layer 11 serving as the base contact layer is formed, the molecular beam intensity of arsenic is changed.

FIG. 2 shows the change over time in the arsenic molecular beam intensity after the start of growth in this step. Similar to the first embodiment of the invention, prior to the growth of the p-GaAs layer 11, the substrate temperature is raised to 600 ° C. while irradiating the molecular beam of arsenic to remove the oxide film on the surface of the p-GaAs layer 4. After doing
The TMG flow rate is maintained at 1 cc / min, the substrate temperature is maintained at 450 ° C., and the arsenic partial pressure is 1.5 × 10 ⁻⁵ Torr → 5 × 10 ^−6.
Growth is performed by changing it to Torr. The growth time at each arsenic partial pressure was 1.5 × 10 ⁻⁵ Torr: 3 minutes,
5 × 10 ⁻⁶ Torr: 2 minutes, but it took about 3 minutes for the transition after the change of arsenic partial pressure. As a result, the p-GaAs layer 11 having a thickness of about 250 nm is formed.

Also in the embodiment of the third invention, as in the embodiments of the first and second inventions described above, FIGS.
A bipolar transistor of a compound semiconductor is obtained through the steps of (c) and FIGS. 5 (d) to 5 (e). However, in this embodiment, the p-GaAs layer 11 serving as the base contact layer is used.
At the time of forming, the substrate surface was irradiated with ultraviolet rays to change its light intensity. A xenon-mercury lamp was used as a light source of ultraviolet rays.

FIG. 3 shows the change over time in the irradiation ultraviolet light intensity after the start of growth in this step. Similar to the first and second embodiments, prior to the growth of the p-GaAs layer 11, the substrate temperature is set to 6 while irradiating the molecular beam of arsenic.
After the temperature was raised to 00 ° C. to remove the surface oxide film on the surface of the p-GaAs layer 4, the TMG flow rate was maintained at 1 cc / min, the substrate temperature was maintained at 450 ° C., and the arsenic partial pressure was maintained at 7 × 10 ⁻⁶ Torr to obtain xenon.・ The irradiation light intensity of the mercury lamp is 0.5 W / cm ² →
The growth is performed by changing it to 0 W / cm ² (that is, no light irradiation). The growth time at each light intensity is 0.3 W /
cm ² : 4 minutes, 0 W / cm ² : 12 minutes. As a result, the p-GaAs layer 11 having a thickness of about 250 nm is formed.

The bipolar transistors obtained in the embodiments of the above-mentioned first, second and third inventions have a high-concentration base contact layer excellent in shape and electric conductivity, and have high speed and high frequency characteristics of the device. It was also very good.

Although the xenon mercury lamp is used as the ultraviolet light source in the above-described third embodiment of the invention, the invention is not limited to this, and various ultraviolet light sources such as a low pressure mercury lamp and an excimer laser can be used. The same effect can be obtained. In that case, a light source whose irradiation light has a wavelength of 400 nm or less is effective.

In the embodiments of the first, second and third inventions described above, p-GaAs is used as in FIG. 6 (a).
Although the case where the layer 11 is formed as the base contact layer has been described, the present invention is not limited to this and p-GaAs is used.
Similar to FIG. 6B, it can be applied to the case where the layer 11 is formed over the entire external base region, and the same effect can be obtained.

Further, although the emitter-up type is described in the above embodiment, the present invention is not limited to this, and the collector-up type can be similarly applied.

Furthermore, in the above-mentioned embodiments, the base layer made of p-GaAs was described, but the present invention is not limited to this, and the Al composition of the base layer made of p-AlGaAs is gradually changed. A graded base structure, an AlInAs / InGaAs or InP / InGaAs heterojunction bipolar transistor whose base layer is made of p-InGaAs, or p-AlInGaAs or p-In
The same applies to those made of GaAsP, etc.
The effect is similar.

[0037]

As described above, according to the present invention, p
The base contact layer or the external base layer made of the high impurity concentration layer can be stably formed with good selectivity without causing large surface roughness or polycrystallization.
As a result, the device yield is improved, and a bipolar transistor of a compound semiconductor having a small base resistance and excellent high-speed / high-frequency characteristics can be stably realized with good reproducibility.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a method for manufacturing a bipolar transistor of the first invention, showing a change over time in a substrate temperature when a base contact layer is formed.

FIG. 2 is a diagram for explaining the manufacturing method of the bipolar transistor of the second invention, which is a diagram showing the time change of the arsenic molecular beam intensity when the base contact layer is formed.

FIG. 3 is a diagram for explaining the method for manufacturing the bipolar transistor according to the third aspect of the invention, showing the change over time in the intensity of the ultraviolet rays with which the substrate surface is irradiated when the base contact layer is formed.

FIG. 4 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a method for manufacturing a bipolar transistor of the first, second and third inventions.

5A to 5C are cross-sectional views of a semiconductor chip in the order of steps for explaining the method for manufacturing the bipolar transistor of the first, second and third inventions.

FIG. 6 is a cross-sectional view of a semiconductor chip for explaining a bipolar transistor obtained by a conventional manufacturing method.

[Explanation of symbols]

1 semi-insulating substrate (GaAs) 2,3,7 n-GaAs layer 4,11 p-GaAs layer 5 n-Al _0.25 Ga _0.75 As layer 6 n-Al _x Ga _1-x As layer (x: 0.25 → 0) 8,10 SiO ₂ film 9, 13, 16 photoresist film 12 insulating region 14 TiPtAu layer 17, 18, 19 AuGeNi layer

Claims (3)

[Claims] 1. At least a collector layer on a semi-insulating substrate,
A step of forming a laminated structure including a base layer and an emitter layer, and a growth temperature is gradually or stepwise changed by a molecular beam epitaxy method in which at least one of source gases contains an organic group III source material, and an external base is formed. And a step of forming at least a part of the region. 2. At least a collector layer on a semi-insulating substrate,
A step of forming a laminated structure including a base layer and an emitter layer, and a molecular beam epitaxy method in which at least one of the source gases contains an organic group III source is used to gradually or stepwise change the molecular beam intensity of the group V source. And a step of forming at least a part of the external base region. 3. At least a collector layer on the semi-insulating substrate,
A step of forming a laminated structure including a base layer and an emitter layer; and a step of irradiating the surface of the substrate during crystal growth with ultraviolet rays by a molecular beam epitaxy method in which at least one source gas contains an organic group III source material, and Forming the at least a part of the external base region by gradually or stepwise changing the light intensity.