CN1610263A - Frequency dividing method with non-integer frequency dividion multiplying power and corresponding signal circuit - Google Patents
Frequency dividing method with non-integer frequency dividion multiplying power and corresponding signal circuit Download PDFInfo
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Abstract
The present invention provides method and device for frequency dividing in non-integral number multiplying power. The method includes generating with a vibrator N reference clock pulses with period T, and phase distributed homogeneously in 360 deg; triggering to generate M intermediate signals with period M*T, and phase distributed homogeneously in 360 deg; and performing logic operation with at least two of the intermediate signals to generate one output clock pulse with period of (M/N)*T, reaching the aim of non-integral number frequency dividing.
Description
Technical field
The invention provides a kind of method and interlock circuit device of frequency division, refer to a kind of method and the interlock circuit device that can realize the non-integer frequency division with the logical circuit of simplifying especially.
Background technology
In modern information-intensive society, file, data, audiovisual materials can both be propagated fast, handle and store in the mode of electronic signal, and be used for handling the electronic circuit (especially Fundamental Digital Circuit) of electronic signal data, also just become one of most important hardware foundation of information-intensive society.Known to the technology personage, in electronic circuit system, all need to integrate the different circuit building square of many functions usually and together operate; In order to coordinate the running between different circuit building squares, each circuit building square all will trigger the sequential of its preface to running with stable clock pulse.Because structure, the function of Modern Electronic Circuits System are all increasingly sophisticated, often need be integrated with the circuit building square of different time sequences in the system; Jointly, just need provide the different frequency clock pulse in (cycle) in the modern electronic circuit, trigger the circuit building square that has different sequential in the electronic circuit.For instance, in modern microprocessor system, the computing circuit of being responsible for data processing be used for the memory circuit of temporal data and may just operate on the clock pulse of different frequency, need trigger running with the clock pulse of different frequency.Be demand in response to the system of vein system for a long time, modern information dealer also actively research and development can in electronic circuit, realize the mode of different frequency clock pulse.
Please refer to Fig. 1.Fig. 1 is the function block schematic diagram of a typical phase lock circuitry 10.Phase lock circuitry 10 can produce an output clock pulse CPo1 according to a benchmark clock pulse CPr, with the preface that triggers other to the circuit building square.Be provided with detector 14, a low pass filter 16, a voltage controlled oscillator 18 and two frequency divider 12A, 12B that have integral frequency divisioil multiplying power Np, Mp respectively of a phase difference in the phase lock circuitry 10.Benchmark clock pulse CPr becomes clock pulse CPa after by frequency divider 12A frequency division, make cycle of clock pulse CPa be the clock pulse CPr cycle Np doubly; On the other hand, the output clock pulse CPo1 that is come out by voltage controlled oscillator 18 vibration will become clock pulse CPb behind the frequency division through frequency divider 12B, and make cycle of clock pulse CPb be clock pulse CPo1 Mp doubly.Detector 14 can detect clock pulse CPa, CPb between the two phase difference and transmit it to filter 16; And filter 16 will produce corresponding control voltage Vcp, adjusts the frequency of its output clock pulse CPo1 with control voltage controlled oscillator 18; Jointly, the cycle of clock pulse CPb also can change thereupon, and the phase difference between itself and the clock pulse CPa can be measured by detector 14 once again.Feedback loop between detector 14, filter 16 and the voltage controlled oscillator 18 is the result of running constantly, just can make the frequency/phase locking of clock pulse CPb consistent with clock pulse CPa, reaches phase-locked purpose.The output clock pulse CPo1 that this moment, voltage controlled oscillator 18 produced also just can be used to stably to trigger other preface and constructs square (not being shown in Fig. 1) to running.Because the running of frequency divider 12A, 12B, will make cycle of output clock pulse CPo1 be the benchmark clock pulse CPr cycle (Np/Mp) doubly.
Please refer to Fig. 2.Fig. 2 is the exemplary illustrated embodiment of voltage controlled oscillator 18 among Fig. 1.Voltage controlled oscillator 18 can be connected to each other by the differential inverter 20 of a plurality of couplings and form (being so-called ring oscillator); Illustrated embodiment among Fig. 2 is then drawn two inverters 20 as representative.In Fig. 2, first inverter 20 exportable two anti-phase each other clock pulse C2, C4 are as the input of second inverter; And anti-phase clock pulse C1, the C3 of the output of second inverter can feedback transmission to first inverter.As for the principle of voltage controlled oscillator 18 runnings, please refer to Fig. 3 (and in the lump with reference to figure 2).The schematic diagram of each clock pulse C1 to C4 waveform sequential when Fig. 3 is voltage controlled oscillator 18 runnings; The transverse axis of each waveform is the time, and the longitudinal axis is the size of amplitude of wave form.As shown in Figure 3, suppose at time point tp0, anti-phase each other clock pulse C1, C3 is upgraded to level H, reduced to level L by level H by level L respectively, after first inverter receives the level transitions of clock pulse C1, C3 at time point tp0, will be after postponing a period Td, time point tp1 with clock pulse C2, the C4 of its output anti-phase respectively be level L, level H.And clock pulse C2, C4 can postpone to cause clock pulse C1, the C3 level transitions at time point tp2 behind the period Td in the level transitions of time point tp1.So repeat down, 4 cycles of will vibrating are all the clock pulse C1 to C4 of Tp, and this period T p is 4 times of period Td.Inverter 20 in the voltage controlled oscillator 18 can receive the delay period Td that controls voltage Vcp and change its introducing, and then changes the cycle of clock pulse C1 to C4; And one of them of clock pulse C1 to C4, just can be as the output clock pulse CPo1 of voltage controlled oscillator 18.
In addition, by also finding out among Fig. 3, though clock pulse C1 to C4 has identical period T p, its phase place is all different.About this situation, please refer to Fig. 4.Fig. 4 is identical with Fig. 3, is the schematic diagram of clock pulse C1 to C4 waveform sequential; By can comparatively being clear that among Fig. 4, the phase place of four clock pulse C1 to C4 in 360 degree, has the phase difference of 90 degree (being equivalent to four/one-period Tp) with regard to mean allocation each other.In other words, the configuration of ring oscillator itself just can directly produce the clock pulse that a plurality of phase averages are allocated in one-period.
As discussed earlier, the modem electronic circuitry clock pulse that needs a plurality of different frequencies usually triggers the circuit building square of different time sequences.Yet the phase lock circuitry of discussing among Fig. 1 10 only can produce preface that an output clock pulse CPo1 triggers other to circuit; In the prior art, if need the clock pulse (frequency and non-integral multiple clock pulse especially each other) of a plurality of different frequencies, will produce required output clock pulse respectively with a plurality of phase lock circuitries.About this situation, please refer to Fig. 5.Fig. 5 is the function block schematic diagram that an existing signal circuit 22 produces two output clock pulse CPo1, CPo2.Produce two output clock pulses, signal circuit 22 also need be established an identical phase lock circuitry 24 of structure in addition and produce another output clock pulse CPo2 except producing output clock pulse CPo1 with the phase lock circuitry of discussing among Fig. 1 10.Owing to need circuit building square (as filter, voltage controlled oscillator) of matching test or the like in the phase lock circuitry, so a single phase lock circuitry will take suitable layout area; If will use a plurality of phase lock circuitries to produce a plurality of output clock pulses, the layout area of summation is just bigger.So, the production cost of electronic circuit integral body, layout area, power consumption also just can't effectively reduce.
Summary of the invention
Therefore, main purpose of the present invention, promptly be to be to propose a kind ofly can realize the method for non-integer frequency division and interlock circuit, device with the logical circuit of simplifying, with according to a single clock pulse that phase lock circuitry was generated, producing frequency in addition is non-integral multiple output clock pulse.
In the present invention, can utilize voltage controlled oscillator in the phase lock circuitry produce N cycle be similarly T, phase average is allocated in the clock pulse in one-period, utilize the different clock pulse of these phase places as the reference clock pulse again, each is used for triggering a state machine (state machine) respectively with reference to clock pulse, to produce M cycle is M*T, and phase average is allocated in intermediary's signal of M*T.In other words, with reference to first intermediary's signal that clock pulse triggered, n just is equivalent to the time difference of ((n-1)/N+ (m-1)) * T with reference to the phase place of m intermediary's signal that clock pulse triggered with respect to first.Utilize this M*N intermediary's signal, just can produce the output clock pulse of one-period at least with logical operation simply, realize the purpose of non-integer frequency division of the present invention for (M/N) * T.In other words, an output clock pulse that can produce in conjunction with phase lock circuitry itself, add that the present invention utilizes the output clock pulse at least one (M/N) * T cycle that produces in addition with reference to clock pulse, just can only produce the different output clock pulse of a plurality of frequencies (frequency and non-integral multiple output clock pulse especially each other) with a phase lock circuitry, meeting the demand of the system of vein system for a long time, be used for triggering in the electronic circuit the different difference of time sequences respectively with different output clock pulses and construct square.
In the present invention, because the application of logic circuit module that state machine, logical operation are used all belongs to the standard component of digital circuit, so it is less that the present invention is used for producing the required layout area that takies of extra output clock pulse, much smaller than setting up the required layout area of another phase lock circuitry.In other words, utilize technology of the present invention, just can produce a plurality of output clock pulses, reduce layout area, power consumption and the production cost of electronic circuit integral body with less layout area.
Description of drawings
Fig. 1 is the function block schematic diagram of a typical phase lock circuitry.
Fig. 2 is the function block schematic diagram of voltage controlled oscillator among Fig. 1.
Fig. 3, Fig. 4 are the schematic diagram of coherent signal function sequential when voltage controlled oscillator operates among Fig. 2.
Function block schematic diagram when Fig. 5 produces a plurality of output clock pulse for existing signal circuit.
Fig. 6 is the function block schematic diagram of one embodiment of the invention.
Fig. 7 is the function block schematic diagram of an embodiment of state machine among Fig. 6.
Fig. 8 is the schematic diagram of coherent signal waveform sequential when state machine operates among Fig. 7.
Fig. 9 is the schematic diagram of each coherent signal waveform sequential when circuit is realized with state machine among Fig. 7 among Fig. 6.
Figure 10 is the function block schematic diagram of logic module one embodiment among Fig. 6.
Figure 11 is the schematic diagram of coherent signal waveform sequential when logic module operates among Figure 10.
Figure 12 is the schematic diagram of another embodiment of logic module among Fig. 6.
Figure 13 is the schematic diagram of coherent signal waveform sequential when logic module operates among Figure 12.
Figure 14 is the schematic diagram of another embodiment of state machine among Fig. 6.
Figure 15 is the schematic diagram of each coherent signal waveform sequential when circuit is realized with state machine among Figure 14 among Fig. 6.
Figure 16 is the schematic diagram of another embodiment of logic module among Fig. 6.
Figure 17 is the schematic diagram of each coherent signal waveform sequential when logic module operates among Figure 16.
Figure 18 is the sequential schematic diagram of the signal that state machine is produced in another embodiment among Fig. 6.
Figure 19 is that logic module cooperates among Figure 18 signal to realize the embodiment schematic diagram of the object of the invention among Fig. 6.
Figure 20 is the schematic diagram of each coherent signal waveform sequential when logic module operates among Figure 19.
Figure 21 is the arrange in pairs or groups configuration schematic diagram of a phase lock circuitry of frequency dividing circuit of the present invention in a signal circuit.
Figure 22 is the schematic diagram of state machine one embodiment among Figure 21.
Figure 23,24 and 25 is the schematic diagram when logic module realizes the non-integer frequency division among Figure 21 under different situations.
The implication of each Reference numeral in the accompanying drawing is described as follows:
10,54 phase lock circuitry 12A-12B, 62A-62B frequency divider
14,64 detectors, 16,66 filters
18,68 voltage controlled oscillators, 20 inverters
22,32,50 signal circuits, 24 phase lock circuitries
30,52 frequency dividing circuits, 34 oscillators
36,56 state machines, 38 triggers
40,60 logic modules, 42 NAND gate
46 with the door 48 or the door
Tp, T period T k clock pulse end
CPr, Cr benchmark clock pulse Vcp control voltage
CPo1-CPo2, CKo, CKo1-CKo2, CKoA-CKoB export clock pulse
CPa, CPb, C1-C4, CK_1-CK_4, CK_n clock pulse
Tp0-tp3, ta0-ta5 time point H, L level
Td period D input
The Q output
Qa-Qg, Qc2-Qf2, CKoB1-CKoB2 signal
Q1_1-Q5_4, Q1_N-QM_N, Qm_n intermediary signal
Embodiment
In order to specify embodiments of the present invention, below will the embodiment that the present invention realizes specific frequency division multiplying power be discussed earlier, extend to general Application Example again.Please refer to Fig. 6.Fig. 6 is disposed in the signal circuit 32 to realize the function block schematic diagram of M/4 frequency division (M is an integer) for the present invention's one frequency dividing circuit 30.For realizing the purpose of frequency division, except frequency dividing circuit 30, also be provided with in the signal circuit 32 oscillator as one with reference to clock pulse circuit (can be the ring oscillator 18 among Fig. 2), to provide 4 clock pulse CK_1 to CK_4 as the reference clock pulse.The cycle of these 4 clock pulse CK_1 to CK_4 is all T, but the phase place of 4 clock pulses is different, and mean allocation is in 360 degree; In other words, concerning n clock pulse CK_n (n=1 to 4), the phase difference between itself and the 1st the clock pulse CK_1 just is equivalent to the time difference of (n-1) * T/4.
Corresponding to these 4 clock pulse CK_1 to CK_4, in frequency dividing circuit 30 of the present invention, promptly be provided with the identical state machine 36 of 4 basic circuits structure forming a trigger module, the triggering that each state machine 36 is used for receiving a clock pulse is with intermediary's signal that to produce M cycle be M*T.Picture is in Fig. 6, and first state machine 36 receives the triggering of clock pulse CK_1 to produce M the signal Q1_1 of intermediary, Q2_1 to QM_1, and second state machine 36 receives the triggering of clock pulse CK_2 to produce the signal Q1_2 of intermediary, Q2_2 to QM_2, by that analogy.This M*N intermediary signal Qm_n (m=1 is to M, n=1 to 4) transfers in the logic module 40 and carries out logical operation, at least just can produce the cycle for the clock pulse of (M/4) * T as output clock pulse CKo.
In order more to offer some clarification on situation of the invention process, below inciting somebody to action first frequency division multiplying power with 0.8 is example, specifies the circuit structure of state machine 36 among Fig. 6.Please refer to Fig. 7 (and in the lump with reference to figure 6).Fig. 7 is the schematic diagram of state machine 36 1 embodiment among Fig. 6.Realize 0.8 frequency division multiplying power, can be provided with 4 triggers 38 (can be the d type flip flop that rising edge triggers) and a NAND gate 42 in the state machine 36, to produce 5 signal Q1_n to Q5_n of intermediary (being M=5).Wherein, each trigger 38 has a clock pulse end Tk, and the triggering of the one reception clock pulse CK_n of system (n=1 to 4 similarly is the triggering that first state machine 36 is subjected to clock pulse CK_1, by that analogy, and as shown in Figure 6).In addition, each trigger 38 also has an input D, an output Q respectively.Wherein, first trigger 38 receives the signal Q5_n of intermediary for input, is output with the signal Q1_n of intermediary; Second trigger 38 receives the signal Q1_n of intermediary, the output signal Q2_n of intermediary, by that analogy, just as shown in Figure 6.At last, the 4th trigger 38 output signal Q4_n of intermediary; Each signal Q1_n to Q4_n of intermediary promptly becomes the signal Q5_n of intermediary that feeds back to first trigger 38 after a NAND gate 42 is done NAND operation.
Please refer to Fig. 8 (and in the lump with reference to figure 7).When 36 runnings of state machine among Fig. 7, the schematic diagram of its each coherent signal waveform sequential promptly is shown in Fig. 8; The transverse axis of Fig. 8 is the time, and the longitudinal axis is a size waveforms.Supposed that before time point ta0 the signal Q1_n to Q4_n of intermediary is level H, so the signal Q5_n of intermediary after the NAND operation just is maintained at level L.Arrived time point ta0, clock pulse CK_n begins to trigger each trigger 38 with rising edge.Because the intermediary's state of signal Q5_n before time point ta0 is level L, first trigger 38 will make the signal Q1_n of intermediary become level L by level H at time point ta0; Other the signal Q2_n to Q4_n of intermediary then keeps original state (level H).Because the change of the signal Q1_n of intermediary, the signal Q5_n of intermediary after the NAND operation also changes into level H after time point ta0.Arrived time point ta1, cycle is that the clock pulse CK_n of T triggers each trigger 38 with a rising edge once again, this moment first trigger 38 can because the signal Q5_n of intermediary before time point ta1 state (level H) and return back to level H, second 38 on trigger can be changed into level L according to the level L state of the signal Q1_n of intermediary before time point ta1.The level H state of the signal Q3_n to Q5_n of intermediary is then constant.
Arrived time point ta2, the 3rd trigger 38 will according to the signal Q2_n of intermediary before time point ta2 level L state and change into level L; The level of the signal Q2_n of intermediary itself then reverts to level H because of the level H of the signal Q1_n of intermediary.So develop, clock pulse Q1_n to Q4_n will respectively at change level L between time point ta0 to ta1, ta1 to ta2, ta2 to ta3, the ta3 to ta4 in regular turn into and during 1T in be maintained at this state.Arrived time point ta4, the replying state of the signal Q4_n of intermediary is to level H, and this makes that also the signal Q5_n of the intermediary change state after the NAND operation is level L.And at time point ta5, the state of each signal Q1_n to Q5_n of intermediary returns back to the state before the time point ta0 again, makes each signal Q1_n to Q5_n of intermediary periodically reappear the variation between time point ta0 to ta4 once again after time point ta5.
In other words, utilize 4 triggers 38 among Fig. 7, just can produce 5 signal Q1_n to Q5_n of intermediary (being M=5), the minimum period that each intermediary's signal waveform repeats is 5T (1T is the cycle of clock pulse CK_n), and phase difference each other then is equivalent to the time difference of 1T.Please refer to Fig. 9 (and in the lump with reference to figure 6 to Fig. 8).Fig. 9 be each clock pulse CK_1 to CK_4 among Fig. 6 and the signal Qm_n of the intermediary waveform sequential that each is corresponding schematic diagram (n=1 to 4, m=1 to 5, M=5); The transverse axis of Fig. 9 is the time, and the longitudinal axis of each waveform is a size waveforms.As mistake illustrated in fig. 8, the cycle of each signal Qm_n of intermediary is 5T, but because the phase difference between each clock pulse CK_n is equivalent to the time difference (k is an integer) of k*T/4, so between intermediary's signal that different clock pulses trigger out, its phase difference also will be equivalent to the time difference of T/4 integral multiple.Specifically, the phase difference between intermediary's signal Qm_n and the signal Q1_1 of intermediary just is equivalent to the time difference of ((m-1)+(n-1)/4) * T.For instance, as shown in Figure 9, the phase difference between signal Q2_2 of intermediary and the signal Q1_1 of intermediary just is equivalent to the time difference of 1.25T, and the phase difference between the signal Q3_3 of intermediary, Q4_4 and the signal Q1_1 of intermediary then is equivalent to the time difference of 2.5T and 3.75T respectively.
Utilize each signal Qm_n of intermediary, logic module 40 just can be combined at least one cycle for the signal of (5/4) T as output clock pulse CKo.Please refer to Figure 10, Figure 11 (and in the lump with reference to figure 6 to Fig. 9).Figure 10 is the schematic diagram of logic module 40 1 embodiment among Fig. 6, and Figure 11 then is the schematic diagram of each coherent signal waveform sequential when logic module 40 operates among Figure 10; The transverse axis of Figure 11 is the time.As shown in figure 10, can utilize in the logic module 40 with door 46 the signal Q1_1 of intermediary, Q3_3 are carried out producing a signal Qa, the signal Q2_2 of intermediary, Q4_4 being carried out producing signal Qb with computing with computing, signal Qa, Qb be carried out producing signal Qc again with computing.And signal Qa, Qb or Qc promptly can be used as output clock pulse CKo.
As shown in figure 11, utilize two the signal Q1_1 of intermediary, Q3_3 with 2.5T time difference carry out with computing after the signal Qa that generates, be exactly one-period be the clock signal of 2.5T.That is to say that in the cycle, the wave form varies of signal Qa has periodically repeated twice at the 5T of the signal Qm_n of intermediary.In like manner, the signal Qb after the signal Q2_2 of intermediary, Q4_4 and the computing is exactly the clock signal of another period of change 2.5T.But, because the phase difference between Q1_1, Q3_3 and Q2_2, the Q4_4 makes the phase difference between signal Qa, the Qb be equivalent to the time difference of 1.25T.And signal Qa, Qb are carried out the signal Qc that generates with computing, its waveform will take place 4 times to be repeated on 5T time intercycle ground, just have the cycle of 1.25T.As output clock pulse CKo, just can reach the purpose of non-integer frequency division of the present invention with signal Qc, the frequency division multiplying power with 0.8 is to clock pulse CK_n (period T) frequency division and the generation cycle is the output clock pulse of 1.25T.Certainly, signal Qa, the Qb of cycle 2.5T also can be used as output clock pulse CKo, as the frequency division result of 0.4 frequency division multiplying power.
Because the phase difference between each signal Qm_n of intermediary is equivalent to the time difference of T/4 integral multiple, suitably selects for use different intermediary's signals to do logical operation in logic module 40, just can produce a plurality of signals with given reference phase difference in addition and be used as exporting clock pulse.About this situation, please refer to Figure 12,13 (and in the lump with reference to figure 6 to Fig. 9).Figure 12 is the schematic diagram of logic module 40 another embodiment among Fig. 6, and Figure 13 then is the schematic diagram of each coherent signal waveform sequential when logic module 40 operates among Figure 12; The transverse axis of Figure 13 is the time.As shown in figure 12, except picture in Figure 10 with the signal Q1_1 of intermediary, Q2_2, Q3_3 and Q4_4 by carrying out producing the signal Qc with computing with door 46, the logic module 40 among Figure 12 is also got the signal Q1_2 of intermediary, Q2_3, Q3_4 and Q5_1 in addition and is carried out producing with computing signal Qd.By finding out among Figure 13, owing to have the phase difference that is equivalent to T/4 respectively between Q1_2, Q2_3, Q3_4 and Q5_1 and Q1_1, Q2_2, Q3_3 and the Q4_4, though event and signal Qc, Qd that computing generated equally have the cycle of 1.25T, and the phase difference that is equivalent to T/4 is also arranged between the two.With or door 48 signal Qc and Qd are made exclusive disjunction just can obtain signal Qe; As shown in figure 13, the cycle of signal Qe also is 1.25T, but its work week (duty cycle) is different with signal Qc, Qd.Signal Qc, Qd and Qe all can be used as output clock pulse CKo, realize 0.8 frequency division, are the output clock pulse of 1.25T with the generation cycle.
Except the clock pulse CK_1 to CK_4 according to period T produces the output clock pulse of 1.25T, the present invention can certainly be lower than the output clock pulse of 1T with the non-integral frequency division multiplying power cycle of producing.Actual execution mode please refer to Figure 14 to Figure 17 (and in the lump with reference to figure 6).To be lower than the output clock pulse of 1T according to the clock pulse CK_n cycle of producing of period T, can realize the state machine 36 among Fig. 6 with the circuit arrangement among Figure 14, with under the triggering of clock pulse CK_n, utilize the trigger 38 of two serial connections and NAND gate 42 to produce 3 signal Q1_n to Q3_n of intermediary (be among Fig. 6 M equal 3).Shown in the sequential schematic diagram of Figure 15, be allocated in the clock pulse CK_1 to CK_4 of T with 4 phase averages, just can produce the signal Q1_1 to Q3_1 of intermediary, Q1_2 to Q3_2, Q1_3 to Q3_3 and Q1_4 to Q3_4 (transverse axis of Figure 15 is the time) with the state machine among Figure 14 36; The cycle of each intermediary's signal is 3T, and it is level L that the time of 1T was arranged in each cycle, and the time remaining that 2T is arranged is level H.
Cooperate the state machine among Figure 14, circuit among 40 available Figure 16 of logic module among Fig. 6 is realized, by carrying out producing signal Qc2 with computing with the signal Q1_2 of 46 pairs of intermediaries of door, Q1_3, Q2_4 and Q3_1, the signal Q2_1 of intermediary, Q2_2, Q3_3 and Q3_4 carry out then being signal Qd2 with the result of computing.Signal Qc2, Qd2 with or door 48 make exclusive disjunction and can produce signal Qe2, and the cycle of signal Qe2 will be 0.75T, realizes out 4/3 frequency division.Shown in the sequential schematic diagram of Figure 17, signal Qc2 during 3T in its waveform can repeat twice, its cycle is 1.5T.Similarly, the cycle of signal Qd2 also is 1.5T, but has the phase difference that is equivalent to 0.75T between signal Qc2, the Qd2.Signal Qc2, Qd2 are carried out exclusive disjunction, and its formed signal Qe2 will have the cycle of 0.75T; And this signal Qe2 also just can be as the output clock pulse CKo of logic module 40, realizes 4/3 frequency division, produces the more output clock pulse of high frequency (cycle is shorter) by the clock pulse CK_n of period T.
In the embodiment of Fig. 7 to Figure 13 and Figure 14 to 17, all be with the trigger 38 (as Fig. 7, shown in Figure 14) of NAND gate 42 collocation serial connections, realize the state machine 36 among Fig. 6.The signal Qm_n of intermediary that this configuration generated, can in the cycle of M*T, have 1T during be maintained at level L, shown in Fig. 8, Fig. 9, Figure 15 etc.Certainly, the present invention's state machine 36 that also can use different circuit structures goes out non-integral frequency division multiplying power with intermediary's signal combination of different wave.About this situation, please refer to Figure 18 to Figure 20 (and in the lump with reference to figure 6).Under the triggering of the clock pulse CK_n of period T, suppose each state machine 36 among Fig. 6 signal Qm_n of intermediary that to produce 5 cycles be 5T, during being arranged in the one-period of each intermediary's signal, 2T is maintained at level L, gather intermediary's signal that 36 of 4 state machines can generate so, its waveform sequential promptly is illustrated in Figure 18.
Though the waveform of each signal Qm_n of intermediary is different from the waveform of Fig. 9 intermediary signal among Figure 18, but still the embodiment in the energy image pattern 9 to Figure 11 is the same, cooperates corresponding logic module design to be combined into identical non-integer frequency division multiplying power.Reach the purpose of frequency division, logic module 40 among Fig. 6 can realize with the configuration among Figure 19, by by the signal Q1_1 of intermediary, Q3_3 and Q2_2, Q4_4 among Figure 18 being carried out and computing with door, produce signal Qf1 and Qf2 respectively, utilization or door 48 couples of signal Qf1, Qf2 make exclusive disjunction again, and the signal Qg that just can produce 1.25T is as output clock pulse CKo.Operation situation about logic module among Figure 19 40 can be with reference to the waveform sequential schematic diagram of Figure 20.As shown in Figure 20, signal Qg has the cycle of 1.25T really.
After with specific embodiment the method that the present invention realizes specific frequency division multiplying power being discussed in front, next the situation that the technology of the present invention is applied will be discussed.Please refer to Figure 21.Figure 21 uses the function block schematic diagram that produce a plurality of alien frequencies output clock pulses with a phase lock circuitry 54 collocation for the present invention's one frequency dividing circuit 52 in a signal circuit 50.Be provided with detector 64, a filter 66, a voltage controlled oscillator 68 of two frequency divider 62A, 62B, a frequency/phase difference in the phase lock circuitry 54, with according to the phase-locked generation of a benchmark clock pulse Cr one output clock pulse CKo1.As discussed earlier, voltage controlled oscillator 68 can be a ring oscillator, and it is that T, phase average are allocated in the clock pulse CK_1 to CK_N in 360 degree (being equivalent to 1T) that N cycle can be provided.So voltage controlled oscillator 68 can be used as one with reference to the clock pulse circuit, and frequency dividing circuit of the present invention 52 can utilize these clock pulses CK_n as the reference clock pulse, realize the function of non-integer frequency division, different output clock pulse CKo2 of another cycle can be provided at least again.So, signal circuit 50 just can provide the different clock pulse of a plurality of frequencies, so that trigger the circuit building square of different time sequences in vein system is united for a long time.
In frequency dividing circuit 52 of the present invention, can be provided with N state machine 56, to form a trigger module; This N state machine 56 can produce M the signal Q1_n to QM_n of intermediary respectively under the triggering of a clock pulse CK_n.And logic module 60 just can be carried out logical operation to these intermediary's signals, is combined into output clock pulse CKo2.Please continue with reference to Figure 22 and 23 (and in the lump with reference to Figure 21).In preferred embodiment of the present invention, state machine 56 can utilize the circuit structure of illustrating among Figure 22 to realize, just with (M-1) individual trigger 38 collocation one NAND gate 42, so that under the triggering of clock pulse CK_n, produces the signal Q1_n to QM_n of intermediary.Figure 23 has then drawn the signal Qm_n of each intermediary that state machine can generate among Figure 22.As shown in figure 23, the cycle of each signal Qm_n of intermediary is M*T, each intermediary's signal in one-period, have 1T during be maintained at level L.Concerning different clock pulse CK_n, CK_n ', owing to have the phase difference (wherein k is an integer) that is equivalent to (k/N) * T between two clock pulses, so concerning signal Qm_n of intermediary and Qm_n ' that two clock pulses trigger out, phase difference between the two also can be equivalent to the phase difference of (k/N) * T.
Because the phase difference between each signal Qm_n of intermediary and the Qm ' _ n ' can be equivalent to the integral multiple of (T/N), and the cycle of each intermediary's signal is M*T, after 60 pairs of each intermediary's signals of logic module carry out logical operation, in the equivalence, can be that unit does to cut apart with time of (T/N) just to time of M*T length; Therefore, logical operation can be during M*T in the periodic waveform that comes out of combination, the minimum period that its waveform repeats is exactly the factor (factor) of M*N.For instance, in the embodiment of Fig. 7 to Fig. 9, because N=4 (4 clock pulses), M=5 (each clock pulse triggers 5 intermediary's signals), so the output clock pulse that logic module makes up out, its cycle just can be expressed as K* (T/4), and integer K can be 2,4,5,10,20; In the embodiment of Figure 11, signal Qa, Qb promptly are the signals (K=10 just) of cycle 2.5T, and signal Qc is the signal (K=5) of cycle 1.25T.In like manner, in the embodiment of Figure 14 to Figure 17, because N=4, M=3 still can show into K* (T/4) so export the cycle of clock pulse, and integer K can be 2,3,6,12.In Figure 17, the cycle of signal Qc2, Qd2 is (6/4) * T, and the cycle of signal Qe2 is (3/4) * T.
When the logic module 60 of design among Figure 21, can design the logic function of its required realization according to the characteristic of output clock pulse.Please refer to Figure 24,25 (and in the lump with reference to figures 21 to 23).Sequential schematic diagram when Figure 24,25 is combined into heterogeneity output clock pulse for the present invention with different intermediaries signal; The transverse axis of this two figure is the time.As shown in figure 24, suppose now and will be combined into output clock pulse CKoA, make the cycle of output clock pulse CKoA be (K/N) * T with each signal Qm_n of intermediary, and have in each cycle (K0/N) * T during be maintained at level L (wherein K, K0 are integer).If the time that output clock pulse CKoA is maintained at level L is maintained at time of level L more than or equal to intermediary's signal, just can directly select the suitable intermediary's signal of phase place, and computing forms the part of exporting level L among the clock pulse CKoA.Picture in Figure 24, suppose output clock pulse CKoA be maintained at level L during greater than each intermediary's signal be maintained at level L during, just can carry out result with computing with a plurality of intermediaries signal, form and export clock pulse CKoA; Similarly be that result with the signal Qm1_n1 of intermediary, Qm2_n2 and computing forms output clock pulse CKoA is maintained at level L in first cycle part, form output clock pulse CKoA is maintained at level L in another cycle part with the result of the signal Qm5_n5 of intermediary, Qm6_n6 and computing.Similarly being in Figure 10, embodiment that Figure 11 discussed, is exactly to produce signal Qc by this way.
On the other hand, if it is shorter than the part that intermediary signal is maintained at level L to export the part that is maintained at level L in the clock pulse, just can earlier the output clock pulse be decomposed into several interleaving signals than low frequency.As shown in figure 25, the logic of propositions module will be combined into the output clock pulse CKoB of cycle for (K/N) * T, but in each cycle of clock pulse CKoB, the part that is maintained at level L is also shorter than the part that each intermediary's signal is maintained at level L.In this case, just output clock pulse CKoB suitably can be decomposed into a plurality of staggered low frequency signal CKoB1, CKoB2 or the like, as shown in figure 25.In other words, output clock pulse CKoB is the result behind each low frequency signal CKoB1, the CKoB2 exclusive disjunction.Because the frequency of low frequency signal CKoB1, CKoB2 is lower, the cycle is longer, its part that is maintained at level L will be maintained at the part of level L more than or equal to each intermediary's signal, can be combined into each low frequency signal with the method for mentioning among Figure 24.That is to say, can utilize the result of each intermediary's signal and computing to be combined into low frequency signal earlier, again low frequency signal is combined into required high frequency output clock pulse with exclusive disjunction.The picture Figure 16,17 and Figure 19,20 in embodiment, just belong to this situation.
Certainly, be stressed that the implementation of logic module of the present invention has multiple, be not limited to and computing, exclusive disjunction or the like.For instance, make the resultant signal of exclusive disjunction after the signal Qm_n of intermediary and Qm ' _ n ' and signal that computing generated and Qm_n, Qm ' _ n ' are anti-phase respectively, two signals all can have the identical cycle (just anti-phase each other).As long as can be combined into the logic configuration of required output clock pulse, just can be used in the logic module among the present invention, go out suitable output clock pulse with each intermediary's signal combination, realize non-integral frequency division.
In summary, frequency dividing circuit of the present invention can utilize a plurality of out-phase clock pulses that annular voltage controlled oscillator generated of phase lock circuitry as the reference clock pulse, produce intermediary's clock pulse with the state machine that triggers in the frequency dividing circuit, utilize logic module to be combined into required output clock pulse again with each intermediary's clock pulse.Compared to prior art, the output clock pulse that the present invention can produce except phase lock circuitry itself can also provide output clock pulse behind at least one non-integer frequency division in addition again with frequency dividing circuit of the present invention.Because the logical circuit (similarly being trigger, gate) that the present invention only needs to simplify with structure just can provide extra output clock pulse (especially frequency is non-integral multiple output clock pulse), so required layout area, power consumption and the circuit structure of the technology of the present invention all comparatively examined and economized, simplifies, and can fully satisfy the modem electronic circuitry demand of arteries and veins for a long time again.When reality realizes, can find that the required layout area of frequency dividing circuit of the present invention approximately only is 1/5th of general phase lock circuitry, sequitur advantage of the present invention; And, be particularly suitable for being used for triggering the preface that only needs to trigger to the circuit building square with rising edge or trailing edge with the output clock pulse that frequency dividing circuit of the present invention makes up out.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (16)
1. the method for a frequency division is used for providing at least one output clock pulse according to a plurality of with reference to clock pulse, and has a default frequency division multiplying power during making cycle of described output clock pulse and described week with reference to clock pulse, and described method includes:
Receive described a plurality ofly with reference to clock pulse, wherein each equated with reference to cycle of clock pulse, and had different phase places between different reference clock pulses;
Carry out one and trigger step, to trigger intermediary's signal of a plurality of correspondences with reference to the cycle of clock pulse according to each, making described a plurality of intermediaries signal waveform change the minimum period that repeats is described integral multiple with reference to the clock pulse cycle, and has different phase places between corresponding same intermediary's signal with reference to clock pulse; And
Correspond respectively to different intermediary's signals with at least two and carry out logical operation with reference to clock pulse, and provide described output clock pulse according to the result of logical operation, make cycle minimum period that described output clock pulse waveform repeats to change, and be not equal to described cycle with reference to clock pulse less than described intermediary signal.
2. the method for claim 1, wherein receive N with reference to clock pulse, and n phase place and the 1st phase difference with reference to clock pulse with reference to clock pulse is ((n-1)/N) * 360 degree.
3. method as claimed in claim 2, wherein, described triggering step make each intermediary signal waveform change the minimum period that repeats be described M with reference to the clock pulse cycle doubly, and when the described cycle with reference to clock pulse is T, the cycle of described output clock pulse is (T/N) L a times, and L is one of factor of M, N product.
4. the method for claim 1, wherein said triggering step triggers M intermediary's signal according to each with reference to clock pulse, make described each intermediary signal waveform change the minimum period that repeats be described M with reference to the clock pulse cycle doubly, and the phase difference of m intermediary's signal and the 1st intermediary's signal is equivalent to described with reference to the clock pulse cycle m times.
5. the method for claim 1, wherein described triggering step triggers M intermediary's signal according to each with reference to clock pulse, and making each intermediary's signal waveform change the minimum period that repeats is described with reference to the clock pulse cycle M times.
6. the time that the method for claim 1, wherein is maintained at one first level in each cycle of each intermediary's signal also is described integral multiple with reference to the clock pulse cycle.
7. the method for claim 1, wherein when carrying out described triggering step, according to each with reference to clock pulse in each cycle the triggering of rising edge or trailing edge produce described a plurality of intermediaries signal.
8. the cycle of the method for claim 1, wherein described output clock pulse is less than the described cycle with reference to clock pulse.
9. a signal circuit is used for providing at least one output clock pulse according to a plurality of with reference to clock pulse, and has a default frequency division multiplying power during making cycle of described output clock pulse and described week with reference to clock pulse, and described signal circuit includes:
One with reference to the clock pulse circuit, is used to provide described a plurality ofly with reference to clock pulse, and wherein each equated with reference to cycle of clock pulse, and had different phase places between different reference clock pulses;
One trigger module, it includes the plurality of states machine, each state machine corresponding to one with reference to clock pulse, can trigger intermediary's signal of a plurality of correspondences according to described cycle with reference to clock pulse, making described a plurality of intermediaries signal waveform change the minimum period that repeats is described integral multiple with reference to the clock pulse cycle, and has different phase places between corresponding same each intermediary's signal that state machine provided with reference to clock pulse; And
One logic module, it includes a plurality of gates, described logic module can correspond respectively to different intermediary's signals with reference to clock pulse with at least two and carry out logical operation, and provide described output clock pulse according to the result of logical operation, make cycle minimum period that described output clock pulse waveform repeats to change, and be not equal to described cycle with reference to clock pulse less than described intermediary signal.
10. signal circuit as claimed in claim 9 wherein saidly can provide N with reference to clock pulse with reference to the clock pulse circuit, and n the phase place with reference to clock pulse is that ((n-1)/N) * 360 spends with the 1st phase difference with reference to clock pulse.
11. signal circuit as claimed in claim 10, wherein, each state machine make described each intermediary signal waveform change the minimum period that repeats be described M with reference to the clock pulse cycle doubly, and when the described cycle with reference to clock pulse is T, the cycle that described logic module makes described output clock pulse for the L of (T/N) doubly, and L is one of factor of M, N product.
12. signal circuit as claimed in claim 9, wherein, described state machine triggers M intermediary's signal according to each with reference to clock pulse, make each intermediary signal waveform change the minimum period that repeats be described M with reference to the clock pulse cycle doubly, and the phase difference of m intermediary's signal and the 1st intermediary's signal is equivalent to described with reference to the clock pulse cycle m times.
13. signal circuit as claimed in claim 9, wherein, each state machine triggers M intermediary's signal according to each with reference to clock pulse, and making each intermediary's signal waveform change the minimum period that repeats is described with reference to the clock pulse cycle M times.
14. signal circuit as claimed in claim 9, wherein, each state machine makes the time that is maintained at one first level in each cycle of each intermediary's signal also be described integral multiple with reference to the clock pulse cycle.
15. signal circuit as claimed in claim 9, wherein, each state machine according to each with reference to clock pulse in each cycle the triggering of rising edge or trailing edge produce described a plurality of intermediaries signal.
16. signal circuit as claimed in claim 9, wherein, described logic module makes the cycle of described output clock pulse less than the described cycle with reference to clock pulse.
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| CNB2003101024310A CN1320763C (en) | 2003-10-20 | 2003-10-20 | Frequency dividing method with non-integer frequency dividion multiplying power and corresponding signal circuit |
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| CNB2003101024310A CN1320763C (en) | 2003-10-20 | 2003-10-20 | Frequency dividing method with non-integer frequency dividion multiplying power and corresponding signal circuit |
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| CN1610263A true CN1610263A (en) | 2005-04-27 |
| CN1320763C CN1320763C (en) | 2007-06-06 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127529B (en) * | 2006-08-18 | 2010-05-12 | 智原科技股份有限公司 | Digital/analog converter and phase locking loop built-in self test circuit and its measurement method |
| CN106291102A (en) * | 2016-08-09 | 2017-01-04 | 西安电子科技大学 | A kind of Frequency Standard Comparison device and method |
| CN111010148A (en) * | 2019-12-19 | 2020-04-14 | 西安紫光国芯半导体有限公司 | Rising edge trigger pulse generator and method of high-frequency DRAM (dynamic random Access memory) |
| CN116667821A (en) * | 2023-08-02 | 2023-08-29 | 深圳市夏繁光电科技有限公司 | Method, circuit, device and control equipment for generating multiple PWM signals with different phases |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3917433A1 (en) * | 1989-05-29 | 1990-12-06 | Siemens Ag | Parallel data and clock signal interface for synchronisation - produces clock signal for further processing from divider clocked at integral multiple of data clock frequency |
| JP2853894B2 (en) * | 1990-08-24 | 1999-02-03 | 三菱電機株式会社 | Frequency divider and pulse signal generator |
| JP2002344308A (en) * | 2001-05-18 | 2002-11-29 | Matsushita Electric Ind Co Ltd | Odd number frequency divider and 90 degree phaser shifter using the same |
-
2003
- 2003-10-20 CN CNB2003101024310A patent/CN1320763C/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127529B (en) * | 2006-08-18 | 2010-05-12 | 智原科技股份有限公司 | Digital/analog converter and phase locking loop built-in self test circuit and its measurement method |
| CN106291102A (en) * | 2016-08-09 | 2017-01-04 | 西安电子科技大学 | A kind of Frequency Standard Comparison device and method |
| CN106291102B (en) * | 2016-08-09 | 2019-05-07 | 西安电子科技大学 | A kind of Frequency Standard Comparison device and method |
| CN111010148A (en) * | 2019-12-19 | 2020-04-14 | 西安紫光国芯半导体有限公司 | Rising edge trigger pulse generator and method of high-frequency DRAM (dynamic random Access memory) |
| CN111010148B (en) * | 2019-12-19 | 2023-08-18 | 西安紫光国芯半导体有限公司 | Rising edge trigger pulse generator and method of high-frequency DRAM |
| CN116667821A (en) * | 2023-08-02 | 2023-08-29 | 深圳市夏繁光电科技有限公司 | Method, circuit, device and control equipment for generating multiple PWM signals with different phases |
| CN116667821B (en) * | 2023-08-02 | 2024-02-23 | 深圳市夏繁光电科技有限公司 | Method, circuit, device and control equipment for generating multiple PWM signals with different phases |
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| CN1320763C (en) | 2007-06-06 |
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