CN1725629A - Low frequency clock signal generating method and low frequency cloc ksignal generator - Google Patents
Low frequency clock signal generating method and low frequency cloc ksignal generator Download PDFInfo
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- CN1725629A CN1725629A CN 200510056467 CN200510056467A CN1725629A CN 1725629 A CN1725629 A CN 1725629A CN 200510056467 CN200510056467 CN 200510056467 CN 200510056467 A CN200510056467 A CN 200510056467A CN 1725629 A CN1725629 A CN 1725629A
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Abstract
A method for generating low frequency clock signal includes confirming frequency multiplication number N1 and frequency division number N2 according to low frequency clock signal cycle T0 and source clock pulse signal TS ; receiving signal Ts and enlarging it to be clock signal of frequency N1 / TS ; narrowing clock signal of frequency N1 / TS to be 1 / N2 then outputting it for obtaining low frequency clock signal with cycle T0 .The device for generating this low frequency clock signal is also disclosed .
Description
Technical field
The present invention relates to IT field such as communication and network, relate in particular to a kind of device and production method that is used to produce low-frequency clock signal.
Background technology
Low-frequency clock signal is widely used in communication and IT industry such as network, as the control of the lighting a lamp of system indicator, house dog etc.See also Fig. 1, it is the structural representation of a kind of low-frequency clock signal generation device in the prior art.It comprises clock source 1 and CPLD (programmable logic device) 2.Clock source 1 is generally a crystal oscillator, and producing frequency is the high frequency clock signal of tens megahertzes (HZ).CPLD 2 need carry out high frequency clock signal frequency division to be handled, and obtains the low-frequency clock signal that a frequency meets the demands.
Existing low-frequency clock signal production method is that CPLD 2 calculates the high frequency clock signal of input earlier and needs output to determine period T
0Low-frequency clock signal between Frequency Dividing Factor, determine trigger condition, then, the high frequency clock signal of 2 pairs of inputs of CPLD counts, when satisfying trigger condition, CPLD 2 just triggers pulse of output, produces low-frequency clock signal with this.
Such as: the high frequency clock signal that CPLD 2 receives is 25MHZ, and what now need output is the low-frequency clock signal of 1HZ.25MHZ represents to produce 25000000 pulse signals in 1 second, and 1HZ then represents to need to produce 1 pulse signal in 1 second.The low-frequency clock signal that produces 1HZ is realized as follows: the clock signal of the 25MHZ of 2 pairs of inputs of CPLD counts, when remembering 25000000 pulses, CPLD just exports a pulse, realizes producing the effect of the low-frequency clock signal of 1HZ with this.
Yet the mnemon of CPLD (macrocell) can only storing binary, and each macrocell is stored a bit.And 25M is a decimal number, and it is converted into binary number is 1011111010111100001000000, therefore needs the macrocell of 25 CPLD to count.
In addition, Frequency Dividing Factor between the low-frequency clock signal of the high frequency clock signal of input and needs output is not all to be integer, such as the high frequency clock signal when input is 25MHZ, when the frequency of the low-frequency clock signal that CPLD2 need export is 4MHZ, CPLD2 count down to 25/4 pulse signal and just produces a pulse signal on the principle, in fact, CPLD2 is difficult to be accurate to 25/4 pulse signal, needs to increase other devices usually.See also Figure 11, it is a kind of realization circuit diagram that frequency is 1/4 times a clock pulse signal of reference clock pulse signal frequency that produces.The characteristics of voltage controlled frequency follower 32 are that when input voltage V was high, output frequency Y was also big.F is four frequency divisions of Y.The characteristics of phase comparator 31 are, the phase lag of f is many more in the phase place of Y, and then output voltage V is high more, thereby Y is increased, and then feedback f is increased, and reduce the phase difference of f and X, finally reach balance, and so X=f at this moment is Y=4X.This just needs to increase above-mentioned circuit and produces 1/4 overtones band signal, not only increases and realizes cost, and increase the difficulty that realizes.
In addition, in the communications field, CPLD also needs to finish the Control work of system's control except in order to produce low-frequency clock signal.Yet the resource of each CPLD is limited, determines such as the number of macrocell, takies a large amount of macrocells when CPLD produces low-frequency clock signal, makes the employed macrocell resource of other Control work of CPLD just reduce.In order to overcome above-mentioned defective, system can also adopt the many CPLD of macrocell number, but the price of this class CPLD is very high, has improved the cost that produces low-frequency clock signal thus.
Summary of the invention
The object of the present invention is to provide a kind of low-frequency clock signal generation device and low-frequency clock signal production method, to solve in the prior art when the Frequency Dividing Factor non-integer, need the extra device that increases to produce low-frequency clock signal, or than a large amount of CPLD resource of conventional method saving, and then feasible low-frequency clock signal cost height, the big technological deficiency of realization difficulty of producing.
For addressing the above problem, the invention discloses a kind of low-frequency clock signal production method, with the generation cycle be T
oLow-frequency clock signal, comprising:
(1) programmable logic device is according to the period T of described low-frequency clock signal
oPeriod T with the source clock pulse signal
SDetermine frequency N
1With divider ratio N
2
(2) receiving the cycle that is sent by the clock source is T
SThe source clock pulse signal, and its frequency is extended to the N of primary frequency
1Doubly obtaining frequency is N
1/ T
SClock signal;
(3) be N with frequency
1/ T
SThe frequency of clock signal be contracted to 1/N
2Back output, and then to obtain the described cycle be T
oLow-frequency clock signal.
Step (2) is specially: (21) are provided with first count value is 1, and the source clock pulse signal is set to first clock signal; (22) judge whether first count value equals N
1If,, first clock signal is that frequency is N
1/ T
SClock signal, otherwise, carry out step (23); (23) first clock signals move right and resemble 90 degree, obtain the second clock signal; (24) first clock signals and second clock signal carry out clock signal that XOR obtains as first clock signal, and after first count value added 1, carry out step (22).
Step (3) is specially: to frequency is N
1/ T
SClock signal count, when pulse number is N
2Multiple the time, export a pulse, realize that with this generation cycle is T
oLow-frequency clock signal.
Step (1) is by calculating T
o/ T
sFraction in lowest term determine frequency N
1With divider ratio N
2, wherein, the denominator of fraction in lowest term is frequency N
1, the molecule of fraction in lowest term is divider ratio N
2
The invention also discloses second kind of low-frequency clock signal production method, with the generation cycle be T
oLow-frequency clock signal, it is characterized in that, comprising:
(1) programmable logic device is according to the period T of described low-frequency clock signal
oPeriod T with the source clock pulse signal
SDetermine frequency N
1With divider ratio N
2
(2) receiving the cycle that is sent by the clock source is T
SThe source clock pulse signal, and the frequency of the source clock pulse signal that receives is contracted to 1/N
2Obtaining frequency doubly is 1/ (T
S* N
2) clock signal;
(3) be 1/ (T with frequency
S* N
2) the frequency of clock signal be extended to N
1Doubly, obtaining the described cycle is T
oLow-frequency clock signal.
Step (2) is specially: the source clock pulse signal is counted, when pulse number is N
2Multiple the time, export a pulse, be 1/ (T to produce frequency
S* N
2) clock signal.
Step (3) is specially: (31) are provided with first count value is 1, and is 1/ (T with frequency
S* N
2) clock signal be set to first clock signal; (32) judge whether first count value equals N
1If,, first clock signal is described low-frequency clock signal output, otherwise, carry out step (33); (33) first clock signals move right and resemble 90 degree, obtain the second clock signal; (34) first clock signals and second clock signal carry out clock signal that XOR obtains as first clock signal, and after first count value added 1, carry out step (32).
Calculate T in the step (1)
o/ T
sFraction in lowest term determine frequency N
1With divider ratio N
2, wherein, the denominator of fraction in lowest term is N
1, the molecule of fraction in lowest term is N
2
The invention discloses a kind of low-frequency clock signal generation device, comprise clock source and programmable logic device, wherein:
Clock source: regularly produce the source clock pulse signal and be sent to programmable logic device;
Programmable logic device: the period T of Shu Chu low-frequency clock signal as required
0Period T with the source clock pulse signal
sDetermine frequency N
1With divider ratio N
2After, the frequency that receives described source clock pulse signal is extended to N
1Be contracted to 1/N doubly
2Doubly, the frequency that perhaps will receive described source clock pulse signal is contracted to 1/N
2Be extended to N again doubly
1Doubly, to produce period T
0The source clock pulse signal.
Described clock source comprises timing device and trigger device, wherein: the timing device, every through sending triggering signal to trigger once the time cycle that sets in advance; Trigger device: whenever receive a triggering signal, shear just takes place in the signal of output.
Described timing device is ADM706, and trigger device is a programmable logic device.
The output WDO of AMD706 connects the input WDI of programmable logic device and AMD706 respectively.
AMD706 also connects a reset key.
Programmable logic device further comprises: determining unit: in order to the period T of low-frequency clock signal of output as required
0Period T with the source clock pulse signal
sDetermine and preservation frequency N
1With divider ratio N
2Perhaps in order to obtain and to preserve frequency N from peripheral hardware
1With divider ratio N
2
Frequency divider: connect determining unit, in order to obtain divider ratio N from determining unit
2, the frequency of the source clock pulse signal that receives is contracted to 1/N
2Obtaining frequency doubly is 1/ (T
S* N
2) clock signal;
Frequency multiplier: connect frequency divider and determining unit, in order to obtain frequency N from determining unit
1, receiving from described frequency divider transmission frequency is 1/ (T
S* N
2) clock signal, and the frequency of described signal is extended to N
1Doubly, obtaining the described cycle is T
oLow-frequency clock signal output.
Programmable logic device further comprises:
Determining unit: in order to the period T of low-frequency clock signal of output as required
0Period T with the source clock pulse signal
sDetermine frequency N
1With divider ratio N
2Perhaps in order to obtain and to preserve frequency N from peripheral hardware
1With divider ratio N
2
Frequency multiplier: connect determining unit, receiving the cycle that is sent by the clock source is T
SThe source clock pulse signal, and its frequency is extended to the N of primary frequency
1Doubly obtaining frequency is N
1/ T
SClock signal;
Frequency divider: connect frequency multiplier and determining unit, in order to obtain divider ratio N from determining unit
2, receiving from described frequency multiplier transmission frequency is N
1/ T
SClock signal, and the frequency of described clock signal is contracted to N
2Doubly back output, and then to obtain the described cycle be T
oLow-frequency clock signal.
Described programmable logic device is one of them among PLD, the FPGA.
Compared with prior art, the present invention has the following advantages:
First: the present invention utilizes the programmable characteristic of programmable logic device, produce the low-frequency clock signal of optional frequency by frequency division step and frequency multiplication step, need not to increase extra device and can produce low-frequency clock signal, reduce and realize cost and reduced the realization difficulty;
Second: the present invention can also by the timing device and trigger device generation frequency be lower and the source clock signal of fixed-frequency, with this clock signal as the reference clock, can reduce requirement, and then make and to adopt the low programmable logic device of cost, reduce cost thus macrocell;
The 3rd: the timing device can utilize ADM706 that existing communication single-board all has as the timing device, produces the source clock signal of fixed frequency, has reduced the timing device thus, has further reduced cost.
Description of drawings
Fig. 1 is the structural representation of a kind of low-frequency clock signal generation device in the prior art;
Fig. 2 is a kind of flow chart of low-frequency clock signal production method of the present invention;
Fig. 3 is that one of frequency multiplication step is implemented illustration;
Fig. 4 is the another kind of flow chart of low-frequency clock signal production method of the present invention;
Fig. 5 is a kind of structural representation of programmable logic device;
Fig. 6 is the another kind of structural representation of programmable logic device;
Fig. 7 is the structural representation in clock of the present invention source;
Fig. 8 is the structural representation that utilizes the ADM706 clocking;
Fig. 9 is the clock signal sequential chart of WDO end output;
Figure 10 is the source clock signal sequential chart that produces Ts=3.2S;
Figure 11 is a kind of realization circuit diagram that frequency is 1/4 times a clock pulse signal of reference clock pulse signal frequency that produces.
Embodiment
Below in conjunction with accompanying drawing, specify the present invention.
The present invention utilizes programmable logic device to have programmable characteristic, as required the period T of Shu Chu low-frequency clock signal
0Period T with the source clock pulse signal
sDetermine frequency N
1With divider ratio N
2After, the frequency that receives described source clock pulse signal is extended to N
1Be contracted to N doubly
2Doubly, the frequency that perhaps will receive described source clock pulse signal is contracted to N
2Be extended to N again doubly
1Doubly, to produce period T
0The source clock pulse signal, overcome when the Frequency Dividing Factor non-integer with this, need the extra technological deficiency that device produces low-frequency clock signal that increases.
Low-frequency clock signal is produced down by programming device able to programme and the acting in conjunction of clock source.The clock source can be adopted and be produced fixed frequency 1/T
SCrystal oscillator, also can adopt timing device, as count down to T at every turn with clocking capability
SThe time produce a pulse signal, with this formation cycle be T
SClock pulse signal.See also Fig. 2, it is for a kind of flow chart of low-frequency clock signal production method of the present invention.It comprises:
S110: programmable logic device is according to the period T of described low-frequency clock signal
oPeriod T with the source clock pulse signal
SDetermine frequency N
1With divider ratio N
2Programmable logic device is provided with input unit usually, and the user can import the period T of low-frequency clock signal by input unit
oPeriod T with the source clock pulse signal
S
Determine frequency N
1With divider ratio N
2A kind of method be by calculating T
o/ T
sFraction in lowest term determine frequency N
1With divider ratio N
2, wherein, the denominator of fraction in lowest term is set to N
1, the molecule of fraction in lowest term is set to N
2Certainly, work as T
o, T
sDuring for integer, also can be directly with T
oNumerical value be set to N
1, with T
sData be set to N
2Individual in addition, the user also can be with frequency N
1With divider ratio N
2Be directly inputted into programmable logic device by input unit.
S120: it is T that programmable logic device receives the cycle that is sent by the clock source
SThe source clock pulse signal, and its frequency is extended to the N of primary frequency
1Doubly obtaining frequency is N
1/ T
SClock signal, the applicant is referred to as the frequency multiplication step with this step.
A kind of implementation of frequency multiplication step is:
(21) first count value being set is 1, and the source clock pulse signal is set to first clock signal;
(22) judge whether first count value equals N
1If,, first clock signal is that frequency is N
1/ T
SClock signal, otherwise, carry out step (23);
(23) first clock signals move right and resemble 90 degree, obtain the second clock signal;
(24) first clock signals and second clock signal carry out clock signal that XOR obtains as first clock signal, and after first count value added 1, carry out step (22).
S130: with frequency is N
1/ T
SThe frequency of clock signal be contracted to N
2Doubly back output, and then to obtain the described cycle be T
oLow-frequency clock signal.The applicant is referred to as the frequency division step with this step.The simplest a kind of frequency division step is: to frequency is N
1/ T
SClock signal count, when pulse number is N
2Multiple the time, export a pulse, realize that with this generation cycle is T
oLow-frequency clock signal.Frequency division has a variety of implementations, and is also not limited thereto.
Below lift a simple case and specify the present invention.Suppose that the clock source produces T
sBe the source clock pulse signal of 3.2S, that now need obtain is T
oBe the low-frequency clock signal of 4.8S, then calculate T
0/ T
SThe fraction in lowest term 3/2,3rd that obtains, divider ratio, the 2nd, frequency.
Then carry out the frequency multiplication step earlier:
The source clock signal is as first clock signal, with first clock signal move right move resemble 90 the degree, obtain second clock signal, then first and second clock signal is carried out XOR, obtain 2 doubled clock, i.e. the generation cycle is the clock signal (seeing also Fig. 3) of 1.6S.
And then carry out the frequency division step:
The clock signal that will be 1.6S the cycle is carried out the frequency division processing, and every through new clock signal of 3 pulses pulse shapings of generation, this clock signal is the T that we want
0Clock signal for 4.8S.
But aforesaid way only is the implementation of a kind of frequency multiplication step of the present invention, frequency division step, can also adopt other frequency multiplication steps and frequency division step.
Therefore, above-mentioned implementation is the usefulness for illustrating only, but not be in order to restriction the present invention.
See also Fig. 4, it is for the another kind of flow chart of low-frequency clock signal production method of the present invention.It comprises:
S210: programmable logic device is according to the period T of described low-frequency clock signal
oPeriod T with the source clock pulse signal
SDetermine frequency N
1With divider ratio N
2Programmable logic device is provided with input unit usually, and the user is by the period T of input unit input source clock pulse signal
SDetermine frequency N
1With divider ratio N
2Method be by calculating T
o/ T
sFraction in lowest term determine frequency N
1With divider ratio N
2, wherein, the denominator of fraction in lowest term is set to N
1, the molecule of fraction in lowest term is set to N
2
S220: it is T that programmable logic device receives the cycle that is sent by the clock source
SThe source clock pulse signal, and the frequency of the source clock pulse signal that receives is contracted to N
2Obtaining frequency doubly is 1/ (T
S* N
2) clock signal;
S230: with frequency is 1/ (T
S* N
2) the frequency of clock signal be extended to N
1Doubly, obtaining the described cycle is T
oLow-frequency clock signal.
The mode that a kind of frequency division is handled is: the source clock pulse signal is counted, when pulse number is N
2Multiple the time, export a pulse, be 1/ (T to produce frequency
S* N
2) clock signal.
A kind of implementation of process of frequency multiplication is:
(31) first count value being set is 1, and is 1/ (T with frequency
S* N
2) clock signal be set to first clock signal;
(32) judge whether first count value equals N
1If,, first clock signal is described low-frequency clock signal output, otherwise, carry out step (33);
(33) first clock signals move right and resemble 90 degree, obtain the second clock signal;
(34) first clock signals and second clock signal carry out clock signal that XOR obtains as first clock signal, and after first count value added 1, carry out step (32).
The invention discloses a kind of low-frequency clock signal generation device.It comprises clock source and programmable logic device, wherein:
Clock source: regularly produce the source clock pulse signal and be sent to programmable logic device.The clock source can be outside the existing crystal oscillator, can also be the time set with clocking capability, such as the control chip etc. that resets, can be that example specifies the clock source with the control chip that resets wherein below.
Programmable logic device: the period T of Shu Chu low-frequency clock signal as required
0Period T with the source clock pulse signal
sDetermine frequency N
1With divider ratio N
2After, the frequency that receives described source clock pulse signal is extended to N
1Be contracted to N doubly
2Doubly, the frequency that perhaps will receive described source clock pulse signal is contracted to N
2Be extended to N again doubly
1Doubly, to produce period T
0The source clock pulse signal.
Programmable logic device is one of them among PLD, the FPGA.
See also Fig. 5, it is a kind of realization circuit diagram of programmable logic device.It comprises: determining unit 221, frequency divider 222 and frequency multiplier 223, wherein:
Determining unit 221: in order to the period T of low-frequency clock signal of output as required
0Period T with the source clock pulse signal
sDetermine frequency N
1With divider ratio N
2Determining unit 221 can be connected with I/O unit, by input unit accept by user's input the period T of low-frequency clock signal
0Period T with the source clock pulse signal
s, determine frequency N with this
1With divider ratio N
2Determining unit 221 also can obtain frequency N from peripheral hardware (I/O unit)
1With divider ratio N
2And preservation frequency N
1With divider ratio N
2
The most frequently used a kind of definite mode is: determining unit is calculated T
o/ T
sFraction in lowest term determine frequency N
1With divider ratio N
2, wherein, the denominator of fraction in lowest term is set to N
1, the molecule of fraction in lowest term is set to N
2
Frequency divider 222: connect determining unit 221, in order to obtain divider ratio N from determining unit
2, the frequency of the source clock pulse signal that receives is contracted to N
2Obtaining frequency doubly is 1/ (T
S* N
2) clock signal;
Frequency multiplier 223: connect frequency divider 222 and determining unit 221, receiving from described frequency divider transmission frequency is 1/ (T
S* N
2) clock signal, and the frequency of described signal is extended to N
1Doubly, obtaining the described cycle is T
oLow-frequency clock signal output.
See also Fig. 6, it is the another kind of structural representation of programmable logic device.It comprises determining unit 221, frequency divider 222 and frequency multiplier 223.Wherein:
Determining unit 221: in order to the period T of low-frequency clock signal of output as required
0Period T with the source clock pulse signal
sDetermine frequency N
1With divider ratio N
2Determining unit 221 also can obtain frequency N from peripheral hardware (I/O unit)
1With divider ratio N
2And preservation frequency N
1With divider ratio N
2
Frequency multiplier 223: connect determining unit 221, in order to obtain divider ratio N from determining unit 221
2, receiving the cycle that is sent by the clock source is T
SThe source clock pulse signal, and its frequency is extended to the N of primary frequency
1Doubly obtaining frequency is N
1/ T
SClock signal;
Frequency divider 222: connect frequency multiplier 223 and determining unit 221, in order to obtain divider ratio N from determining unit 221
2, receiving from described frequency multiplier 223 transmission frequency is N
1/ T
SClock signal, and the frequency of described clock signal is contracted to N
2Doubly back output, and then to obtain the described cycle be T
oLow-frequency clock signal.
Below specifically introduce clock of the present invention source.The applicant long-term practice process find can clocking except traditional crystal oscillator, can also come clocking by timing device and trigger.For this reason, see also Fig. 7, it is the structural representation in clock of the present invention source.It comprises timing device 31 and trigger 32.Wherein:
Timing device 31, every through sending triggering signal to trigger 32 once the time cycle that sets in advance;
Trigger device 32: whenever receive a triggering signal, shear just takes place in the signal of output.
Timing device 31 can be a timer, control chip or other special timing chips reset.Trigger device 32 can be trigger, also can be to have the chip that triggers function.In the present invention, the function of trigger device 32 can be finished in programmable logic device, omits special trigger device with this.
ADM706 is the control chip that resets that present nearly all communication class veneer is all used.Because veneer can have the ADM706 chip usually, therefore need not to increase any hardware, in existing single board system, utilize ADM706 and programmable logic device to get final product clocking, reach the purpose that reduces cost thus.
See also Fig. 8, for utilizing the structural representation of ADM706 clocking.The output WDO of ADM706 connects the input WDI of programmable logic device and AMD706 respectively, and input WDI connects a power supply by a resistance.
The switching of the level of WDO is that the WDO signal feeds back to WDI by resistance R 1, adds that the timing of the 1.6S of ADM706 finishes again.In case power on or during button S1, the WDO of AMD706 end all can be exported the high level of a lasting 1.6S, can become low level automatically behind this high level 1.6S, and it can be kept this low level always and remain unchanged if do not give WDI a feedback input this moment.But the feedback fraction that couple WDI is arranged in circuit, so, carry out so repeatedly in case the WDI input low level can make the WDO of AMD706 export high level immediately, and carry out the timing of 1.6S again.See also Fig. 9, it is the clock signal of WDO end output.T1 is exactly a feedback time, and the T1 time is very short, be ns rank (10E-9 second) this be very short with respect to 1.6 seconds, can ignore, but programmable logic device detect be by level pulse along triggering, the signal of ns level is can be detected.
ADM706 also connects a reset key S1, and button S1 system reset is used, and promptly in system's running, presses S1, decontrols again, and system can be from new operation.
ADM706 also plays filtering by inductance and electric capacity, with the burr filtering in power supply and the signal, thus the reliability when guaranteeing system works.
In the drawings, 2 metering functions of resistance R, electric current is excessive when preventing to push button S1; Resistance R 3 is pull down resistors, avoids the pin of U1 unsettled, so that produce concussion; Resistance R 1 is a feedback resistance, the WDO output of U1 is fed back to the WDI of U1; R4 is a pull-up resistor, cooperates the high level part of stable generation signal with chip.
Programmable logic device receives the clock signal that ADM706 sends, and when detecting the rising edge of input signal, the clock signal generation shear of output can produce the source clock signal (seeing also Figure 10) of Ts=3.2S.Based on above-mentioned disclosed method, can obtain the low-frequency clock signal in any cycle.
Can produce the very low source clock signal of frequency by above-mentioned timing device, such as utilizing ADM706 can produce T
SThe source clock signal of=3.2S, the source clock signal very low by those frequencies obtains the low-frequency clock signal that requires, and just need not to take a large amount of macrocells of programmable logic device.Such as: still produce T
0The low-frequency clock signal of=1S need can obtain through 7 frequencys multiplication and 2 frequency divisions, does not need to take 25 macrocells, makes thus to need not to select in order to produce low-frequency clock signal expensive programmable logic device (CPLD), and then reduces cost.
More than disclosed only be several specific embodiment of the present invention, but the present invention is not limited thereto, any those skilled in the art can think variation, all should drop in protection scope of the present invention.
Claims (16)
1, a kind of low-frequency clock signal production method, with the generation cycle be T
oLow-frequency clock signal, it is characterized in that, comprising:
(1) programmable logic device is according to the period T of described low-frequency clock signal
oPeriod T with the source clock pulse signal
SDetermine frequency N
1With divider ratio N
2
(2) receiving the cycle that is sent by the clock source is T
SThe source clock pulse signal, and its frequency is extended to the N of primary frequency
1Doubly obtaining frequency is N
1/ T
SClock signal;
(3) be N with frequency
1/ T
SThe frequency of clock signal be contracted to 1/N
2Back output, and then to obtain the described cycle be T
oLow-frequency clock signal.
2, low-frequency clock signal production method as claimed in claim 1 is characterized in that, step (2) is specially:
(21) first count value being set is 1, and the source clock pulse signal is set to first clock signal;
(22) judge whether first count value equals N
1If,, first clock signal is that frequency is N
1/ T
SClock signal, otherwise, carry out step (23);
(23) first clock signals move right and resemble 90 degree, obtain the second clock signal;
(24) first clock signals and second clock signal carry out clock signal that XOR obtains as first clock signal, and after first count value added 1, carry out step (22).
3, low-frequency clock signal production method as claimed in claim 1 or 2 is characterized in that, step (3) is specially: to frequency is N
1/ T
SClock signal count, when pulse number is N
2Multiple the time, export a pulse, realize that with this generation cycle is T
oLow-frequency clock signal.
4, low-frequency clock signal production method as claimed in claim 1 is characterized in that, step (1) is by calculating T
o/ T
sFraction in lowest term determine frequency N
1With divider ratio N
2, wherein, the denominator of fraction in lowest term is frequency N
1, the molecule of fraction in lowest term is divider ratio N
2
5, a kind of low-frequency clock signal production method, with the generation cycle be T
oLow-frequency clock signal, it is characterized in that, comprising:
(1) programmable logic device is according to the period T of described low-frequency clock signal
oPeriod T with the source clock pulse signal
SDetermine frequency N
1With divider ratio N
2
(2) receiving the cycle that is sent by the clock source is T
SThe source clock pulse signal, and the frequency of the source clock pulse signal that receives is contracted to 1/N
2Obtaining frequency doubly is 1/ (T
S* N
2) clock signal;
(3) be 1/ (T with frequency
S* N
2) the frequency of clock signal be extended to N
1Doubly, obtaining the described cycle is T
oLow-frequency clock signal.
6, low-frequency clock signal production method as claimed in claim 5 is characterized in that, step (2) is specially: the source clock pulse signal is counted, when pulse number is N
2Multiple the time, export a pulse, be 1/ (T to produce frequency
S* N
2) clock signal.
7, as claim 5 or 6 described low-frequency clock signal production methods, it is characterized in that step (3) is specially:
(31) first count value being set is 1, and is 1/ (T with frequency
S* N
2) clock signal be set to first clock signal;
(32) judge whether first count value equals N
1If,, first clock signal is described low-frequency clock signal output, otherwise, carry out step (33);
(33) first clock signals move right and resemble 90 degree, obtain the second clock signal;
(34) first clock signals and second clock signal carry out clock signal that XOR obtains as first clock signal, and after first count value added 1, carry out step (32).
8, low-frequency clock signal production method as claimed in claim 5 is characterized in that, calculates T in the step (1)
o/ T
sFraction in lowest term determine frequency N
1With divider ratio N
2, wherein, the denominator of fraction in lowest term is N
1, the molecule of fraction in lowest term is N
2
9, a kind of low-frequency clock signal generation device is characterized in that comprising clock source and programmable logic device, wherein:
Clock source: regularly produce the source clock pulse signal and be sent to programmable logic device;
Programmable logic device: the period T of Shu Chu low-frequency clock signal as required
0Period T with the source clock pulse signal
sDetermine frequency N
1With divider ratio N
2After, the frequency that receives described source clock pulse signal is extended to N
1Be contracted to 1/N doubly
2Doubly, the frequency that perhaps will receive described source clock pulse signal is contracted to 1/N
2Be extended to N again doubly
1Doubly, to produce period T
0The source clock pulse signal.
10, low-frequency clock signal generation device as claimed in claim 9 is characterized in that, described clock source comprises timing device and trigger device, wherein:
The timing device, every through sending triggering signal to trigger once the time cycle that sets in advance;
Trigger device: whenever receive a triggering signal, shear just takes place in the signal of output.
11, low-frequency clock signal generation device as claimed in claim 10 is characterized in that, described timing device is ADM706, and trigger device is a programmable logic device.
12, low-frequency clock signal generation device as claimed in claim 10 is characterized in that, the output WDO of AMD706 connects the input WDI of programmable logic device and AMD706 respectively.
13, low-frequency clock signal generation device as claimed in claim 12 is characterized in that, AMD706 also connects a reset key.
14, low-frequency clock signal generation device as claimed in claim 9 is characterized in that programmable logic device further comprises:
Determining unit: in order to the period T of low-frequency clock signal of output as required
0Period T with the source clock pulse signal
sDetermine and preservation frequency N
1With divider ratio N
2Perhaps in order to obtain and to preserve frequency N from peripheral hardware
1With divider ratio N
2
Frequency divider: connect determining unit, in order to obtain divider ratio N from determining unit
2, the frequency of the source clock pulse signal that receives is contracted to 1/N
2Obtaining frequency doubly is 1/ (T
S* N
2) clock signal;
Frequency multiplier: connect frequency divider and determining unit, in order to obtain frequency N from determining unit
1, receiving from described frequency divider transmission frequency is 1/ (T
S* N
2) clock signal, and the frequency of described signal is extended to N
1Doubly, obtaining the described cycle is T
oLow-frequency clock signal output.
15, low-frequency clock signal generation device as claimed in claim 9 is characterized in that programmable logic device further comprises:
Determining unit: in order to the period T of low-frequency clock signal of output as required
0Period T with the source clock pulse signal
sDetermine frequency N
1With divider ratio N
2Perhaps in order to obtain and to preserve frequency N from peripheral hardware
1With divider ratio N
2
Frequency multiplier: connect determining unit, receiving the cycle that is sent by the clock source is T
SThe source clock pulse signal, and its frequency is extended to the N of primary frequency
1Doubly obtaining frequency is N
1/ T
SClock signal;
Frequency divider: connect frequency multiplier and determining unit, in order to obtain divider ratio N from determining unit
2, receiving from described frequency multiplier transmission frequency is N
1/ T
SClock signal, and the frequency of described clock signal is contracted to N
2Doubly back output, and then to obtain the described cycle be T
oLow-frequency clock signal.
16, low-frequency clock signal generation device as claimed in claim 9 is characterized in that, described programmable logic device is one of them among PLD, the FPGA.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100564679A CN100456630C (en) | 2005-03-22 | 2005-03-22 | Low frequency clock signal generating method and low frequency cloc ksignal generator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100564679A CN100456630C (en) | 2005-03-22 | 2005-03-22 | Low frequency clock signal generating method and low frequency cloc ksignal generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1725629A true CN1725629A (en) | 2006-01-25 |
| CN100456630C CN100456630C (en) | 2009-01-28 |
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|---|---|---|---|
| CNB2005100564679A Expired - Fee Related CN100456630C (en) | 2005-03-22 | 2005-03-22 | Low frequency clock signal generating method and low frequency cloc ksignal generator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101888299A (en) * | 2010-06-22 | 2010-11-17 | 中兴通讯股份有限公司 | Method and device for implementing display mode switching by low-frequency clock |
| CN101710814B (en) * | 2009-12-25 | 2011-12-14 | 青岛朗讯科技通讯设备有限公司 | Method for generating random frequency pulse and method for controlling acceleration and deceleration of stepper motor |
| CN106066660A (en) * | 2016-05-13 | 2016-11-02 | 江苏省新沂地震台 | A kind of frequency and amplitude program-controlled low-frequency sine reference signal production method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103618501A (en) * | 2013-11-13 | 2014-03-05 | 哈尔滨电工仪表研究所 | Alternating current sampling synchronous frequency multiplier based on FPGA |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05243853A (en) * | 1992-03-02 | 1993-09-21 | Fujitsu Ltd | Frequency multiplier equipment |
| JPH11110065A (en) * | 1997-10-03 | 1999-04-23 | Mitsubishi Electric Corp | Internal clock signal generating circuit |
| JP3977591B2 (en) * | 2000-04-27 | 2007-09-19 | 株式会社東芝 | Frequency multiplication circuit and semiconductor integrated circuit |
| CN1211929C (en) * | 2002-01-30 | 2005-07-20 | 威盛电子股份有限公司 | Low power consumption high frequency time pulse generator |
-
2005
- 2005-03-22 CN CNB2005100564679A patent/CN100456630C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101710814B (en) * | 2009-12-25 | 2011-12-14 | 青岛朗讯科技通讯设备有限公司 | Method for generating random frequency pulse and method for controlling acceleration and deceleration of stepper motor |
| CN101888299A (en) * | 2010-06-22 | 2010-11-17 | 中兴通讯股份有限公司 | Method and device for implementing display mode switching by low-frequency clock |
| CN106066660A (en) * | 2016-05-13 | 2016-11-02 | 江苏省新沂地震台 | A kind of frequency and amplitude program-controlled low-frequency sine reference signal production method |
| CN106066660B (en) * | 2016-05-13 | 2019-01-04 | 江苏省新沂地震台 | A kind of frequency and the program-controlled low-frequency sine reference signal production method of amplitude |
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| Publication number | Publication date |
|---|---|
| CN100456630C (en) | 2009-01-28 |
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