CN116667821B - Method, circuit, device and control equipment for generating multiple PWM signals with different phases - Google Patents
Method, circuit, device and control equipment for generating multiple PWM signals with different phases Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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Abstract
The invention relates to the field of signal generation, in particular to a method, a circuit, a device and control equipment for generating multiple PWM signals with different phases. The method for generating the multipath PWM signals with different phases comprises the following steps: setting the number N of output signals; changing the voltage state of the ith intermediate signal when the ith rising edge or falling edge of the input signal is detected, and changing the voltage state of the ith intermediate signal when the (i+1) th rising edge or falling edge of the input signal is detected; performing logic operation on the ith intermediate signal and the input signal to obtain an output signal PWM-Oi; adding 1 to i; repeating the steps until i is greater than N; setting i to 1; repeating the steps to obtain N output signals PWM-Oi; wherein i is the ordinal number of the rising edge or the falling edge of the input signal PWM-IN, and the initial value of i is 1. The invention solves the problem of generating multiple PWM signals with different phases through one PWM signal.
Description
Technical Field
The invention relates to the field of signal generation, in particular to a method, a circuit, a device and control equipment for generating multiple PWM signals with different phases.
Background
PWM stands for pulse width modulation (Pulse Width Modulation), a modulation technique. It represents or controls a particular parameter by varying the pulse width of the signal. PWM is commonly used for controlling current, voltage, rotation speed, etc., and in electronic circuits, power sources for outputting energy, such as constant current sources, constant voltage sources, etc., generally need PWM signals for controlling the energy conversion switch circuit. By changing the duty ratio of PWM, the output current or voltage can be controlled, and the purpose of precise control and regulation is achieved.
At present, a path of PWM signal is generally used in the power supply to control the energy conversion switch circuit. One PWM signal means only one energy conversion switch circuit. If the output power becomes large, the output current or voltage becomes large, and the circuit heat generation becomes large. In order to protect the normal operation of the circuit, a post-stage device with a large current parameter is required, and the post-stage device with the large current parameter tends to increase the volume of the circuit. If multiple PWM signals of different phases can be used, the output energy can be output through the multiplexing switch circuit. Although the number of paths is increased, smaller circuit devices can be used, and the design difficulty of the circuit is reduced.
How to generate multiple PWM signals with different phases by one PWM signal is a problem to be solved.
Disclosure of Invention
Based on this, it is necessary to provide a multi-path different-phase PWM signal generation method, circuit, device, and control apparatus in view of the above-described problems.
The embodiment of the invention is realized in such a way that the method for generating the multi-path PWM signals with different phases comprises the following steps:
s101, setting the number N of output signals;
s102, changing the voltage state of an ith intermediate signal PWM-i when the ith rising edge or falling edge of the input signal PWM-IN is detected, and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected;
s103, performing logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
s104, adding 1 to i;
s105, repeating S102-S104 until i is greater than N;
s106, setting i to 1;
s107, repeating S102-S106, and repeating S102-S106 each time to obtain N output signals PWM-Oi;
wherein i is the ordinal number of the rising edge or the falling edge of the input signal PWM-IN, and the initial value of i is 1.
In one embodiment, the present invention provides a multi-path out-of-phase PWM signal generation circuit comprising a logic processing circuit and an arithmetic logic module;
the logic processing circuit is used for changing the voltage state of the ith intermediate signal PWM-i when the ith rising edge or the falling edge of the input signal PWM-IN is detected, changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or the falling edge of the input signal PWM-IN is detected, and accumulating, judging and setting the i;
the arithmetic logic module is connected with the logic processing circuit and is used for carrying out logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi.
In one embodiment, the present invention provides a multi-path different phase PWM signal generating apparatus, comprising:
the setting number module is used for setting the number N of the output signals;
the intermediate signal module is used for changing the voltage state of the ith intermediate signal PWM-i when the ith rising edge or falling edge of the input signal PWM-IN is detected, and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected;
the input signal module is used for carrying out logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
the accumulation ordinal number module is used for adding 1 to i;
the ordinal number judging module is used for repeating S102-S104 until i is larger than N;
the reset ordinal module is used for setting i to 1.
In one embodiment, the present invention provides a control device, including a memory and a processor, where the memory stores a software program, and the software program when executed by the processor causes the processor to execute the steps of the above-mentioned multiple different-phase PWM signal generating method.
According to the method for generating the multi-channel PWM signals with different phases, the rising edge or the falling edge of the input signal PWN-IN is used as a trigger signal, counting is carried out, an intermediate signal is generated, each intermediate signal and the input signal PWM-IN are subjected to logic operation, multi-channel PWM output signals with different phases are generated, the generated multi-channel PWM signals with different phases are rectified and filtered, and then combined output is identical to the output of the input signal PWM-IN after rectification and filtration, so that the problem that multi-channel PWM signals with different phases are generated through one channel of PWM signals is solved.
Drawings
FIG. 1 is a flow chart of a method for generating multiple PWM signals with different phases in one embodiment;
FIG. 2 is a partial signal diagram of an output PWM signal when N is equal to 2 in one embodiment;
FIG. 3 is a partial signal diagram of an output PWM signal when N is equal to 3 in one embodiment;
FIG. 4 is a circuit diagram of a multi-path different phase PWM signal generation circuit in one embodiment;
FIG. 5 is a circuit diagram of a portion of a multi-path different phase PWM signal generation circuit according to one embodiment;
FIG. 6 is a block diagram illustrating a configuration of a multi-path different phase PWM signal generating apparatus according to one embodiment;
fig. 7 is a block diagram showing an internal structure of the control device in one embodiment.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms unless otherwise specified. These terms are only used to distinguish one element from another element. For example, a first xx script may be referred to as a second xx script, and similarly, a second xx script may be referred to as a first xx script, without departing from the scope of this disclosure.
As shown in fig. 1, in one embodiment, a method for generating multiple PWM signals with different phases is provided, which specifically includes the following steps:
s101, setting the number N of output signals;
s102, changing the voltage state of an ith intermediate signal PWM-i when the ith rising edge or falling edge of the input signal PWM-IN is detected, and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected;
s103, performing logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
s104, adding 1 to i;
s105, repeating S102-S104 until i is greater than N;
s106, setting i to 1;
s107, repeating S102-S106, and repeating S102-S106 each time to obtain N output signals PWM-Oi;
wherein i is the ordinal number of the rising edge or the falling edge of the input signal PWM-IN, and the initial value of i is 1.
IN this embodiment, detecting the i-th rising edge or falling edge of the input signal PWM-IN, changing the voltage state of the i-th intermediate signal PWM-i refers to using the rising edge or falling edge of the input signal PWM-IN as a trigger signal, and changing the voltage state of the i-th intermediate signal PWM-i when the trigger signal occurs.
IN this embodiment, as shown IN fig. 2, the voltage state of the ith intermediate signal PWM-i is changed, and the rising edge of the input signal PWM-IN may be used as the trigger signal, or the falling edge of the input signal PWM-IN may be used as the trigger signal, but only one of them may be selected as the trigger signal.
In this embodiment, the rising edge or the falling edge is selected as the trigger signal, and the final output PWM signals are combined and output after rectifying and filtering.
In this embodiment, the voltage state of the PWM signal is only two states of high level and low level, so the voltage state returns to the initial state after two changes.
IN this embodiment, the logic operation means that the real-time voltage state of the intermediate signal PWM-i and the real-time voltage state of the input signal PWM-IN are logically operated.
IN this embodiment, as shown IN fig. 3, when i is greater than N, the rising edge or the falling edge of the input signal PWM-IN is counted again, for example, if N is equal to 3 and the rising edge is selected as the trigger signal, the rising edge of the input signal PWM-IN is always cycled with the ordinal numbers of 1, 2 and 3.
IN this embodiment, as shown IN fig. 3, each time S102 to S106 obtain N output signals, which are continuous signals IN time of the N output signals obtained IN the previous repetition step, for example, N is 3, the 3 output signals obtained IN the first repetition step are PWM-O1, PWM-O2 and PWM-O3, respectively, and the time is 1 st to 3 rd periods of the output signal PWM-IN, then the 3 output signals obtained IN the second repetition step are still PWM-O1, PWM-O2 and PWM-O3, and the time is changed to 4 th to 6 th periods of the output signal PWM-IN.
In the present embodiment, as shown in fig. 2, when N is equal to 2, the period of the output signal is 2 times that of the input signal, the duty ratio is 1/2 of that of the input signal, and if the input voltage is 12V, each output voltage is 6V; as shown in fig. 3, when N is equal to 3, the period of the output signal is 3 times that of the input signal, the duty ratio is 1/3 of that of the input signal, and if the input voltage is 12V, each output voltage is 4V; similarly, the voltage of each output signal is 1/N of the voltage of the input signal.
According to the method for generating the multi-channel PWM signals with different phases, the rising edge or the falling edge of the input signal PWN-IN is used as a trigger signal, counting is carried out, an intermediate signal is generated, each intermediate signal and the input signal PWM-IN are subjected to logic operation, multi-channel PWM output signals with different phases are generated, the generated multi-channel PWM signals with different phases are rectified and filtered, and then combined output is identical to the output of the input signal PWM-IN after rectification and filtration, so that the problem that multi-channel PWM signals with different phases are generated through one channel of PWM signals is solved.
IN one embodiment, when the ith rising edge or falling edge of the input signal PWM-IN is detected, changing the voltage state of the ith intermediate signal PWM-i includes:
judging whether the input signal PWM-IN is IN the ith rising edge or falling edge state, if so, changing the ith intermediate signal PWM-i from a first level to a second level;
wherein the first level and the second level are opposite to each other.
In this embodiment, as shown in fig. 2, the voltage state of the PWM signal has only two states of high level and low level, and the high level and the low level are opposite to each other, so that the first level and the second level are opposite to each other, for example, if the first level is the low level, the second level is the high level, and if the first level is the high level, the second level is the low level.
IN this embodiment, as shown IN fig. 2, if the rising edge of the input signal PWM-IN is used as the trigger signal and the first level is low, the instant when the intermediate signal changes from the first level to the second level is the rising edge of the intermediate signal, and the rising edge of the intermediate signal is synchronous with the rising edge of the input signal PWM-IN.
IN one embodiment, when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected, changing the voltage state of the (i) th intermediate signal PWM-i includes:
when the ith intermediate signal PWM-i is at the second level, judging whether the input signal PWM-IN is IN the (i+1) th rising edge or falling edge state, and if so, changing the ith intermediate signal PWM-i from the second level to the first level.
IN the present embodiment, as shown IN fig. 2, if the transition of the intermediate signal from the first level to the second level is to use the i-th rising edge of the input signal PWM-IN as the trigger signal, only the rising edge can be used as the trigger signal IN the entire process.
IN the present embodiment, as shown IN fig. 2, if the rising edge of the input signal PWM-IN is used as the trigger signal and the first level is the low level, the high level duration of each PWM intermediate signal is equal to one period of PWM-IN.
IN one embodiment, the logic operation of the ith intermediate signal PWM-i and the input signal PWM-IN to obtain the output signal PWM-Oi includes:
for any moment, acquiring the voltage state of the ith intermediate signal PWM-i and the voltage state of the input signal PWM-IN at the moment;
performing AND logic operation on the obtained voltage state of the ith intermediate signal PWM-i and the voltage state of the input signal PWM-IN;
and generating an output signal PWM-Oi corresponding to the ith intermediate signal PWM-i.
In this embodiment, as shown in fig. 2, the and logic operation outputs a high level only when both voltage states are high, and outputs a low level when the voltage state is high and the voltage state is low or when both voltage states are low.
IN this embodiment, the nature of the output signal is such that the input signal PWM-IN outputs a periodic square wave every N-1 cycles.
In one embodiment, the multi-path different phase PWM signal generation circuit includes a logic processing circuit and an arithmetic logic module;
the logic processing circuit is used for changing the voltage state of the ith intermediate signal PWM-i when the ith rising edge or the falling edge of the input signal PWM-IN is detected, changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or the falling edge of the input signal PWM-IN is detected, and accumulating, judging and setting the i;
the arithmetic logic module is connected with the logic processing circuit and is used for carrying out logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi.
IN this embodiment, as shown IN fig. 4, the input signal PWM-IN is output after passing through the logic processing circuit, and the intermediate signal is output after performing an and logic operation with the input signal PWM-IN through the arithmetic logic module.
In this embodiment, 1 arithmetic logic block can generate 2 output signals, and the value of N cannot exceed twice that of the arithmetic logic block, for example, two arithmetic logic blocks can generate 4 output signals, and the value of N cannot be greater than 4.
The multi-channel different-phase PWM signal generating circuit provided by the embodiment of the invention counts through the input signal PWN-IN and generates the intermediate signals, each intermediate signal and the input signal PWM-IN are subjected to logic operation to generate multi-channel different-phase PWM output signals, the generated multi-channel different-phase PWM signals are rectified and filtered and then combined to output the same as the input signal PWM-IN after rectification and filtering, and the problem that multi-channel different-phase PWM signals are generated through one channel of PWM signals is solved.
In one embodiment, the logic processing circuit includes a counting module and a trigger circuit;
the counting module is connected with the trigger circuit and is used for accumulating, judging and setting i;
the trigger circuit is connected with the arithmetic logic module and is used for changing the voltage state of the ith intermediate signal PWM-i when the ith rising edge or the falling edge of the input signal PWM-IN is detected and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or the falling edge of the input signal PWM-IN is detected.
IN this embodiment, as shown IN fig. 4, the counter detects the rising edge or the falling edge of the input signal PWM-IN, and performs accumulation, judgment and setting of i.
IN this embodiment, the counter controls the on-off of the corresponding flip-flop circuits to generate multiple paths of PWM signals, for example, when N is equal to 4, the counter gates the first flip-flop circuit IN the 1 st to 2 nd period of the input signal PWM-IN to generate the output signals PWM-O1 and PWM-O2, and gates the second flip-flop circuit IN the 3 rd to 4 th period of the input signal PWM-IN to generate the output signals PWM-O3 and PWM-O4.
In one embodiment, for output signal PWM-i and output signal PWM- (i+1), the flip-flop circuit includes a chip U1 and an inverter U2A;
the output pin of the chip U1 is connected with the input pin of the inverter U2A, and the input pin is connected with the output pin of the inverter U2A and is used for obtaining an ith intermediate signal PWM-i;
the inverter U2A is used for obtaining an i+1th intermediate signal PWM- (i+1).
IN this embodiment, as shown IN fig. 5, when N is equal to 2, the input signal PWM-IN is used as the clock signal of the chip U1, and when the counter gates the flip-flop, i.e. the \oe pin of the chip U1 is turned on, the chip U1 generates the output signal PWM-1, and the output signal PWM-1 passes through the inverter U2A to generate the output signal PWM-2.
In this embodiment, 1 flip-flop circuit can generate 2 intermediate signals, and the number of flip-flop circuits and the number of arithmetic logic blocks are identical, so that the value of N is related to the flip-flop circuits, for example, when N is equal to 2, there are at least 1 flip-flop circuits, and when N is equal to 3 and 4, there are at least 2 flip-flop circuits.
In one embodiment, for output signal PWM-i and output signal PWM- (i+1), the arithmetic logic module includes a chip U3 and a chip U4;
the first input pin of the chip U3 is connected with the output pin of the chip U1, and the second input pin is connected with the input signal PWM-IN and is used for carrying out logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
the first input pin of the chip U4 is connected with the input pin of the chip U1, and the second input pin is connected with the input signal PWM-IN, and is used for carrying out logic operation on the (i+1) th intermediate signal PWM- (i+1) and the input signal PWM-IN to obtain an output signal PWM-O (i+1).
In this embodiment, as shown in fig. 5, the chip U3 and the chip U4 are the same device, and the functions are the same.
IN this embodiment, for both the chip U3 and the chip U4, the second input pin is connected to the input signal PWM-IN, the first input pin is connected to the intermediate signal, and the resulting output signal is dependent on the intermediate signal.
In this embodiment, if N is equal to 3, for the second arithmetic logic module, only the corresponding chip U3 needs to have the intermediate signal input to generate the output signal, and the 4 th intermediate signal PWM-4 is not generated at this time, so the corresponding chip U4 does not need to work, that is, the output signal PWM-O4 is not generated.
As shown in fig. 6, in one embodiment, a multi-path PWM signal generating apparatus with different phases is provided, which may specifically include:
the setting number module is used for setting the number N of the output signals;
the intermediate signal module is used for changing the voltage state of the ith intermediate signal PWM-i when the ith rising edge or falling edge of the input signal PWM-IN is detected, and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected;
the input signal module is used for carrying out logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
the accumulation ordinal number module is used for adding 1 to i;
the ordinal number judging module is used for repeating S102-S104 until i is larger than N;
the reset ordinal module is used for setting i to 1.
In this embodiment, each module of the multi-path PWM signal generating apparatus with different phases is modularized in the method of the present invention, and for specific explanation of each module, please refer to the corresponding content of the method of the present invention, the embodiments of the present invention are not described herein again.
Fig. 7 shows an internal structural diagram of the control device in one embodiment. As shown in fig. 7, the control device includes a processor, a memory, an input interface, and an output interface connected by a system bus. The memory includes a nonvolatile storage medium and an internal memory. The non-volatile storage medium of the control device stores an operating system and may also store a software program, which when executed by the processor, causes the processor to implement the multi-path different-phase PWM signal generation method provided by the embodiment of the present invention. The internal memory may also store a software program, which when executed by the processor, causes the processor to execute the multi-path different-phase PWM signal generating method provided by the embodiments of the present invention.
It will be appreciated by those skilled in the art that the structure shown in fig. 7 is merely a block diagram of a portion of the structure associated with the present inventive arrangements and is not limiting of the control device to which the present inventive arrangements are applied, and that a particular control device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, the multiple different phase PWM signal generating apparatus provided in the embodiments of the present invention may be implemented in a software program, which may be executed on a control device as shown in fig. 7. The memory of the control device may store various program modules constituting the multiple PWM signal generating devices with different phases, for example, a set number module, an intermediate signal module, an input signal module, an accumulated ordinal number module, a determine ordinal number module, and a reset ordinal number module shown in fig. 6. The software program constituted by the respective program modules causes the processor to execute the steps in the multi-path different-phase PWM signal generation method of the respective embodiments of the present invention described in the present specification.
For example, the control apparatus shown in fig. 7 may perform step S101 by a set number module in the multi-path different-phase PWM signal generation device shown in fig. 6; the control device may execute step S102 through the intermediate signal module; the control device may execute step S103 through the input signal module; the control device may execute step S104 through the accumulated ordinal module; the control device may execute step S105 by determining an ordinal number module; the control device may perform step S106 by resetting the ordinal module.
In one embodiment, a control device is provided, the control device comprising a memory, a processor and a software program stored on the memory and executable on the processor, the processor implementing the following steps when executing the software program:
s101, setting the number N of output signals;
s102, changing the voltage state of an ith intermediate signal PWM-i when the ith rising edge or falling edge of the input signal PWM-IN is detected, and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected;
s103, performing logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
s104, adding 1 to i;
s105, repeating S102-S104 until i is greater than N;
s106, setting i to 1;
s107, repeating S102-S106, and repeating S102-S106 each time to obtain N output signals PWM-Oi;
wherein i is the ordinal number of the rising edge or the falling edge of the input signal PWM-IN, and the initial value of i is 1.
In one embodiment, a control device readable storage medium is provided, the control device readable storage medium having stored thereon a software program which, when executed by a processor, causes the processor to perform the steps of:
s101, setting the number N of output signals;
s102, changing the voltage state of an ith intermediate signal PWM-i when the ith rising edge or falling edge of the input signal PWM-IN is detected, and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected;
s103, performing logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
s104, adding 1 to i;
s105, repeating S102-S104 until i is greater than N;
s106, setting i to 1;
s107, repeating S102-S106, and repeating S102-S106 each time to obtain N output signals PWM-Oi;
wherein i is the ordinal number of the rising edge or the falling edge of the input signal PWM-IN, and the initial value of i is 1.
It should be understood that, although the steps in the flowcharts of the embodiments of the present invention are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in various embodiments may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
Those skilled in the art will appreciate that implementing all or part of the above-described methods may be accomplished by way of a software program to instruct the associated hardware, where the program may be stored on a non-volatile control device readable storage medium, and the program, when executed, may include the steps of the above-described embodiments of the methods. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention.
Claims (10)
1. The method for generating the multiple different-phase PWM signals is characterized by comprising the following steps:
s101, setting the number N of output signals;
s102, changing the voltage state of an ith intermediate signal PWM-i when the ith rising edge or falling edge of the input signal PWM-IN is detected, and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected;
s103, performing logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
s104, adding 1 to i;
s105, repeating S102-S104 until i is greater than N;
s106, setting i to 1;
s107, repeating S102-S106, and repeating S102-S106 each time to obtain N output signals PWM-Oi;
wherein i is the ordinal number of the rising edge or the falling edge of the input signal PWM-IN, and the initial value of i is 1.
2. The method of generating multiple different phase PWM signals according to claim 1, wherein when the i-th rising edge or falling edge of the input signal PWM-IN is detected, changing the voltage state of the i-th intermediate signal PWM-i includes:
judging whether the input signal PWM-IN is IN the ith rising edge or falling edge state, if so, changing the ith intermediate signal PWM-i from a first level to a second level;
wherein the first level and the second level are opposite to each other.
3. The method for generating multiple different phase PWM signals according to claim 2, wherein when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected, changing the voltage state of the (i) th intermediate signal PWM-i comprises:
when the ith intermediate signal PWM-i is at the second level, judging whether the input signal PWM-IN is IN the (i+1) th rising edge or falling edge state, and if so, changing the ith intermediate signal PWM-i from the second level to the first level.
4. The method for generating multiple PWM signals with different phases according to claim 1, wherein the logic operation of the i-th intermediate signal PWM-i and the input signal PWM-IN to obtain the output signal PWM-Oi includes:
for any moment, acquiring the voltage state of the ith intermediate signal PWM-i and the voltage state of the input signal PWM-IN at the moment;
performing AND logic operation on the obtained voltage state of the ith intermediate signal PWM-i and the voltage state of the input signal PWM-IN;
and generating an output signal PWM-Oi corresponding to the ith intermediate signal PWM-i.
5. The multi-channel different-phase PWM signal generating circuit is characterized by comprising a logic processing circuit and an arithmetic logic module;
the logic processing circuit is used for changing the voltage state of the ith intermediate signal PWM-i when the ith rising edge or the falling edge of the input signal PWM-IN is detected, changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or the falling edge of the input signal PWM-IN is detected, and accumulating, judging and setting the i;
the arithmetic logic module is connected with the logic processing circuit and is used for carrying out logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
wherein i is the ordinal number of the rising edge or the falling edge of the input signal PWM-IN, the initial value of i is 1, i is reset to 1 when the accumulated value of i is larger than N, and N is the number of output signals.
6. The multi-path out-of-phase PWM signal generation circuit according to claim 5, wherein the logic processing circuit comprises a counting module and a flip-flop circuit;
the counting module is connected with the trigger circuit and is used for accumulating, judging and setting i;
the trigger circuit is connected with the arithmetic logic module and is used for changing the voltage state of the ith intermediate signal PWM-i when the ith rising edge or the falling edge of the input signal PWM-IN is detected and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or the falling edge of the input signal PWM-IN is detected.
7. The multi-path different-phase PWM signal generation circuit according to claim 6, wherein the flip-flop circuit includes a chip U1 and an inverter U2A for the output signal PWM-i and the output signal PWM- (i+1);
the output pin of the chip U1 is connected with the input pin of the inverter U2A, and the input pin is connected with the output pin of the inverter U2A and is used for obtaining an ith intermediate signal PWM-i;
the inverter U2A is used for obtaining an i+1th intermediate signal PWM- (i+1).
8. The multi-path out-of-phase PWM signal generation circuit according to claim 7, wherein for output signal PWM-i and output signal PWM- (i+1), the arithmetic logic module comprises a chip U3 and a chip U4;
the first input pin of the chip U3 is connected with the output pin of the chip U1, and the second input pin is connected with the input signal PWM-IN and is used for carrying out logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
the first input pin of the chip U4 is connected with the input pin of the chip U1, and the second input pin is connected with the input signal PWM-IN, and is used for carrying out logic operation on the (i+1) th intermediate signal PWM- (i+1) and the input signal PWM-IN to obtain an output signal PWM-O (i+1).
9. The device for generating the multiple PWM signals with different phases is characterized by comprising:
the setting number module is used for setting the number N of the output signals;
the intermediate signal module is used for changing the voltage state of the ith intermediate signal PWM-i when the ith rising edge or falling edge of the input signal PWM-IN is detected, and changing the voltage state of the ith intermediate signal PWM-i when the (i+1) th rising edge or falling edge of the input signal PWM-IN is detected;
the input signal module is used for carrying out logic operation on the ith intermediate signal PWM-i and the input signal PWM-IN to obtain an output signal PWM-Oi;
the accumulation ordinal number module is used for adding 1 to i;
the ordinal number judging module is used for repeating S102-S104 until i is larger than N;
a reset ordinal module for setting i to 1;
wherein i is the ordinal number of the rising edge or the falling edge of the input signal PWM-IN, and the initial value of i is 1.
10. A control device comprising a memory and a processor, the memory having stored therein a software program which, when executed by the processor, causes the processor to perform the steps of the multi-path out-of-phase PWM signal generation method according to any one of claims 1 to 4.
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