CN113987981B - Power-down time sequence control method, device and storage medium - Google Patents
Power-down time sequence control method, device and storage medium Download PDFInfo
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- CN113987981B CN113987981B CN202111141841.0A CN202111141841A CN113987981B CN 113987981 B CN113987981 B CN 113987981B CN 202111141841 A CN202111141841 A CN 202111141841A CN 113987981 B CN113987981 B CN 113987981B
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims description 75
- 238000004146 energy storage Methods 0.000 claims description 8
- 238000004590 computer program Methods 0.000 claims description 7
- 238000007599 discharging Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000012938 design process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The application relates to a power-down time sequence control method, a device and a storage medium. The method comprises the following steps: judging the type of a power-down circuit, wherein the type comprises a reset signal power-down circuit and a delay power-down circuit; and based on the type of the power-down circuit, adopting a control circuit corresponding to the type to perform power-down time sequence control on the power-down circuit. The method can enable the time sequence control of the power-down circuit to be more accurate and reliable, and simultaneously can give consideration to the power-down sequence of the chip reset signal.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a power-down timing control method, apparatus, and storage medium.
Background
In a general circuit design process, there are two main types of control of power on and power off time sequences of a circuit: the scheme is that the chip enable signal and the chip reset signal are converted by adopting the IO control power supply of the CPLD to meet the power-on and power-off time sequence requirement of the chip. In another scheme, the power-on time sequence is realized by gradually pushing the chip EN signal of the next stage by adopting the PG signal of the power chip and controlling the discharging speed of each circuit by the resistance value of the discharging resistor. The above schemes have the disadvantages of different degrees: the scheme one relates to CPLD control time sequence, the cost is higher, and the workload is larger; in the second scheme, the discharging resistor is controlled to be powered down, the time sequence is inaccurate, and the power down sequence of the chip reset signal cannot be considered.
Disclosure of Invention
Based on this, it is necessary to provide a power-down time sequence control method, a device and a storage medium for solving the above technical problems, so that the time sequence control of the power-down circuit is more accurate and reliable, and the power-down sequence of the chip reset signal can be considered.
In one aspect, a power-down timing control method is provided, the method including:
judging the type of a power-down circuit, wherein the type comprises a reset signal power-down circuit and a delay power-down circuit;
and based on the type of the power-down circuit, adopting a control circuit corresponding to the type to perform power-down time sequence control on the power-down circuit.
In one embodiment, the method comprises:
if the type is a reset signal powering-down circuit, enabling a first control circuit to perform powering-down time sequence control on the reset signal powering-down circuit;
and if the type is a delay power-down circuit, enabling a second control circuit to perform power-down time sequence control on the delay power-down circuit.
In one embodiment, the method comprises:
the first control circuit detects the power supply voltage of the circuit under the reset signal in real time, and when the power supply voltage is smaller than a preset voltage threshold value, the switch of the reset signal is pulled to a grounding state.
In one of the embodiments of the present invention,
the first control circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a third capacitor; the first resistor and the second resistor are connected in series, and the first capacitor, the second capacitor and the third capacitor are connected in parallel; the third resistor is connected between the first capacitor and the second capacitor.
In one of the embodiments of the present invention,
the second control circuit comprises a tank circuit and a diode, and the tank circuit and the diode are connected in series.
In one of the embodiments of the present invention,
the energy storage circuit comprises a plurality of capacitors, and the capacitors are connected in parallel.
In another aspect, there is provided a power-down timing control apparatus, the apparatus comprising:
the judging module is used for judging the type of the power-down circuit, wherein the type comprises a reset signal power-down circuit and a delay power-down circuit;
and the control module is used for controlling the power-down time sequence of the power-down circuit by adopting the control circuit corresponding to the type based on the type of the power-down circuit.
In one embodiment, the control module is configured to:
if the type is a reset signal powering-down circuit, enabling a first control circuit to perform powering-down time sequence control on the reset signal powering-down circuit;
and if the type is a delay power-down circuit, enabling a second control circuit to perform power-down time sequence control on the delay power-down circuit.
In one of the embodiments of the present invention,
the first control circuit detects the power supply voltage of the circuit under the reset signal in real time, and when the power supply voltage is smaller than a preset voltage threshold value, the switch of the reset signal is pulled to a grounding state.
In yet another aspect, a computer readable storage medium is provided, having stored thereon a computer program which when executed by a processor performs the steps of:
judging the type of a power-down circuit, wherein the type comprises a reset signal power-down circuit and a delay power-down circuit;
and based on the type of the power-down circuit, adopting a control circuit corresponding to the type to perform power-down time sequence control on the power-down circuit.
According to the power-down time sequence control method, the power-down time sequence control device and the storage medium, the power-down time sequence control is performed on the power-down circuit based on the type of the power-down circuit by judging the type of the power-down circuit, so that the time sequence control of the power-down circuit is more accurate and reliable, and meanwhile, the power-down sequence of the chip reset signal can be considered.
Drawings
FIG. 1 is a flowchart of a power-down timing control method according to an embodiment;
FIG. 2 is a circuit diagram of a first control circuit in one embodiment;
FIG. 3 is a circuit diagram of a second control circuit in one embodiment;
FIG. 4 is a block diagram of a power down timing control apparatus according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, a power-down timing control method is provided, the method comprising:
s1: and judging the type of the power-down circuit, wherein the type comprises a reset signal power-down circuit and a delay power-down circuit.
In this step, the types of the power-down circuits include a reset signal power-down circuit and a delay power-down circuit, wherein the reset signal power-down circuit refers to a circuit requiring input and output of a reset signal, and the delay power-down circuit refers to a circuit requiring delay power-down.
After receiving the power-down instruction, executing the judging operation of the type of the power-down circuit, and transmitting a judging result to a module with a function of controlling the power-down time sequence.
S2: and based on the type of the power-down circuit, adopting a control circuit corresponding to the type to perform power-down time sequence control on the power-down circuit.
Different power-down circuit types have different requirements on power-down time delay, the reset signal power-down circuit needs to be powered down quickly, and the time delay power-down circuit needs to be powered down in a time delay mode.
According to the power-down time sequence control method, the power-down time sequence control is carried out on the power-down circuit based on the type of the power-down circuit by judging the type of the power-down circuit, so that the time sequence control of the power-down circuit is more accurate and reliable, and meanwhile, the power-down sequence of the chip reset signals can be considered.
In one embodiment, the method comprises:
if the type is a reset signal powering-down circuit, enabling a first control circuit to perform powering-down time sequence control on the reset signal powering-down circuit;
and if the type is a delay power-down circuit, enabling a second control circuit to perform power-down time sequence control on the delay power-down circuit.
Specifically, the control circuit corresponding to the type of the power-down circuit comprises a first control circuit and a second control circuit.
For the reset signal power-down circuit, the first control circuit capable of realizing quick power-down is started to perform power-down time sequence control on the reset signal power-down circuit, so that quick power-down is achieved.
For the delay power-down circuit, the delay power-down circuit is required, and then a second control circuit capable of realizing delay power-down is started to perform power-down time sequence control on the delay power-down circuit, so that delay power-down is achieved.
In one embodiment, the method comprises:
the first control circuit detects the power supply voltage of the circuit under the reset signal in real time, and when the power supply voltage is smaller than a preset voltage threshold value, the switch of the reset signal is pulled to a grounding state.
Specifically, when the first control circuit detects that the power supply voltage drops to a certain preset threshold value, the switch of the reset signal is pulled to the ground, so that the power supply is rapidly discharged, the reset signal is pulled down before the power supply drops, and the requirements of the chip on the reset signal are met.
In one of the embodiments of the present invention,
the first control circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a third capacitor; the first resistor and the second resistor are connected in series, and the first capacitor, the second capacitor and the third capacitor are connected in parallel; the third resistor is connected between the first capacitor and the second capacitor.
Specifically, as shown in fig. 2, the first control circuit may be implemented as a potential detection circuit including a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, and a third capacitor C3; the first resistor R1 and the second resistor R2 are connected in series, and the first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected in parallel; the third resistor R3 is connected between the first capacitor C1 and the second capacitor C2. The potential detection circuit is connected to the S port of the chip.
In addition, fig. 2 further includes a reset signal output circuit and a discharging path, where the reset signal output circuit is composed of a resistor R4, a resistor R5 and a capacitor C4, one end of the resistor R4 is connected to the a port of the chip, the other end of the resistor R5 is connected to one end of the capacitor C4, and then connected to the power VCC, and the other end of the resistor R5 is connected to the other end of the capacitor C4 and then grounded. One end of a resistor R6 in the discharging path is connected to the port B0 of the chip, and the other end of the resistor R6 is connected with the GND port of the chip and then grounded. The B1 port of the chip is a reset signal input port.
In one of the embodiments of the present invention,
the second control circuit comprises a tank circuit and a diode, and the tank circuit and the diode are connected in series.
Specifically, for a circuit needing to be powered down by time delay, an energy storage circuit is added and a diode is connected in series, and the time delay power-down circuit can still maintain a power supply state for a period of time under the condition that other circuits are powered down due to the energy storage characteristic of the energy storage circuit and the unidirectional conduction characteristic of the diode.
In one of the embodiments of the present invention,
the energy storage circuit comprises a plurality of capacitors, and the capacitors are connected in parallel.
Specifically, as shown in fig. 3, the tank circuit is implemented as a tank capacitor, which includes 5 capacitors, namely, capacitors C5, C6, C7, C8 and C9, and the 5 capacitors are connected in parallel. One end of each of the 5 parallel capacitors is grounded, the other end of each of the 5 parallel capacitors is connected with a diode D1 and a resistor R7 in series in sequence and then connected with a power supply VCC, and the diode D1 has the characteristic of unidirectional conduction.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or sub-steps of other steps.
In one embodiment, as shown in fig. 4, there is provided a power-down timing control apparatus, the apparatus comprising:
a judging module 401, configured to judge a type of a power-down circuit, where the type includes a reset signal power-down circuit and a delay power-down circuit;
and the control module 402 is configured to perform power-down timing control on the power-down circuit by using a control circuit corresponding to the type based on the type of the power-down circuit.
In one embodiment, the control module 402 is configured to:
if the type is a reset signal powering-down circuit, enabling a first control circuit to perform powering-down time sequence control on the reset signal powering-down circuit;
and if the type is a delay power-down circuit, enabling a second control circuit to perform power-down time sequence control on the delay power-down circuit.
In one of the embodiments of the present invention,
the first control circuit detects the power supply voltage of the circuit under the reset signal in real time, and when the power supply voltage is smaller than a preset voltage threshold value, the switch of the reset signal is pulled to a grounding state.
In one of the embodiments of the present invention,
the first control circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a third capacitor; the first resistor and the second resistor are connected in series, and the first capacitor, the second capacitor and the third capacitor are connected in parallel; the third resistor is connected between the first capacitor and the second capacitor.
In one of the embodiments of the present invention,
the second control circuit comprises a tank circuit and a diode, and the tank circuit and the diode are connected in series.
In one of the embodiments of the present invention,
the energy storage circuit comprises a plurality of capacitors, and the capacitors are connected in parallel.
For specific limitation of the power-down timing control apparatus, reference may be made to the limitation of the power-down timing control method hereinabove, and the description thereof will not be repeated. The above-mentioned various modules in the power-down timing control apparatus may be implemented in whole or in part by software, hardware, and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer readable storage medium is provided having stored thereon a computer program which when executed by a processor performs the steps of:
judging the type of a power-down circuit, wherein the type comprises a reset signal power-down circuit and a delay power-down circuit;
and based on the type of the power-down circuit, adopting a control circuit corresponding to the type to perform power-down time sequence control on the power-down circuit.
In one embodiment, the computer program when executed by the processor further performs the steps of:
if the type is a reset signal powering-down circuit, enabling a first control circuit to perform powering-down time sequence control on the reset signal powering-down circuit;
and if the type is a delay power-down circuit, enabling a second control circuit to perform power-down time sequence control on the delay power-down circuit.
In one embodiment, the computer program when executed by the processor further performs the steps of:
the first control circuit detects the power supply voltage of the circuit under the reset signal in real time, and when the power supply voltage is smaller than a preset voltage threshold value, the switch of the reset signal is pulled to a grounding state.
In one of the embodiments of the present invention,
the first control circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a third capacitor; the first resistor and the second resistor are connected in series, and the first capacitor, the second capacitor and the third capacitor are connected in parallel; the third resistor is connected between the first capacitor and the second capacitor.
In one of the embodiments of the present invention,
the second control circuit comprises a tank circuit and a diode, and the tank circuit and the diode are connected in series.
In one of the embodiments of the present invention,
the energy storage circuit comprises a plurality of capacitors, and the capacitors are connected in parallel.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (6)
1. A power down timing control method, the method comprising:
judging the type of a power-down circuit, wherein the type comprises a reset signal power-down circuit and a delay power-down circuit;
based on the type of the power-down circuit, adopting a control circuit corresponding to the type to perform power-down time sequence control on the power-down circuit;
if the type is a reset signal powering-down circuit, enabling a first control circuit to perform powering-down time sequence control on the reset signal powering-down circuit; the first control circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a third capacitor; the first resistor and the second resistor are connected in series, and the first capacitor, the second capacitor and the third capacitor are connected in parallel; the third resistor is connected between the first capacitor and the second capacitor;
if the type is a time delay power-down circuit, a second control circuit is started to perform power-down time sequence control on the time delay power-down circuit; the second control circuit comprises a tank circuit and a diode, and the tank circuit and the diode are connected in series.
2. The method of claim 1, wherein the method comprises:
the first control circuit detects the power supply voltage of the circuit under the reset signal in real time, and when the power supply voltage is smaller than a preset voltage threshold value, the switch of the reset signal is pulled to a grounding state.
3. The method of claim 1, wherein,
the energy storage circuit comprises a plurality of capacitors, and the capacitors are connected in parallel.
4. A power-down timing control apparatus, the apparatus comprising:
the judging module is used for judging the type of the power-down circuit, wherein the type comprises a reset signal power-down circuit and a delay power-down circuit;
the control module is used for performing power-down time sequence control on the power-down circuit by adopting a control circuit corresponding to the type based on the type of the power-down circuit;
if the type is a reset signal powering-down circuit, enabling a first control circuit to perform powering-down time sequence control on the reset signal powering-down circuit; the first control circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a third capacitor; the first resistor and the second resistor are connected in series, and the first capacitor, the second capacitor and the third capacitor are connected in parallel; the third resistor is connected between the first capacitor and the second capacitor;
if the type is a time delay power-down circuit, a second control circuit is started to perform power-down time sequence control on the time delay power-down circuit; the second control circuit comprises a tank circuit and a diode, and the tank circuit and the diode are connected in series.
5. The apparatus of claim 4, wherein,
the first control circuit detects the power supply voltage of the circuit under the reset signal in real time, and when the power supply voltage is smaller than a preset voltage threshold value, the switch of the reset signal is pulled to a grounding state.
6. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 3.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111141841.0A CN113987981B (en) | 2021-09-28 | 2021-09-28 | Power-down time sequence control method, device and storage medium |
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| CN202111141841.0A CN113987981B (en) | 2021-09-28 | 2021-09-28 | Power-down time sequence control method, device and storage medium |
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| CN113987981B true CN113987981B (en) | 2024-01-12 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110750378A (en) * | 2019-09-30 | 2020-02-04 | 山东信通电子股份有限公司 | Multi-power-supply power-off sequential circuit and power-off method |
| CN111490762A (en) * | 2020-06-23 | 2020-08-04 | 深圳市芯天下技术有限公司 | Novel power-on and power-off reset circuit |
| CN113246887A (en) * | 2021-06-09 | 2021-08-13 | 中国第一汽车股份有限公司 | Sequential circuit control method and device, electronic equipment and storage medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7304521B2 (en) * | 2005-01-28 | 2007-12-04 | Altera Corporation | Delay circuit for synchronizing arrival of a clock signal at different circuit board points |
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- 2021-09-28 CN CN202111141841.0A patent/CN113987981B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110750378A (en) * | 2019-09-30 | 2020-02-04 | 山东信通电子股份有限公司 | Multi-power-supply power-off sequential circuit and power-off method |
| CN111490762A (en) * | 2020-06-23 | 2020-08-04 | 深圳市芯天下技术有限公司 | Novel power-on and power-off reset circuit |
| CN113246887A (en) * | 2021-06-09 | 2021-08-13 | 中国第一汽车股份有限公司 | Sequential circuit control method and device, electronic equipment and storage medium |
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