CN110750378A - Multi-power-supply power-off sequential circuit and power-off method - Google Patents
Multi-power-supply power-off sequential circuit and power-off method Download PDFInfo
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- CN110750378A CN110750378A CN201910942279.8A CN201910942279A CN110750378A CN 110750378 A CN110750378 A CN 110750378A CN 201910942279 A CN201910942279 A CN 201910942279A CN 110750378 A CN110750378 A CN 110750378A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
Abstract
The application discloses many powers time sequence circuit and method of cutting off power supply, the circuit includes: the power supply monitoring circuit comprises a power supply monitoring circuit, a plurality of power-off sequential circuits and a plurality of power supplies; the plurality of power-down time sequence circuits are respectively connected with each power supply one by one, and the input ends of one or more first power-down time sequence circuits in the plurality of power-down time sequence circuits are connected with the voltage output end of the power supply monitoring circuit; when the first power-down time sequence circuit detects that the output voltage of the power supply monitoring circuit is different from the preset voltage value, the first power-down time sequence circuit firstly controls the power supply connected with the first power-down time sequence circuit to be powered down according to the preset delay time, and a second power-down time sequence circuit in the plurality of power-down time sequence circuits controls the power supply connected with the second power-down time sequence circuit to be powered down according to the preset delay time. According to the power supply monitoring circuit, each power supply in the power supply network can be controlled to be powered off according to the preset time sequence under the abnormal condition of the power supply monitoring circuit.
Description
Technical Field
The application relates to the technical field of electronic circuits, in particular to a multi-power-supply power-down sequential circuit and a power-down method.
Background
With the development of electronic circuits and chip technologies, power supplies with different voltage levels can be used in complex circuits, such as CPU chips in mobile phones and computers, and the power supply level for supplying power is often several to tens of.
In order to solve the problem of power-off management of a multi-power supply network, a power supply monitoring circuit is arranged in a product, and each power supply in the multi-power supply network is controlled to be powered off through the power supply monitoring circuit.
However, once the power monitoring circuit has a problem, the power supply controlled by the power monitoring circuit cannot be powered off actively, and if the power-off timing sequence of the critical power supply is abnormal, irreversible damage to the chip and the circuit device can be caused, so that the circuit board is directly damaged, and even more, the circuit board is burnt to cause fire.
Disclosure of Invention
In order to solve the above problems, the present application provides a multi-power-supply power-down sequence apparatus and a power-down method, which can control each power supply in a power supply network to power down according to a preset sequence when a power supply monitoring circuit is abnormal.
In a first aspect, an embodiment of the present application provides a multi-power-supply power-down sequential circuit, including: the power supply monitoring circuit comprises a power supply monitoring circuit, a plurality of power-off sequential circuits and a plurality of power supplies;
the plurality of power-down time sequence circuits are respectively connected with the power supplies one by one, and the input end of one or more first power-down time sequence circuits in the plurality of power-down time sequence circuits is connected with the voltage output end of the power supply monitoring circuit;
the plurality of power-down time sequence circuits are respectively connected with the power supplies one by one, and the input end of one or more first power-down time sequence circuits in the plurality of power-down time sequence circuits is connected with the voltage output end of the power supply monitoring circuit;
when the first power-off time sequence circuit detects that the output voltage of the power supply monitoring circuit is different from a preset voltage value, the first power-off time sequence circuit firstly controls the power supply connected with the first power-off time sequence circuit to be powered off according to preset delay time, a second power-off time sequence circuit in the plurality of power-off time sequence circuits controls the power supply connected with the second power-off time sequence circuit to be powered off according to the preset delay time, and the second power-off time sequence circuit is a power-off time sequence circuit of which the input end is not connected with the voltage output end of the power supply monitoring circuit and is connected with the voltage output end of the power supply.
In one example, the output end of each first power-down sequential circuit is respectively connected with an enabling pin of the power supply.
In one example, the input ends of a plurality of second power-down sequential circuits are respectively connected with the voltage output end of the first power supply;
the output end of each second power-off time sequence circuit is respectively connected with an enabling pin of a second power supply;
the second power supply is a power supply which is adjacent to the first power supply in power-down sequence and is behind the first power supply in power-down sequence.
In one example, the power down timing circuit includes: a detection circuit and a delay circuit;
for the first power-down sequence circuit, the input end of the detection circuit is connected with the voltage output end of the power supply monitoring circuit, and the output end of the detection circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with an enabling pin of the power supply;
for the second power-off sequential circuit, the input end of the detection circuit is connected with the voltage output end of the power supply, and the output end of the detection circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with an enabling pin of the power supply.
In one example, the detection circuit includes: a constant voltage power supply and a comparator;
one end of the constant voltage power supply is connected with the first input end of the comparator, and the other end of the constant voltage power supply is grounded;
the second input end of the comparator is connected with the voltage output end of the power supply monitoring circuit or the voltage output end of the power supply
In one example, the delay circuit includes: a delay resistor and a delay chip;
one end of the delay resistor is connected with the delay chip, and the other end of the delay resistor is grounded;
the input end of the delay chip is connected with the output end of the comparator, and the output end of the delay chip is connected with the enabling pin of the power supply.
In one example, the circuit further comprises: a shaping circuit;
the input end of the shaping circuit is connected with the output end of the delay chip, and the output end of the shaping circuit is connected with the enabling pin of the power supply.
In a second aspect, an embodiment of the present application provides a power supply power down method based on any of the circuits in the first aspect, including:
the detection circuit detects whether the output voltage of the power supply monitoring circuit is abnormal;
when the output voltage of the power supply monitoring circuit is abnormal, the detection circuit triggers the delay circuit;
the delay circuit generates a power-off signal when the current time reaches a preset power-off time node;
and the time delay circuit sends the power-off signal to a power supply enabling pin to control the power supply to be powered off.
In one example, the detection circuit includes: a constant voltage power supply and a comparator;
the comparator receives a voltage output signal of the power supply monitoring circuit;
the comparator determines whether the voltage of the power supply monitoring circuit is the same as the voltage of the constant voltage power supply or not according to the voltage output signal;
when the voltage of the power supply monitoring circuit is the same as the voltage of the constant voltage power supply, the comparator determines that the output voltage of the power supply monitoring circuit is normal;
when the voltage of the power supply monitoring circuit is different from the voltage of the constant voltage power supply, the comparator determines that the output voltage of the power supply monitoring circuit is abnormal.
In one example, the detection circuit detects whether an output voltage of the first power supply is abnormal;
when the output voltage of the first power supply is abnormal, the detection circuit triggers the delay circuit;
the time delay circuit controls a second power supply to be powered off, and the second power supply is a power supply which is adjacent to the first power supply in a power-off sequence and behind the first power supply in the power-off sequence. .
The embodiment of the application provides a multi-power-supply power-off sequential circuit, wherein the input end of the power-off sequential circuit is used for detecting whether the output voltage of a power supply or a power supply monitoring circuit is normal, and the output end of the power-off sequential circuit controls the power supply to power off according to a preset power-off sequential sequence according to the detection result of the input end. And meanwhile, the time sequence power-off circuit connected with the power supply monitoring circuit preferentially controls the power supply to be powered off so as to ensure that the power-off time sequence circuit can be triggered to control the power supply to be powered off only under the condition that the output voltage of the power supply monitoring circuit is abnormal. Therefore, under the condition that the power supply monitoring circuit is abnormal, the power-off time sequence circuits connected with the power supplies replace the power supply monitoring circuit to control the power supplies in the power supply network to power off according to the preset time sequence, and therefore the passive time-delay power-off operation of the power supplies is achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of a multi-power-down timing circuit according to an embodiment of the present disclosure;
FIG. 2 is a circuit diagram of a power down sequence circuit according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a power down method based on the circuits shown in fig. 1 and fig. 2 according to an embodiment of the present application.
Detailed Description
In order to more clearly explain the overall concept of the present application, the following detailed description is given by way of example in conjunction with the accompanying drawings.
An embodiment of the present application discloses a multi-power-supply power-down sequential circuit, as shown in fig. 1, including: the power supply monitoring circuit 100, the power-down sequence circuit 200 and the power supply 300, wherein the number of the power-down sequence circuit 200 and the power supply 300 is multiple.
As can be seen from the figure, the power-down sequence circuit 200 can be divided into a first power-down sequence circuit and a second power-down sequence circuit according to the connection relationship. The first power-down sequence circuit and the second power-down sequence circuit are only different in connection relationship, and functions of the circuits are the same.
Specifically, the input terminal of the first power-down sequence circuit is connected to the voltage output terminal of the power supply monitoring circuit, and is used for detecting whether the output voltage of the power supply monitoring circuit is normal. The output end of the first power-down time sequence circuit is connected with a power supply for controlling power-down, so that when the output voltage of the power supply monitoring circuit is abnormal, the first power-down time sequence circuit controls the corresponding power supply to power down.
The input end of the second power-off time sequence circuit is connected with the voltage output end of the power supply and is used for detecting whether the output voltage of the power supply is abnormal or not, and the output end of the second power-off time sequence circuit is connected with the power supply which controls power-off. In the embodiment of the present application, since each power supply is controlled to be powered down in time series, a second power-down sequence circuit is required to connect two power supplies adjacent in power-down time series. Therefore, once the power supply which is powered off firstly is powered off, the second power-off time sequence circuit finds that the output voltage of the power supply is abnormal, so that the power supply which is powered off later is controlled to be powered off, and further, the power supply which is powered off from multiple power supplies is powered off according to the preset time sequence.
In addition, the power-down sequence of the first power-down sequence circuit is prior to that of the second power-down sequence circuit, so that the power-down of each power supply is prevented from being triggered due to the abnormality of other power supplies. It should be noted that fig. 1 is a schematic diagram of the connection relationship among the power supply monitoring circuit 100, the power-down sequence circuit 200 and the power supply 300, and cannot be regarded as actual circuits of the power supply monitoring circuit 100, the power-down sequence circuit 200 and the power supply 300.
As shown in fig. 2, an embodiment of the present application discloses a power down sequence circuit, including: a detection circuit 210, a delay circuit 220 and a shaping circuit 230.
For the first power-down sequence circuit, the input end of the detection circuit 210 is connected to the voltage output end of the power monitoring circuit 100, and the output end of the detection circuit 210 is connected to the input end of the delay circuit 220; the output terminal of the delay circuit 220 is connected to the input terminal of the shaping circuit 230, and the output terminal of the shaping circuit 230 is connected to the enable pin of the power supply 300.
The detection circuit 210 is configured to detect whether the output voltage of the power supply monitoring circuit 100 is normal, the delay circuit 220 is configured to control the power-off time of the power supply, and the shaping circuit 230 is configured to shape the power-off signal generated by the delay circuit 220 to ensure the accuracy of the power-off signal.
For the second power-down sequential circuit, the input terminal of the detection circuit 210 is connected to the voltage output terminal of the power supply 300, and the output terminal of the detection circuit 210 is connected to the input terminal of the delay circuit 220; the output terminal of the delay circuit 220 is connected to the input terminal of the shaping circuit 230, and the output terminal of the shaping circuit 230 is connected to the enable pin of another power supply 300.
The detection circuit 210 is configured to detect whether the output voltage of the power supply 300 is normal, the delay circuit 220 is configured to control the power-down time of the power supply, and the shaping circuit 230 is configured to shape the power-down signal generated by the delay circuit 220 to ensure the accuracy of the power-down signal.
Specifically, the detection circuit 210 includes: a constant voltage power supply 211, and a comparator 212. The constant voltage source 211 has one end connected to the first input terminal of the comparator 212 and the other end grounded. For the first power-down sequence circuit, the second input terminal of the comparator 212 is connected to the voltage output terminal of the power monitoring circuit 100; for the second power down sequence, the second input of the comparator 212 is connected to the voltage output of the power supply 300. The output of comparator 212 is connected to the input of delay circuit 220. The comparator 212 is used to compare whether the input voltage is consistent with the voltage set by the constant voltage power supply 211, if so, the input voltage is normal, otherwise, the input voltage is abnormal.
A delay circuit 220, comprising: delay resistor 221 and delay chip 222. One end of the delay resistor 221 is connected to the delay chip 222, and the other end is grounded. The input end of the delay chip 222 is connected to the output end of the comparator 212, the output end of the delay chip 222 is connected to the input end of the shaping circuit 230, and the output end of the shaping circuit 230 is connected to the enable pin of the power supply 300. The delay chip 220 is preset with the power-down time of each power supply 300, and the power-down time of the delay chip 220 can be changed by adjusting the delay resistor 221. The power-down time can be set in a range of mS level to 10S level.
As shown in fig. 3, an embodiment of the present application provides a power down method based on the circuits shown in fig. 1 and fig. 2, including the following steps:
in step 301, the detection circuit 210 detects whether the output voltage of the power monitoring circuit 100 is abnormal.
In the embodiment of the present application, the detection circuit 210 includes: a constant voltage power supply 211, and a comparator 212.
The comparator 212 receives the voltage output signal of the power monitoring circuit 100. The comparator 212 determines whether the voltage of the power supply monitoring circuit 100 is the same as the voltage of the constant voltage power supply 211 based on the voltage-out signal. If so, the comparator 212 determines that the output voltage of the power monitoring circuit 100 is normal. Otherwise, the comparator 212 determines that the output voltage of the power monitoring circuit 100 is abnormal.
In order to realize the sequential power-down of multiple power supplies, in the embodiment of the present application, the detection circuit 210 detects whether the output voltage of the first power supply is abnormal. When the output voltage of the first power supply is abnormal, the detection circuit 210 triggers the delay circuit 220. The delay circuit 220 controls the second power supply to be powered down, where the second power supply is adjacent to the first power supply in the power-down sequence and is behind the first power supply in the power-down sequence.
Correspondingly, the comparator 212 receives the voltage output signal of the first power supply. The comparator 212 determines whether the voltage of the first power supply is the same as the voltage of the constant voltage power supply 211 based on the voltage-out signal. If so, the comparator 212 determines that the output voltage of the first power supply is normal. Otherwise, the comparator 212 determines that the output voltage of the first power supply is abnormal.
In this way, the detection circuit 210 and the delay circuit 220 are arranged between two power supplies adjacent to each power-off sequence, and the power-off circuits in the steps 301 and 302 are combined, so that the power-off circuit for sequentially powering off a plurality of power supplies can be formed by replacing the power supply monitoring circuit 100.
In the embodiment of the application, the power-off time of each power supply is set in advance
In the embodiment of the present application, in order to ensure that the down-signal is not mistaken as another signal by the power supply 300, the shaping circuit 230 is disposed between the delay circuit 220 and the power supply 300, and the shaping circuit 230 is configured to shape the down-signal into a relatively stable square wave, so as to ensure the accuracy of the down-signal.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A multi-power down sequencer circuit, comprising: the power supply monitoring circuit comprises a power supply monitoring circuit, a plurality of power-off sequential circuits and a plurality of power supplies;
the plurality of power-down time sequence circuits are respectively connected with the power supplies one by one, and the input end of one or more first power-down time sequence circuits in the plurality of power-down time sequence circuits is connected with the voltage output end of the power supply monitoring circuit;
when the first power-off time sequence circuit detects that the output voltage of the power supply monitoring circuit is different from a preset voltage value, the first power-off time sequence circuit firstly controls the power supply connected with the first power-off time sequence circuit to be powered off according to preset delay time, a second power-off time sequence circuit in the plurality of power-off time sequence circuits controls the power supply connected with the second power-off time sequence circuit to be powered off according to the preset delay time, and the second power-off time sequence circuit is a power-off time sequence circuit of which the input end is not connected with the voltage output end of the power supply monitoring circuit and is connected with the voltage output end of the power supply.
2. The circuit of claim 1,
and the output end of each first power-down time sequence circuit is respectively connected with an enabling pin of the power supply.
3. The circuit of claim 1 or 2,
the input ends of the second power-down sequential circuits are respectively connected with the voltage output end of the first power supply;
the output end of each second power-off time sequence circuit is respectively connected with an enabling pin of a second power supply;
the second power supply is a power supply which is adjacent to the first power supply in power-down sequence and is behind the first power supply in power-down sequence.
4. The circuit of claim 3,
the power down sequence circuit includes: a detection circuit and a delay circuit;
for the first power-down sequence circuit, the input end of the detection circuit is connected with the voltage output end of the power supply monitoring circuit, and the output end of the detection circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with an enabling pin of the power supply;
for the second power-off sequential circuit, the input end of the detection circuit is connected with the voltage output end of the power supply, and the output end of the detection circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with an enabling pin of the power supply.
5. The circuit of claim 4,
the detection circuit includes: a constant voltage power supply and a comparator;
one end of the constant voltage power supply is connected with the first input end of the comparator, and the other end of the constant voltage power supply is grounded;
and the second input end of the comparator is connected with the voltage output end of the power supply monitoring circuit or the voltage output end of the power supply.
6. The circuit of claim 5,
the delay circuit includes: a delay resistor and a delay chip;
one end of the delay resistor is connected with the delay chip, and the other end of the delay resistor is grounded;
the input end of the delay chip is connected with the output end of the comparator, and the output end of the delay chip is connected with the enabling pin of the power supply.
7. The circuit of claim 6, further comprising: a shaping circuit;
the input end of the shaping circuit is connected with the output end of the delay chip, and the output end of the shaping circuit is connected with the enabling pin of the power supply.
8. A method of powering down a power supply based on the circuit of any of claims 1 to 7, comprising:
the detection circuit detects whether the output voltage of the power supply monitoring circuit is abnormal;
when the output voltage of the power supply monitoring circuit is abnormal, the detection circuit triggers the delay circuit;
the delay circuit generates a power-off signal when the current time reaches a preset power-off time node;
and the time delay circuit sends the power-off signal to a power supply enabling pin to control the power supply to be powered off.
9. The method of claim 8,
the detection circuit detects whether the output voltage of the power monitoring circuit is abnormal, and comprises:
the detection circuit includes: a constant voltage power supply and a comparator;
the comparator receives a voltage output signal of the power supply monitoring circuit;
the comparator determines whether the voltage of the power supply monitoring circuit is the same as the voltage of the constant voltage power supply or not according to the voltage output signal;
when the voltage of the power supply monitoring circuit is the same as the voltage of the constant voltage power supply, the comparator determines that the output voltage of the power supply monitoring circuit is normal;
when the voltage of the power supply monitoring circuit is different from the voltage of the constant voltage power supply, the comparator determines that the output voltage of the power supply monitoring circuit is abnormal.
10. The method of claim 9, further comprising:
the detection circuit detects whether the output voltage of the first power supply is abnormal;
when the output voltage of the first power supply is abnormal, the detection circuit triggers the delay circuit;
the time delay circuit controls a second power supply to be powered off, and the second power supply is a power supply which is adjacent to the first power supply in a power-off sequence and behind the first power supply in the power-off sequence.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910942279.8A CN110750378A (en) | 2019-09-30 | 2019-09-30 | Multi-power-supply power-off sequential circuit and power-off method |
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| CN201910942279.8A CN110750378A (en) | 2019-09-30 | 2019-09-30 | Multi-power-supply power-off sequential circuit and power-off method |
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| CN113741252A (en) * | 2021-08-19 | 2021-12-03 | 武汉光迅科技股份有限公司 | Power-off time sequence control circuit of multi-power-supply system |
| CN113987981A (en) * | 2021-09-28 | 2022-01-28 | 苏州浪潮智能科技有限公司 | Power-off sequence control method, device and storage medium |
| CN114724527A (en) * | 2022-03-18 | 2022-07-08 | 海宁奕斯伟集成电路设计有限公司 | Time sequence control chip, time sequence control system, time sequence monitoring method and display |
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Application publication date: 20200204 |