TWM644193U - Discharge protection device - Google Patents
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本案涉及一種電子裝置。詳細而言,本案涉及一種放電保護裝置。This case involves an electronic device. Specifically, this case involves a discharge protection device.
現有電腦或筆電之主機板於移除直流電源供電後,主機板上電容殘餘之能量導致電壓下降過慢,且主機板之電源輸入端並無其他路徑可供電壓放電,而電源輸入端至主機板之間所殘餘的電荷,如無法被快速放電,將可能導致電腦或筆電開機時產生損壞及連接電腦或筆電之周邊設備產生錯誤。After the main board of an existing computer or notebook is removed from the DC power supply, the residual energy of the capacitor on the main board causes the voltage to drop too slowly, and there is no other path for the power input of the main board to discharge the voltage, and the power input to the If the residual charge between the main boards cannot be quickly discharged, it may cause damage to the computer or laptop when it is turned on and cause errors in the peripheral devices connected to the computer or laptop.
因此,上述技術尚存諸多缺陷,而有待本領域從業人員研發出其餘適合且快速放電的放電保護裝置。Therefore, the above-mentioned technology still has many defects, and practitioners in the field need to develop other suitable and fast-discharging discharge protection devices.
本案的一面向涉及一種放電保護裝置。放電保護裝置包含負載、電子保險晶片以及放電電路。電子保險晶片用以偵測外部電源之輸入電壓。若輸入電壓低於第一預設電壓,則電子保險晶片用以產生控制訊號。放電電路耦接於電子保險晶片及負載,並用以接受控制訊號,藉以根據控制訊號以將外部電源之輸入電壓引導至接地端。One aspect of this case relates to a discharge protection device. The discharge protection device includes a load, an electronic insurance chip and a discharge circuit. The electronic fuse chip is used to detect the input voltage of the external power supply. If the input voltage is lower than the first preset voltage, the electronic insurance chip is used to generate a control signal. The discharge circuit is coupled to the electronic fuse chip and the load, and is used to receive the control signal, so as to guide the input voltage of the external power supply to the ground terminal according to the control signal.
有鑑於前述之現有技術的缺點及不足,本案提供一種放電保護裝置,藉由放電保護裝置之內部電路設計,以監控或偵測外部電源輸入之電壓及電流,藉以保持負載(例如:主機板)穩定,並於外部電源復電時,使放電保護裝置之負載(例如:主機板)能正常運作。In view of the shortcomings and deficiencies of the aforementioned prior art, this case provides a discharge protection device, through the design of the internal circuit of the discharge protection device, to monitor or detect the voltage and current input by the external power supply, so as to maintain the load (for example: motherboard) Stable, and when the external power supply is restored, the load of the discharge protection device (such as: the motherboard) can operate normally.
以下將以圖式及詳細敘述清楚說明本案之精神,任何所屬技術領域中具有通常知識者在瞭解本案之實施例後,當可由本案所教示之技術,加以改變及修飾,其並不脫離本案之精神與範圍。The following will clearly illustrate the spirit of this case with drawings and detailed descriptions. Anyone with common knowledge in the technical field can change and modify the technology taught in this case after understanding the embodiment of this case. It does not depart from the spirit of this case. Spirit and scope.
本文之用語只為描述特定實施例,而無意為本案之限制。單數形式如“一”、“這”、“此”、“本”以及“該”,如本文所用,同樣也包含複數形式。The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the present case. Singular forms such as "a", "the", "the", "this" and "the", as used herein, also include plural forms.
關於本文中所使用之『包含』、『包括』、『具有』、『含有』等等,均為開放性的用語,即意指包含但不限於。"Includes", "including", "has", "containing" and so on used in this article are all open terms, meaning including but not limited to.
關於本文中所使用之用詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在本案之內容中與特殊內容中的平常意義。某些用以描述本案之用詞將於下或在此說明書的別處討論,以提供本領域技術人員在有關本案之描述上額外的引導。Regarding the terms (terms) used in this article, unless otherwise specified, generally have the ordinary meaning of each term used in this field, in the content of this case and in the special content. Certain terms used to describe the subject matter are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the subject matter.
第1圖為根據本案一些實施例繪示的放電保護裝置100之電路方塊示意圖。在一些實施例中,請參閱第1圖,放電保護裝置100包含負載110、放電電路120以及電子保險晶片130。在一些實施例中,放電保護裝置100為電腦或筆電。在一些實施例中,負載110為電腦內部之主機板或筆電內部之主機板。放電電路120耦接於負載110及電子保險晶片130。電子保險晶片130耦接於外部電源900。FIG. 1 is a schematic circuit block diagram of a
在一些實施例中,電子保險晶片130用以偵測外部電源900之輸入電壓(圖中未示)。若輸入電壓(圖中未示)低於第一預設電壓,則電子保險晶片130用以產生控制訊號(圖中未示)。放電電路120用以接受控制訊號(圖中未示),藉以根據控制訊號(圖中未示)以將外部電源900之輸入電壓(圖中未示)引導至接地端。In some embodiments, the
在一些實施例中,接地端包含電腦之外殼或筆電之外殼。In some embodiments, the ground terminal includes a casing of a computer or a casing of a laptop.
第2圖為根據本案一些實施例繪示的第1圖之放電保護裝置100之放電電路120及電子保險晶片130示意圖。在一些實施例中,放電電路120包含第一節點N1、第二節點N2、第一電晶體T1、第二電晶體T2、第一分壓電路121、第二分壓電路122及限流電路123。FIG. 2 is a schematic diagram of the
在一些實施例中,請參閱第2圖,並請以圖示中元件的上方及右方起算為第一端。第一電晶體T1包含第一端、第二端及控制端(即第一電晶體T1之閘極端G)。第一電晶體T1之第一端耦接於第二節點N2。第一電晶體T1之第二端耦接於接地端。第一電晶體T1之控制端耦接於第一節點N1,並用以響應第一節點N1之控制訊號CS之第一準位導通。In some embodiments, please refer to FIG. 2 , and count from the top and right of the components in the figure as the first end. The first transistor T1 includes a first terminal, a second terminal and a control terminal (ie, the gate terminal G of the first transistor T1 ). The first end of the first transistor T1 is coupled to the second node N2. The second end of the first transistor T1 is coupled to the ground end. The control terminal of the first transistor T1 is coupled to the first node N1, and is used for conducting in response to the first level of the control signal CS of the first node N1.
在一些實施例中,第二電晶體T2包含第一端、第二端及控制端(即第二電晶體T2之閘極端G)。第二電晶體T2之第一端耦接於負載110及電子保險晶片130。第二電晶體T2之第二端耦接於接地端。第二電晶體T2之控制端耦接於第二節點N2,並用以響應第二節點N2之第二準位導通。In some embodiments, the second transistor T2 includes a first terminal, a second terminal and a control terminal (ie, the gate terminal G of the second transistor T2 ). The first end of the second transistor T2 is coupled to the
在一些實施例中,第一分壓電路121耦接於第一節點N1及第一電晶體T1之控制端。第一分壓電路121用以接收輸入電壓Vin,以根據控制訊號CS之第一準位以調整輸入電壓Vin,藉以使第一電晶體T1導通或關閉。In some embodiments, the first voltage dividing
在一些實施例中,請參閱第2圖,第一分壓電路121包含電阻R1及電阻R2。電阻R1包含第一端及第二端。電阻R1之第一端用以接收輸入電壓Vin。電阻R1之第二端耦接於第一節點N1。電阻R2包含第一端及第二端。電阻R2之第一端耦接於第一節點N1。電阻R2之第二端耦接於接地端。電阻R1及電阻R2之電阻值可依據實際需求設計,並不以本案實施例為限。電阻R1及電阻R2為串聯。In some embodiments, please refer to FIG. 2 , the first voltage dividing
在一些實施例中,第二分壓電路122耦接於該第二節點N2、第一電晶體T1之第一端及第二電晶體T2之控制端,並用以接收輸入電壓Vin,以根據第二節點N2之第二準位以調整輸入電壓Vin。In some embodiments, the second
在一些實施例中,第二分壓電路122包含電阻R3及電阻R4。電阻R3包含第一端及第二端。電阻R3之第一端用以接收輸入電壓Vin。電阻R1之第二端耦接於第二節點N2。電阻R4包含第一端及第二端。電阻R4之第一端耦接於第二節點N2。電阻R2之第二端耦接於接地端。電阻R3及電阻R4之電阻值可依據實際需求設計,並不以本案實施例為限。電阻R3及電阻R4為串聯。In some embodiments, the second
在一些實施例中,限流電路123耦接於負載110、電子保險晶片130及第二電晶體T2之第一端,並用以偵測輸出電壓Vout。若輸出電壓Vout於負載110及電子保險晶片130之間形成電流超過預設電流時,則限流電路123用以斷開以形成斷路。In some embodiments, the current limiting
在一些實施例中,請參閱第2圖,限流電路123包含電阻R5及電阻R6。電阻R5包含第一端及第二端。電阻R6包含第一端及第二端。電阻R5之第一端及電阻R6之第一端皆耦接於負載110及電子保險晶片130。電阻R5之第二端及電阻R6之第二端皆耦接於第二電晶體T2之第一端。In some embodiments, please refer to FIG. 2 , the current limiting
在一些實施例中,電子保險晶片130包含電壓輸入引腳IN、電壓輸出引腳OUT及訊號輸出引腳PD。電壓輸入引腳IN耦接於外部電源900,並用以接收輸入電壓Vin。電壓輸出引腳OUT耦接於負載110,並用以根據輸入電壓Vin產生輸出電壓Vout至負載110。訊號輸出引腳PD耦接於放電電路120,並用以根據輸入電壓Vin產生控制訊號CS。在一些實施例中,電子保險晶片130包含電子保險絲(electronic fuse, e-fuse) 。在一些實施例中,電子保險晶片130包含複數種引腳(圖中未示),引腳之數量並不以圖式實施例為限。In some embodiments, the
在一些實施例中,若輸入電壓Vin高於第二預設電壓,電子保險晶片130關閉,以於外部電源900及負載110之間形成斷路。In some embodiments, if the input voltage Vin is higher than the second preset voltage, the
為使本案放電保護裝置100之放電電路120及電子保險晶片130之操作易於理解,請一併參閱第3圖至第4圖。第3圖為根據本案一些實施例繪示的第2圖之放電保護裝置100之輸入電壓Vin及控制訊號CS之時序示意圖。第4圖為根據本案一些實施例繪示的第2圖之放電保護裝置100之放電電路120之電路狀態示意圖。第5圖為根據本案一些實施例繪示的第2圖之放電保護裝置100之放電電路120之電路狀態示意圖。在一些實施例中,第3圖之縱軸單位為伏特(V),橫軸單位為毫秒(ms)。In order to make the operation of the
在一些實施例中,請參閱第3圖及第4圖,於第一階段I1中,外部電源900持續提供輸入電壓Vin,放電保護裝置100用以接收輸入電壓Vin。若輸入電壓Vin未低於第一預設電壓,則電子保險晶片130用以將控制訊號CS調整至第一準位,並傳輸該控制訊號CS至N1第一節點,以使第一電晶體T1導通,進而使第二電晶體T2關閉。In some embodiments, please refer to FIG. 3 and FIG. 4 , in the first phase I1 , the
舉例而言,輸入電壓Vin為24V。若輸入電壓Vin低於第一預設電壓(例如:19V) ,則電子保險晶片130用以將控制訊號CS之電壓準位調整至第一準位(例如:接近-12V),以超過第一電晶體T1之第二端(即源極端S)及控制端(即閘極端G)之間的閾值電壓(例如:0.7V)。此時,第一電晶體T1導通,使第一分壓電路121及第二分壓電路122所接收之輸入電壓Vin引導至第一電晶體T1之第二端所連接之接地端,進而使第二節點N2接地,導致第二電晶體T2關閉。For example, the input voltage Vin is 24V. If the input voltage Vin is lower than the first preset voltage (for example: 19V), the
在一些實施例中,請參閱第3圖及第5圖,於時間點P1,外部電源900停止提供輸入電壓Vin,放電保護裝置100用以偵測輸入電壓Vin之電壓變化。若輸入電壓Vin低於第一預設電壓(例如:19V),則電子保險晶片130用以將控制訊號CS調整至第三準位,並傳輸控制訊號CS至第一節點N1,以使第一電晶體T1關閉,進而使第二電晶體T2導通,藉以將外部電源900之輸入電壓Vin透過限流電路123及第二電晶體T2引導至接地端。In some embodiments, please refer to FIG. 3 and FIG. 5 , at time point P1 , the
舉例而言,於時間點P1,輸入電壓Vin自24V下降至19V時,電子保險晶片130用以將控制訊號CS調整至第三準位(例如:接近0V),並傳輸控制訊號CS至第一節點N1,以使第一電晶體T1之控制端響應第一節點N1之電壓準位而關閉。此時,第二分壓電路122將接收之輸入電壓Vin(例如:24V)分壓。假設電阻R3與電阻R4之電阻值均相同的情況下,第二節點N2為12V,第二電晶體T2之控制端響應第二節點N2之第二準位(例如:12V)而導通,藉以將外部電源900之輸入電壓Vin透過限流電路123及第二電晶體T2引導至接地端,以使外部電源900及負載110之間的電壓迅速放電至接地(即0V)。For example, at time point P1, when the input voltage Vin drops from 24V to 19V, the
在一些實施例中,請參閱第3圖至第4圖,於第二階段I2中,放電保護裝置100已無接收輸入電壓Vin。In some embodiments, please refer to FIG. 3 to FIG. 4 , in the second phase I2 , the
須說明的是,此時放電電路120亦用以將負載110上電容(圖中未示) 所殘存之電荷一併引導至第二電晶體T2之第二端所連接之接地端。進一步說明的是,由於限流電路123之電阻R5及電阻R6、第二電晶體T2之等效電阻遠低於負載110,可於1ms內使19V放電至0V。It should be noted that, at this time, the
第6圖為根據本案一些實施例繪示的第2圖之放電保護裝置100之輸入電壓Vin及控制訊號CS之時序示意圖。在一些實施例中,第3圖之縱軸單位為伏特(V),橫軸單位為毫秒(ms)。在一些實施例中,請參閱第2圖及第6圖,放電保護裝置100於第一階段I1持續接收輸入電壓Vin,以維持正常運作。FIG. 6 is a timing diagram of the input voltage Vin and the control signal CS of the
接著,於第二階段I2時,外部電源900斷電,放電保護裝置100響應輸入電壓Vin變化,將外部電源900及負載110間之電壓及負載110上電容(圖中未示)所殘存之電荷快速放電至接電端。Then, in the second stage I2, the
再者,於第三階段I3時,外部電源900復電,放電保護裝置100響應輸入電壓Vin變化,以根據輸入電壓Vin開機並恢復運作。Moreover, in the third stage I3, the
須說明的是,上述電壓準位均為訊號之最低準位到最高準位之變化量。進一步說明的是,上述第一預設電壓、第二預設電壓及預設電流之數值均可依據實際需求設計,並不以本案實施例為限。It should be noted that the above voltage levels are the variation from the lowest level to the highest level of the signal. It should be further explained that the values of the above-mentioned first preset voltage, second preset voltage and preset current can be designed according to actual needs, and are not limited to this embodiment.
依據前述實施例,本案提供一種放電保護裝置,藉以藉由放電保護裝置之電子保險晶片,以監控或偵測外部電源輸入之電壓及電流,藉以保持負載(例如:主機板)穩定,並藉由放電保護裝置之放電電路,以將外部電源及負載間之電壓及負載上電容殘餘電荷迅速放電。此外,於外部電源復電時,使放電保護裝置之負載(例如:主機板)能正常運作。依據前述實施例,本案放電保護裝置實作上已可使外部電源及負載(例如:主機板)於斷電時,在1ms內從高電壓(例如:19V)完成放電至0V。由此可知,本案放電技術之速度超快速並遠超過現有規範標準。According to the foregoing embodiments, this case provides a discharge protection device, which monitors or detects the voltage and current input by the external power supply through the electronic insurance chip of the discharge protection device, so as to keep the load (for example: motherboard) stable, and by The discharge circuit of the discharge protection device is used to quickly discharge the voltage between the external power supply and the load and the residual charge of the capacitor on the load. In addition, when the external power supply is restored, the load of the discharge protection device (for example: main board) can operate normally. According to the above-mentioned embodiments, the discharge protection device of this case can realize the discharge from high voltage (for example: 19V) to 0V within 1 ms when the external power supply and load (for example: motherboard) are powered off. It can be seen from this that the speed of the discharge technology in this case is super fast and far exceeds the existing norms and standards.
雖然本案以詳細之實施例揭露如上,然而本案並不排除其他可行之實施態樣。因此,本案之保護範圍當視後附之申請專利範圍所界定者為準,而非受於前述實施例之限制。Although this case discloses the above with detailed embodiments, this case does not exclude other feasible implementation forms. Therefore, the scope of protection of this case should be defined by the scope of the appended patent application, rather than being limited by the foregoing embodiments.
對本領域技術人員而言,在不脫離本案之精神和範圍內,當可對本案作各種之更動與潤飾。基於前述實施例,所有對本案所作的更動與潤飾,亦涵蓋於本案之保護範圍內。For those skilled in the art, without departing from the spirit and scope of this document, various changes and modifications can be made to this document. Based on the foregoing embodiments, all changes and modifications made to this case are also covered within the scope of protection of this case.
100:放電保護裝置 110:負載 120:放電電路 121:第一分壓電路 122:第二分壓電路 123:限流電路 130:電子保險晶片 R1~R6:電阻 T1~T2:電晶體 IN:電壓輸入引腳 OUT:電壓輸出引腳 PD:訊號輸出引腳 900:外部電源 Vin:輸入電壓 Vout:輸出電壓 CS:控制訊號 G:閘極端 D:汲極端 S:源極端 I1~I3:階段 P1:時間點 100: discharge protection device 110: load 120: discharge circuit 121: The first voltage divider circuit 122: The second voltage divider circuit 123: Current limiting circuit 130: electronic insurance chip R1~R6: resistance T1~T2: Transistor IN: voltage input pin OUT: voltage output pin PD: signal output pin 900: external power supply Vin: input voltage Vout: output voltage CS: control signal G: gate terminal D: drain terminal S: source terminal I1~I3: stage P1: time point
參照後續段落中的實施方式以及下列圖式,當可更佳地理解本案的內容: 第1圖為根據本案一些實施例繪示的放電保護裝置之電路方塊示意圖; 第2圖為根據本案一些實施例繪示的放電保護裝置之放電電路及電子保險晶片示意圖; 第3圖為根據本案一些實施例繪示的放電保護裝置之輸入電壓及控制訊號之時序示意圖; 第4圖為根據本案一些實施例繪示的放電保護裝置之放電電路之電路狀態示意圖; 第5圖為根據本案一些實施例繪示的放電保護裝置之放電電路之電路狀態示意圖;以及 第6圖為根據本案一些實施例繪示的放電保護裝置之輸入電壓及控制訊號之時序示意圖。 The content of this case can be better understood with reference to the implementation manner in the following paragraphs and the following drawings: Figure 1 is a schematic circuit block diagram of a discharge protection device according to some embodiments of the present case; Figure 2 is a schematic diagram of the discharge circuit and electronic insurance chip of the discharge protection device according to some embodiments of the present case; Figure 3 is a schematic diagram of the timing sequence of the input voltage and control signal of the discharge protection device according to some embodiments of the present case; Figure 4 is a schematic diagram of the circuit state of the discharge circuit of the discharge protection device according to some embodiments of the present case; Figure 5 is a schematic diagram of the circuit state of the discharge circuit of the discharge protection device according to some embodiments of the present application; and FIG. 6 is a schematic diagram of the timing sequence of the input voltage and the control signal of the discharge protection device according to some embodiments of the present invention.
100:放電保護裝置 100: discharge protection device
110:負載 110: load
120:放電電路 120: discharge circuit
130:電子保險晶片 130: electronic insurance chip
PD:訊號輸出引腳 PD: signal output pin
900:外部電源 900: external power supply
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW112203427U TWM644193U (en) | 2023-04-14 | 2023-04-14 | Discharge protection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW112203427U TWM644193U (en) | 2023-04-14 | 2023-04-14 | Discharge protection device |
Publications (1)
Publication Number | Publication Date |
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TWM644193U true TWM644193U (en) | 2023-07-21 |
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ID=88148755
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW112203427U TWM644193U (en) | 2023-04-14 | 2023-04-14 | Discharge protection device |
Country Status (1)
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TW (1) | TWM644193U (en) |
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2023
- 2023-04-14 TW TW112203427U patent/TWM644193U/en unknown
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