CN111490762A - Novel power-on and power-off reset circuit - Google Patents
Novel power-on and power-off reset circuit Download PDFInfo
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- CN111490762A CN111490762A CN202010581454.8A CN202010581454A CN111490762A CN 111490762 A CN111490762 A CN 111490762A CN 202010581454 A CN202010581454 A CN 202010581454A CN 111490762 A CN111490762 A CN 111490762A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/24—Storing the actual state when the supply voltage fails
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Abstract
The invention discloses a novel power-on and power-off reset circuit, which comprises: the power-on threshold control main circuit is used for controlling the power-on threshold of the POR circuit; the power-off reset control circuit can realize quick response when being powered off and generate a POR reset signal; the quick power-on response circuit can realize quick response when being powered on quickly; the NM0 turns off the latch circuit, turns off the first MOS transistor in the power-on threshold control main circuit in the standby state, and cuts off the direct current channel of the power-on threshold control main circuit; the output circuit is used for logic control of the output end; the quick-response capacitor discharging circuit controls the fourth capacitor in the quick-power-on response circuit to discharge after quick power-off, so as to ensure quick power-on response; according to the technical scheme, the conditions of fast power-on, fast power-off, slow power-on and slow power-off can be well considered, and meanwhile, through logic control, when the standby mode is carried out, the direct current path is switched off, so that extremely low current consumption can be achieved.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a novel power-on and power-off reset circuit.
Background
In a common power-on and power-off reset circuit, no one can well give consideration to the conditions of fast power-on, fast power-off, slow power-on and slow power-off, and the current in a standby state is large and can reach microampere level or even higher.
Typical power-on reset circuits generally include the following:
the first is a simple RC reset circuit, as shown in fig. 1. When VCC is electrified, C0 is charged, the voltage of a point a rises to the threshold voltage, the inverter is turned over, the reset signal POR is released, the turning over is 0, and the reset is successful. When the circuit is powered off, the POR signal is always 0, and the reset can not be effectively realized.
The second is a sample-and-compare circuit, as shown in fig. 2. In the figure, the resistor R may be a resistor or a MOS diode, and vref is usually a relatively stable voltage value, and may be a band gap voltage or a threshold voltage of a MOS transistor. The basic principle is that when the voltage vsen sampled by the resistor string is less than vref, the comparator makes POR be 1 signal (follow VCC), and when vsen > vref, the comparator makes POR be 0 signal, and the reset is successful. The threshold voltage of POR upset of this circuit depends on vref's stability, and the comparator needs normal work, and VCC that needs is higher, in the power-off process, probably appears the work anomaly, resets failure, and resistance string and comparator all will consume current in standby state simultaneously, and the power consumption is not neglected.
There are other power-on reset circuits, which are not described herein in detail. In short, many power-on reset circuits fail to take account of fast power-on, fast power-off, slow power-on, slow power-off, and low power consumption, and thus do not take into account the above considerations.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a novel power-on and power-off reset circuit, which well solves the problem of taking account of quick power-on, quick power-off, slow power-on and slow power-off and has extremely low standby power consumption.
The technical scheme of the invention is as follows: a novel power-on and power-off reset circuit comprises:
the power-on threshold control main circuit is used for controlling the power-on threshold of the POR circuit;
the power-off reset control circuit can realize quick response when being powered off and generate a POR reset signal;
the quick power-on response circuit can realize quick response when being powered on quickly;
the NM0 turns off the latch circuit, turns off the first MOS transistor in the power-on threshold control main circuit in the standby state, and cuts off the direct current channel of the power-on threshold control main circuit;
the output circuit is used for logic control of the output end;
the quick-response capacitor discharging circuit controls the fourth capacitor in the quick-power-on response circuit to discharge after quick power-off, so as to ensure quick power-on response;
the power-on threshold control main circuit is connected with the output circuit, the power-on threshold control main circuit is connected with the NM0 turn-off latch circuit, and the power-on threshold control main circuit is connected with the quick-response capacitor discharge circuit; the lower power reset control circuit is connected with the NM0 cut-off latch circuit, the output circuit and the quick response capacitor discharge circuit; the fast power-on response circuit is connected with the NM0 turn-off latch circuit, the fast power-on response circuit is connected with the output circuit, and the fast power-on response circuit is connected with the fast response capacitor discharge circuit; the NM0 turns off the latch circuit and connects with the fast response capacitor discharging circuit, NM0 turns off the latch circuit and connects with the output circuit; the output circuit is connected with the fast response capacitor discharging circuit.
The novel power-on and power-off reset circuit comprises a power-on threshold control main circuit, a power-on threshold control main circuit and a power-off and power-off control main circuit, wherein the power-on threshold control main circuit comprises a first P-channel mos tube, a first resistor, a first N-channel mos tube, a second capacitor, a third capacitor, a fifth capacitor and a first phase inverter, the drain electrode of the first P-channel mos tube is connected with power supply voltage, the grid electrode and the source electrode of the first P-channel mos tube are connected in parallel and then connected with one end of the first resistor, the other end of the first resistor is connected with the drain electrode of the first N-channel mos tube, the source electrode of the first N-channel mos tube is grounded, the grid electrode of the first N-channel mos tube is connected with one end of the fifth capacitor, and the; the grid electrode of the first N-channel mos tube is also connected with the drain electrode of the second N-channel mos tube, the source electrode of the second N-channel mos tube is grounded, and the grid electrode of the second N-channel mos tube is connected with the NM0 turn-off latch circuit; the source electrode of the first P-channel mos tube is also connected with one end of a second capacitor, and the other end of the second capacitor is grounded; the source electrode of the first P-channel mos tube is also connected with the input end of a first phase inverter, the output end of the first phase inverter is connected with one end of a third capacitor, the other end of the third capacitor is grounded, the output end of the first phase inverter is also connected with the input end of a first buffer, and the output end of the first buffer is connected with an output circuit; the output end of the first phase inverter is also connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the quick response capacitor discharging circuit.
The novel power-on and power-off reset circuit comprises a power-off reset control circuit, a power-on reset control circuit and a power-off reset control circuit, wherein the power-off reset control circuit comprises a second P-channel mos tube, a third N-channel mos tube, a fourth N-channel mos tube, a sixth capacitor and a third phase inverter, the drain electrode of the second P-channel mos tube is connected with a power supply voltage, the grid electrode and the source electrode of the second P-channel mos tube are connected in parallel and then connected with the input end of the third phase inverter, the output end of the third phase inverter is connected with an NM0 turn-off latch circuit, the output end of the third phase inverter is further connected with a fast-response capacitor discharge circuit, and the output end of the third phase inverter is; the source electrode of the second P-channel mos tube is also connected with the drain electrode of a third N-channel mos tube, the grid electrode of the third N-channel mos tube is grounded, the source electrode of the third N-channel mos tube is connected with one end of a sixth capacitor, and the other end of the sixth capacitor is connected with a power supply voltage; and the drain electrode and the grid electrode of the fourth N-channel mos tube are connected in parallel and then are connected with the source electrode of the third N-channel mos tube, and the source electrode of the fourth N-channel mos tube is grounded.
The novel power-on and power-off reset circuit comprises a first capacitor, a fifth N-channel mos tube and a second buffer, wherein one end of the first capacitor is connected with a power supply voltage, the other end of the first capacitor is connected with a drain electrode of the fifth N-channel mos tube, a grid electrode of the fifth N-channel mos tube is connected with a fast response capacitor discharging circuit, the grid electrode of the fifth N-channel mos tube is also connected with an NM0 turn-off latch circuit, and a source electrode of the fifth N-channel mos tube is grounded; the other end of the first capacitor is connected with the input end of a second buffer, the output end of the second buffer is connected with the input end of a fourth phase inverter, the output end of the fourth phase inverter is connected with the NM0 turn-off latch circuit, and the output end of the second buffer is further connected with the output circuit.
The novel power-on and power-off reset circuit comprises an NM0 turn-off latch circuit, a power-on reset control circuit, a power-off reset control circuit, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a fast power-on response circuit, a fast power-on reset control circuit, a fast power-off reset circuit and a power-on reset circuit, wherein the first input end of the fourth NOR gate is connected with the fast power-on response circuit; the output end of the fourth NOR gate is connected with the input end of the seventh inverter, the output end of the seventh inverter is connected with the power-on threshold control main circuit, and the output end of the fourth NOR gate is also connected with the power-on threshold control main circuit.
The novel power-on and power-off reset circuit comprises an output circuit, a first transmission amplifier, a second transmission amplifier, a third transmission amplifier, a fourth transmission amplifier, a fifth transmission amplifier, a sixth transmission amplifier, a fifth transmission amplifier, a sixth transmission amplifier, a; the output end of the third NOR gate is also connected with the input end of a fifth inverter, the output end of the fifth inverter is connected with the first input end of a sixth NOR gate, the second input end of the sixth NOR gate is connected with a quick response capacitor discharging circuit, the second input end of the sixth NOR gate is also connected with a lower power reset control circuit, and the second input end of the sixth NOR gate is also connected with an NM0 turn-off latch circuit; and the output end of the sixth NOR gate is connected with the input end of the sixth inverter, and the output end of the sixth inverter outputs a reset signal.
The novel power-on and power-off reset circuit comprises a fourth capacitor and a sixth N-channel mos tube, one end of the fourth capacitor is connected with the output end of a second phase inverter, the other end of the fourth capacitor is grounded, one end of the fourth capacitor is connected with the drain electrode of the sixth N-channel mos tube, the source electrode of the sixth N-channel mos tube is grounded, the grid electrode of the sixth N-channel mos tube is connected with an output circuit, the grid electrode of the sixth N-channel mos tube is connected with a power-off reset control circuit, the grid electrode of the sixth N-channel mos tube is connected with an NM0 turn-off latch circuit, one end of the fourth capacitor is connected with an NM0 turn-off latch circuit, and one end of the fourth capacitor is connected with a fast power-on response circuit.
The invention has the beneficial effects that: the invention provides a novel power-on and power-off reset circuit, which comprises: the power-on threshold control main circuit is used for controlling the power-on threshold of the POR circuit; the power-off reset control circuit can realize quick response when being powered off and generate a POR reset signal; the quick power-on response circuit can realize quick response when being powered on quickly; the NM0 turns off the latch circuit, turns off the first MOS transistor in the power-on threshold control main circuit in the standby state, and cuts off the direct current channel of the power-on threshold control main circuit; the output circuit is used for logic control of the output end; the quick-response capacitor discharging circuit controls the fourth capacitor in the quick-power-on response circuit to discharge after quick power-off, so as to ensure quick power-on response; according to the technical scheme, the conditions of fast power-on, fast power-off, slow power-on and slow power-off can be well considered, and meanwhile, through logic control, when the standby mode is carried out, the direct current path is switched off, so that extremely low current consumption can be achieved.
Drawings
Fig. 1 is a circuit schematic diagram of an RC reset circuit in the prior art.
Fig. 2 is a circuit diagram of a prior art sampling comparison circuit.
Fig. 3 is a circuit diagram of the novel power-on/power-off reset circuit of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
As shown in fig. 3, a novel power-on/power-off reset circuit includes:
a power-on threshold control main circuit 1 for controlling a power-on threshold of a POR circuit (power-on reset circuit);
the power-off reset control circuit 2 can realize quick response when powering off, and generates a POR reset signal (namely a power-on reset signal);
the fast power-on response circuit 3 can realize fast response when being powered on quickly;
the NM0 turns off the latch circuit 4, turns off the first MOS transistor NM0 in the power-on threshold control main circuit 1 in the standby state, and cuts off the direct current path of the power-on threshold control main circuit 1;
an output circuit 5 for logic control of the output terminal;
the fast response capacitor discharging circuit 6 controls the fourth capacitor C3 in the fast power-on response circuit 3 to discharge after fast power-off, so as to ensure fast power-on response;
the power-on threshold control main circuit 1 is connected with the output circuit 5, the power-on threshold control main circuit 1 is connected with the NM0 turn-off latch circuit 4, and the power-on threshold control main circuit 1 is connected with the quick-response capacitor discharging circuit 6; the power-down reset control circuit 2 is connected with the NM0 turn-off latch circuit 4, the power-down reset control circuit 2 is connected with the output circuit 5, and the power-down reset control circuit 2 is connected with the quick-response capacitor discharging circuit 6; the fast power-on response circuit 3 is connected with the NM0 turn-off latch circuit 4, the fast power-on response circuit 3 is connected with the output circuit 5, and the fast power-on response circuit 3 is connected with the fast response capacitor discharging circuit 6; the NM0 turns off the latch circuit 4 to connect with the fast response capacitor discharging circuit 6, and the NM0 turns off the latch circuit 4 to connect with the output circuit 5; the output circuit 5 is connected with the fast response capacitor discharging circuit 6.
In some embodiments, the main power-on threshold control circuit 1 includes a first P-channel mos transistor PM0, a first resistor R0, a first N-channel mos transistor NM0, a second N-channel mos transistor NM1, a second capacitor C1, a third capacitor C2, a fifth capacitor C4, and a first inverter INV0, where a drain of the first P-channel mos transistor PM0 is connected to the supply voltage Vcc, a gate and a source of the first P-channel mos transistor PM0 are connected in parallel and then connected to one end of the first resistor R0, the other end of the first resistor R0 is connected to a drain of the first N-channel mos transistor NM0, a source of the first N-channel mos transistor NM0 is grounded, a gate of the first N-channel mos transistor NM0 is connected to one end of the fifth capacitor C4, and the other end of the fifth capacitor C4 is connected to the NM0 shutdown latch circuit 4; the grid electrode of the first N-channel mos transistor NM0 is further connected with the drain electrode of the second N-channel mos transistor NM1, the source electrode of the second N-channel mos transistor NM1 is grounded, and the grid electrode of the second N-channel mos transistor NM1 is connected with the NM0 turn-off latch circuit 4; the source electrode of the first P-channel mos transistor PM0 is also connected with one end of a second capacitor C1, and the other end of the second capacitor C1 is grounded; the source electrode of the first P-channel mos transistor PM0 is further connected with the input end of a first inverter INV0, the output end of the first inverter INV0 is connected with one end of a third capacitor C2, the other end of the third capacitor C2 is grounded, the output end of the first inverter INV0 is further connected with the input end of a first buffer BUF0, and the output end of the first buffer BUF0 is connected with the output circuit 5; the output end of the first inverter INV0 is further connected to the input end of the second inverter INV1, and the output end of the second inverter INV1 is connected to the fast response capacitor discharging circuit 6.
The main working principle of the power-on threshold control main circuit 1 is as follows: when VCC starts to be electrified, because the voltage at two ends of a capacitor can not be suddenly changed, the voltage at the node g rises along with VCC, when VCC is greater than MAX (VTHN, | VTHP |) (wherein VTHN is the starting voltage of an N-channel mos tube, and VTHP is the starting voltage of a P-channel mos tube), a direct current path formed by PM0, R0 and NM0 is opened, and the capacitor C1 starts to be charged, at the moment, because the voltage at a is lower, a PMOS tube in INV0 is conducted, and the capacitor at b end C2 is charged, and logically shows 1; after the time T1, when the voltage Va at the terminal a is charged to the capacitor C1 and is greater than the inverted voltage of INV0, the capacitor C2 at the terminal b starts to discharge, and after the time T2, it is represented as logic 0, and the charging and discharging time is equal to T1+ T2.
In some embodiments, the power-down reset control circuit 2 includes a second P-channel mos transistor PM1, a third N-channel mos transistor NM2, a fourth N-channel mos transistor NM3, a sixth capacitor C5, and a third inverter INV2, a drain of the second P-channel mos transistor PM1 is connected to the power supply voltage Vcc, a gate and a source of the second P-channel mos transistor PM1 are connected in parallel and then connected to an input terminal of the third inverter INV2, an output terminal of the third inverter INV2 is connected to the NM0 turn-off latch circuit 4, an output terminal of the third inverter INV2 is further connected to the fast-response capacitor bleeder circuit 6, and an output terminal of the third inverter INV2 is further connected to the output circuit 5; the source of the second P-channel mos transistor PM1 is further connected with the drain of a third N-channel mos transistor NM2, the gate of the third N-channel mos transistor NM2 is grounded, the source of the third N-channel mos transistor NM2 is connected with one end of a sixth capacitor C5, and the other end of the sixth capacitor C5 is connected with a power supply voltage Vcc; the drain and the gate of the fourth N-channel mos transistor NM3 are connected in parallel and then connected to the source of the third N-channel mos transistor NM2, and the source of the fourth N-channel mos transistor NM3 is grounded.
The main working principle of the power-down reset control circuit 2 is as follows: when VCC is rapidly powered down, because the voltage at the two ends of C5 can not suddenly change, the voltage at the node n will drop by delta VCC and become negative voltage, the NM2 tube is conducted, the voltage at the node h is rapidly pulled down, the INV2 is inverted, the node k is represented as logic 1, and the POR reset signal is generated after the output of NOR5 and INV 5. When VCC is slowly powered down, the node h is clamped to a voltage VCC-VTHP, and when VTHP < VCC < VTHP + VTHN, INV2 is inverted, node k appears as a logic 1, and is output through NOR5, INV5 of the output circuit 5, generating the POR reset signal.
In some embodiments, the fast power-on response circuit 3 includes a first capacitor C0, a fifth N-channel mos transistor NM4 and a second buffer BUF1, one end of the first capacitor C0 is connected to the supply voltage Vcc, the other end of the first capacitor C0 is connected to the drain of the fifth N-channel mos transistor NM4, the gate of the fifth N-channel mos transistor NM4 is connected to the fast response capacitor bleeder circuit 6, the gate of the fifth N-channel mos transistor NM4 is further connected to the NM0 turn-off latch circuit 4, and the source of the fifth N-channel mos transistor NM4 is grounded; the other end of the first capacitor C0 is connected with the input end of the second buffer BUF1, the output end of the second buffer BUF1 is connected with the input end of the fourth inverter INV3, the output end of the fourth inverter INV3 is connected with the NM0 turn-off latch circuit 4, and the output end of the second buffer BUF1 is further connected with the output circuit 5.
The main working principle of the fast power-on response circuit 3 is as follows: when VCC is electrified quickly, the voltage at the two ends of C0 can not change suddenly, the voltage at the node d rises by delta VCC, and after the action of BUF1, the node e is represented as logic 1.
In some embodiments, the NM0 shutdown latch circuit 4 includes a fourth NOR gate NOR3, a fifth NOR gate NOR4, a seventh inverter INV6, a first input terminal of the fourth NOR gate NOR3 is connected to an output terminal (i.e., the fast power-on response circuit 3) of the second buffer BUF1, a second input terminal of the fourth NOR gate NOR3 is connected to an output terminal (i.e., the power-down reset control circuit 2) of the third inverter INV2, a third input terminal of the fourth NOR gate NOR3 is connected to an output terminal of the fifth NOR gate NOR4, a first input terminal of the fourth NOR gate NOR3 is connected to an output terminal of the fourth NOR gate NOR3, a second input terminal of the fourth NOR gate NOR3 is connected to a gate (i.e., the fast power-on response circuit 3) of the fifth N-channel mos transistor NM4, a second input terminal of the fourth NOR gate NOR3 is further connected to the fast response capacitor bleeder circuit 6, and a second input terminal of the fourth NOR gate 3 is further connected to the output circuit 5; an output end of the fourth NOR gate NOR3 is connected to an input end of the seventh inverter INV6, an output end of the seventh inverter INV6 is connected to a drain of the second N-channel mos transistor NM1 (i.e., the power-on threshold control main circuit 1), and an output end of the fourth NOR gate NOR3 is further connected to a gate of the second N-channel mos transistor NM1 (i.e., the power-on threshold control main circuit 1).
The main operation principle of the NM0 turning off the latch circuit 4 is as follows: in the standby state, the node c is logic 1, the node k is logic 0, the node e is logic 0, the latch node f is logic 1, the node g is logic 0, and the power-on threshold is turned off to control the NM0 of the main circuit 1.
In some embodiments, the output circuit 5 includes a second NOR gate NOR1, a third NOR gate NOR2, a fifth inverter INV4, a sixth NOR gate NOR5, and a sixth inverter INV5, a first input of the second NOR gate NOR1 is connected to an output of the fourth inverter INV3, a second input of the second NOR gate NOR1 is connected to an output of the third NOR gate NOR2, an output of the second NOR gate NOR1 is connected to a first input of the third NOR gate NOR2, and a second input of the third NOR gate NOR2 is connected to an output of the first transport amplifier BUF 0; the output end of the third NOR gate NOR2 is further connected to the input end of a fifth inverter INV4, the output end of the fifth inverter INV4 is connected to the first input end of a sixth NOR gate NOR5, the second input end of the sixth NOR gate NOR5 is connected to the quick response capacitor discharging circuit 6, the second input end of the sixth NOR gate NOR5 is further connected to the output end of the third inverter INV2 (i.e., the power-down reset control circuit 2), and the second input end of the sixth NOR gate NOR5 is further connected to the second input end of the fourth NOR gate NOR3 (i.e., the NM0 turns off the latch circuit 4); an output terminal of the sixth NOR gate NOR5 is connected to an input terminal of the sixth inverter INV5, and an output terminal of the sixth inverter INV5 outputs the reset signal POR.
The main operating principle of the output circuit 5 is as follows: the NOR1 and the NOR2 form a latch, and mainly latch an overturning signal of the main circuit 1 controlled by a power-on threshold value; the NOR5 is mainly responsible for sending out the power-on and power-off reset signals correctly.
In some embodiments, the fast response capacitor discharging circuit 6 includes a fourth capacitor C3 and a sixth N-channel mos transistor NM5, one end of the fourth capacitor C3 is connected to the output end of the second inverter INV1, the other end of the fourth capacitor C3 is grounded, one end of the fourth capacitor C3 is further connected to the drain of the sixth N-channel mos transistor NM5, the source of the sixth N-channel mos transistor NM5 is grounded, the gate of the sixth N-channel mos transistor NM5 is connected to the second input end (i.e., the output circuit 5) of the sixth NOR gate NOR5, the gate of the sixth N-channel mos transistor NM5 is further connected to the output end (i.e., the lower electrical reset control circuit 2) of the third inverter INV2, the gate of the sixth N-channel mos transistor NM5 is further connected to the second input end (i.e., the NM0 shutdown latch circuit 4) of the fourth NOR gate NOR3, one end of the fourth capacitor C3 is further connected to the second input end (i.e., the NM0 shutdown latch circuit 4) of the first NOR gate 4, and one end of the fourth capacitor C3 is further connected to the NM4 (i.e., the upper electrical reset control circuit 4) of the fifth N-channel NOR gate NOR.
The fast response capacitor discharging circuit 6 mainly works according to the following principle: when VCC is in fast power-down condition, the k terminal of the node is presented as logic 1, NM5 is conducted, and C3 is discharged. The purpose is to avoid that when the power is quickly powered up after the power is quickly powered down, the C3 has no power leakage and influences the response of the quick power up.
The work of six parts of circuits, namely a power-on threshold control main circuit 1, a power-off reset control circuit 2, a fast power-on response circuit 3, an NM0 turn-off latch circuit 4, an output circuit 5 and a fast response capacitor power-off circuit 6 in the novel power-on and power-off reset circuit is coherent and orderly, and four power-on and power-off conditions are analyzed as follows:
(1) slow power-up: from the output circuit 5, we mainly care about three signals of the node i, the node j and the node k. When the power is slowly powered on, the end d of the node is logic 0, and after the action of the BUF1 and the INV3, the end i of the node is logic 1, and the end q of the node is logic 0. When the point b is still logic 1, the point j is logic 1, the point m is logic 1, the output POR is logic 1, POR is not released and is in a reset state, when the point b is inverted into logic 0, the point j is logic 0, meanwhile, the point q is logic 0, the point m is inverted into logic 0, the output POR is inverted into logic 0, POR is released and reset is finished; i.e. the slow power-up logic sequence is node a-b-j-m-POR.
(2) And (3) fast power-on: the voltage at the end of the node d is increased to VCC and is expressed as logic 1, and after the action of BUF1 and INV3, the end of the node i is made to be logic 0; when the point b is also logic 1, the node j end is logic 1, the node m end is logic 1, the output POR is logic 1, and the POR is not released and is in a reset state; meanwhile, the node p end is logic 0, the node i end is logic 0, the node q end is logic 1, when the point b is turned into logic 0, the node j end is logic 0, and at the moment, because the node q end is logic 1, the logic of the end m is still 1, and the node is not turned; continuing to look down, the node b is 0, so that the end of the node c is 1, NM4 is conducted, the node d is pulled down to be logic 0, so that the node i is turned to be logic 1, the node q is turned to be logic 0, the node m is turned to be logic 0, the output POR is turned to be logic 0, POR is released, and reset is finished; i.e. the slow power-up logic sequence is the nodes a-b-c-d-e-i-m-POR.
(3) And (3) slowly powering down: in the power-down reset control circuit 2, when the power is slowly powered down, the end k of the node is inverted into logic 1, after the action of NOR5 and INV5, POR is inverted into logic 1, and the power is reset; during slow power-off, in the power-on threshold control main circuit 1, the voltage at the node b is also turned into logic 1, so that the node m is logic l, the POR is turned into logic 1, and power-off reset is performed; namely, the slow power-down reset logic sequence is the node h-k-POR or a-b-j-m-POR.
(4) Quickly powering off: in the power-down reset control circuit 2, when power is turned off quickly, the point k end is inverted into logic 1, after the action of NOR5 and INV5, POR is inverted into logic 1, and power is reset; namely, the fast power-down reset logic sequence node is h-k-POR.
It can be seen from the above description that the novel power-on/power-off reset circuit can well give consideration to the situations of fast power-on, fast power-off, slow power-on and slow power-off, and meanwhile, through logic control, during standby, a direct current path is turned off, so that extremely low current consumption can be achieved.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (7)
1. A novel power-on and power-off reset circuit is characterized by comprising:
the power-on threshold control main circuit (1) is used for controlling the power-on threshold of the POR circuit;
the power-down reset control circuit (2) can realize quick response when being powered down and generate a POR reset signal;
the quick power-on response circuit (3) can realize quick response when being powered on quickly;
the NM0 turns off the latch circuit (4), turns off the first MOS transistor (NM 0) in the power-on threshold control main circuit (1) in the standby state, and cuts off the direct current channel of the power-on threshold control main circuit (1);
an output circuit (5) for logic control of the output terminal;
the fast response capacitor discharging circuit (6) controls a fourth capacitor (C3) in the fast power-on response circuit (3) to discharge after fast power-off, so as to ensure fast power-on response;
the power-on threshold control main circuit (1) is connected with the output circuit (5), the power-on threshold control main circuit (1) is connected with the NM0 cut-off latch circuit (4), and the power-on threshold control main circuit (1) is connected with the quick-response capacitor leakage circuit (6); the lower power reset control circuit (2) is connected with the NM0 turn-off latch circuit (4), the lower power reset control circuit (2) is connected with the output circuit (5), and the lower power reset control circuit (2) is connected with the quick-response capacitor bleeder circuit (6); the fast power-on response circuit (3) is connected with the NM0 turn-off latch circuit (4), the fast power-on response circuit (3) is connected with the output circuit (5), and the fast power-on response circuit (3) is connected with the fast response capacitor bleeder circuit (6); NM0 turns off latch circuit (4) to connect with fast response capacitor bleeder circuit (6), NM0 turns off latch circuit (4) to connect with output circuit (5); the output circuit (5) is connected with the fast response capacitor bleeder circuit (6).
2. The novel power-on and power-off reset circuit as claimed in claim 1, wherein the main power-on threshold control circuit (1) comprises a first P-channel mos transistor PM0, a first resistor R0, a first N-channel mos transistor NM0, a second N-channel mos transistor NM1, a second capacitor C1, a third capacitor C2, a fifth capacitor C4 and a first inverter INV0, wherein a drain of the first P-channel mos transistor PM0 is connected to a supply voltage Vcc, a gate and a source of the first P-channel mos transistor PM0 are connected in parallel to one end of a first resistor R0, the other end of the first resistor R0 is connected to a drain of the first N-channel mos transistor NM0, a source of the first N-channel mos transistor NM0 is grounded, a gate of the first N-channel mos transistor NM0 is connected to one end of a fifth capacitor C4, and the other end of the fifth capacitor C4 is connected to the NM0 latch circuit (4); the grid electrode of the first N-channel mos transistor NM0 is also connected with the drain electrode of the second N-channel mos transistor NM1, the source electrode of the second N-channel mos transistor NM1 is grounded, and the grid electrode of the second N-channel mos transistor NM1 is connected with the NM0 turn-off latch circuit (4); the source electrode of the first P-channel mos transistor PM0 is also connected with one end of a second capacitor C1, and the other end of the second capacitor C1 is grounded; the source electrode of the first P-channel mos transistor PM0 is further connected with the input end of a first inverter INV0, the output end of the first inverter INV0 is connected with one end of a third capacitor C2, the other end of the third capacitor C2 is grounded, the output end of the first inverter INV0 is further connected with the input end of a first buffer BUF0, and the output end of the first buffer BUF0 is connected with an output circuit (5); the output end of the first inverter INV0 is further connected with the input end of the second inverter INV1, and the output end of the second inverter INV1 is connected with the fast response capacitor discharge circuit (6).
3. The novel power-on and power-off reset circuit as claimed in claim 1, wherein the power-off reset control circuit (2) comprises a second P-channel mos transistor PM1, a third N-channel mos transistor NM2, a fourth N-channel mos transistor NM3, a sixth capacitor C5 and a third inverter INV2, the drain of the second P-channel mos transistor PM1 is connected to the supply voltage Vcc, the gate and the source of the second P-channel mos transistor PM1 are connected in parallel and then connected to the input of a third inverter INV2, the output of the third inverter INV2 is connected to the NM0 turn-off latch circuit (4), the output of the third inverter INV2 is further connected to the fast-response capacitor bleeder circuit (6), and the output of the third inverter INV2 is further connected to the output circuit (5); the source of the second P-channel mos transistor PM1 is further connected with the drain of a third N-channel mos transistor NM2, the gate of the third N-channel mos transistor NM2 is grounded, the source of the third N-channel mos transistor NM2 is connected with one end of a sixth capacitor C5, and the other end of the sixth capacitor C5 is connected with a power supply voltage Vcc; the drain and the gate of the fourth N-channel mos transistor NM3 are connected in parallel and then connected to the source of the third N-channel mos transistor NM2, and the source of the fourth N-channel mos transistor NM3 is grounded.
4. The novel power-on and power-off reset circuit as claimed in claim 1, wherein the fast power-on response circuit (3) comprises a first capacitor C0, a fifth N-channel mos transistor NM4 and a second buffer BUF1, one end of the first capacitor C0 is connected to the supply voltage Vcc, the other end of the first capacitor C0 is connected to the drain of the fifth N-channel mos transistor NM4, the gate of the fifth N-channel mos transistor NM4 is connected to the fast response capacitor bleeder circuit (6), the gate of the fifth N-channel mos transistor NM4 is further connected to the NM0 turn-off latch circuit (4), and the source of the fifth N-channel mos transistor NM4 is grounded; the other end of the first capacitor C0 is connected with the input end of a second buffer BUF1, the output end of the second buffer BUF1 is connected with the input end of a fourth inverter INV3, the output end of the fourth inverter INV3 is connected with an NM0 turn-off latch circuit (4), and the output end of the second buffer BUF1 is further connected with an output circuit (5).
5. The new power-on power-down reset circuit as claimed in claim 1, wherein the NM0 shutdown latch circuit (4) comprises a fourth NOR gate NOR3, a fifth NOR gate NOR4, a seventh inverter INV6, a first input of the fourth NOR gate NOR3 is connected to the fast power-on response circuit (3), a second input of the fourth NOR gate NOR3 is connected to the power-down reset control circuit (2), a third input of the fourth NOR gate NOR3 is connected to an output of the fifth NOR gate NOR4, a first input of the fourth NOR gate NOR3 is connected to an output of the fourth NOR gate NOR3, a second input of the fourth NOR gate NOR3 is connected to the fast power-on response circuit (3), a second input of the fourth NOR gate 3 is further connected to the fast response capacitor bleeder circuit (6), and a second input of the fourth NOR gate 3 is further connected to the output (5); an output end of the fourth NOR gate NOR3 is connected to an input end of the seventh inverter INV6, an output end of the seventh inverter INV6 is connected to the power-on threshold control main circuit (1), and an output end of the fourth NOR gate NOR3 is further connected to the power-on threshold control main circuit (1).
6. The novel power-on and power-off reset circuit as claimed in claim 1, wherein the output circuit (5) comprises a second NOR gate NOR1, a third NOR gate NOR2, a fifth inverter INV4, a sixth NOR gate NOR5, and a sixth inverter INV5, wherein a first input of the second NOR gate NOR1 is connected to an output of the fourth inverter INV3, a second input of the second NOR gate NOR1 is connected to an output of the third NOR gate 2, an output of the second NOR gate NOR1 is connected to a first input of the third NOR gate NOR2, and a second input of the third NOR gate NOR2 is connected to an output of the first transport amplifier BUF 0; the output end of the third NOR gate NOR2 is also connected with the input end of a fifth inverter INV4, the output end of the fifth inverter INV4 is connected with the first input end of a sixth NOR gate NOR5, the second input end of the sixth NOR gate NOR5 is connected with a fast response capacitor bleeder circuit (6), the second input end of the sixth NOR gate NOR5 is also connected with a power-down reset control circuit (2), and the second input end of the sixth NOR gate NOR5 is also connected with a NM0 shutdown latch circuit (4); an output terminal of the sixth NOR gate NOR5 is connected to an input terminal of the sixth inverter INV5, and an output terminal of the sixth inverter INV5 outputs the reset signal POR.
7. The new power-on/power-off reset circuit as claimed in claim 1, wherein the fast-response capacitor bleeder circuit (6) comprises a fourth capacitor C3 and a sixth N-channel mos transistor NM5, one end of the fourth capacitor C3 is connected to the output end of the second inverter INV1, the other end of the fourth capacitor C3 is grounded, one end of the fourth capacitor C3 is further connected to the drain of the sixth N-channel mos transistor NM5, the source of the sixth N-channel mos transistor NM5 is grounded, the gate of the sixth N-channel mos transistor NM5 is connected to the output circuit (5), the gate of the sixth N-channel mos transistor NM5 is further connected to the lower power-off control circuit (2), the gate of the sixth N-channel mos transistor NM5 is further connected to the NM0 turn-off latch circuit (4), one end of the fourth capacitor C3 is further connected to the NM0 turn-off latch circuit (4), and one end of the fourth capacitor C3 is further connected to the fast-response circuit (3).
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| CN113741261A (en) * | 2021-08-27 | 2021-12-03 | 普源精电科技股份有限公司 | Power-on and power-off control circuit and signal output device |
| WO2021258615A1 (en) * | 2020-06-23 | 2021-12-30 | 芯天下技术股份有限公司 | Novel power-on/off reset circuit |
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| CN114390757A (en) * | 2022-03-02 | 2022-04-22 | 浙江中川电气技术有限公司 | Integrated control module for emergency lighting centralized power supply |
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