CN1610065A - 形成半导体组件的方法 - Google Patents

形成半导体组件的方法 Download PDF

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CN1610065A
CN1610065A CN200410062342.2A CN200410062342A CN1610065A CN 1610065 A CN1610065 A CN 1610065A CN 200410062342 A CN200410062342 A CN 200410062342A CN 1610065 A CN1610065 A CN 1610065A
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semiconductor subassembly
chip
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郝静晨
林鸿仁
季明华
沈志恒
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种形成半导体组件的方法，至少包含以下步骤：形成一结构于一芯片上，该结构具有一第一层与一罩幕层，且该第一层具有一预掺杂的多晶硅层；在移除该罩幕层之前，氧化该芯片以产生一氧化层；以及移除该罩幕层。

Description

形成半导体组件的方法
技术领域
本发明涉及半导体组件的制造形成方法，且特别涉及在半导体组件中制造多晶硅图案的方法。
背景技术
互补式金氧半导体(Complementary Metal Oxide Semiconductor；CMOS)组件，例如金氧半导体场效晶体管(Metal Oxide Semiconductor Field-EffectTransistors；MOSFETs)，普遍使用在超大规模集成电路(Ultra-Large ScaleIntegrated；ULSI)组件的制造中。缩小组件尺寸及降低电力耗损需求，是持续不断的趋势。因此，近来的趋势已于CMOS组件中使用超浅接面。
举例而言，NMOS与PMOS晶体管一般在基材上形成有闸极绝缘体与门极多晶硅。基材，一般为硅基材，再闸极的另一面进行掺杂以形成源极与汲极。电极连接于闸极多晶硅、源极与汲极。为了使组件尽可能的小，在设计CMOS组件时，源极与汲极区以及绝缘薄膜也尽可能的小，即CMOS组件设计成具有超浅接面。
再者，在许多例子中，在闸极多晶硅中执行预掺杂(Pre-Doping)以布植n型杂质于NMOS组件中，或者布植p型杂质于PMOS组件中，以形成闸电极。预掺杂改善起始电压以及驱动电流的特性，更加强晶体管的表现。
然而，n型预掺杂常会在多晶硅闸极轮廓中导致非所要求的特性。一般说来，执行预掺杂通过布植n型杂质，例如磷，于多晶硅闸极中。涂上并图案化罩幕层，以蚀刻出闸极。移除罩幕层并进行氧化步骤。然而，罩幕层移除后，常会造成闸极轮廓出现「颈化(Necking)」或「基脚(Footing)」，意即闸极的侧壁不是垂直的，由于掺质渗透不一，从而导致组件变异。
举例而言，图1绘示在执行n型预掺杂制程之后，于芯片100上形成闸极结构。在基材110上形成有闸极绝缘体112。闸极114形成在闸极绝缘体112上，而氧化层形成在闸极114与闸极绝缘体112所暴露出的区域上。颈部118形成在闸极114上面的部分。颈部118引起n型掺质趋入n型轻掺杂汲极(n-Light Doped Drain；NLDD)区，而导致多晶硅指状接面漏电(Poly FingerJunction Leakage)。
发明内容
因此本发明的目的在于提供一种制造多晶硅图案的方法，通常可藉由本发明的实施例，减少、解决或避开这些及其它问题，以及达到技术上的优点。
为实现上述目的，本发明提供一种形成半导体组件的方法，其至少包含以下步骤：
形成一结构于一芯片上，该结构具有一第一层与一罩幕层，且该第一层具有一预掺杂的多晶硅层；
在移除该罩幕层之前，氧化该芯片以产生一氧化层；以及
移除该罩幕层。
本发明还提出一种在具有基材的芯片上形成半导体组件的方法，其至少包含以下步骤：
于该基材上形成一多晶硅层；
预掺杂该多晶硅层；
形成一罩幕层于该多晶硅层上；
蚀刻该罩幕层以及该多晶硅层；
氧化该芯片以产生一氧化层；以及
移除该罩幕层与该氧化层。
在本发明的一实施例中，在多晶硅结构形成后以及移除罩幕前，执行氧化步骤。氧化步骤可避免常见的颈化问题形成，藉此减少指状接面漏电。
附图说明
图1是绘示具有颈化轮廓结构的芯片剖面图；
图2至图2e绘示依照本发明的一方法实施例于形成多晶硅结构的制程中的芯片剖面图；以及
图3绘示依照本发明的一实施例的晶体管制造剖面图。
具体实施方式
以下详细讨论本发明的较佳实施例的制造及使用。然而，本发明提供许多可应用的发明构想，并于多种特定内容中据以实施，是值得鼓励的。更进一步而言，本发明的方法中描述形成晶体管的闸极的来龙去脉。不过熟习此项技艺的人士会意识到使用此处所描述的制程，可利用n型预掺杂多晶硅结构形成任何形式的组件或结构。因此，此处所讨论的特定实施例仅为说明特定的制造及使用，并非用来限制本发明的范围。
图2a至图2e绘示在本发明的方法实施例中，半导体芯片在不同步骤中的部分剖面图。制程始于图2a，其中半导体芯片200具有基材210，在基材上形成有闸极绝缘层212与闸极层214。基材210可以是其它半导体：硅、玻璃、砷化镓(GaAs)以及绝缘层上硅(Silicon-On-Insulator；SOI)等，但以硅为较佳。
闸极绝缘层212可避免电子空乏，以任何氧化制程所形成的氧化层为较佳，其中氧化制程是例如通过在包含氧化物、水、一氧化氮(NO)或其上述的组合的气体中进行的湿式或干式热氧化，或者利用四乙基邻硅甲烷(Tetra-Ethyl-Ortho-Silicate；TEOS)及作为前驱物的氧进行的化学气相沉积(Chemical Vapor Deposition；CVD)技术。然而在较佳实施例中，闸极绝缘层212是由湿式或干式氧化制程形成的二氧化硅材料，其中湿式或干式氧化制程是例如在氧、水或其上述的组合等的气体环境中进行的炉管氧化(Furnace Oxidation)，或者在氧、水、一氧化氮或其上述的组合等的气体环境中进行的同步蒸气产生(In-Situ Steam Generation；ISSG)制程。在较佳实施例中，闸极绝缘层的厚度约15埃(Angstrom；)至约25埃，但更佳为约20埃。
闸极层214一般为半导体材料，例如多晶硅、非晶硅等。在较佳实施例中，通过低压化学气相沉积(Low-Pressure Chemical Vapor Deposition；LPCVD)法沉积未掺杂的多晶硅，其中多晶硅的厚度在约2500埃至约1500埃的范围，但以约1800埃较佳。
在较佳实施例中，其中闸极层214包含多晶硅材料，而此多晶硅材料以磷离子在每平方公分约3.0e15至约6.0e15原子的剂量以及约10至约30千电子伏特(Kiloelectron Volt；KeV)的能量中进行预掺杂。另一种方式，闸极层214可利用氮、砷、锑等进行预掺杂。
视情况而定，闸极层214在预掺杂之前可先进行图案化，以限制离子布植到闸极层214的预掺杂的区域中。举例而言，倘若需要改变掺杂程度或改变掺杂形式(例如N型掺杂、P型掺杂、无掺杂等)来形成多数组件，可利用罩幕层(图未绘示)来选择性掺杂闸极层214。
图2b绘示依据本发明的实施例在涂上罩幕层后的芯片200。在后续处理步骤中，例如蚀刻以形成要求的结构，罩幕层213用来保护在下方的闸极层214。在较佳实施例中，罩幕层213包含电浆加强氧化(Plasma-EnhancedOxide；PEOX)层216以及氮氧化硅(Silicon Oxynitride；SiON)层218，不过可以使用其它的罩幕层，例如光阻、TEOS氧化物等。电浆加强氧化层216的厚度以约200埃至约300埃为较佳，不过以260埃为更佳。氮氧化硅层218的厚度以约100埃至约200埃为较佳，不过以150埃为更佳。通过技术中已知任何适合的方法，例如CVD-氮化物，可沉积电浆加强氧化层216与氮氧化硅层218。
图2c依据本发明的一实施例，在闸极绝缘层212与闸极层214完成蚀刻后，所绘示图2b的芯片200。在较佳实施例中，闸极绝缘层212与闸极层214经过图案化与蚀刻，形成闸极结构220。为了将闸极绝缘层212与闸极层214图案化，图案化的罩幕(图未示)，例如光阻罩幕，可形成于罩幕层213上。在使用光阻制程的情况下，光阻材料沉积在氮氧化硅层218上，依据罩幕进行曝光以及显影，以去除光阻材料中不要的区域。
在氮氧化硅层218与电浆加强氧化层216完成图案化后，就蚀刻芯片200以去除闸极绝缘层212、闸极层214、电浆加强氧化层216以及氮氧化硅层218中不要的部分。蚀刻制程可为湿式或干式、非等向性或等向性的蚀刻制程，但以非等向性干式蚀刻制程为较佳。
图2d依据本发明的一实施例于完成氧化步骤后，所绘示的图2c的芯片200。通常在基材210上并沿着闸极结构220的侧壁会形成氧化区域222。在后续步骤中氧化区域222于基材210上且沿着闸极结构220的侧壁形成保护阻障层。
氧化反应可通过任何氧化程序执行，例如湿式或干式热氧化。然而，以干式氧化步骤为较佳，例如炉管回火、快速热氧化(Rapid ThermalOxidation；RTO)等执行。更佳者以温度约900℃至约1010℃，在包含氧化物、氧、及上述的组合等的气体中，维持约5秒至约15秒，执行RTO制程。氧化区域222的厚度以约15埃至约25埃为较佳。
图2e依据本发明的一实施例于罩幕层213完成移除后所绘示图2c的芯片200。在较佳实施例中，其中罩幕层213包含电浆加强氧化层216与氮氧化硅层218，并在磷酸中执行约8秒至约12秒的湿蚀刻来移除罩幕层213为较佳，但以约10秒为更佳。移除的罩幕层213会造成沿着闸极结构220与基材210边的氧化区域222部分或整个移除。在移除罩幕层213后，闸极结构220应该留下大体上为垂直的侧壁，提供较佳的指状接面轮廓并减少多晶硅指状接面漏电。
此后，可执行标准处理步骤例如掺杂、氧化、蚀刻、堆积成层等，以制造半导体组件，例如晶体管。
图3绘示依据本发明上述的实施例参照图2a至图2e所形成的晶体管300，其中类似图号代表类似组件。在这个例子中，闸极绝缘层212与闸极层214合称为闸极308，并形成晶体管300的闸极308。基材210含有的掺杂区310(源极/汲极)，代表晶体管300的源极与汲极。沿着闸极308侧壁的绝缘区312提供闸极308使用的间隙壁。
虽然本发明已以一特定实施例详细揭露如上，然其并非用来限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视后附的申请专利范围所界定者为准。举例而言，可使用不同形式的罩幕材料与光阻材料、不同厚度的闸极层、闸极绝缘层、罩幕层等。因此，当了解本发明可扩及其它结构及材料，故说明书及图标用来说明而非限定的意味。

Claims (15)

1、一种形成半导体组件的方法，其特征在于，该方法至少包含以下步骤：
形成一结构于一芯片上，该结构具有一第一层与一罩幕层，且该第一层具有一预掺杂的多晶硅层；
在移除该罩幕层之前，氧化该芯片以产生一氧化层；以及
移除该罩幕层。
2、根据权利要求1所述的形成半导体组件的方法，其特征在于：该结构为一闸极结构且包括一绝缘层。
3、根据权利要求2所述的形成半导体组件的方法，其特征在于：该绝缘层由一材料形成，该材料选自于实质上由氧化物、二氧化硅及上述的组合所组成的一族群。
4、根据权利要求1所述的形成半导体组件的方法，其特征在于：该氧化步骤由一快速热氧化法所执行。
5、根据权利要求4所述的形成半导体组件的方法，其特征在于：该快速热氧化法在900℃至1010℃的温度中执行。
6、根据权利要求4所述的形成半导体组件的方法，其特征在于：该快速热氧化法执行5秒至15秒。
7、根据权利要求1所述的形成半导体组件的方法，其特征在于：移除该罩幕层的步骤于磷酸中进行一湿蚀刻。
8、根据权利要求1所述的形成半导体组件的方法，其特征在于：该罩幕层包括一电浆加强氧化层与一氮氧化硅层。
9、一种在具有基材的芯片上形成半导体组件的方法，其特征在于，该方法至少包含以下步骤：
于该基材上形成一多晶硅层；
预掺杂该多晶硅层；
形成一罩幕层于该多晶硅层上；
蚀刻该罩幕层以及该多晶硅层；
氧化该芯片以产生一氧化层；以及
移除该罩幕层与该氧化层。
10、根据权利要求9所述的在具有基材的芯片上形成半导体组件的方法，其特征在于：该多晶硅层形成于一绝缘层上，且该绝缘层以选自于实质上由氧化物、二氧化硅及上述的组合所组成的一族群的一材料形成。
11、根据权利要求9所述的在具有基材的芯片上形成半导体组件的方法，其特征在于：形成该氧化步骤通过一快速热氧化法所执行。
12、根据权利要求11所述的在具有基材的芯片上形成半导体组件的方法，其特征在于：该快速热氧化法于900℃至1010℃的温度中执行。
13、根据权利要求11所述的在具有基材的芯片上形成半导体组件的方法，其特征在于：该快速热氧化法执行5秒至15秒。
14、根据权利要求9所述的在具有基材的芯片上形成半导体组件的方法，其特征在于：移除该罩幕层的步骤于磷酸中进行一湿蚀刻。
15、根据权利要求9所述的在具有基材的芯片上形成半导体组件的方法，其特征在于：该罩幕层包括一电浆加强氧化层与一氮氧化硅层。
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