CN1581983B

CN1581983B - On-board clock rapid measuring method

Info

Publication number: CN1581983B
Application number: CN2004100382426A
Authority: CN
Inventors: 徐春雨; 姚发定
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2004-05-18
Filing date: 2004-05-18
Publication date: 2011-01-05
Anticipated expiration: 2024-05-18
Also published as: CN1581983A

Abstract

The testing method includes (1) single board power on; (2) testing one timing route output; if testing result is error, then ending test after outputting error tested result; (3) if testing is correct; then testing whether there is output timing signal of another route; if testing is passed, then ending test, after outputting correct tested result; otherwise, test is added after error tested result is output. The method tests one route of timing signal output from timing buffer chip accurately so as to test functions of timing buffer chip. The method tests other timing signals output from timing buffer chip roughly so as to test on/off of PCB between pins of timing output of timing buffer chip and socket of single board. The invention raised testing efficiency suitable to requirement of quick production.

Description

A kind of veneer clock method for rapidly testing

Technical field

The present invention relates to the production test of communication equipment, in particular to a kind of clock test method of veneer.

Background technology

In the production test procedure of communication apparatus,, be the project that to test to the test of clock signal on the veneer socket.The method of accurate test is all adopted in present test.That is to say that several clock output signals for from a clock buffer chip output all carry out the test of the accuracy and the stability of frequency.Accurately the method for test has following two kinds:

1,, clock signal to be measured is guided to the test lead of frequency meter, directly reading of data respectively by special-purpose frequency meter test.

2,, clock signal to be measured is guided to the test lead of frequency meter, the accuracy and the stability of the long observing frequency of method with the naked eye respectively by oscilloscope.

3, the clock test circuit by Special Automaticization, the method of counting with the higher frequency reference clock, or the method that adopts lower frequency that clock is counted in some cycles, in the long time, carry out the test of frequency accuracy and stability.The benefit of this kind method than first kind has been to realize the automation of test.

But all clock signals that clock buffer chip branch is sent are all accurately tested and can be caused the testing time long, can not improve test speed, and particularly in large batch of production test field, long shortcoming of testing time is particularly remarkable.

Summary of the invention

The objective of the invention is to propose a kind of veneer clock method for rapidly testing of producing test in enormous quantities that is applicable to.

Following two characteristics based on the veneer clock test: 1, because the characteristics of modern IC manufacturing process, can make the performance of each road clock signal of being exported from a clock buffer chip all is the same with characteristics.2, from clock buffer chip clock output pin to one section PCB cabling is arranged the socket of veneer, and necessary to the test of PCB cabling path or disconnection.Therefore the core concept of the method for rapidly testing that proposes of the present invention is: on the veneer from wherein a tunnel accurately the testing of the clock signal of clock buffer chip output, the test whether clock signal on other road is existed.

The method for rapidly testing that the present invention proposes is as follows:

(1) Board Power up;

(2) output is accurately tested to one road clock wherein, if test result mistake then finish after exporting the result of test errors;

(3) if test is correct, the then the test whether clock signal on other road is existed, if test by finish behind the correct result of output test, otherwise finish behind the result of output test errors.

Perhaps:

(1) Board Power up;

(2) test that earlier whether the clock output that removes last road is existed continues if test is passed through, otherwise finishes behind the result of output test errors;

(3) last road clock output is accurately tested, if test result is correct, then finished behind the result that the output test is correct, otherwise finish behind the result of output test errors.

The method of testing whether clock signal is existed has two kinds:

1, the clock signal that will be output as differential signal is converted to non-differential clock signal; Adopt analog circuit, whether the characteristic of utilizing electric capacity to reset electricity when clock signal exists comes test clock signals to exist by the voltage that detects the electric capacity two ends.

2, the clock signal that will be output as differential signal is converted to non-differential clock signal; Adopt the monostable flip chip, by the numerical value of calculated resistance and electric capacity, make Q hold the cycle of the cycle of the clock signal of exporting less than the measured clock output signal, having under the situation of clock signal like this, the Q end is output as high level; Whether do not having under the situation of clock signal, the Q end is output as low level, come test clock signals to exist by the output level that detects the Q end.

The method of testing of using the present invention to propose, by the road clock signal of exporting from the clock buffer chip is accurately tested, can be to the functional test of whole clock buffer chip; By to walk through test, can test logical or disconnected from the clock output pin of clock buffer chip to PCB cabling the veneer socket from other clock signals of clock buffer chip output.

The method that adopts accurately test and walk through test to combine can shorten testing time of clock signal effectively, and the testing efficiency in raising production test field is particularly useful for the requirement of large batch of quick production test.

Description of drawings

Fig. 1 is the connection diagram that the present invention carries out quick clock test;

Fig. 2 is a kind of test circuit schematic diagram whether clock exists that carries out;

Fig. 3 is that another kind carries out the test circuit schematic diagram whether clock exists;

Fig. 4 is the flow chart of a specific embodiment of the present invention;

Fig. 5 is the flow chart of another specific embodiment of the present invention.

Embodiment

The present invention is described in further detail below in conjunction with drawings and Examples.

Fig. 1 is the connection diagram that the present invention carries out quick clock test.As shown in Figure 1, the clock output signal that comes out from the clock buffer chip has: clock output-1, clock output-2 ... clock output-n.When the present invention tests, only need test accurately, and other road clocks are carried out walk through test from the clock buffer chip, dividing the road clock signal that sends.Specifically in Fig. 1, select " clock output-1 " is accurately tested, to " clock output-2 " ..., " clock output-n " carry out walk through test.

Fig. 2 is a kind of test circuit schematic diagram whether clock exists that carries out.As shown in Figure 2, this test circuit adopts analog circuit to realize.Wherein resistance R 1 prevents that clock signal from passing through the direct shorted to earth of capacitor C, resistance R 2 has realized capacitor C discharge loop over the ground, the value of resistance R 1, resistance R 2 and capacitor C is in tested clock frequency, can realize the level on the capacitor C is effectively detected: when clock signal was arranged, the voltage on the capacitor C was detectable high level in the certain limit; If clock signal does not have, the electric capacity source of not charging so, the level that this moment, level detection can detect on the electric capacity is a low level.

Fig. 3 is that another kind carries out the test circuit schematic diagram whether clock exists, and this test circuit adopts the monostable chip to realize.As shown in Figure 3, in one embodiment of the invention, the monostable flip chip is 74LS123.By the value of calculated resistance R and capacitor C, make Q hold the cycle of the cycle of the clock signal of exporting less than the measured clock output signal, having under the situation of clock signal like this, Q end perseverance remains high level; Do not having under the situation of clock signal, the Q end is permanent low level.

Fig. 4 is the flow chart of a specific embodiment of the present invention.As shown in Figure 4, specifically comprise:

(1) Board Power up;

Fig. 5 is the flow chart of another specific embodiment of the present invention.As shown in Figure 5, specifically comprise:

(1) Board Power up;

(3) last road clock output is accurately tested, if test result is correct, then correct result is tested in output.

Claims

1. veneer clock method for rapidly testing, it is characterized in that: the performance of each road clock signal of being exported from a clock buffer chip all is the same with characteristics, to wherein a tunnel accurately testing from the clock signal of clock buffer chip output on the veneer, to the test whether clock signal on other road exists, described accurate test is for to the accuracy that output signal frequency carried out of clock buffer chip and the test of stability.

2. method of testing according to claim 1 is characterized in that comprising the following steps:

(1) Board Power up;

3. method of testing according to claim 1 is characterized in that comprising the following steps:

(1) Board Power up;

4. according to claim 2 or 3 described method of testings, it is characterized in that the described method of testing whether clock signal is existed is:

The clock signal that is output as differential signal is converted to non-differential clock signal;

Adopt analog circuit, whether the characteristic of utilizing electric capacity to reset electricity when clock signal exists comes test clock signals to exist by the voltage that detects the electric capacity two ends.

5. according to claim 2 or 3 described method of testings, it is characterized in that the described method of testing whether clock signal is existed is:

Adopt the monostable flip chip, by the numerical value of calculated resistance and electric capacity, make Q hold the cycle of the cycle of the clock signal of exporting less than the measured clock output signal, having under the situation of clock signal like this, the Q end is output as high level; Whether do not having under the situation of clock signal, the Q end is output as low level, come test clock signals to exist by the output level that detects the Q end.

6. method of testing according to claim 5 is characterized in that described monostable flip chip is 74LS123.