CN1577765A - Process kit for erosion resistance enhancement - Google Patents
Process kit for erosion resistance enhancement Download PDFInfo
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- CN1577765A CN1577765A CNA2004100589510A CN200410058951A CN1577765A CN 1577765 A CN1577765 A CN 1577765A CN A2004100589510 A CNA2004100589510 A CN A2004100589510A CN 200410058951 A CN200410058951 A CN 200410058951A CN 1577765 A CN1577765 A CN 1577765A
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- polymer material
- procedure assembly
- process kit
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- 238000000034 method Methods 0.000 title claims abstract description 92
- 230000008569 process Effects 0.000 title abstract description 23
- 230000003628 erosive effect Effects 0.000 title abstract 3
- 239000002861 polymer material Substances 0.000 claims abstract description 14
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000012545 processing Methods 0.000 claims description 64
- 239000000463 material Substances 0.000 claims description 20
- 238000005260 corrosion Methods 0.000 claims description 12
- 230000007797 corrosion Effects 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims description 3
- 239000004810 polytetrafluoroethylene Substances 0.000 claims description 3
- -1 polytetrafluoroethylene Polymers 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 239000002245 particle Substances 0.000 abstract description 5
- 230000000750 progressive effect Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 31
- 239000010410 layer Substances 0.000 description 23
- 239000007789 gas Substances 0.000 description 15
- 239000013078 crystal Substances 0.000 description 14
- 229920000642 polymer Polymers 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 9
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 8
- 230000008859 change Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229920002313 fluoropolymer Polymers 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- PRPAGESBURMWTI-UHFFFAOYSA-N [C].[F] Chemical compound [C].[F] PRPAGESBURMWTI-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000013047 polymeric layer Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32458—Vessel
- H01J37/32477—Vessel characterised by the means for protecting vessels or internal parts, e.g. coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
- H01J37/32642—Focus rings
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Plasma Technology (AREA)
Abstract
A process kit is described that resists plasma erosion, preserves the spatial uniformity of plasma properties, reduces particle generation in the chamber, and significantly enhances the lifetime of the process kit. A layer of polymer material covers the top surface of the process kit. The polymer material is fluorocarbon-based and not reactive with the species in the plasma. The polymer material not only protects the process kit from progressive erosion, but also prevents the generation of particles in the chamber. The polymer material has similar permittivity to that of the process kit and therefore maintains the spatial uniformity of plasma properties, e.g., etch rate, near the wafer perimeter. The thickness of the layer is controlled between 0.5 and 1.5 mm such that the difference between its coefficient of thermal expansion and that of the process kit will not cause the layer to peel off the process kit's top surface.
Description
Technical field
The invention relates to a kind of processing procedure assembly, its be centered around semiconductor work package in the plasma chamber around, to improve the spatially uniform that the lip-deep energy of plasma of work package distributes.Particularly, the invention relates to a kind of fluorocarbon polymer layer, it covers the upper surface of processing procedure assembly, but the life-span of its resisting plasma corrosion, the pollution that reduces particle in the etching process and raising processing procedure assembly.
Background technology
Manufacture of semiconductor comprises a series of fabrication steps, and to produce the integrated circuit of many definition in the semiconductor work package, this semiconductor workpiece for example is the Silicon Wafer that is applied to circuit design.Wherein an important processing procedure promptly is the plasma etching processing procedure, it is in order to cover the design transfer of curtain material layer to another beneath rete of cover curtain with one, rete under the cover curtain for example is conductive layer or dielectric materials layer, and plasma etching promptly is that this film material is removed by this crystal column surface.
Plasma etching is to carry out in as the plasma-reaction-chamber that Fig. 1 illustrated.Reative cell 100 comprises a chamber 110, and it comprises a sidewall 112, a bottom 114 and a top 160.Chamber 110 comprises the position in a processing procedure district 118 of centre, and its volume of containing is about 5,000 to 50,000cm
3Reative cell 100 more comprises a process gas supply 120, its in order to gas to be provided so that gas enter in the chamber 110 through a gas manifold 162, and a gas panel or shower nozzle 164, it is positioned at the top 160 of chamber 110.The discharge gas of processing procedure, it for example is gas or the etch products of using up, and discharges outside the chamber 110 by pump 140.In addition, the pressure in the choke valve 145 control chambers 110.And the sidewall 112 of ground connection, bottom 114, top 160 and shower nozzle 164 generally all are made with aluminium, and it is by the inner surface of Electroplating Aluminum in chamber 110.Chamber 110 also comprises pedestal 130, and it is in order to support semiconductor wafer 190.Pedestal 130 by a supports insulative thing 132 and with bottom 114 electrical isolation, and pedestal 130 can be connected to a radio frequency (RF) power system 150 by a radio frequency (RF) matching network 155.
Control system 180 comprises a CPU 182, an internal memory 184 and supports circuit 186.CPU 182 is coupled to a plurality of assemblies of reative cell 100 to operate this a little assemblies.Internal memory 184 can be any computer-readable media, and it for example is the digital storage device of random access memory (RAM), read-only memory (ROM), floppy disk, hard disk or other form, and it can be the zone or long-range for reative cell 100 or CPU 182.And there are software routine or a series of program command in system in internal memory 184, when CPU 182 carries out, and the processing procedure that chamber 100 is scheduled to.
When the material layer on 100 pairs of wafers 150 of desire use plasma-reaction-chamber carries out etching, at first utilize pump 140 that chamber 110 is vacuumized so that the pressure in the chamber 110 are lower than 1mTorr.Afterwards wafer is moved in the chamber 110 by remaining near the loading transfer chamber (not illustrating) of vacuum is middle, and it is positioned on the pedestal 130.In dielectric etch processing procedure process, can utilize the machinery or the Electrostatic Absorption utmost point (not illustrating) that wafer is fixed.In addition, some grooves are arranged on the surface of pedestal 130, refrigerating gas is arranged in the groove, it for example is a helium, and it is in order to the temperature of control wafer.
Afterwards, the process gas that will be made of the gas composition thing of multiple volume flow rate is released in the chamber 110, when the pressure in the chamber 110 has been stabilized in a predetermined degree, opens RF power-supply system 150 and in the processing procedure district, form plasma sheath (plasma sheath) to supply with the process gas energy.Can open RF matching network 155 so that the plasma in RF power system 150 and the process chamber 110 effectively couples.Improve plasma density, the higher ion volume density is defined as the long-pending number of ions of every monomer, can see through in a plurality of magnet 170 of chamber sidewall 112 placed around to reach in the chamber 110 inner modes that produce slow rotating magnetic field.Magnet can be the electromagnet (not illustrating) by low frequency (0.1-0.5Hertz) phase AC driven with current sources.In addition, magnet can be the permanent magnet that is fixed on the supporting construction (not illustrating), the rotating speed rotation that it changes with for example per second 0.1-0.5.
Utilize pedestal 130 as a cathode electrode, and with sidewall 112, top 160 and shower nozzle 164 ground connection with jointly as an anode electrode, and the RF power-supply system can produce a negative voltage in processing procedure district 118.Therefore the DC bias voltage can be formed between plasma and the wafer in fact, and produces the ionic bombardment that energy is arranged on wafer, with undesired part on the etched wafer surface.When etching is finished, close RF power-supply system 150 earlier, close the plasma of process gas again.
In order to make plasma chamber have productivity and reliability, the problem of many particles need be handled, and one of them problem promptly is how to keep the uniformity of the plasma etching rate on the crystal column surface.Rate of etch refers to a material layer by the speed that removes on the crystal column surface, and it is the key factor of the usefulness of assessment one etch process.Because the integrated circuit of many definition can form simultaneously, and must very determine that it is best therefore can uniform rate of etch being arranged above whole wafer by the integrated circuit that the fabrication steps of many definition is made.It is easy uniform rate of etch being arranged in crystal circle center, but uniform rate of etch to be arranged at the periphery of wafer be difficult, and this is because the snag on the surface at crystal round fringes place tends to influence the distribution of energy of plasma.And the problem of such edge rate of etch can be more serious because of the development of the increase of wafer size and integrated circuit downsizing.
A kind of method that solves edge problem of tradition is to install a circular processing procedure assembly 195 in chamber 110 around wafer 190.The opposite of the upper surface of conventional process assembly before being corroded can form plasma field, and guarantees the uniformity of the rate of etch of crystal round fringes.For example, upper surface can become an obtuse angle with crystal column surface is capable, and this angle for example is to 135 degree by 120 degree.Because the orientation of this angle is, the plasma ion of vertical impact surface can produce lateral drift toward crystal circle center, and the wide region on wafer spreads out, and is not concentrated in the edge of wafer.
Yet when the upper surface of processing procedure assembly was exposed to some etch chemistries, it can produce reaction with etchant, therefore can be corroded after a period of time.For example, with quartzy, the made processing procedure assembly of silicon dioxide crystal, when it was exposed in the fluorocarbon plasma, it for example was CF
4, be very easy to produce reaction.CF
4With SiO
2Reaction can produce etch products SiF
4, CO, CO
2And COF
2Or the like.
The corrosion of processing procedure assembly not only can produce a large amount of particle contaminations, but also can destroy the spatial uniformity near the rate of etch of wafer periphery, and causes more a plurality of defectives.Obvious, its special angle that distributes and exert an influence for plasma ion has been lost on the surface of corrosion.
Therefore, though the conventional process assembly can be avoided the space problem of non-uniform near the rate of etch of wafer periphery, reducing the corrosion of processing procedure assembly upper surface and improving its life-span has needs.
Summary of the invention
The present invention can be used for the etch process of oxide especially and other has the etch process of high response for dielectric material in manufacture of semiconductor.
According to first purpose of the present invention, the part upper surface of processing procedure assembly is covered by a fluorocarbon polymer layer.Because polymeric layer is the fluorine carbide, so its influence that is subjected to fluorocarbon plasma gas is less.Therefore, this rete can effective isolation processing procedure assembly preventing the corrosion of reactive material, and life-span of the increase processing procedure assembly of essence.
According to second purpose of the present invention, the dielectric constant of polymeric material is similar to the dielectric constant of processing procedure assembly.Such arrangement can be so that the spatial uniformity of the plasma properties of close crystal round fringes be maintained in the processing procedure process.
According to the 3rd purpose of the present invention, the thickness of fluorocarbon polymer layer is to be controlled at enough thin degree, and it for example is 1.5mm, the impact that causes with the difference that reduces the thermal coefficient of expansion (CTE) between polymeric material and the processing procedure assembly.Even the CTE of polymer is significantly different with the CTE of processing procedure assembly, but because therefore the restriction of its thickness can reduce the influence that is caused of the variations in temperature on polymeric layer.
Description of drawings
Fig. 1 illustrates known a kind of in order to carry out the schematic diagram of the etched plasma-enhanced reactor of dielectric medium;
Fig. 2 illustrates known a kind of generalized section of not carrying out the processing procedure assembly of plasma etching protection;
Fig. 3 illustrates the generalized section of a kind of processing procedure assembly of the embodiment of the invention.The element numbers explanation
100: reative cell 110: chamber
112: sidewall 114: bottom
160: top 118: the processing procedure district
120: process gas supply 162: gas manifold
164: shower nozzle 140: pump
145: choke valve 130: pedestal
190: semiconductor crystal wafer 132: the supports insulative thing
155: radio frequency (RF) matching network 150: power system
180: control system 182:CPU
184: internal memory 186: support circuit
Embodiment
Processing procedure assembly of the present invention can provide uniform plasma ion and make energy of plasma be evenly distributed on the surface of semiconductor crystal wafer.And the corrosion of the high response material that processing procedure assembly of the present invention can prevent from the plasma to be produced, therefore, effectively life-saving increases production capacity, reduces the consume cost of processing procedure.In addition, processing procedure assembly of the present invention can be applied in the plasma reactor, for example is dielectric medium etching eMAX system (DielectricEtch eMAX System), the super eCentura of dielectric medium etching system (Dielectric Etch SupereCentura System) or the Centura MxP dielectric medium etch system (Centura MxP DielectricEtch System) of US business Applied Materials.
The thin portion of Fig. 2 illustrates the profile of known pedestal 130, wafer 190 and the processing procedure assembly 195 of Fig. 1.Wafer 190 is firmly on the Electrostatic Absorption utmost point (electrostatic chuck) (not illustrating) or e-chuck.E-chuck system is positioned at embedding and on the dielectric components 390 of negative electrode 350, and wherein negative electrode is corresponding with the anode (not illustrating) that is positioned at the chamber top.Negative electrode RF power supply unit 150 can produce negative voltage on negative electrode 350.Dielectric post 360 and support insulator 370 can be in order to protection dielectric medium parts 390 and the parts that are positioned within the support insulator 370 other, to prevent corrosion.Processing procedure assembly 195 is looped around around the wafer 190, and basically, this kind processing procedure assembly 195 is a kind of very special circuluses, its explanation as after, and it comprises in one ring 340 and outer shroud 330.
The serious problems that above-mentioned processing procedure assembly 195 is produced in the use are that the employed material of processing procedure assembly can corrode gradually because of the chemical characteristic of chamber ionic medium body.Therefore, the size and dimension of processing procedure assembly can influence the distribution of wafer periphery energy of plasma, and corrosion can make various characteristics change, and for example carries out the etch-rate of etch process in the chamber.When this change reaches to a certain degree, will make the quality of product descend.In addition, the particulate that corrosion is produced also can be deposited on the wafer, makes product produce defective.Because the energy of plasma of interior ring 340 is much larger than outer shroud 330, therefore, the corrosion phenomenon of interior ring 340 is far seriously in outer shroud 330.
Fig. 3 illustrates embodiments of the invention, and the upper surface of processing procedure assembly 420 is covered with fluorine carbon polymeric material, and its material for example is a polytetrafluoroethylene (PTFE).
Processing procedure assembly of the present invention has a plurality of advantages compared to known processing procedure assembly.The first, the material of polymer is exposed under the fluorocarbon plasma environment and is inertia, can prevent that the upper surface of processing procedure assembly from producing chemical reaction as a good insulation performance body when dielectric layer etch.The second, polymeric material has identical dielectric constant (permittivity or dielectric constant), can be used as the material that contains dielectric layer on the crystal column surface.Crystal column surface is evenly distributed to the dielectric constant on the processing procedure assembly and helps the uniformity of its plasma distribution.Dielectric layer can make the rate of etch of wafer periphery produce obviously change to the dielectric constant utmost point change hurriedly of polymeric material.Three, bombardment that polymer layer also can anti-chamber ionic medium body ion and circulation change that can the heatproof degree are with the access times that increase the processing procedure assembly and prolong its useful life.In addition, this kind processing procedure assembly can reduce and repeat to be coated with polymer layer situation in its surface.
Though the fluorocarbon polymer material has preferable chemical characteristic and dielectric property,, in use, its thermo-mechanical property but has its challenge.More particularly, this kind material coefficient of thermal expansion coefficient (CTE) is normally very high, for example is 50-200PPM/ ℃.On the contrary, quartzy thermal coefficient of expansion but is low-down, normally is lower than 5PPM/ ℃.Therefore, when temperature change, the thermal deformation of polymer layer will be much larger than quartz, and polymer layer is understood distorted deformation and peeled off when rising-heat contracting-cold.The thickness of limit polymerization layer can reduce the influence that thermal expansion coefficient difference causes.On the other hand,, can not effectively make the processing procedure assembly completely cut off plasma, stand the bombardment of plasma ion if the thickness of polymer layer is too thin.In one embodiment, the thickness of polymer layer is less than 1.5mm, and can avoid thermal expansion is the influence of different difference, and can have enough anti-corrosion effects.The polymer layer 425 that Fig. 3 illustrated, compared to wafer 410 and processing procedure assembly 420, its thickness is big.
The processing procedure assembly is exposed in radio frequency (RF) signal of plasma etch conditions, to measure its life-span (hourage).Processing procedure assembly of the present invention in the plasma environment of gentleness the RF hourage be 500-600RF hour; Known do not have the processing procedure assembly of fluorine carbon coating layer then to be 150RF hour.
Fluorocarbon layer on the processing procedure assembly of the present invention can be with the several different methods manufacturing.When the thinner thickness of polymer layer, when for example being 0.5mm, the method for its formation, can adopt for example is the mode of sputter, with material layer depositions on the surface of processing procedure assembly.When the thickness of polymer layer is thicker, it for example is hot rubbing method that the method for its formation can adopt, and material is formed on the surface of processing procedure assembly.
Special term is used in the front narration, in order to illustrate, with thorough understanding the present invention.Yet for being familiar with this skill person, this specific detail clearly is not to implement necessary condition of the present invention.Just in order preferable explanation to be arranged, be familiar with the various embodiment that this skill person can utilize the present invention and be suitable for the difference variation of various special-purposes at this selected and described embodiment so as to making to principle of the present invention and its practical application.Therefore, other kenel is not got rid of in the description of front, or limits the invention to this specific kenel, in other words, above institute teaching, various modification and variation can be arranged.
Claims (10)
1. processing procedure assembly, it is characterized in that in order to promote the corrosion resistance in the plasma etching reaction chamber, comprising:
One ring is around the semiconductor wafer; And
One polymer material layer covers the surface of this ring at least.
2. processing procedure assembly as claimed in claim 1 is characterized in that this ring is made by quartz.
3. processing procedure assembly as claimed in claim 1 is characterized in that, this polymer material layer is a fluorocarbon material layer.
4. processing procedure assembly as claimed in claim 1 is characterized in that, this polymer material layer is a polytetrafluoroethylene.
5. processing procedure assembly as claimed in claim 1 is characterized in that this polymer material layer covers the upper surface of this ring at least fully.
6. processing procedure assembly as claimed in claim 1 is characterized in that, this polymer material layer can not react with the etchant in the plasma.
7. processing procedure assembly as claimed in claim 1 is characterized in that the dielectric constant of this polymer material layer is similar to the dielectric constant of silicon dioxide.
8. processing procedure assembly as claimed in claim 1 is characterized in that the thickness of this polymer material layer is between between the 0.5mm to 1.5mm.
9. processing procedure assembly as claimed in claim 1 is characterized in that, this polymer material layer sputter is on the surface of this ring.
10. processing procedure assembly as claimed in claim 1 is characterized in that this polymer material layer is coated on the surface of this ring.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/627,213 US20050016684A1 (en) | 2003-07-25 | 2003-07-25 | Process kit for erosion resistance enhancement |
| US10/627,213 | 2003-07-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1577765A true CN1577765A (en) | 2005-02-09 |
Family
ID=34080593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2004100589510A Pending CN1577765A (en) | 2003-07-25 | 2004-07-23 | Process kit for erosion resistance enhancement |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20050016684A1 (en) |
| KR (1) | KR20050012694A (en) |
| CN (1) | CN1577765A (en) |
| TW (1) | TW200504816A (en) |
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| US11566324B2 (en) | 2020-02-27 | 2023-01-31 | Applied Materials, Inc. | Conditioning treatment for ALD productivity |
| US20240018648A1 (en) * | 2022-07-14 | 2024-01-18 | Applied Materials, Inc. | Purge Ring for Reduced Substrate Backside Deposition |
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| US4174994A (en) * | 1976-11-05 | 1979-11-20 | Savelkouls Leonardus J | Apparatus for metal coatings |
| US6284093B1 (en) * | 1996-11-29 | 2001-09-04 | Applied Materials, Inc. | Shield or ring surrounding semiconductor workpiece in plasma chamber |
| US6074488A (en) * | 1997-09-16 | 2000-06-13 | Applied Materials, Inc | Plasma chamber support having an electrically coupled collar ring |
| US6364957B1 (en) * | 1997-10-09 | 2002-04-02 | Applied Materials, Inc. | Support assembly with thermal expansion compensation |
| KR100258984B1 (en) * | 1997-12-24 | 2000-08-01 | 윤종용 | Dry etching apparatus |
| US6123791A (en) * | 1998-07-29 | 2000-09-26 | Applied Materials, Inc. | Ceramic composition for an apparatus and method for processing a substrate |
| US6620520B2 (en) * | 2000-12-29 | 2003-09-16 | Lam Research Corporation | Zirconia toughened ceramic components and coatings in semiconductor processing equipment and method of manufacture thereof |
-
2003
- 2003-07-25 US US10/627,213 patent/US20050016684A1/en not_active Abandoned
-
2004
- 2004-07-23 TW TW093122031A patent/TW200504816A/en unknown
- 2004-07-23 CN CNA2004100589510A patent/CN1577765A/en active Pending
- 2004-07-26 KR KR1020040058183A patent/KR20050012694A/en not_active Application Discontinuation
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| CN101643895B (en) * | 2008-08-04 | 2011-03-23 | 中芯国际集成电路制造(北京)有限公司 | Plasma reaction chamber pretreatment method |
| CN107978507A (en) * | 2013-07-19 | 2018-05-01 | 应用材料公司 | Method for the chamber part and article of manufacture of processing chamber housing |
| CN107978507B (en) * | 2013-07-19 | 2019-12-06 | 应用材料公司 | Chamber component for a processing chamber and method of manufacturing an article |
| CN104425202A (en) * | 2013-09-02 | 2015-03-18 | 松下电器产业株式会社 | Plasma processing apparatus |
| CN104425202B (en) * | 2013-09-02 | 2018-09-18 | 松下知识产权经营株式会社 | Plasma treatment appts |
| US11145494B2 (en) | 2013-09-02 | 2021-10-12 | Panasonic Intellectual Property Management Co., Ltd. | Plasma processing apparatus |
| US9792547B2 (en) | 2014-03-18 | 2017-10-17 | Panasonic Intellectual Property Management Co., Ltd. | Neural network circuit and learning method for neural network circuit |
| CN111319324A (en) * | 2020-03-17 | 2020-06-23 | 李珮豪 | Composite material for cooker, stainless steel cooker and preparation method of stainless steel cooker |
| CN111319324B (en) * | 2020-03-17 | 2022-05-20 | 李珮豪 | Composite material for cooker, stainless steel cooker and preparation method of stainless steel cooker |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200504816A (en) | 2005-02-01 |
| US20050016684A1 (en) | 2005-01-27 |
| KR20050012694A (en) | 2005-02-02 |
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