CN1567219A - Test circuit for non-contact type integrated circuit and test method thereof - Google Patents
Test circuit for non-contact type integrated circuit and test method thereof Download PDFInfo
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- CN1567219A CN1567219A CN 03129680 CN03129680A CN1567219A CN 1567219 A CN1567219 A CN 1567219A CN 03129680 CN03129680 CN 03129680 CN 03129680 A CN03129680 A CN 03129680A CN 1567219 A CN1567219 A CN 1567219A
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Abstract
This invention relates to a kind of non-contact integrated circuit card testing circuit and testing method. The PC (5) inputs the testing logic circuit to FPGA part (1) by programming; when the testing software in PC (5) sends command to read-write equipment (4), the read-write equipment (4) receives the command from PC (5), and issues modulating signal according to the command. The modulating signal is sent to radio frequency interface circuit (2) through aerial coil (3), and sent to FPGA part (1), which receives signal and transfers the responding signal to radio frequency interface circuit (2), and sends to the read-write equipment (4) through aerial coil (3) and transmits to PC (5). The testing software captures the responding signal then judges the testing is right or wrong, and outputs the corresponding result.
Description
Technical field
The present invention relates to a kind of integrated circuit card test circuit and method of testing thereof, relate in particular to a kind of contactless integrated circuit card test circuit and method of testing thereof.
Background technology
In the design process of integrated circuit, be very important to the test and the checking of the logic function of designed integrated circuit.Along with integrated level increase and system more and more complicated, the cost of test is costliness more and more also.By statistics and theoretical analysis, we know that the time that produces test pattern sets is directly proportional with the cube of circuit input end mouth number.Therefore, do two if can evenly divide circuit-under-test, then the T.T. that two sub-pieces tests are spent only is original about 1/8th.
The basic point of design for Measurability is controllability and observability.Controllability is meant can both carry out the set and the control that resets to each node of circuit inside.Observability is directly or indirectly to observe the state of any node in the circuit.
The combinational circuit that n input arranged.Need add 2 if test this combinational circuit fully
nInferior input and carry out 2
nInferior observation.If this circuit is added m latch and internal feedback that storage capacity is arranged.At this moment the state of circuit depends on current input and previous state.
In order thoroughly to detect this sequential circuit, just need add 2
N+mIndividual input also carries out 2
N+mInferior observation.To a large scale integrated circuit, if n=25, m=50 then needs 2
75Individual test pattern.Even such test pattern is arranged and with the operating speed work of each test pattern 1 μ S, be to 2
75Individual pattern is all tested a required shortest time will be above 1,000,000,000 years!
If will test, need to generate test patterns to chip.Test patterns comprises input stimulus and export target value, utilizes circuit simulation model can determine the export target value, in test process, the real response and the export target value of circuit-under-test is compared.To reach test purpose, at first be to study the qualified degree that generates minimum testing time and guarantee circuit-under-test.
In the smart card of band microprocessor, extensively adopt special method of testing.Special test is to adopt the method for simpler and easy row that the main basic function of circuit and system is tested.Normally test point is divided and added to big circuit, for example, will be divided into less counter than long counter circuit and test respectively, can significantly be reduced the test vector of required usefulness.Division is often decided by the function of each module to circuit, in order specially to push up test, has a mind to add multiplexer channel during design, thereby two submodules can independently be tested respectively.
Test for contactless integrated-circuit card, because signal communication is coupled by antenna, test and checking to its logic function are the comparison difficulties, and be very consuming time, thereby design a correct effectively test circuit system and find one fully efficiently method of testing be very important.
Summary of the invention
The technical issues that need to address of the present invention have provided a kind of contactless integrated circuit card test circuit and method of testing thereof, are intended to solve at present also not the defective of method of testing fully efficiently to correct effectively test circuit of testing contactless integrated circuit card and.
In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions:
Circuit of the present invention comprises FPGA part (field programmable gate array), radio-frequency interface circuit, aerial coil, read write line, PC; Described PC is input to the FPGA part with tested logical circuit through programming; When the testing software on the PC sends instruction to read write line, read write line is accepted the instruction of PC and is sent modulation signal according to instruction, the signal that aerial coil is come coupling is passed to radio-frequency interface circuit, radio-frequency interface circuit is given FPGA part signal through demodulation, FPGA part acknowledge(ment) signal also can send specific response signal according to signal and give radio-frequency interface circuit, radio-frequency interface circuit is modulated again, signal after the modulation is delivered on the aerial coil, send to PC again after being come by read write line coupling, the correctness of test just can be judged after capturing response signal by testing software, and makes corresponding output:
Method of the present invention realizes as follows:
By PC tested logical circuit is input to the FPGA part through programming;
Send instruction by the testing software on the PC to read write line;
Send modulation signal by read write line;
By aerial coil output modulation signal;
Give FPGA part signal by radio-frequency interface circuit through demodulation;
Also can send specific response signal by FPGA part acknowledge(ment) signal and give radio-frequency interface circuit according to signal;
Modulate by radio-frequency interface circuit, the signal after the modulation is delivered on the aerial coil;
The signal of coupling being come by read write line sends to PC again;
Judge test result and make corresponding output by the testing software of PC; Perhaps FPGA is partly resetted, again test by reset circuit;
Compared with prior art, the invention has the beneficial effects as follows: can make things convenient for and quickly the logic function in the contactless integrated circuit card is tested and verify.
Description of drawings
Fig. 1 is a circuit block diagram of the present invention;
Fig. 2 is the block scheme of radio-frequency interface circuit;
Fig. 3 is the circuit diagram of radio-frequency interface circuit;
Fig. 4 is the circuit diagram of reset circuit;
Fig. 5 is the circuit diagram of DOWNLOAD CABLE (download line);
Fig. 6 is a method flow diagram of the present invention;
Wherein: FPGA part 1, radio-frequency interface circuit 2, aerial coil 3, read write line 4, PC 5, reset circuit 6, clock generating circuit 21, rectification circuit 22, mu balanced circuit 23, modulation/demodulation circuit 24, electrify restoration circuit 25.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:
By Fig. 1, Fig. 2 as seen: circuit of the present invention comprises FPGA part 1, radio-frequency interface circuit 2, aerial coil 3, read write line 4, PC 5; Described PC 5 is input to FPGA part 1 with tested logical circuit through programming; When the testing software on the PC 5 sends instruction for read write line 4, read write line 4 is accepted the instruction of PC 5 and is sent modulation signal according to instruction, the signal that aerial coil 3 is come coupling is passed to radio-frequency interface circuit 2, radio-frequency interface circuit 2 is given FPGA part 1 signal through demodulation, FPGA part 1 acknowledge(ment) signal also can send specific response signal according to signal and give radio-frequency interface circuit 2, radio-frequency interface circuit 2 is modulated again, signal after the modulation is delivered on the aerial coil 3, send to PC 5 again after being come by read write line 4 coupling, the correctness of test just can be judged after capturing response signal by testing software, and makes corresponding output;
Circuit of the present invention also comprises reset circuit 6; Described reset circuit 6 is connected between FPGA part 1 and the PC 5, so that FPGA part 1 is resetted;
Described FPGA part 1, radio-frequency interface circuit 2 and aerial coil 3 are placed on the circuit board;
Described FPGA part 1 is to be connected with PC 5 by DOWNLOAD CABLE; The end of DOWNLOADCABLE comprises 25 pins and links to each other with the parallel port of PC 5, and the other end comprises on the circuit board of 10 pins and FPGA part 1 and links to each other;
Described FPGA part 1 can be EEPROM, SRAM, and EPROM is to use the internal storage of storer as the contactless integrated circuit card chip;
Described radio-frequency interface circuit 2 comprises clock generating circuit 21, rectification circuit 22, mu balanced circuit 23, modulation/demodulation circuit 24, electrify restoration circuit 25; The electromagnetic wave that described rectification circuit 22 is sensed the aerial coil 3 and induction current that produces offers described clock generating circuit 21, modulation/demodulation circuit 24, electrify restoration circuit 25, FPGA part 1 by mu balanced circuit 23 after rectification; Described clock generating circuit 21, modulation/demodulation circuit 24, electrify restoration circuit 25 are respectively with clock signal, and data-signal and reset signal are transferred to FPGA part 1;
Described reset circuit 6 can be to produce reset signal by button to carry out hardware reset, perhaps by cable reset signal is connected to produce reset signal by software on the parallel port of PC 5 and carry out the software reset;
As seen from Figure 6: method of the present invention realizes as follows:
By PC tested logical circuit is input to FPGA part 101 through programming;
Send instruction 102 by the testing software on the PC to read write line;
Send modulation signal 103 by read write line;
By aerial coil output modulation signal 104;
Give FPGA part 105 signal by radio-frequency interface circuit through demodulation;
Also can send specific response signal by FPGA part acknowledge(ment) signal and give radio-frequency interface circuit 106 according to signal;
Modulate by radio-frequency interface circuit, the signal after the modulation delivers on the aerial coil 107;
The signal of coupling being come by read write line sends to PC 108 again;
Judge test result and make corresponding output 109 by the testing software of PC; Perhaps FPGA is partly resetted, again test by reset circuit;
Below in conjunction with physical circuit figure principle of the present invention is described as follows:
Programming to the FPGA part realizes by PC and DOWNLOAD CABLE.DOWNLOAD CABLE one end (25 pins) is connected on the parallel port of PC, and the other end (10 pins) is connected on the FPGA partial circuit plate, can carry out online programming easily like this.Programming mode is followed the jtag boundary scan protocols.Can programme with MAX+PLUS II software, also available additive method is realized.Table 1 table 2 and Fig. 5 are respectively pin figure and the circuit diagrams of DOWNLOAD CABLE.
Table 1:DOWNLOAD CABLE pin figure a
| ????25-PIN?HEADER | ????JTAG?MODE?SIGNAL ????NAME |
| ????2 | ????TCK |
| ????3 | ????TMS |
| ????8 | ????TDI |
| ????11 | ????TDO |
| ????13 | ????NC |
| ????15 | ????GND |
| ????18?TO?25 | ????GND |
Table 2:DOWNLOAD CABLE pin figure b
| ??10-Pin ??Header | ???????????JTAG?Mode | |
| ??Signal ??Name | ??Description | |
| ??1 | ??TCK | ??Clock?signal |
| ??2 | ??GND | ??Signal?ground |
| ??3 | ??TDO | ??Data?from?device |
| ??4 | ??VCC | ??Power?supply |
| ??5 | ??TMS | ??JTAG?state ??machine?control |
| ??6 | ??NC | ??No?connect |
| ??7 | ??NC | ??No?connect |
| ??8 | ??NC | ??No?connect |
| ??9 | ??TDI | ??Data?to?device |
| ??10 | ??GND | ??Signal?ground |
Test to the FPGA part is to finish to read write line transmission instruction by the testing software that carries out on PC.PC and read write line connect together by serial ports, and the data communication between them all is serial.
To the retouching operation of storer or register may be also will be by verifying the modification correctness carrying out a read operation.Carry out follow-on test and also need to write complete test code for the complete test of FPGA part.Write complete test code and will consider the various situations of test or the possible conditions of needing, test code whether fully be directly connected to the complete of follow-on test result.Just can verify the logic function correctness of the circuit of being tested according to the result of follow-on test.
This non-contact card chip has the storer of 64BLOCK, and each BLOCK may carry out following instruction: read (read data piece), write (write data piece), initvalue (initialization value piece), readvalue (value of reading piece), inc (adding), dec (subtracting) etc.Such as testing read instruction, then testing software sends the read instruction, and through above-described testing process, the FPGA part can be returned test result, if read out, then can return the value of reading back and, if do not read out then can return error code.And for the write instruction, when the value of writing was in block, FPGA can return the result who writes, if do not write into then return error code, if write into then return correct code, but at this moment also will carry out the read operation of this block, the result who comes according to reading back could judge and writes correctness.Then will consider all conditions for testing fully, the block that has during such as logical design can not read, and what have can read, and will judge the correctness of reading according to the readable nature of situation about reading out and this piece when testing so.Like this too for other instructions.Could guarantee the integrality of test like this.
FPGA partly is the numerical portion that is used for simulating the contactless integrated circuit chip, just tested circuit.Can select suitable capacity ground FPGA partly to load the code of noncontact chip as required, also be that a socket is arranged on pcb board as required when the design pcb board, can plug respective pin ground fpga chip.This circuit has DOWNLOAD CABLE interface, and chip code can download in the FPGA part by DOWNLOAD CABLE, and the available I/O mouth of FPGA part is drawn on circuit board, can easily the signal of drawing be tested.The signal that FPGA part receiving radio-frequency interface circuit passes over is handled, to sending corresponding feedback signal after the signal Processing.
Fig. 3 has explained the principle of radio-frequency interface circuit:
The contactless integrated circuit chip is when work, and read write line is launched carrier signal always, and L1 (being aerial coil) is by the coupling carrier signal, at R3, R1 end produces a signal, and this signal is through Q10, Q11, Q12, Q13 carries out rectification, last working power as the contactless integrated circuit chip.When read write line sends order, at the R3 end signal input is arranged just, this signal (FILTER) is sent to the input of U3A.U3A is NAND gate circuit, after the signal L9 of FPGA output and FILTER and negate, imports a phase inverter again, generation CLR1 signal, and this signal is input to the FPGA part, uses as internal chip enable signal.Can also produce needed clock signal of contactless integrated circuit chip and data-signal from the FILTER signal simultaneously, these signals also are imported into FPGA and partly use for it is inner.This process is the process of noncontact chip acknowledge(ment) signal.When chip sends a signal to read write line, export a signal IN, send into Q14 after process U2B is anti-phase, the Q15 modulation generates modulation signal, sends into L1 at last, is coupled to read write line then.A complete radio-frequency interface circuit course of work that Here it is.
The signal that radio-frequency interface circuit is come aerial coil coupling carries out demodulation, sends to the FPGA part, perhaps modulates the signal that FPGA partly comes and sends to aerial coil.Aerial coil has been coupling, and it transmits radiofrequency signal between read write line and radio-frequency interface circuit, is a very important vection, and it is the media that contactless chip and read write line carry out data communication.Aerial coil is attached on the empty pcb board, links to each other with radio-frequency interface circuit by the two ends lead-in wire, and coil meets the ISO/IEC7810ID-1 standard.
Fig. 4 has explained the principle of reset circuit.Reset circuit plays reset response to the FPGA partial circuit, and Circuits System is carried out initialization, perhaps under some irrecoverable condition Circuits System is arranged to original state.Can select high level or low level to reset as required.Can produce reset signal by button and carry out hardware reset, also can reset signal be connected on certain data lines of parallel port of PC or on other output lines, produce reset signal by software and carry out the software reset by cable.Be very easily when non-contact card is tested fully like this, test process can be controlled by software by PC fully, and does not need manual control.When hardware reset, press KEYRST, U402 /the MR level is pulled to ground, decontrols again, just produces a high level pulse at the RESET of U402 end, then produces a low level pulse at/RESET end.The pulse that produces just is used for the reset signal of circuit.Select high or low level to reset according to circuit design, can by wire jumper with the RESET of U402 port or/ RESET that RESET is connected to J54 gets final product.
When the software reset, the input of/MR end produces by software, with U402 /the MR end is connected on certain data lines of PC parallel port or on other output lines, and altogether, send a low level pulse by PC to give/MR just can realize the software reset.The PC parallel port is sent earth pulse and is realized by programming, and in VC, realizes by the OUTP function, realizes by the OUTPORTB function in TURBO C2.0.Equally just produce a high level pulse, then produce a low level pulse at/RESET end at the RESET of U402 end.By wire jumper with the RESET of U402 port or/RESET is connected to the RESET of J54, selects high or low level to reset.
Claims (8)
1. a contactless integrated circuit card test circuit is characterized in that: comprise FPGA part (1), radio-frequency interface circuit (2), aerial coil (3), read write line (4), PC (5); Described PC (5) is input to FPGA part (1) with tested logical circuit through programming; When the testing software on the PC (5) sends instruction for read write line (4), read write line (4) is accepted the instruction of PC (5) and is sent modulation signal according to instruction, the signal that aerial coil (3) is come coupling is passed to radio-frequency interface circuit (2), radio-frequency interface circuit (2) is given FPGA part (1) signal through demodulation, FPGA part (1) acknowledge(ment) signal also can send specific response signal according to signal and give radio-frequency interface circuit (2), radio-frequency interface circuit (2) is modulated again, signal after the modulation is delivered on the aerial coil (3), send to PC (5) again after being come by read write line (4) coupling, the correctness of test just can be judged after capturing response signal by testing software, and makes corresponding output.
2. contactless integrated circuit card test circuit according to claim 1 is characterized in that: also comprise reset circuit (6); Described reset circuit (6) is connected between FPGA part (1) and the PC 5, so that FPGA part (1) is resetted.
3. contactless integrated circuit card test circuit according to claim 1 is characterized in that: described FPGA part (1), radio-frequency interface circuit (2) and aerial coil (3) are placed on the circuit board.
4. contactless integrated circuit card test circuit according to claim 3 is characterized in that: described FPGA part (1) is to be connected with PC (5) by DOWNLOAD CABLE; The end of DOWNLOADCABLE comprises 25 pins and links to each other with the parallel port of PC (5), and the other end comprises on the circuit board of 10 pins and FPGA part (1) and links to each other.
5. according to claim 1 or 2 or 3 or 4 described contactless integrated circuit card test circuits, it is characterized in that: described FPGA part (1) can be EEPROM, SRAM, EPROM is to use the internal storage of storer as the contactless integrated circuit card chip.
6. contactless integrated circuit card test circuit according to claim 1, it is characterized in that: described radio-frequency interface circuit (2) comprises clock generating circuit (21), rectification circuit (22), mu balanced circuit (23), modulation/demodulation circuit (24), electrify restoration circuit (25); The electromagnetic wave that described rectification circuit (22) is sensed aerial coil (3) and the induction current that produces offers described clock generating circuit (21), modulation/demodulation circuit (24), electrify restoration circuit (25), FPGA part (1) by mu balanced circuit (23) after rectification; Described clock generating circuit (21), modulation/demodulation circuit (24), electrify restoration circuit (25) are respectively with clock signal, and data-signal and reset signal are transferred to FPGA part (1).
7. contactless integrated circuit card test circuit according to claim 2, it is characterized in that: described reset circuit (6) can be to produce reset signal by button to carry out hardware reset, perhaps by cable reset signal is connected to produce reset signal by software on the parallel port of PC (5) and carry out the software reset.
8. contactless integrated circuit card method of testing is characterized in that: realize as follows:
By PC tested logical circuit is input to FPGA part (101) through programming;
Send instruction (102) by the testing software on the PC to read write line;
Send modulation signal (103) by read write line;
By aerial coil output modulation signal (104);
Give FPGA part (105) signal by radio-frequency interface circuit through demodulation;
Also can send specific response signal by FPGA part acknowledge(ment) signal and give radio-frequency interface circuit (106) according to signal;
Modulate by radio-frequency interface circuit, the signal after the modulation is delivered to (107) on the aerial coil;
The signal of coupling being come by read write line sends to PC (108) again;
Judge test result and make corresponding output (109) by the testing software of PC; Perhaps FPGA is partly resetted, again test by reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03129680 CN1567219A (en) | 2003-07-04 | 2003-07-04 | Test circuit for non-contact type integrated circuit and test method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03129680 CN1567219A (en) | 2003-07-04 | 2003-07-04 | Test circuit for non-contact type integrated circuit and test method thereof |
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| CN1567219A true CN1567219A (en) | 2005-01-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03129680 Pending CN1567219A (en) | 2003-07-04 | 2003-07-04 | Test circuit for non-contact type integrated circuit and test method thereof |
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| CN (1) | CN1567219A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100373164C (en) * | 2005-10-31 | 2008-03-05 | 李博航 | Testing system of IC card interface electric characteristics |
| CN101446988B (en) * | 2007-11-27 | 2010-10-27 | 上海摩波彼克半导体有限公司 | Device for automated testing universal asynchronous receiver-transmit based on software and method thereof |
| CN106908709A (en) * | 2015-12-23 | 2017-06-30 | 上海华虹集成电路有限责任公司 | The system and method for electromagnetic distu during detection intelligent card non-contact communication |
| CN109344934A (en) * | 2018-12-12 | 2019-02-15 | 威胜集团有限公司 | Pre-payment radio-frequency card and electric energy meter data exchange process detection device and detection method |
-
2003
- 2003-07-04 CN CN 03129680 patent/CN1567219A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100373164C (en) * | 2005-10-31 | 2008-03-05 | 李博航 | Testing system of IC card interface electric characteristics |
| CN101446988B (en) * | 2007-11-27 | 2010-10-27 | 上海摩波彼克半导体有限公司 | Device for automated testing universal asynchronous receiver-transmit based on software and method thereof |
| CN106908709A (en) * | 2015-12-23 | 2017-06-30 | 上海华虹集成电路有限责任公司 | The system and method for electromagnetic distu during detection intelligent card non-contact communication |
| CN109344934A (en) * | 2018-12-12 | 2019-02-15 | 威胜集团有限公司 | Pre-payment radio-frequency card and electric energy meter data exchange process detection device and detection method |
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