CN1561023A - Digital clock recovery method and its circuit - Google Patents
Digital clock recovery method and its circuit Download PDFInfo
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- CN1561023A CN1561023A CNA2004100061603A CN200410006160A CN1561023A CN 1561023 A CN1561023 A CN 1561023A CN A2004100061603 A CNA2004100061603 A CN A2004100061603A CN 200410006160 A CN200410006160 A CN 200410006160A CN 1561023 A CN1561023 A CN 1561023A
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Abstract
This invention relates to a digitalized clock recovery method and its circuit. First of all, the phase comparison is carried out between input signal and a recovery clock to get a phase error signal, then utilizing the digital signal process to filter the phase error signal for removing interference and noise in it to get a smooth phase error value to be synthesized in definite time by a sum-increment quantification method so as to get a regulation order regulating one of the set reference clock and the recovery clock to get a regulated clock phase-locked with a non-regulated clock signal and filtering the high frequency component to get a recovered clock. The circuit includes a phase discriminator, a digital filter, sum-increment phase quantiser and a phase locking circuit.
Description
Technical field the present invention relates to a kind of digitlization clock recovery method and circuit thereof, belongs to digital communication technology field.
Background technology is along with the increase of communication bandwidth and the development of SOC (system on a chip) (hereinafter to be referred as SoC) technology, and the data bandwidth that needs to handle on one chip sharply increases.The single channel bandwidth is from 622Mb/s to 10Gb/s, even to 40Gb/s.A chip can need to handle ten road to tens road such data.Monolithic is handled the level that bandwidth has reached Tb/s.When these serial datas of processing were carried out clock recovery, SoC was also carrying out complicated protocol processes, and these often need a large amount of digital circuits.These digital circuits can be brought very high power supply and substrate noise, influence the work of clock recovery circuitry.In order to reduce The noise, reduce requirement to technology, improve integrated level, the developed gradually and attention of digitizing solution.Timing recovery circuit is made up of comprehensive three parts of phase demodulation, filtering and clock generally as shown in Figure 1.Recover for low-speed clock, digitizing solution is widely used.All-digital receiver is used a lot.Utilize high-frequency clock or direct frequency synthesizing to carry out also comparative maturity of algorithm that low-speed clock recovers.In the comprehensive part of high-frequency clock, phase-locked loop and delay phase-locked loop (hereinafter to be referred as DLL) are two kinds of topmost clock generation circuits.The DLL interference free performance cuts with scissors, and does not have jitter accumulation problem and stability problem.But simple DLL is owing to can only carry out the limited adjustment of phase place, so the reference clock that it must an absolute synchronization.This condition has limited its application in clock recovery circuitry greatly.People have proposed the scheme of double loop DLL for this reason, and the DLL of major loop obtains reference clock evenly spaced a plurality of out of phase values in a complete cycle with the phase place discretization of reference clock, in fact is exactly the digitlization of reference clock phase place.Utilize digital interpolative from the DLL of loop, select suitable discrete phase comprehensively to become continuous clock.Because digital interpolative is easy to solve the border issue of phase place,, recovers double loop DLL so can carrying out quasi synchronous timing.
Existing clock recovery method has following limitation.Both in the filtering loop of phase difference signal, in the filtering loop of system noise, both required contradiction again for traditional simulated clock simulation clock restoration methods, phase-locked loop.When input data long even " 0 " or " 1 ", analogy method causes losing lock easily owing to can't guarantee the frequency plot stability.Adopt the DLL method, require reference clock strict Phase synchronization relation to be arranged with recovered clock, this does not have the system constraint of independent clock excessive for telecommunication and other.Method by double loop DLL need be carried out the clock interpolation, needs the high speed simulation process, and is complicated on the Method and circuits structure, and can only be operated in the accurate method of synchronization, requires reference clock and frequency input signal to differ very little, and the scope of application is received restriction.
Summation-increment (hereinafter to be referred as SDM) method utilizes repeatedly quantized value to force into exact value, is a kind of effective quantization method at narrow band signal.The digitlization that utilizes SDM to carry out clock recovery is subjected to the inspiration of following aspect.One, the frequency synthesis field of substantial connection is arranged with clock recovery, and digitizing solution has occupied critical role.Adopt the SDM theory during fractional frequency is comprehensive, by the adjustment of phase field reference clock one-period, be equivalent to the quantified precision of 2 π, filtering obtains the fractional frequency that phase error is lower than 2 π through PLL.Though because the noise that quantizes to introduce has limited its extensive use in frequency than big and the non-linear line spectrum that causes of SDM.But this theory combines frequency synthesis and over-sampling quantification theory.Two, the SDM theory is widely used in over-sampling amplitude quantizing, at the medium and low frequency signal quantization, utilizes repeatedly sampled value to force into amplitude exact value, linearity excellence.It also has inherent mechanism with comprehensive the combining of clock.The frequency of clock signal itself is generally very high, and particularly the frequency of high-frequency clock is often in the GHz magnitude.But the bandwidth of clock is but much lower than its frequency, generally from KHz to MHz.According to sampling thheorem, quantize and composite clock and it get bandwidth and is directly proportional.That is to say that " information " speed after the clock digitlization is not high.Therefore, theoretically, digitized clock signal is handled has feasibility.Clock recovery does not have comprehensive middle high spectrum purity and the high s/n ratio that requires of picture frequency rate, and SDM is a feasible digitizing solution.
Summary of the invention the objective of the invention is to propose a kind of digitlization clock recovery method and circuit thereof, avoids simulation process and analog circuit as far as possible, and with the influence of minimizing noise to clock recovery, thereby reduction is to the requirement of semiconductor integrated circuit fabrication process.
The digitlization clock recovery method that the present invention proposes comprises the steps:
(1) input signal in the digital communication and recovered clock are carried out obtaining phase error signal than mutually;
(2) utilize Digital Signal Processing that above-mentioned phase error signal is carried out filtering,, obtain the phase error after level and smooth with interference in the filtering phase error signal and noise;
(3) it is comprehensive above-mentioned phase error to be carried out timing by summation-increment quantization method, to obtain adjusting instruction;
(4) with above-mentioned adjustment instruction the reference clock of setting and any one in the recovered clock are adjusted, obtain adjusting clock, should adjust clock and another unadjusted clock signal carry out phase-locked, the high fdrequency component that produces during the filtering adjustment quantizes, clock is restored;
(5) repeating step (1)～(4).
Being undertaken regularly to phase value by summation-increment quantization method in the said method, comprehensive process comprises the steps:
(1) the adjustment instruction d (n) after phase error p (n) and the quantification is compared, obtain quantization error e (n);
(2) above-mentioned quantization error e (n) is carried out filtering, suppress wherein high fdrequency component, keep low frequency component, obtain filtered low frequency aberration s (n);
(3) filtered low frequency aberration s (n) compares with the threshold value of setting, the adjustment instruction d (n) after obtaining quantizing;
(4) repeating step (1)～(3) are finished regularly comprehensive.
The method of in the said method clock signal being adjusted is: adjust the corresponding integer of instruction d (n) for one, make the corresponding clock stationary phase constant of an integer, plus-minus corresponding phase value obtains adjusting phase place after adding up.
The digitlization clock recovery circuitry that the present invention proposes comprises:
(1) phase discriminator is used for the input signal of digital communication is carried out than mutually, to obtain phase error signal with recovered clock;
(2) digital filter is used for above-mentioned phase error signal is carried out filtering, with interference in the filtering phase error signal and noise, obtains the phase error after level and smooth;
(3) summation-incremental phase quantizer, it is comprehensive to be used for that above-mentioned phase error is carried out timing, to obtain adjusting instruction;
(4) phase lock circuitry is used for according to adjusting the instruction clock that is restored.
In the foregoing circuit, summation-incremental phase quantizer comprises:
(1) subtracter is used for phase error p (n) and the adjustment instruction d (n) after quantizing compares, and obtains quantization error e (n);
(2) digital filter is used for quantization error e (n) is carried out filtering, suppresses wherein high fdrequency component, keeps low frequency component, obtains filtered low frequency aberration s (n);
(3) comparator is used for filtered low frequency aberration s (n) is compared with the threshold value of setting, the adjustment instruction d (n) after obtaining quantizing.
Phase lock circuitry in the foregoing circuit comprises:
(1) decoder is used to select frequency dividing ratio, becomes required frequency dividing ratio with adjusting instruction transformation;
(2) frequency divider is used to adjust the clock division ratio, and clock phase is adjusted to and adjusts the corresponding phase place of instruction;
(3) phase-locked loop is used for the high fdrequency component that the filtering adjustment quantizes generation, and clock is restored.
Digitlization clock recovery method and circuit thereof that the present invention proposes adopt major loop that differing of data of input carried out filtering, from loop quantized result are carried out filtering, have solved the contradiction of high precision timing recovery with PLL noise.One of advantage of the present invention is that clock frequency keeps excellent performance, when input data long even " 0 " or " 1 ", though the phase feedback that does not have external data to introduce, but because PLL is locked in reference clock and additional quantification is adjusted, be equivalent to accurately synchronous with reference clock, as long as reference clock has high stability, clock recovered just can keep quite long Phase synchronization relation.Two of advantage is, because the simulation in entire method and the circuit thereof partly has only phase locked-loop unit, and this pll lock is reference clock, and the design Time Bandwidth can broad, so its good stability, noise resisting ability is strong.Three of advantage: can make full use of existing phase-locked loop module on the circuit design, add digital integrated filter circuit module provided by the invention, just can constitute new clock recovery circuitry.
Description of drawings
Fig. 1 is the clock recovery circuitry structural representation in the prior art.
Fig. 2 is summation-increment digitlization clock recovery method schematic diagram that the present invention proposes.
Fig. 3 is summation in this method-incremental phase quantization method schematic diagram.
Fig. 4 is a phase adjusting method schematic diagram in this method.
Fig. 5 is summation-increment digitlization clock recovery circuitry schematic diagram that the present invention proposes.
Fig. 6 is the summation-incremental phase sample circuit schematic diagram among the present invention.
Fig. 7 is the phase lock circuitry schematic diagram among the present invention.
Embodiment
The digitlization clock recovery method that the present invention proposes, its system block diagram carries out assisting into signal and recovered clock in the digital communication to obtain phase error signal than mutually as shown in Figure 2; Utilize Digital Signal Processing that phase error signal is carried out filtering,, obtain the phase error after level and smooth with interference in the filtering phase error signal and noise; It is comprehensive that phase error is carried out timing by summation-increment quantization method, to obtain adjusting instruction; With adjusting instruction the reference clock of setting and any one in the recovered clock are adjusted, obtain adjusting clock, should adjust clock and another unadjusted clock signal carry out phase-locked, the high fdrequency component that produces during the filtering adjustment quantizes, the clock that is restored, said process is a cyclic process.
In the said method phase value is carried out regularly comprehensive process by summation-increment quantization method, as shown in Figure 3, the adjustment instruction d (n) after phase error p (n) and the quantification is compared, obtain quantization error e (n); Quantization error e (n) is carried out filtering, suppress wherein high fdrequency component, keep low frequency component, obtain filtered low frequency aberration s (n); Filtered low frequency aberration s (n) compares with the threshold value of setting, the adjustment instruction d (n) after obtaining quantizing, and this process also is a repetitive cycling process.
The method of in the said method clock signal being adjusted, as shown in Figure 4, each adjusts the corresponding integer of instruction d (n), makes the corresponding clock stationary phase constant of an integer, and plus-minus corresponding phase value obtains adjusting phase place after adding up.
The digitlization clock recovery circuitry that the present invention proposes, circuit theory diagrams comprise as shown in Figure 5: phase discriminator is used for the input signal of digital communication is carried out than mutually, to obtain phase error signal with recovered clock; Digital filter is used for phase error signal is carried out filtering, with interference in the filtering phase error signal and noise, obtains the phase error after level and smooth; Summation-incremental phase quantizer, it is comprehensive to be used for that phase error is carried out timing, to obtain adjusting instruction; Phase lock circuitry is used for according to adjusting the instruction clock that is restored.
The circuit theory of the summation in the foregoing circuit-incremental phase quantizer comprises as shown in Figure 6:
(1) subtracter is used for phase error p (n) and the adjustment instruction d (n) after quantizing compares, and obtains quantization error e (n);
(2) digital filter is used for quantization error e (n) is carried out filtering, suppresses wherein high fdrequency component, keeps low frequency component, obtains filtered low frequency aberration s (n);
(3) comparator is used for filtered low frequency aberration s (n) is compared with the threshold value of setting, the adjustment instruction d (n) after obtaining quantizing.
The circuit theory of the phase lock circuitry in the foregoing circuit comprises as shown in Figure 7:
(1) decoder is used to select frequency dividing ratio, becomes required frequency dividing ratio with adjusting instruction transformation;
(2) frequency divider is used to adjust the clock division ratio, and clock phase is adjusted to and adjusts the corresponding phase place of instruction;
(3) phase-locked loop is used for the high fdrequency component that the filtering adjustment quantizes generation, and clock is restored.
Digitlization clock recovery method and circuit working principle thereof that the present invention proposes are as follows:
1, at first phase demodulation obtains digitized differing.Undertaken obtaining phase error signal by input signal and recovered clock than mutually.
2, obtain phase value after level and smooth through digital filter filtering shake then, interference and noise in can filtering differing by Digital Signal Processing.Generally the estimated value that obtains frequency difference respectively and differ by Filtering Processing is constantly revised and is carried out the tracking of phase value.
3, this phase value regularly comprehensively obtains adjusting instruction by SDM.This is the emphasis of this method.The digitlization of high-frequency clock can not obtain by dividing method or DDFS as low-speed clock.This method quantizes (with respect to " over-sampling " of bandwidth) by SDM, utilizes the clock that comprehensively is restored after the PLL filtering.Characteristics according to clock recovery, the frequency values of single stable was different when SDM quantized with frequency synthesis, in clock recovery, need to follow the tracks of the drift and the shake of external data, not only want simultaneously the picture frequency rate comprehensive in such tracking frequency, the more important thing is and to follow the tracks of phase place, just can recover clock with data sync.Its principle as shown in Figure 3.Wherein p (n) is phase value (the definite relative phase value of saying is promptly with the difference mutually of reference clock), and e (n) is a phase place and the error of the phase value that obtains of quantizing to add up, and s (n) is filtered error, and d (n) is the error quantization result.D (n) is exactly the phase place adjustment.Because it is an integer, be " 1 ", " 0 ", "+1 " or other integer among a small circle generally speaking, corresponding clock adjustment, " 1 " just corresponding clock stationary phase constant.If our adjustment is by deduction or add pulse, promptly changes frequency dividing ratio and carry out, " 1 " just corresponding clock cycle.Noise shaped technology is adopted in filtering in the quantization method, because the phase-locked filtering of back can filter away high frequency noise, the low frequency characteristic of e (n) give prominence in the filtering here, obtains adjusting d (n) as a result by quantification then.Simple filtered version commonly used has
Form, at this moment quantization system constitutes a second order SDM.
4, phase-locked filtering obtains output regularly.Adjustment after quantification instruction acts on the clock, to the phase place adjustment of dispersing.It can act on reference clock, perhaps can act on the phase-locked output clock.When adjusting phase place by frequency dividing ratio, one is adjusted step-length is exactly a clock cycle.Adjust clock and just obtain recovered clock after by phase-locked loop filtering.
The digitlization clock recovery circuitry operation principle that the present invention proposes is as follows:
1, phase discriminator adopts digital phase discriminator.Can obtain the phase discriminator of numeric results as Alexander phase discriminator etc.
2, digital filter.Utilize Digital Signal Processing, to obtaining phase estimation value by differing filtering.As digital filters such as single order, second order IIR low pass filters.
3, summation-incremental phase quantizer.Adopt summation-incremental phase to quantize quantization method, will estimate that phase value is converted to digitized discrete adjustment signal.Utilize Digital Signal Processing to carry out filtering, quantize by the comparative figures circuit.
4, phase lock circuitry.To adjust signal effect and reference clock or recovered clock, change phase value, by the phase-locked loop filtering clock that is restored.Phase-locked loop can utilize existing circuit unit, as phase locked-loop unit of phase-locked loop built-in among the FPGA, semiconductor manufacturer etc.
Claims (6)
1, a kind of digitlization clock recovery method is characterized in that this method comprises the steps:
(1) input signal in the digital communication and recovered clock are carried out obtaining phase error signal than mutually;
(2) utilize Digital Signal Processing that above-mentioned phase error signal is carried out filtering,, obtain the phase error after level and smooth with interference in the filtering phase error signal and noise;
(3) it is comprehensive above-mentioned phase error to be carried out timing by summation-increment quantization method, to obtain adjusting instruction;
(4) with above-mentioned adjustment instruction the reference clock of setting and any one in the recovered clock are adjusted, obtain adjusting clock, should adjust clock and another unadjusted clock signal carry out phase-locked, the high fdrequency component that produces during the filtering adjustment quantizes, clock is restored;
(5) repeating step (1)～(4).
2, the method for claim 1, comprehensive process comprises the steps: to it is characterized in that being undertaken regularly to phase value by summation-increment quantization method step (3)
(1) the adjustment instruction d (n) after phase error p (n) and the quantification is compared, obtain quantization error e (n);
(2) above-mentioned quantization error e (n) is carried out filtering, suppress wherein high fdrequency component, keep low frequency component, obtain filtered low frequency aberration s (n);
(3) filtered low frequency aberration s (n) compares with the threshold value of setting, the adjustment instruction d (n) after obtaining quantizing;
(4) repeating step (1)～(3) are finished regularly comprehensive.
3, the method for claim 1, it is characterized in that the method for in the step (4) clock signal being adjusted is: adjust the corresponding integer of instruction d (n) for one, make the corresponding clock stationary phase constant of an integer, plus-minus corresponding phase value obtains adjusting phase place after adding up.
4, a kind of digitlization clock recovery circuitry is characterized in that this method circuit comprises:
(1) phase discriminator is used for the input signal of digital communication is carried out than mutually, to obtain phase error signal with recovered clock;
(2) digital filter is used for above-mentioned phase error signal is carried out filtering, with interference in the filtering phase error signal and noise, obtains the phase error after level and smooth;
(3) summation-incremental phase quantizer, it is comprehensive to be used for that above-mentioned phase error is carried out timing, to obtain adjusting instruction;
(4) phase lock circuitry is used for according to adjusting the instruction clock that is restored.
5, method as claimed in claim 4 is characterized in that summation-incremental phase quantizer wherein comprises:
(1) subtracter is used for phase error p (n) and the adjustment instruction d (n) after quantizing compares, and obtains quantization error e (n);
(2) digital filter is used for quantization error e (n) is carried out filtering, suppresses wherein high fdrequency component, keeps low frequency component, obtains filtered low frequency aberration s (n);
(3) comparator is used for filtered low frequency aberration s (n) is compared with the threshold value of setting, the adjustment instruction d (n) after obtaining quantizing.
6, method as claimed in claim 4 is characterized in that phase lock circuitry wherein comprises:
(1) decoder is used to select frequency dividing ratio, becomes required frequency dividing ratio with adjusting instruction transformation;
(2) frequency divider is used to adjust the clock division ratio, and clock phase is adjusted to and adjusts the corresponding phase place of instruction;
(3) phase-locked loop is used for the high fdrequency component that the filtering adjustment quantizes generation, and clock is restored.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170398B (en) * | 2007-11-30 | 2010-04-14 | 北京卫星信息工程研究所 | High dynamic scope quick clock recovery system based on voltage crystal oscillator |
| CN102164031A (en) * | 2011-03-16 | 2011-08-24 | 华为技术有限公司 | Link clock recovery method and device |
| CN101674173B (en) * | 2009-10-26 | 2011-09-21 | 西安空间无线电技术研究所 | System and method for recovering high-speed 8PSK clocks parallelly |
| CN104363016A (en) * | 2014-10-17 | 2015-02-18 | 青岛歌尔声学科技有限公司 | Clock and data recovery circuit and clock and data recovery method |
| CN105262480A (en) * | 2015-10-22 | 2016-01-20 | 江苏绿扬电子仪器集团有限公司 | System for recovering clock signal from high-speed serial signals |
| CN106685631A (en) * | 2015-11-06 | 2017-05-17 | 创意电子股份有限公司 | Clock data recovery device |
| CN107528658A (en) * | 2017-08-02 | 2017-12-29 | 北京交通大学 | A kind of clock recovery method and device |
| CN115189862A (en) * | 2022-07-06 | 2022-10-14 | 中国电子科技集团公司第五十四研究所 | High-precision synchronous data synchronous clock recovery method |
| WO2024010630A1 (en) * | 2022-07-06 | 2024-01-11 | Intel Corporation | Dynamic spread-spectrum-clocking control |
-
2004
- 2004-03-04 CN CN 200410006160 patent/CN1278509C/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170398B (en) * | 2007-11-30 | 2010-04-14 | 北京卫星信息工程研究所 | High dynamic scope quick clock recovery system based on voltage crystal oscillator |
| CN101674173B (en) * | 2009-10-26 | 2011-09-21 | 西安空间无线电技术研究所 | System and method for recovering high-speed 8PSK clocks parallelly |
| CN102164031A (en) * | 2011-03-16 | 2011-08-24 | 华为技术有限公司 | Link clock recovery method and device |
| CN104363016A (en) * | 2014-10-17 | 2015-02-18 | 青岛歌尔声学科技有限公司 | Clock and data recovery circuit and clock and data recovery method |
| CN105262480A (en) * | 2015-10-22 | 2016-01-20 | 江苏绿扬电子仪器集团有限公司 | System for recovering clock signal from high-speed serial signals |
| CN106685631A (en) * | 2015-11-06 | 2017-05-17 | 创意电子股份有限公司 | Clock data recovery device |
| CN107528658A (en) * | 2017-08-02 | 2017-12-29 | 北京交通大学 | A kind of clock recovery method and device |
| CN115189862A (en) * | 2022-07-06 | 2022-10-14 | 中国电子科技集团公司第五十四研究所 | High-precision synchronous data synchronous clock recovery method |
| CN115189862B (en) * | 2022-07-06 | 2023-12-29 | 中国电子科技集团公司第五十四研究所 | High-precision synchronous data synchronous clock recovery method |
| WO2024010630A1 (en) * | 2022-07-06 | 2024-01-11 | Intel Corporation | Dynamic spread-spectrum-clocking control |
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