CN101170398B - High dynamic scope quick clock recovery system based on voltage crystal oscillator - Google Patents

Abstract

The invention discloses a large dynamic range fast clock recovery system based on VCXO. The clock recovery system is arranged before a carrier synchronization loop and comprises an ADC, a forming filter, a TED, a LF, a CSG and a VCXO; wherein, the TED calculates phase discrimination error signal P values in accordance with the output data of the forming filter, carries out the difference processing to the two continuous phase discrimination error signal P values, multiplies the multiplication factor with the difference processing result, sends the multiplication result to the LF until capturing the sampling frequency offset, and finally sends the phase discrimination error signal P values to the LF to realize the sampling frequency offset tracking. After the continuous correction of the loop, the VCXO oscillation frequency is at last locked with a transmitter sampling clock to realize the clock recovery. The invention has the advantages of wide dynamic range and rapid clock recovery.

Description

A kind of quick clock recovery system of the great dynamic range based on VCXO

Technical field

The present invention relates to a kind of clock recovery system of signal of communication, particularly adopt clock recovery system based on the modulus hybrid mode of VCXO (VCXO).

Background technology

In communication system, the clock mismatch (mismatch) of transmitting terminal and receiving terminal can cause receiver to separate timing intersymbol interference occurring (Inter-symbol Interference ISI), and seriously reduces systematic function, so must finish clock recovery at receiving terminal, to eliminate or alleviation ISI.The principle of clock recovery is, at first extracts timing information from received signal, utilizes this timing information regenerate sampling clock or sampled data then, thereby realizes clock recovery.Clock recovery mainly contains three kinds of modes: analog form, modulus hybrid mode (as shown in Figure 1), digital form (as shown in Figure 2).Analog form generally appears in the early stage receiver application, and it is to the environmental factor sensitivity, and implementation complexity is higher relatively.Current receiver adopts modulus hybrid mode or digital form to realize clock recovery mostly.What digital form recovered is sampled data, does not rebuild sampling clock, so be restricted in the application that needs this method under the occasion of sampling clock.

The modulus hybrid mode generally constitutes (see figure 1) by formed filter, phase detectors, loop filter, DDS chip parts such as (or VCO+DAC).Difference according to the phase demodulation algorithm in the phase detectors can be divided into two kinds with modulus mix clock recovery system: (1) phase demodulation algorithm depends on the clock recovery system of carrier synchronization; (2) the phase demodulation algorithm is independent of the clock recovery system of carrier synchronization.In (1) and (2), the phase demodulation process is generally carried out in carrier synchronization loop inside, this structure has increased the time delay of carrier synchronization loop, has reduced clock recovery system and has resisted the ability of big sampling frequency deviation, and made the most of computing in the demodulation all be in fast state.

Summary of the invention

The technical problem to be solved in the present invention: a kind of quick clock recovery system of the great dynamic range based on VCXO is provided, the wide dynamic range of this system, clock recovery is quick.

Technical solution of the present invention: based on the quick clock recovery system of the great dynamic range of VCXO, its characteristics are: described clock recovery system places before the carrier synchronization loop, and it comprises:

Analog-to-digital conversion ADC, base-band analog signal x (t) are admitted to formed filter after finishing analog-to-digital conversion through ADC;

Formed filter, the sampled data that ADC is come suppresses the intersymbol interference processing, recovers optimum sampling point;

Timing Error Detector TED is used for the signal of formed filter output is carried out frequency discrimination and phase discrimination processing, produces signal of timing error, and implementation procedure is: (1) calculates phase demodulation error signal P value according to the dateout of formed filter; (2) two continuous phase demodulation error signal P values are carried out difference processing, multiplication factor and difference processing result are multiplied each other, and multiplied result is sent into loop filter LF, up to catching sampling frequency deviation; (3) phase demodulation error signal P value is sent into loop filter LF, realize the sampling frequency deviation tracking;

Loop filter LF is used for the error signal of Timing Error Detector TED output is made low-pass filtering, to remove the high fdrequency component in the error signal;

Control-signals generator CSG, the error signal of exporting according to loop filter LF produces the control signal of revising VCXO;

VCXO VXCO produces the frequency of revising according to control signal, and the frequency of this frequency and transmitting terminal crystal oscillator is more approaching, and is used as the sample frequency of ADC;

Constantly revise through loop, the final and transmitting terminal sampling clock locking of the frequency of oscillation of VCXO realizes clock recovery.

The present invention compared with prior art has following advantage:

(1) TED of the present invention is when catching sampling frequency deviation, and every L symbol produces a signal of timing error, and introduces the accelerating ated test multiplication factor, improved the acquisition speed of sampling frequency deviation; Clock recovery process TED is divided into catches and follow the tracks of two steps and realize, further increased the capture range of sampling frequency deviation; Finally, make the clock recovery time less than 70ms, the capture range of sampling frequency deviation surpasses 200ppm.

(2) the present invention adopts the control method of control-signals generator CSG, and is simple;

(3) the present invention partly places clock recovery before the carrier synchronization loop, makes between clock recovery and the carrier synchronization separately, has reduced loop delay and operating frequency in the carrier synchronization loop;

(4) the present invention has avoided employing DDS chip, has reduced hardware complexity and hardware cost;

(5) according to test result, the present invention dynamically situation under can smoothly realize clock recovery greater than 4dB, carrier frequency shift less than 1.1MHz and height at S/N.

Description of drawings

Fig. 1 is existing modulus hybrid mode schematic diagram;

Fig. 2 is existing digital form schematic diagram;

Fig. 3 is a composition frame chart of the present invention;

Fig. 4 is a RRCF output signal schematic diagram of the present invention;

Fig. 5 is a TED principle schematic of the present invention;

Fig. 6 is a LF structured flowchart of the present invention.

Embodiment

As shown in Figure 3, the present invention is adapted at FPGA or the realization of DSP+FPGA platform.If adopt FPGA to realize, then among Fig. 3 except that ADC and two modules of VCXO, all the other modules all realize in FPGA; If adopt DSP+FPGA to realize that then the Timing Error Detector TED among Fig. 3 can realize in DSP, other module of removing ADC and VCXO realizes in FPGA.Formed filter employing root raised cosine filter (Root Raised Cosine Filter, RRCF); VCXO VXCO adopts general VCXO, and it comprises four pins: i.e. input control signal pin, power pins, grounding pin and clock signal pin.

As shown in Figure 3, the course of work of clock recovery loop is: (RootRaised Cosine Filter RRCF) carries out molding filtration to the sampled signal of ADC to (1) root raised cosine filter, recovers optimum sampling point; (2) (Timing Error Detector TED) carries out frequency discrimination and phase discrimination processing according to the output signal of RRCF to Timing Error Detector, produces signal of timing error; (3) loop filter (LoopFilter, LF) high fdrequency component in the filtering signal of timing error; (4) (Control Signal Generator CSG) produces the voltage control signal of VCXO to control-signals generator according to the LF output signal; (5) VCXO produces the sampling clock that recovers according to voltage control signal; (6) ADC carries out analog-to-digital conversion according to the sampling clock that recovers.Loop makes and output clock and the modulating clock locking of VCXO realizes clock recovery by constantly revising the frequency of oscillation of VCXO.

When realizing, formed filter adopts common RRCF, and its time domain impulse response is:

$h\left(t\right)=\frac{\sin [\mathrm{\πt}(1-\mathrm{\α})/T]+4\mathrm{\α}t\cos [\mathrm{\πt}(1+\mathrm{\α})/T]/T}{(\mathrm{\πt}/T){(1-4\mathrm{\αt}/T)}^2}$

Wherein α is a rolloff-factor, and T is a symbol period, and its output class is similar to unsharp signal shown in Figure 4 (supposition is input as the QPSK/BPSK signal), and this signal is admitted to TED, is used for recovering optimum sampling point.

TED of the present invention is embodied as: if there is skew in sample frequency, relation is as shown in Figure 5 arranged between the actual samples moment and the desirable sampling instant so, every

Symbol, sampling phase changes one-period, and the periodicity of then utilizing this sampling phase to change can estimate phase demodulation error signal P, and its expression formula is

$\frac{1}{2\mathrm{\&pi;}}\left(\underset{m=0}{\overset{\mathrm{LN}-1}{\mathrm{\&Sigma;}}}{\left|r_m\right|}^2\exp \left(\frac{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="H2007101785057E00013.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;m}}{N}\right)\right)$

Wherein L is for calculating the data symbol length that P intercepted, and N is an ADC over-sampling multiple, and m is the sequence number of sampling, r _mSample sequence for input.The estimation of sampling frequency deviation can be expressed as

$\mathrm{\&Delta;f}=\frac{p_i-p_{i-1}}{L}$

Wherein L is the symbol lengths of intercepting, and Δ f is a sampling frequency deviation.At acquisition phase, directly continuous P value is made difference processing, and introduce a multiplication factor that is used for accelerating ated test, be multiplication coefficient, general span is: 2-15, multiply each other this multiplication factor and difference result, deliver to LF then, finally realize catching fast of sampling frequency deviation; At tracking phase, directly the P value is delivered to LF, finally realize the tracking of sampling frequency deviation.

Be illustrated in figure 6 as loop filter LF, the error signal that TED produces is admitted to LF, to keep DC component and the first harmonic component in the error signal, removes high fdrequency component.

CSG module of the present invention is a pulse duty factor controller, it at first adds up to the value of duty cycle register according to the output of loop filter or successively decreases, again according to the value of this duty cycle register produce square wave control signal at VCXO (if promptly LF export on the occasion of, the value of the duty cycle register that then adds up, if LF exports negative value, the value of the duty cycle register of then successively decreasing), by the frequency of oscillation of continuous adjustment square wave control signal correction VCXO, the final realization regularly recovered.

Claims (5)

1. quick clock recovery system based on the great dynamic range of VCXO, it is characterized in that: described clock recovery system places before the carrier synchronization loop, and it comprises:

Analog-to-digital conversion ADC, base-band analog signal x (t) are admitted to formed filter after finishing analog-to-digital conversion through ADC;

Formed filter, the sampled data that ADC is come suppresses the intersymbol interference processing, recovers optimum sampling point;

Timing Error Detector TED, be used for the signal of formed filter output is carried out frequency discrimination and phase discrimination processing, produce signal of timing error, implementation procedure is: (1) calculates phase demodulation error signal P value according to the dateout of formed filter, and phase demodulation error signal P value computing formula is

Wherein L is for calculating the data symbol length that P intercepted, and N is an ADC over-sampling multiple, and m is the sequence number of sampling, r _mDateout for formed filter; (2) two continuous phase demodulation error signal P values are carried out difference processing, multiplication factor and difference processing result are multiplied each other, and multiplied result is sent into loop filter LF, up to catching sampling frequency deviation, sampling frequency deviation is expressed as

Wherein L is for calculating the data symbol length that P intercepted, and Δ f is a sampling frequency deviation; (3) phase demodulation error signal P value is sent into loop filter LF, realize the sampling frequency deviation tracking;

Loop filter LF is used for the error signal of Timing Error Detector TED output is made low-pass filtering, to remove the high fdrequency component in the error signal;

Control-signals generator CSG, the error signal of exporting according to loop filter LF produces the control signal of revising VCXO VCXO;

VCXO VCXO produces the frequency of revising according to control signal, and the frequency of this frequency and transmitting terminal crystal oscillator is more approaching, and is used as the sample frequency of ADC;

Constantly revise through loop, the final and transmitting terminal sampling clock locking of the frequency of oscillation of VCXO realizes clock recovery.

2. the quick clock recovery system of the great dynamic range based on VCXO according to claim 1 is characterized in that: described formed filter adopts root raised cosine filter RRCF, and its time domain impulse response is:

$h\left(t\right)=\frac{\sin [\mathrm{\&pi;t}(1-\mathrm{\&alpha;})/T]+4\mathrm{\&alpha;}t\cos [\mathrm{\&pi;t}(1+\mathrm{\&alpha;})/T]/T}{(\mathrm{\&pi;t}/T){(1-4\mathrm{\&alpha;t}/T)}^2}$

Wherein α is a rolloff-factor, and wherein T is a symbol period.

3. the quick clock recovery system of the great dynamic range based on VCXO according to claim 1, it is characterized in that: the span of described multiplication factor is 2-15.

4. the quick clock recovery system of the great dynamic range based on VCXO according to claim 1, it is characterized in that: described control-signals generator CSG is the pulse duty factor controller, it produces negative feedback control signal at VCXO according to the output of loop filter LF, if i.e. LF output on the occasion of, then increase the control voltage of VCXO, if LF exports negative value, then reduce the control voltage of VCXO, utilize the frequency of oscillation of this voltage control VCXO again, the final realization regularly recovered.

5. the quick clock recovery system of the great dynamic range based on VCXO according to claim 1, it is characterized in that: described VCXO VCXO adopts general VCXO, and it comprises four pins: i.e. input control signal pin, power pins, grounding pin and clock signal pin.

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