CN110708065B - Digital phase locking and transmitting device for time-frequency signal - Google Patents
Digital phase locking and transmitting device for time-frequency signal Download PDFInfo
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Abstract
The digital phase locking and transmitting device for time-frequency signal uses the output signal of voltage-controlled crystal oscillator as AD sampling clock, at the same time the output signal of voltage-controlled crystal oscillator is fed into FPGA for synchronous sampling data and frequency modulation phase modulation control, the AD sampling data result directly enters into FPGA, the interior of FPGA is passed through frequency modulation phase modulator to produce new modulation data information (DDS digital sine signal), the modulation data information is passed through digital phase discriminator to produce phase difference of initial clock and target clock, the phase difference data is passed through second-order loop filter to produce voltage-controlled voltage value, the voltage-controlled voltage is passed through DA module circuit to make feedback control for voltage-controlled crystal oscillator, finally the closed-loop satellite-borne time-frequency signal digital high-accuracy phase locking and low-loss transmitting device implemented by means of digital phase-locked loop is formed.
Description
Technical Field
The invention relates to a time-frequency signal digital phase locking and transmitting device, in particular to a satellite-borne time-frequency signal digital high-precision phase locking and low-loss transmitting device.
Background
The navigation satellite takes an atomic clock signal as a standard time reference signal, the nominal frequency of the atomic clock is usually 10M signal, the effective load of the navigation satellite needs 10.23M signal as the reference frequency, the time frequency generation and maintenance system transmits the 10M atomic clock signal into the 10.23M reference frequency signal needed by the effective load of the navigation satellite in a low loss mode, and the 10.23M signal index is ensured to be equivalent to the atomic clock signal.
In the existing time-frequency generation and maintenance system, two paths of 10M atomic clock signals respectively generate two paths of 230K signals through a DDS (direct digital frequency synthesizer), the two paths of 230K signals and the respective 10M signals are mixed to generate two paths of 10.23M signals, one path of 10.23M signals is selected by an electronic switch to serve as a reference signal of an analog phase-locked loop, the analog phase-locked loop locks a high voltage-stabilizing crystal-controlled oscillator to output a 10.23MHz reference signal, and when one path of 10M atomic clock fails, the electronic switch is used for realizing stable switching of the two paths of 10.23M signals. The final high temperature voltage controlled crystal oscillator locked by the analog phase-locked loop provides a reference frequency of 10.23M for the navigation satellite payload.
The existing time-frequency generation and maintenance system is limited by a scheme, so that stable switching in the existing time-frequency generation and maintenance system can only be realized through an electronic switch, a reference signal can be lost at the moment of switching the electronic switch by an analog phase-locked loop, the time-frequency transmission performance is limited by the speed of the electronic switch, and the phase maintenance of an output signal can not be realized; meanwhile, the navigation satellite time-frequency reference needs to be adjusted in frequency, phase and frequency drift rate, and the analog phase-locked loop scheme can only be realized by adjusting the reference signal. In addition, the original scheme adopts more analog circuits such as a mixer, a filter and the like, so that the flexibility of the scheme is reduced, and the performance index is greatly influenced by environmental factors.
Disclosure of Invention
The invention aims to solve the technical problems that: the utility model provides a time-frequency signal digital phase lock and transfer device, use the output signal of voltage-controlled crystal oscillator (VCXO) as the sampling clock of AD, external clock signal samples, the output signal of voltage-controlled crystal oscillator is given into FPGA simultaneously, be used for synchronous sampling data and frequency modulation phase modulation control, AD sampling data result directly gets into FPGA, generate new modulation data information (DDS digital sinusoidal signal) through the frequency modulation phase modulator in FPGA inside, the modulation data information produces the phase difference of initial clock and target clock through digital phase discriminator, the phase difference data produces voltage-controlled voltage value through second order loop filter, voltage-controlled voltage carries out feedback control to voltage-controlled crystal oscillator through DA module circuit, finally constitute the satellite-borne time-frequency signal digital high accuracy lock phase and low loss transfer device that realizes with digital phase-locked loop mode of closed loop.
The invention aims at realizing the following technical scheme:
a digital phase lock and transfer device of time-frequency signal, including AD module, frequency modulation phase modulator, phase discriminator, loop filter, DA module, voltage controlled crystal oscillator;
the AD module receives an external initial clock, and a second clock signal output by the voltage-controlled crystal oscillator is sent to the AD module and the frequency modulation phase modulator; the AD module samples the initial clock signal according to the second clock signal and then sends a sampling result to the frequency modulation phase modulator; the frequency modulation phase modulator generates modulation data information by using the sampling results of the second clock signal and the initial clock signal and sends the modulation data information to the phase discriminator; the phase discriminator obtains the phase difference between the initial clock and the second clock according to the modulation data information and sends the phase difference to a loop filter; the loop filter generates a voltage-controlled voltage value according to the phase difference; the voltage-controlled voltage value is used for carrying out feedback control on the voltage-controlled crystal oscillator after passing through the DA module; and the second clock signal output by the voltage-controlled crystal oscillator is used as a target clock output by the time-frequency signal digital phase-locking and transmitting device.
Preferably, the fm modulator includes a DDS and a mixer; the second clock signal is sent to the mixer after passing through the DDS; the sampling result is sent to the mixer; and the mixer generates modulation data information according to the sampling result and a second clock signal passing through the DDS.
Preferably, the fm accuracy of the fm modulator is better than 0.018uHz.
Preferably, the phase discriminator uses an all-phase fast fourier transform method to obtain the phase difference between the initial clock and the second clock.
Preferably, the loop filter adopts a second-order loop filter.
Preferably, the DA module includes at least two DA converters, at least two amplifying circuits, and at least one adding circuit; the number of the DA converters is equal to that of the amplifying circuits; the DA converter and the amplifying circuit form a branch circuit respectively, and the plurality of branch circuits are output to the adding circuit.
A digital phase lock and transfer device of time-frequency signal, including at least two AD modules, at least two frequency modulation phase modulators, at least two phase detectors, at least one selector, a loop filter, a DA module, a voltage controlled crystal oscillator;
the AD modules, the frequency modulation phase modulators and the phase detectors are equal in number; the AD module, the frequency modulation phase modulator and the phase discriminator form a passage respectively, and a plurality of passages are output to the selector;
each AD module receives an external initial clock, and a second clock signal output by the voltage-controlled crystal oscillator is sent to each AD module and each frequency modulation phase modulator; each AD module samples the initial clock signal according to the second clock signal and then sends a sampling result to a frequency modulation phase modulator of a corresponding channel; the frequency modulation phase modulator generates modulation data information by using the second clock signal and the sampling result and then sends the modulation data information to a phase discriminator of a corresponding channel; the phase discriminator obtains the phase difference between the initial clock and the second clock according to the modulation data information and then sends the phase difference to the selector, and the selector selects the phase difference output by a certain phase discriminator and sends the phase difference to the loop filter; the loop filter generates a voltage-controlled voltage value according to the phase difference selected by the selector; the voltage-controlled voltage value is used for carrying out feedback control on the voltage-controlled crystal oscillator after passing through the DA module; and the second clock signal output by the voltage-controlled crystal oscillator is used as a target clock output by the time-frequency signal digital phase-locking and transmitting device.
Preferably, the fm modulator includes a DDS and a mixer; the second clock signal is sent to the mixer after passing through the DDS; the sampling result is sent to the mixer; and the mixer generates modulation data information according to the sampling result and a second clock signal passing through the DDS.
Preferably, the phase discriminator uses an all-phase fast fourier transform method to obtain the phase difference between the initial clock and the second clock.
Preferably, the loop filter adopts a second-order loop filter.
A time-frequency signal digital phase locking and transmitting device comprises an AD module, an FPGA, a DA module and a voltage-controlled crystal oscillator;
the AD module is used for sampling an external initial clock according to a second clock signal output by the voltage-controlled crystal oscillator and then sending a sampling result to the FPGA; the FPGA sequentially carries out digital frequency modulation, phase modulation, digital phase discrimination and digital filtering on the sampling result output by the AD module by utilizing a second clock signal output by the voltage-controlled crystal oscillator to obtain a voltage-controlled voltage value; the voltage-controlled voltage value is subjected to feedback control on the voltage-controlled crystal oscillator after passing through the DA module;
and the second clock signal output by the voltage-controlled crystal oscillator is used as a target clock output by the time-frequency signal digital phase-locking and transmitting device.
Compared with the prior art, the invention has the following beneficial effects:
(1) The phase discrimination method of the invention has the advantages of flexibility and high precision: in the existing digital phase-locked loop system, the implementation forms of the phase discriminator are various, but the phase discriminator has various limitations: the phase discrimination problem between analog signals can not be directly processed, or the phase discrimination can only be carried out on input signals with the same frequency or fixed frequency, or the phase discrimination precision can not meet the transmission requirement of navigation satellite time-frequency signals. The invention applies the full-phase fast Fourier phase discrimination method in the phase-locked loop, and by reasonably selecting the sampling bandwidth of the A/D converter and optimizing the processing algorithm, not only can realize direct phase extraction of the different-frequency analog signals in a digital form, but also can ensure the higher phase discrimination precision of 5e-4 orders of magnitude, so that the system has stronger flexibility while ensuring high precision.
(2) The invention has the characteristics of digitalization, integration and expandability: the traditional satellite-borne time-frequency transmission equipment adopts an analog phase-locked loop, frequency modulation, phase modulation or drift adjustment of a frequency signal is mainly completed by adjusting a reference signal, and an additional processing circuit is needed, so that the functions and performances of the whole time-frequency transmission are realized by depending on more complex hardware, the complexity of the hardware is improved, the integration level of the system is low, the robustness of the system is influenced, the time-frequency transmission is realized by adopting a digital phase-locked loop, and the phase-discrimination and loop filtering of different-frequency signals and the processing of frequency modulation, phase modulation and drift adjustment of an output signal in a loop can be realized by only one processor, so that the circuit structure is greatly simplified, and the hardware cost is reduced. Meanwhile, the digital phase-locked loop overcomes the defects that the traditional analog phase-locked loop cannot be flexibly adjusted in loop parameters, has poor anti-interference performance, cannot keep VCXO phase and the like, and realizes the digitalization and integration of a complex analog circuit.
(3) The VCXO voltage-controlled signal is generated with high precision: the precision of the VCXO voltage-controlled signal is limited to be not high enough, the digital control of the VCXO voltage-controlled signal cannot reach the fine level of an analog loop, so that the time-frequency device is limited in time-frequency index transmission of a second stability level and cannot reach a higher level in digital application.
(4) The invention is realized in a digital phase-locked loop mode, avoids the physical switching of an electronic switch of a target clock signal, can realize the phase maintenance of an output target clock signal, and realizes real seamless switching; the frequency modulation, phase modulation and drift rate adjustment of the target clock signal can be completed in the digital phase-locked loop, so that an analog hardware circuit of the mixer is omitted under the same performance, and the hardware cost is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of a satellite-borne time-frequency signal digitized high-precision lock phase and low-loss transfer device;
FIG. 2 is a schematic diagram of the expansion of the satellite-borne time-frequency signal digitized high-precision lock phase and low-loss transmission device;
FIG. 3 is a schematic diagram of a FM phase modulator;
FIG. 4 is a schematic diagram of data preprocessing composition;
FIG. 5 is a loop filter discrete signal flow diagram;
fig. 6 is a schematic hardware structure diagram of the DA module.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The technical scheme of the invention is as follows: the output signal of the VCXO is used as a sampling clock of the AD, the input signal is sampled, the sampling clock and sampling data enter the FPGA together, new modulation data information is generated after the FPGA passes through a frequency modulation phase modulator, the frequency modulation phase modulator outputs data information, after phase discrimination of a phase discriminator, the data information is filtered by a second-order digital filter, and finally feedback control of the VCXO is formed through a DA module, so that the output signal of the VCXO is locked to the input signal, and low-loss transmission of time-frequency signals is realized.
The invention realizes low-loss transmission of a time-frequency signal based on a digital loop mode, and the realization process comprises the following steps:
and step 1, reading the sampling data of the AD by using an FPGA (field programmable gate array) control, and feeding the read data and a synchronous clock to a frequency modulation phase modulator.
And step 2, the frequency modulation phase modulator controls the DDS according to the corresponding external instruction, and the output of the DDS is mixed with the sampling signal to realize the frequency modulation phase modulation of the sampling signal.
And 3, preprocessing the data obtained by frequency modulation and phase modulation, wherein the preprocessing is usually not windowing, single windowing and double windowing. The invention adopts a form of adding double Hamming windows for pretreatment. The preprocessed data is subjected to FFT algorithm, peak value is selected, and phase information is calculated by combining with CORDIC algorithm.
And 4, the phase information of the phase discriminator is given to a second-order digital loop filter, parameters such as the bandwidth of the loop filter can be set according to engineering requirements, and meanwhile, real-time control can be adopted to realize variable bandwidth filtering.
And step 5, the filtered voltage data controls the DA to carry out rough adjustment, and the DA module is controlled to be converted into fine adjustment after loop capturing is realized, so that high-precision time-frequency transmission is realized.
Examples:
the development of the satellite-borne time-frequency signal digital high-precision phase locking and low-loss transmission device takes the time-frequency transmission from a 10M signal to a 10.23M signal as a background, is realized in the form of an all-digital phase-locked loop, in the realization, a sampling clock with an output signal of a VCXO (voltage controlled crystal oscillator) as an AD is used for sampling a 10M atomic clock signal, meanwhile, the signal of the VCXO is fed into an FPGA for synchronous sampling data and frequency modulation phase modulation control, the AD sampling data (230K signal) directly enter the FPGA, new modulation data information (DDS digital sinusoidal signal) is generated in the FPGA through a frequency modulation phase modulator, the modulation information generates the phase difference between the 10M (initial clock) and the 10.23M (target clock) through a digital phase discriminator, the phase difference data generates a voltage controlled voltage value through a second-order loop filter, and the voltage controlled voltage is fed back to the VCXO through a DA module circuit, so that the satellite-borne time-frequency signal digital high-precision phase locking and low-loss transmission device realized in a digital phase-locked loop mode is finally formed, as shown in figures 1 and 2.
In the FPGA, the FM phase modulator is realized by an internal DDS and a mixer, as shown in FIG. 3, the 10.23M signal of the VCXO samples the 10M signal to generate a 230K signal, and then generates a certain frequency point f through the DDS in the FPGA c (the frequency point should be as close as possible to the integral multiple of the FFT frequency resolution, and should have the same least common multiple period as the sampled signal and the sampled signal, and multiple frequency points can be selected), the functions of frequency modulation, phase modulation and frequency drift rate adjustment are realized by controlling the DDS, and then the sampled signal and f c Mixing is carried out, and the mixed signals are subjected to phase discrimination by a phase discriminator. In the existing time-frequency transmission device, the functions of frequency modulation, phase modulation and frequency drift rate adjustment are realized outside the loop, the common practice is that the functions are realized at the front end of the loop through adjusting the related parameters of reference (the prior art scheme is realized by a DDS and a hardware mixer), the method can be realized by corresponding hardware support, the hardware complexity of the whole scheme is improved, the frequency modulation, phase modulation and frequency drift rate adjustment in the scheme is realized by a frequency modulation phase modulator inside the loop, and the adjusted signals have no physical and chemical processes, no extra hardware cost is needed, and the reduction of the hardware cost is realizedThe complexity is improved, meanwhile, the frequency modulation precision of the DDS special chip is limited, and the digital DDS is adopted in the embodiment, so that the frequency modulation precision is better than 0.018uHz, the precision of frequency modulation and phase modulation is improved, and the application requirement of high precision is met.
The phase discrimination between signals in the scheme has very high flexibility, is not limited to the phase discrimination between 10M signals and 10.23M signals, and can realize the phase discrimination between two paths of different-frequency signals as long as the frequency points of the two paths of signals are not in integer multiple relation, so that the phase discrimination and the time frequency transmission application can be covered relatively widely. The 10M signal and the 10.23M signal are illustrated in the figures. The phase discriminator is realized by APFFT (full-phase fast Fourier transform), and the principle of discrete Fourier transform proves that a signal is formed by a real part and an imaginary part after being subjected to discrete Fourier transform, and the phase value of the signal can be obtained by the real part and the imaginary part of a Fourier transform peak value. In the APFFT, the original signal is first preprocessed (usually without windowing, single windowing or double windowing), and the signal after preprocessing is then subjected to fast fourier transform, so that the phase invariance of the signal can be ensured, and the signal after FFT transformation is subjected to peak value phase selection, so that a high-precision phase discrimination result can be obtained, as shown in fig. 4.
In the phase-locked system of the prior art, whether it is a digital or analog system, the input of the phase discriminator must be two signals with the same nominal frequency, and if the output signal and the input signal of the loop are different in frequency, the output signal must be processed, and the nominal frequency is converted to be consistent with the input signal to ensure the locking of the loop, which reduces the flexibility of the application of the system and increases the complexity and cost of hardware. In the digital high-precision phase locking and low-loss transmission device of the satellite-borne time-frequency signal, the digital high-precision phase locking and low-loss transmission device is realized by a digital phase locking system, the adopted phase discriminator adopts a full-phase Fourier transform method, and phase information is periodically extracted by utilizing the relation of frequency points between input signals and output signals, so that stable high-precision phase output can be ensured, the defects of the traditional phase locking system are avoided, the flexibility of system application is improved, the phase discrimination between different frequency signals can be realized by modifying an algorithm, and the phase discrimination can be carried out on signals with any different frequencies within a certain bandwidth.
The satellite-borne time-frequency signal digital high-precision phase locking and low-loss transmission device is realized by means of a digital phase locking system and has the functions of frequency modulation, phase modulation and frequency drift rate adjustment, so that a loop filter adopts a second-order digital loop filter (with the capability of tracking a frequency ramp signal) to form a third-order digital loop, as shown in fig. 5. The continuous function of the second-order loop filter is shown in the formula (1), and the discrete expression is shown in the formula (2).
Where K is the product of the phase detector gain and the VCXO frequency control sensitivity (gain coefficient), T is the data rate (sampling period other than AD) input to the filter, ω n =bl/0.7845, BL is loop bandwidth, a 3 ＝1.1，b 3 ＝2.4。
In a satellite-borne time-frequency signal digital high-precision phase locking and low-loss transmission device, the voltage control precision of the VCXO is a key link, and the short-term stability of frequency transmission can be directly affected by the voltage control precision. The highest bit 16bit of the existing aerospace-level single-chip D/A converter cannot meet the additional short-term frequency stability transmission requirement of the 10-13 magnitude of the satellite-borne time-frequency signal due to insufficient voltage resolution, and the control of the VCXO is realized by adopting a mode that two 16bit D/A converters are connected in parallel, and meanwhile, the large-range coverage and high-precision adjustment of voltage-controlled voltage are met, as shown in figure 6. And in the capturing stage, the coarse tuning is utilized to realize quick locking, and after the loop is locked, the loop is converted from the coarse tuning to the fine tuning, so that the high-precision low-loss transmission of the time-frequency signal is realized.
What is not described in detail in the present specification is a well known technology to those skilled in the art.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
Claims (4)
1. The digital phase locking and transmitting device for the time-frequency signals is characterized by comprising at least two AD modules, at least two frequency modulation phase modulators, at least two phase detectors, at least one selector, a loop filter, a DA module and a voltage-controlled crystal oscillator;
the AD modules, the frequency modulation phase modulators and the phase detectors are equal in number; the AD module, the frequency modulation phase modulator and the phase discriminator form a passage respectively, and a plurality of passages are output to the selector;
each AD module receives an external initial clock, and a second clock signal output by the voltage-controlled crystal oscillator is sent to each AD module and each frequency modulation phase modulator; each AD module samples the initial clock signal according to the second clock signal and then sends a sampling result to a frequency modulation phase modulator of a corresponding channel; the frequency modulation phase modulator generates modulation data information by using the second clock signal and the sampling result and then sends the modulation data information to a phase discriminator of a corresponding channel; the phase discriminator obtains the phase difference between the initial clock and the second clock according to the modulation data information and then sends the phase difference to the selector, and the selector selects the phase difference output by a certain phase discriminator and sends the phase difference to the loop filter; the loop filter generates a voltage-controlled voltage value according to the phase difference selected by the selector; the voltage-controlled voltage value is used for carrying out feedback control on the voltage-controlled crystal oscillator after passing through the DA module; and the second clock signal output by the voltage-controlled crystal oscillator is used as a target clock output by the time-frequency signal digital phase-locking and transmitting device.
2. A time-frequency signal digital phase locking and transmitting device according to claim 1, characterized in that the fm modulator comprises a DDS and a mixer; the second clock signal is sent to the mixer after passing through the DDS; the sampling result is sent to the mixer; and the mixer generates modulation data information according to the sampling result and a second clock signal passing through the DDS.
3. A device for digitally phase locking and transferring a time-frequency signal according to claim 1 or 2, wherein the phase detector uses an all-phase fast fourier transform method to obtain the phase difference between the initial clock and the second clock.
4. A time-frequency signal digital phase locking and transferring device according to claim 1 or 2, wherein the loop filter is a second order loop filter.
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| CN101908858B (en) * | 2010-07-26 | 2013-03-20 | 四川九洲电器集团有限责任公司 | Method for processing broadband receiving digital front end |
| CN108809305B (en) * | 2018-05-02 | 2021-10-08 | 深圳市鼎阳科技股份有限公司 | Method for reducing stray of radio frequency signal source and radio frequency signal source |
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