CN1471232A - Clock restoring circuit phase discriminator design method and structure for realising same - Google Patents

Abstract

The designing method in the invention is the improvement of Mueller-Muller phase discriminator algorithm. Based on characteristic of impulse response function, error function is designed, and coincidence relation between decision sequence and coefficient vector is created so as to calculate out the error function. The invention lowers power consumption of system and difficulty of ADC design, and overcomes too large jitter of recovering clock in prior art. Thus, clock-recovering circuit with high performances can be obtained.

Description

The method for designing of clock recovery circuitry phase discriminator and implementation structure thereof

Technical field

The present invention relates to a kind of clock recovery circuitry that adopts digital signal processing method to realize, relate in particular to the method for designing and the implementation structure thereof of the phase discriminator in the clock recovery circuitry.

Background technology

Clock recovery circuitry is a requisite module in the communication system, and it is mainly used in the clock that produces and receive data sync, has maximum signal to noise ratio to guarantee the sampling instant data, thereby makes the bit error rate minimum that receives data.And phase discriminator is exactly the key modules in the clock recovery circuitry, and it is used to extract the phase error information between sampling clock and the reception data, and adjusts phase place to reach final Phase synchronization through loop filtering and phase adjusting module.

Clock recovery circuitry mainly contains the scheme of two kinds of realizations: based on the Analog Circuit Design scheme of phase-locked loop structures and the digital scheme that adopts digital signal processing method to realize.Adopt its operating rate of clock recovery circuitry of modeling scheme can be very high, the ratio that the precision of recovered clock also can be done be higher, but circuit antimierophonic indifferent, technology is portable also poor; In order to improve the phase demodulation speed of phase acquisition process, needing increases extra supplementary module simultaneously, has increased the difficulty of design; And the clock recovery circuitry that adopts digital scheme to realize, because processing is digital signal, so the circuit noise resisting ability is very strong, process transplanting is also fine.Just adopted digital scheme to realize clock recovery circuitry here.

The clock recovery circuitry that adopts digital scheme to realize, phase discriminator design wherein also has different algorithms, as the phase demodulation algorithm of M times of over-sampling and the phase demodulation algorithm of single times of speed sampling.M times of over-sampling phase demodulation algorithm requires ADC (analog to digital converter) to be operated on the 2M message transmission rate doubly, therefore when message transmission rate when higher, the design difficulty of high-speed ADC will improve greatly, system power dissipation is increase greatly also.And the phase demodulation algorithm that adopts single times of speed to sample, ADC only need be operated on the reportedly defeated speed of haploidy number, not only reduced the design difficulty of ADC, also saved system power dissipation, wherein most popular is exactly Mueller-M ü ller algorithm, the sampled value h of channel impulse response function when it utilizes the Phase synchronization of clock and data (T)=characteristic of h (T) is as the phase demodulation standard, but this algorithm obtains optimum phase by long statistical average, the shake of recovered clock is bigger, so the performance of clock recovery circuitry will be subjected to certain influence.Reference: [1] John G.Proakis; " Digital Communications " (Third Edition) [2] Mark Berman; " System Analysis and Design of High-Speed Local Area Network Transceiver "; Ph.D Dissertation; UCLA; 1995[3] Kurt H.Mueller; Markus M ü ller; " Timing Recovery in Digital Synchronous Data Receivers "; IEEE Trans.Commun.Vol.COM-24; pp516-530, May, 1975

Summary of the invention

The object of the invention is to design a kind of system power dissipation and ADC design difficulty of reducing, and avoids the phase discriminator algorithm and the implementation structure thereof of the clock recovery circuitry of recovered clock shake.

The transmission rate of data is 125MHz under the 100Base-T situation, in order to reduce system power dissipation and ADC design difficulty, simultaneously in order to overcome the big problem of recovered clock shake that exists in the Mueller-M ü ller phase demodulation algorithm, the present invention has adopted a kind of improved Mueller-M ü ller phase demodulation algorithm, to obtain a high performance clock recovery circuitry.

For an actual channel, its impulse response function has the symmetry characteristic of single order usually, that is to say when receiving data and sampling clock when synchronous, and impulse response function is at-T sampled value h constantly _-1With T sampled value h constantly ₁Equate, i.e. h _-1=h (T)=h ₁=h (T), so we can set transposition and the corresponding u vector multiplied result of phase error function for the h vector of impulse function h (t) the sampled value sequence composition of consideration finite term intersymbol interference influence:

F (τ)=h ^TU=h _-1-h ₁(1) when Phase synchronization, f (τ)=0; When phase place is leading, f (τ)＜0; When phase lag, f (τ)＞0.Because the impulse response function of each sampled value and channel is relevant, and sampled value and balanced court verdict have relation one to one, so we can be to sampled value data and equalizer judgement output sequence a _K-iAnalyze, handle, extract the phase error function that we need.

If vector X _kSet for p+1 sampled value:

K _k＝[x _k-px _k-p+1…x _k] ^T???????????????????(2)

Establishing error function in addition is the linear combination of sampled value set:

E _k＝g _k ^TX _k???????????????????????????????(3)

Consider the influence of finite term intersymbol interference, then vector g _k ^TIn each element g _iBe and judgement sequence of vectors D _k=[a _K-p-mA _K+n] ^TThe function that is associated:

g _i＝g(a _-m-p?a _-m-p+1……a _n)i＝[k-p，k-p+1，……，k]??????(4)

Concerning a stable receiving system, correct judgement sequence should be consistent with the data sequence that sends.So the sampled value sequence of choosing can be expressed as by the judgement sequence D _k=[a _K-p-mA _K+n] ^TThe A that forms _kThe h vector multiplied result that transpose of a matrix and impulse response function sampled value sequence are formed: $X_k=X(\mathrm{\τ}+\mathrm{kT})={[\underset{i=-N}{\overset{M}{\mathrm{\Σ}}}{a}_{k-p-i}h(\mathrm{\τ}+\mathrm{iT})\·\·\·\·\·\·\underset{i=-N}{\overset{M}{\mathrm{\Σ}}}{a}_{k-i}h(\mathrm{\τ}+\mathrm{iT})]}^T={A_k}^{T}h....\left(5\right)$

Because E _kBe scalar, so

E _k ^T＝E _k＝(g _k ^TA _k ^Th) ^T＝h ^TA _kg _k＝h ^Tu＝h _-1-h ₁??????????(7)

If get feedforward exponent number n=1, the hangover exponent number

Sampled value sequence p+1=3, then h ^T=[h _-1h ₀h ₁h ₂h ₃] f (τ)=h _-1-h ₁, u=A then _k* g _k=[1 0-1 0 0]

According to aforementioned analysis, for the clock recovery circuitry of different application, the employing that the present invention proposes improves Mueller-M ü ller phase demodulation algorithm computation phase error E _kGeneral step following (seeing shown in the figure (1)):

(1) determines feedforward exponent number n, hangover exponent number m and the sampled value sequence X of channel impulse function h (t) _kMiddle element number p+1.By actual conditions as can be known, channel is very weak for the perception that does not send data (particularly random data) as yet, and it is less by the response behind the channel therefore not send data, and the feedforward effect is more weak; And for the data that sent, its effect generally needs could eliminate by several all after dates, so smearing is more intense.Based on this: generally getting n is 1～2, and getting m is 2～5, and considers that from the angle of area and power consumption in order to reduce operand, the number of element generally gets 2～5 in the sampled value sequence, gets 1～4 corresponding to p.

(2) after n and m determine, be met h ^TU=h _-1-h ₁Vector h ^T=[h _-nh _-n+1H _M-1h _m] and u; Simultaneously to each sampled value sequence X _k, the judgement sequence D that obtains being associated _k=[a _K-p-mA _K+n] ^TThe number of middle element is n+m+p+1.If the possible value number of each element has L, then co-exist in L ^(n+m+p+1)Plant possible transfer sequence D _k

(3) determine each judgement sequence D _kCorresponding coefficient vector g _k, with each D _kSequence is formed corresponding A _kMatrix adopts the method for exhaustion to choose g _kVector makes it satisfy A _k* g _k=u, this can realize by a matlab or c program.In addition, in order to simplify the hardware spending in computing and the saving side circuit, can set g _kIn element g _tValue be limited, as+1 ,-1,0 ,+2 ,-2 etc.

(4) according to (3) formula, can calculate phase error E _k

In concrete hardware is realized, to each sampled value sequence X _k=[x _K-px _K-p+1X _k] ^T, can determine the equilibrium judgement sequence D that is associated _k=[a _K-p-mA _K+n] ^T, pass through D then _k=[a _K-p-mA _K+n] ^TCan from coefficients R OM, choose suitable g _kVector.With g _kVector and X _kSequence multiplies each other, and just can obtain phase error E _k

The phase discriminator structure of the improvement Mueller-M ü ller phase demodulation algorithm that employing the present invention proposes as shown in Figure 5.It is by equalizer 31, n+m+p level shift register 32, L position p+1 level parallel shift register 33, g _kCoefficient memory (ROM) 34, multiplier 35,36 and adder 37 connect and compose through circuit; Sampled value is latched by the parallel shift register 33 of L position p+1 level, and the figure place of each sampled value is by the figure place L decision of ADC; Sampled value is adjudicated the balanced court verdict of output through equalizer 31, and is latched by the shift register 32 of n+m+p level; The judgement sequence of output is to g _kCoefficients R OM 34 carries out addressing decode, obtains corresponding g _kCoefficient; The p+1 that parallel shift register 33 a latchs sampled value and g _kAfter corresponding element multiplies each other through p+1 multiplication unit in the multiplier 35,36 in the coefficient, obtain phase error E by adder 37 additions output _k

Description of drawings

Fig. 1 is the phase demodulation error E _kThe computational process block diagram.

Fig. 2 is the fundamental block diagram of clock recovery circuitry.

Fig. 3 is the reception sampled data diagram that has intersymbol interference.

The impulse response function of Fig. 4 perfect low pass filtering channel.

Fig. 5 adopts the phase discriminator structure of improving Mueller-M ü ller phase demodulation algorithm.

Fig. 6 is the circuit structure of 100Base-Tx transceiver clock recovery circuitry phase discriminator.

Fig. 7 is the simulation result of clock recovery circuitry.

Number in the figure: 21 is phase discriminator, and 22 is loop filter, and 23 is clock generator, and 24 is analog to digital converter, and 25 is balanced decision device; 30 is clock recovery circuitry, and 31 is equalizer, and 32 is m+n+p level shift register, and 33 is L position p+1 level parallel shift register, and 34 is g _kCoefficient memory, 35,36 is multiplier, 37 is adder; 41,42,43 is latch, and 44-49 is a d type flip flop, and 50 is equalizer, and 51,52,53 is multiplier, and 54 is g _kCoefficient memory, 55 is adder.

Embodiment

Phase discriminator with the clock recovery circuitry in the 100Base-Tx ethernet transceiver is an example below, specifically describes the present invention.

The fundamental block diagram of clock recovery circuitry 30 as shown in Figure 2, it mainly is made up of phase discriminator 21, loop filter 22 and 16 phase clock generators, 23 3 parts.The sampled value X of 21 couples of ADC 24 of phase discriminator _kWith balanced court verdict D _k25 analyze, extract the phase error information that receives between data and the sampling clock, after the noise signal by loop filter 22 filtering high frequencies, produce the phase digit selection line of 4bit, from the clock generator 23 of 16 same frequencys, choose the sampling clock output of appropriate phase.

The schematic diagram that the baseband waveform that receives in the actual samples system is influenced by intersymbol interference is seen shown in Figure 3.In data communication, the data-signal that receives inevitably is subjected to the influence of interchannel noise, amplitude fading and intersymbol interference, and amplitude fading can compensate by the automatic gain control module, and The noise also can be eliminated by filter segment.For a sampling system, if do not consider noise, t=τ+KT sampled value constantly is exactly that this baseband waveform that receives constantly receives the summation of baseband waveform in the influence in this moment constantly with other.So its sampled value can be expressed as: $x(\mathrm{\τ}+\mathrm{KT})=\underset{i}{\mathrm{\Σ}}{a}_{k-i}h(\mathrm{\τ}+\mathrm{iT})=\underset{i}{\mathrm{\Σ}}{a}_{k-i}{h}_i$ -T/2≤τ≤T/2 is a wherein _K-iThe data code flow (MLT-3 is-1,0,1) of expression transmission, h (t) is the impulse response function of channel, h _iThen be that the channel impulse response function is in t=τ+KT sampled value constantly.T is the cycle of transfer of data, and τ represents the side-play amount of actual samples phase place and optional sampling phase point.

Fig. 4 is the impulse response function of perfect low pass filtering channel, characteristic by impulse response function, As time goes on we know, the very fast decay of h (t), so the influence of intersymbol interference and the time interval between data are inversely proportional to, two signal transmission times are big more at interval, and the influence of intersymbol interference is just more little.Can think that the channel impulse response function is a time-limited function, generally only get the intersymbol interference value in several cycles and be similar to that its general mathematic(al) representation can be expressed as:

$X_k=X(\mathrm{\τ}+\mathrm{kT})=\underset{i=-n}{\overset{m}{\mathrm{\Σ}}}{a}_{k-i}h(\mathrm{\τ}+\mathrm{iT})$ So the intersymbol interference of each sampling instant can be regarded n rank feedforward effect as, be that n does not send data and by channel this received influence and the m rank smearing that baseband waveform causes constantly, promptly m has sent data and by channel this has been received the summation of the influence that baseband waveform causes constantly.Get n=1, during m=3: $X_k=\underset{i=-1}{\overset{3}{\mathrm{\Σ}}}{a}_{k-i}h(\mathrm{\τ}+\mathrm{iT})$ $=a_{k+1}h(\mathrm{\τ}-T)+a_{k}h\left(\mathrm{\τ}\right)+a_{k-1}h(\mathrm{\τ}+T)+a_{k-2}h(\mathrm{\τ}+2T)+a_{k-3}h(\mathrm{\τ}+3T)$

The circuit structure of the phase discriminator of clock recovery circuitry as shown in Figure 6 in the 100Base-Tx ethernet transceiver.It has adopted the sampled value sequence (p=2) on 3 rank, and the feedforward effect of channel is decided to be 1 rank (n=1), and smearing is decided to be 3 rank (m=3), so need the criterion sequence on 7 rank.X _K+1Be the sampled value of current time, the sampled value X in it first three cycle _k, X _K-1And X _K-2Latch by three 6 bit latch 41,42,43; a _K+1Be the decision value of the current time of equalizer 50 output, the balanced court verdict a in preceding 6 cycles _k, a _K-1, a _K-2, a _K-3, a _K-4And a _K-5Then latch by 6 d type flip flop 44-49 respectively.Therefore for each group sampled data X _kSequence [x _kx _K-1x _K-2] can determine the judgement sequence D of one group of correspondence _k=[a _K+1a _ka _K-1a _K-2a _K-3a _K-4a _K-5], sequence D _kChoose corresponding G among the coefficients R OM 54 that from chip, solidifies _kCoefficient vector [g _kg _K-1g _K-2], finish G by three multipliers 51,52,53 _kVector and X _kDiffering of sequence, and obtain concrete phase error function E by adder 54 _k=h _-1-h ₁

Table 1 is the equilibrium judgement sequence D that is applicable to 100Base-Tx _kCoefficient g with correspondence _kSince the data of MLT-3 coding transmission be-1,0 and+1, then all possible transfer sequence has 3 ^M+n+p+1=3 ⁷=2187 kinds of compound modes, in addition in the MLT-3 coding rule: (1 ,+1) and (+1 ,-1) is to forbid sequence; So what wherein meet coding rule has 2 ⁷+ 2 ⁶+ 2 ⁵+ 2 ⁴+ 2 ³+ 2 ²+ 2 ¹The combination of+1=255 kind promptly has 255 kinds of possible transfer sequences.Calculate and hardware complexity g in order to simplify _kThe element span is defined as (1,0,1), has 44 kinds of D _kCombined sequence can satisfy A _k* g _k=u.

Fig. 7 is the simulation result that the 100Base-Tx receiving system has adopted improved Mueller-M ü ller phase demodulation algorithm.First subgraph is the recovered clock phase place of clock recovery circuitry, can see that clock phase is more stable, only shakes in adjacent phase; Second phase demodulation error E that subgraph is each cycle _kCalculated value, it 0 the value near randomized jitter; The 3rd subgraph then is the result of equalizer soft-decision, initial time, because every coefficient of equalizer is also being adjusted, sampling clock phase does not yet have and data sync, so the soft-decision result has very big discreteness, receive data and exist error code, through after the adjustment of certain clock cycle, equalizer begins steady operation, and also fundamental sum data sync of recovered clock phase place this moment, therefore the result of soft-decision is just relatively clearer and more definite, eye pattern open and desirable-1,0 ,+fluctuate near 1 three values.The 4th subgraph is the variance of noise, it has determined the signal to noise ratio of soft decision signal, index according to system definition is less than 0.075, and simulation result is 0.018, and the clock recovery circuitry that as seen adopts improved Mueller-Muller phase demodulation algorithm to realize has good performance.Table 1

?Number	????D k	????g k	?Number	????D k	????g k
						????1	??1??1?0??0?-1?0??1	????0?0?1	????23	????0?0??1?0?-1??0??1	????-1?0??0
????2	??1??0?0??0?-1?0??1	????0?0?1	????24	????0?0??1?0?-1?-1?-1	????-1?0??0
						????3	??0??1?0??0?-1?0??1	????0?0?1	????25	????0?0??0?0??1??1??0	?????0?1?-1
????4	??0??0?0??0?-1?0??1	????0?0?1	????26	???-1?0??0?0??1??1??0	?????0?1?-1
						????5	?-1??0?0??0??1?0?-1	????0?0-1	????27	????1?0??0?0?-1?-1??0	?????0-1??1
????6	??0??0?0??0??1?0?-1	????0?0-1	????28	????0?0??0?0?-1?-1??0	?????0-1?-1
						????7	?-1?-1?0??0??1?0?-1	????0?0-1	????29	????1?0?-1?0??0??0??1	?????1?0??1
????8	??0?-1?0??0??1?0?-1	????0?0-1	????30	????0?0??0?0??1??0??0	?????1?0?-1
						????9	??0??0?0?-1??0?1??0	????0?1?0	????31	???-1-1?-1-1??0?-1?-1	?????1?0?-1
????10	??1??0?0?-1??0?1??0	????0?1?0	????32	????0?0??0?0?-1??0??0	????-1?0??1
						????11	??0??0?0?-1??0?1??1	????0?1?0	????33	????1?1??1?1??0??1??1	????-1?0??1
????12	??1??0?0?-1??0?1??1	????0?1?0	????34	???-1?0??1?0??0??0?-1	????-1?0?-1

????13	????0?0?0?1?0-1-1	????0-1?0	????35	????0?0?0-1-1?0?0	???-1?1?0
						????14	????0?0?0?1?0-1?0	????0-1?0	????36	????0?0?0-1-1?0?1	???-1?1?0
????15	???-1?0?0?1?0-1?0	????0-1?0	????37	????0?0?0?1?1?0?0	????1-1?0
						????16	????1?0?0?1?0-1-1	????0-1?0	????38	????0?0?0?1?1?0-1	????1-1?0
????17	????0?0-1?0?1?0-1	????1?0?0	????39	????0?0?0?0?1?1?1	????1?1-1
						????18	????0?0-1?0?1?0?0	????1?0?0	????40	???-1-1?0?1?0-1?0	????1-1?1
????19	????0?0-1?0?1?1?0	????1?0?0	????41	????0-1-1?0?0?0?1	????1-1?1
						????20	????0?0-1?0?1?1?1	????1?0?0	????42	????0?1?1?0?0?0-1	???-1?1-1
????21	????0?0?1?0-1-1?0	???-1?0?0	????43	????1?1?0-1?0?1?0	???-1?1-1
						????22	????0?0?1?0-1?0?0	???-1?0?0	????44	????0?0?0?0-1-1-1	???-1-1?1

Claims (3)

1, a kind of method for designing that is applicable to the phase discriminator of clock circuit, its specific implementation step is as follows:

(1) establish phase error function f (t) and be the transposition of the h vector of impulse response function h (t) the sampled value sequence composition of consideration finite term intersymbol interference influence and the product of corresponding u vector:

F (τ)=h ^TU=h _-1-h ₁(1) wherein: h ^T=[h _-nh _-n+1H _M-1h _m],

If vector X _kSet for p+1 sampled value:

X _k＝[x _k-px _k-p+1…x _k] ^T?????????????(2)

Here n is the feedforward exponent number of h (t), and n is taken as 1～2, and m is the hangover exponent number of h (t), and m is taken as 2～5, and p+1 is sample sequence X _kIn element number, getting p is 1～4;

(2) determine each judgement sequence D _k=[a _K-p-mA _K+n] ^TCorresponding coefficient vector g _k, specifically be with each D _kThe A that sequence is formed _kMatrix, the sampling method of exhaustion is chosen g _kVector makes it satisfy A _k* g _k=u, here

(3) according to following formula

E _k＝g _k ^TX _k??????????????????????????????(3)

Can calculate and obtain phase error function f (t), i.e. E _k

2. the phase discriminator structure according to the described method design of claim 1 is characterized in that: by equalizer (31), n+m+p level shift register (32), L position p+1 level parallel shift register (33), g _kCoefficient memory (ROM) (34), multiplier (35), (36) and adder (37) connect and compose through circuit: sampled value is latched by the parallel shift register (33) of L position p+1 level, and the figure place of each sampled value is by the figure place L decision of ADC; Sampled value is adjudicated the balanced court verdict of output through equalizer (31), and is latched by the shift register (32) of n+m+p level; The judgement sequence of output is to g _kCoefficients R OM (34) carries out addressing decode, obtains corresponding g _kCoefficient; P+1 sampled value that parallel shift register (33) latchs and g _kElement corresponding in the coefficient obtains phase error E through after p+1 multiplication unit multiplies each other in multiplier (35), (36) by adder (37) addition output _k

3. phase discriminator structure according to claim 2 is characterized in that getting n=1, m=3, p=2, X _K+1Be the sampled value of current time, the sampled value X in it first three cycle _k, X _K-1And X _K-2Latch by three 6 bit latch (41), (42), (43); a _K+1Be the decision value of the current time of equalizer (50) output, the balanced court verdict a in preceding 6 cycles _k, a _K-1, a _K-2, a _K-3, a _K-4And a _K-5Then latch by 6 d type flip flops (44)-(49) respectively: for each group sampled data X _kSequence [x _kx _K-1x _K-2] determine the judgement sequence D of one group of correspondence _k=[a _K+1a _ka _K-1a _K-2a _K-3a _K-4a _K-5], sequence D _kThe coefficients R OM that solidifies from chip chooses corresponding G in (54) _kCoefficient vector [g _kg _K-1g _K-2], finish G by three multipliers (51), (52), (53) _kVector and X _kDiffering of sequence, and obtain concrete phase error function E by adder (54) _k=h _-1-h ₁

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