CN114448595A - Clock data recovery circuit and serial receiver - Google Patents
Clock data recovery circuit and serial receiver Download PDFInfo
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- CN114448595A CN114448595A CN202210097853.6A CN202210097853A CN114448595A CN 114448595 A CN114448595 A CN 114448595A CN 202210097853 A CN202210097853 A CN 202210097853A CN 114448595 A CN114448595 A CN 114448595A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Abstract
The invention discloses a clock data recovery circuit and a serial receiver. The clock data recovery circuit comprises a first clock data recovery unit, a second clock data recovery unit and a phase interpolator. The first clock data recovery unit is used for acquiring high-order quantized data of the ADC and processing the high-order quantized data to obtain a first sampling moment phase to be adjusted; the second clock data recovery unit is used for acquiring data of the ADC after digital calibration and equalization processing, and processing the data to obtain a second sampling time phase to be adjusted; the phase interpolator is used for updating the sampling clock phase of the ADC according to the fluctuation amplitude of the first sampling time phase and the second sampling time phase, and the iteration result of the first clock data recovery unit and the iteration result of the second clock data recovery unit are fused, so that the loop delay of the clock data recovery circuit is reduced, and the stability of the clock data recovery circuit is ensured.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a clock data recovery circuit and a serial receiver.
Background
The serial communication chip is an essential module in high-speed wired data communication, and high-speed data transmission is realized under the condition of small port number. At present, an ultra-high-speed wired serial receiver with a rate of 56Gb/s or higher generally adopts a PAM4(4Pulse Amplitude Modulation, fourth generation Pulse Amplitude Modulation) Modulation method, and an ADC (Analog-to-Digital Converter) is introduced to quantize an Analog front-end signal. The Equalization mode adopts a mode of combining Feed-forward Equalization (FFE) and Decision-feedback Equalization (DFE), and realizes better high-order Equalization through a Feed-forward Equalization technology, so that the error rate of the whole system under the PAM4 modulation mode is improved.
At present, in the ultra-high speed serial receiver structure based on ADC, a Clock Data Recovery Circuit (CDR) generally extracts a phase error between a receiving Clock and collected Data based on a phase detector, and a Data input of the phase detector is derived from output Data of an equalizer. In this case, the CDR loop needs to go through the following stages: firstly, on the analog circuit level, a sampling clock under the control of a CDR loop samples an analog front end balanced signal, and an ADC quantizes data; then, the quantized data of the ADC is transmitted to a digital domain, the error between ADC channels and error between ADC channels of the quantized data are calibrated by a time-interleaved ADC calibration algorithm, the calibrated data are transmitted to an FFE/DFE equalizer, a filtering unit in the equalizer transmits generated data to a phase discriminator, and the output result of the phase discriminator is subjected to extraction, integration and other operations to obtain a phase of a sampling moment to be adjusted and is fed back to a phase interpolator to update the phase of the sampling clock of the ADC. Through the operation, one phase iteration of the CDR loop is realized.
In a traditional receiver based on a Slicer (two-way amplitude limiter), digital domain FFE/DFE equalization is not available, the Slicer receiving signals after analog DFE equalization directly transmits decision results of the signals to a CDR phase discriminator, a whole CDR loop is realized based on an analog circuit, the loop speed is high, and the operation can be finished only by 20-30 unit code element time (UI).
However, in the current ADC-based receiver, the CDR loop delay is long, and in the ultra-high-speed serial interface, because there is a large difference between the digital domain operating frequency and the analog domain operating frequency, an extraction scheme is introduced in the digital domain equalization coefficient iteration and the CDR phase iteration, which causes the problems of slow CDR loop response speed, difficulty in tracking high-frequency offset, and the like in the ADC-based receiver, and reduces the stability of the receiver system. Meanwhile, in the practical application of the serial interface, under the conditions that data is to be transmitted and no data is to be transmitted, the working state of the serial interface is controlled, and the invalid output transmission caused by the slow CDR establishing speed can reduce the power consumption of the system.
Disclosure of Invention
The invention aims to overcome the defects of long CDR loop delay and low response speed in the conventional ADC-based serial receiver, and provides a clock data recovery circuit and a serial receiver.
The invention solves the technical problems through the following technical scheme:
a first aspect of the present invention provides a clock data recovery circuit, including a first clock data recovery unit, a second clock data recovery unit, and a phase interpolator:
the first clock data recovery unit is used for acquiring high-order quantized data of the ADC and processing the high-order quantized data to obtain a first sampling moment phase to be adjusted; the first phase discriminator in the first clock data recovery unit takes the characteristic that a sampling value h (0) of an impulse response function of a channel is h (1) when the phases of a clock and data are synchronous as a phase discrimination standard;
the second clock data recovery unit is used for acquiring data of the ADC after digital calibration and equalization processing, and processing the data to obtain a second sampling time phase to be adjusted; the second phase detector in the second clock data recovery unit takes the characteristic that a sampling value h (-1) ═ h (1) of an impulse response function of a channel when the phases of the clock and the data are synchronous as a phase detection standard;
the phase interpolator is used for updating the sampling clock phase of the ADC according to the fluctuation amplitude of the first sampling moment phase and the fluctuation amplitude of the second sampling moment phase.
Optionally, the phase interpolator is specifically configured to update the sampling clock phase of the ADC according to the first sampling time phase when the fluctuation amplitude of the first sampling time phase is greater than a preset threshold or the fluctuation amplitude of the second sampling time phase is greater than the preset threshold; and
and updating the sampling clock phase of the ADC according to the second sampling moment phase under the condition that the fluctuation amplitude of the first sampling moment phase and the fluctuation amplitude of the second sampling moment phase are both smaller than or equal to a preset threshold value.
Optionally, the first clock data recovery unit further includes a first voter, a first phase integrator, and a first encoder, where the first phase discriminator, the first voter, the first phase integrator, the first encoder, and the phase interpolator are sequentially connected;
the second clock data recovery unit further comprises a second voter, a second phase integrator, a frequency integrator and a second encoder, wherein the output end of the second phase detector is connected with the input end of the second voter, the output end of the second voter is respectively connected with the input end of the second phase integrator and the input end of the frequency integrator, the output end of the second phase integrator and the output end of the frequency integrator are both connected with the input end of the second encoder, and the output end of the second encoder is connected with the phase interpolator.
Optionally, the first encoder is configured to remove dc information in the phase of the first sampling instant.
Optionally, the first encoder is configured to convert the format of the phase at the first sampling instant into a format recognizable by the phase interpolator.
Optionally, the second encoder is configured to convert the format of the phase at the second sampling instant into a format recognizable by the phase interpolator.
Optionally, the first clock data recovery unit is specifically configured to collect high-order quantized data of the ADC after serial-to-parallel conversion.
Optionally, the number of bits of the high-bit quantization data is at least two bits.
The second aspect of the present invention also provides a serial receiver comprising a clock data recovery circuit as described in the first aspect.
Optionally, the serial receiver further includes an analog front end, a serial-to-parallel conversion unit, a digital calibration unit, and an equalizer connected in sequence; the analog front end includes an ADC.
The positive progress effects of the invention are as follows: the first phase discriminator and the second phase discriminator adopt different phase discrimination standards so as to realize that the convergence phase of the first clock recovery unit is closer to the convergence phase of the second clock recovery unit. The first clock data recovery unit can quickly lock the phase of the first sampling moment by collecting high-order quantized data of the ADC, so that the loop delay of the clock data recovery circuit can be reduced. The second clock data recovery unit acquires complete data of the ADC after digital calibration and equalization processing, and locks the phase of the second sampling moment through long-time statistical average, so that the stability of the clock data recovery circuit can be ensured.
The phase interpolator updates the sampling clock phase of the ADC according to the fluctuation amplitude of the first sampling moment phase and the second sampling moment phase, integrates the iteration result of the first clock data recovery unit and the iteration result of the second clock data recovery unit, reduces the loop delay of the clock data recovery circuit, ensures the stability of the clock data recovery circuit, and further improves the stability of the serial receiver and the working energy efficiency of the transceiving system.
Drawings
Fig. 1 is a block diagram of a clock data recovery circuit according to embodiment 1 of the present invention.
Fig. 2 is an impulse response curve chart provided in embodiment 1 of the present invention.
Fig. 3 is another impulse response graph provided in embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of an internal structure of a clock data recovery circuit according to embodiment 1 of the present invention.
Fig. 5 is a schematic structural diagram of a serial receiver according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
The present embodiment provides a clock data recovery circuit, as shown in fig. 1, including a first clock data recovery unit, a second clock data recovery unit, and a phase interpolator.
The first clock data recovery unit is used for collecting high-order quantized data of the ADC and processing the high-order quantized data to obtain a first sampling time phase to be adjusted. The first phase discriminator in the first clock data recovery unit takes the characteristic that a sampling value h (0) of an impulse response function of a channel is h (1) when the phases of the clock and the data are synchronous as a phase discrimination standard.
In a specific implementation, the first clock data recovery unit may directly collect the high-order quantized data output by the ADC, or may collect the high-order quantized data after serial-to-parallel conversion by the ADC. The serial-to-parallel conversion is to convert 1 channel of serial data into N channels of parallel data, where N can be determined according to the operating frequency of the analog front end and the operating frequency of the digital domain in the serial receiver. In a specific example, the operating frequency of the analog front end in the serial receiver is 1GH, the operating frequency of the digital domain is 250MHz, and N is 1GHz/250MHz is 4.
In an alternative embodiment, the high-order quantized data has at least two bits. In a specific example, the ADC is a time-interleaved ADC, and the output data of the ADC is collected after the quantization with 2 bits high is completed, considering that the structure of the sub-ADC is generally a successive approximation ADC.
And the second clock data recovery unit is used for acquiring data of the ADC after digital calibration and equalization processing, and processing the data to obtain a second sampling time phase to be adjusted. The second phase detector in the second clock data recovery unit uses a Mueller-muller algorithm, and uses the characteristic that a sampling value h (-1) ═ h (1) of an impulse response function of a channel when the phases of the clock and the data are synchronous as a phase detection standard. In some examples, the second phase detector may also be referred to as a MM decision based phase detector.
In a specific implementation, the digital calibration process is specifically to calibrate errors in the ADC channels and between the ADC channels, and may be implemented by using a digital calibration unit. The equalization process described above may be implemented using an equalizer, such as an FFE/DFE equalizer.
The phase interpolator is used for updating the sampling clock phase of the ADC according to the fluctuation amplitude of the first sampling moment phase and the fluctuation amplitude of the second sampling moment phase.
In this embodiment, the first phase discriminator and the second phase discriminator use different phase discrimination standards, that is, different criteria, and it is expected that the converged phase of the first phase discriminator and the converged phase of the second phase discriminator are as close as possible when the first phase discriminator processes unbalanced data, thereby reducing the time for high-precision convergence of the second clock data recovery unit. In the impulse response curve 301 as shown in fig. 2, the phase position corresponding to the main term 302 converges. Due to the influence of the equalization process, the phase converged by the second phase detector is more advanced than the phase converged by the first phase detector without the equalization process. Therefore, in order to achieve that the convergence phase of the first clock recovery unit is closer to the convergence phase of the second clock recovery unit, in the impulse response curve shown in fig. 3, the sampling value h (0) is h (1) as the criterion of the first phase detector, that is, the converged phase satisfies that the size of the main term 305 is the same as the size of the latter term 306; and in the impulse response curve 301 as shown in fig. 2, the sampled value h (-1) ═ h (1) is used as the criterion of the second phase detector, that is, the size of the previous term 303 and the size of the next term 304 which converge to a phase satisfying the main term 302 are the same.
The clock data recovery circuit provided by the embodiment includes two clock data recovery units, wherein the first clock data recovery unit can quickly lock the phase of the first sampling time by collecting high-order quantized data of the ADC, so that the loop delay of the clock data recovery circuit can be reduced, and therefore the first clock data recovery unit can also be referred to as a fast clock data recovery unit. The second clock data recovery unit acquires the complete data of the ADC after digital calibration and equalization processing, and locks the phase of the second sampling moment through long-time statistical average, so that the stability of the clock data recovery circuit can be ensured, and the second clock data recovery unit can also be called as a slow clock data recovery unit.
In this embodiment, the phase interpolator updates the sampling clock phase of the ADC according to the fluctuation amplitudes of the first sampling time phase and the second sampling time phase, and integrates the iteration result of the fast clock data recovery unit and the iteration result of the slow clock data recovery unit, thereby reducing the loop delay of the clock data recovery circuit and ensuring the stability of the clock data recovery circuit.
In an optional embodiment, as shown in fig. 4, the first clock data recovery unit further includes a first voter 202, a first phase integrator 203, a first encoder 204, and a first phase detector 201, the first voter 202, the first phase integrator 203, the first encoder 204, and the phase interpolator 107 are sequentially connected to implement extraction, integration, and feedback of the clock data phase error. In specific implementation, the first voter is configured to vote on an output result of the first phase detector, the first phase integrator is configured to perform phase integration on the output result of the first voter, and the first encoder is configured to encode the output result of the first phase integrator and output a phase at a first sampling time to be adjusted.
The second clock data recovery unit further includes a second voter 206, a second phase integrator 208, a frequency integrator 207, and a second encoder 209, an output end of the second phase detector 205 is connected with an input end of the second voter 206, an output end of the second voter 206 is connected with an input end of the second phase integrator 208 and an input end of the frequency integrator 207, an output end of the second phase integrator 208 and an output end of the frequency integrator 207 are both connected with an input end of the second encoder 209, and an output end of the second encoder 209 is connected with the phase interpolator 107, so as to achieve extraction, integration, and feedback of the clock data phase error and the frequency error. In specific implementation, the second voter is configured to vote on an output result of the second phase detector, the first phase integrator is configured to perform phase integration on an output result of the second voter, the frequency integrator is configured to perform frequency integration on an output result of the second voter, and the second encoder is configured to encode an output result of the second phase integrator and an output result of the frequency integrator and output a phase at the second sampling time to be adjusted.
In specific implementation, a gating unit may be arranged at the front end of the phase interpolator, or a gating unit may be added inside the phase interpolator based on the existing phase interpolator, as shown in fig. 4. The gating unit is used for gating the first sampling moment phase or the second sampling moment phase according to the fluctuation amplitude of the first sampling moment phase and the fluctuation amplitude of the second sampling moment phase. The phase interpolator updates the sampling clock phase of the ADC according to the gated first sampling time phase or the gated second sampling time phase.
It should be noted that, since the first phase detector only collects the high-order quantized data of the ADC, the data throughput of the first voter is much less than that of the second voter.
In an optional embodiment, the phase interpolator is specifically configured to update the sampling clock phase of the ADC according to the first sampling time phase when the fluctuation amplitude of the first sampling time phase is greater than a preset threshold or the fluctuation amplitude of the second sampling time phase is greater than the preset threshold; and under the condition that the fluctuation amplitude of the first sampling moment phase and the fluctuation amplitude of the second sampling moment phase are both smaller than or equal to a preset threshold value, updating the sampling clock phase of the ADC according to the second sampling moment phase.
In a specific implementation, the preset threshold may be set according to actual conditions, for example, may be set to 10 LSBs (Least Significant bits), and if the fluctuation amplitude of the first sampling time phase, that is, the adjacent coding result of the first encoder is greater than 10, or the fluctuation amplitude of the second sampling time phase, that is, the adjacent coding result of the second encoder is greater than 10, the sampling clock phase of the ADC is updated according to the coding result of the first encoder, that is, the first sampling time phase. And if the adjacent coding result of the first coder and the adjacent coding result of the second coder are both less than or equal to 10, updating the sampling clock phase of the ADC according to the coding result of the second coder, namely the second sampling time phase.
In an optional embodiment, the first encoder is configured to remove dc information in the phase of the first sampling time, and only retain ac information that can follow high-frequency offset, so as to avoid an influence of the dc offset in the ADC on an integration result of phase error information of clock data.
In an alternative embodiment, the first encoder is configured to convert the format of the phase at the first sampling instant into a format recognizable by the phase interpolator. The second encoder is configured to convert the format of the phase at the second sampling instant into a format recognizable by the phase interpolator. In the present embodiment, format conversion is performed by the first encoder and the second encoder.
In an alternative embodiment, the phase interpolator is configured to convert the format of the first sample time phase output by the first encoder to a recognizable format and to convert the format of the second sample time phase output by the second encoder to a recognizable format. In the present embodiment, format conversion is performed by a phase interpolator.
In another embodiment, a format conversion unit may be provided between the phase interpolator and the first encoder or the second encoder to convert the format of the first sampling-time phase and the second sampling-time phase into a format recognizable by the phase interpolator.
Example 2
This embodiment provides a serial receiver including the clock data recovery circuit described in embodiment 1.
In an alternative embodiment, the serial receiver further includes an analog front end, a serial-to-parallel conversion unit, a digital calibration unit, and an equalizer, which are connected in sequence. The analog front end includes an ADC for receiving and sampling analog signals transmitted by a serial transmitter over a channel.
In a specific implementation, as shown in fig. 5, the analog front end further includes a CTLE (Continuous Time Linear Equalization) 101, the ADC may be a Time-interleaved ADC102, which is formed by Time-interleaving 32 sub-channel ADCs of 1GS/s, output data enters a digital domain after being subjected to serial-parallel conversion by 1:4 of a serial-parallel conversion unit, and is completed at a rate of 250MHz in a digital calibration unit 103, and a second clock data recovery unit 105 collects data and errors output by an equalizer 104, and completes processing on the data at the rate of 250 MHz. Wherein the equalizer 104 may be an FFE/DFE equalizer.
In order to realize lower loop delay, the first clock data recovery unit 106 directly collects the high-bit quantized data of the ADC, performs parallel processing and fast voting operation on the quantized data of each sub-channel ADC at a rate of 1 GHz. The phase interpolator 107 receives the first sampling timing phase output from the first clock data recovery unit, the second sampling timing phase output from the second clock data recovery unit, and the clock signal generated from the phase locked loop 108, and updates the sampling clock phase of the time-interleaved ADC at a rate of 1 GHz.
In this embodiment, the phase interpolator updates the sampling clock phase of the ADC according to the fluctuation range of the first sampling time phase and the second sampling time phase, and integrates the iteration result of the first clock data recovery unit and the iteration result of the second clock data recovery unit, thereby reducing the loop delay of the clock data recovery circuit, ensuring the stability of the clock data recovery circuit, and further improving the stability of the serial receiver and the work energy efficiency of the transceiver system.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes or modifications to these embodiments may be made by those skilled in the art without departing from the principle and spirit of this invention, and these changes and modifications are within the scope of this invention.
Claims (10)
1. A clock data recovery circuit comprising a first clock data recovery unit, a second clock data recovery unit, and a phase interpolator:
the first clock data recovery unit is used for acquiring high-order quantized data of the ADC and processing the high-order quantized data to obtain a first sampling moment phase to be adjusted; the first phase discriminator in the first clock data recovery unit takes the characteristic that a sampling value h (0) of an impulse response function of a channel is h (1) when the phases of a clock and data are synchronous as a phase discrimination standard;
the second clock data recovery unit is used for acquiring data of the ADC after digital calibration and equalization processing, and processing the data to obtain a second sampling time phase to be adjusted; the second phase detector in the second clock data recovery unit takes the characteristic that a sampling value h (-1) ═ h (1) of an impulse response function of a channel when the phases of the clock and the data are synchronous as a phase detection standard;
the phase interpolator is used for updating the sampling clock phase of the ADC according to the fluctuation amplitude of the first sampling moment phase and the fluctuation amplitude of the second sampling moment phase.
2. The clock data recovery circuit of claim 1, wherein the phase interpolator is specifically configured to update the sampling clock phase of the ADC according to the first sampling-time phase if the fluctuation amplitude of the first sampling-time phase is greater than a preset threshold or the fluctuation amplitude of the second sampling-time phase is greater than the preset threshold; and
and under the condition that the fluctuation amplitude of the first sampling moment phase and the fluctuation amplitude of the second sampling moment phase are both smaller than or equal to a preset threshold value, updating the sampling clock phase of the ADC according to the second sampling moment phase.
3. The clock data recovery circuit of claim 1, wherein the first clock data recovery unit further comprises a first voter, a first phase integrator, a first encoder, the first phase discriminator, the first voter, the first phase integrator, the first encoder, the phase interpolator being connected in sequence;
the second clock data recovery unit further comprises a second voter, a second phase integrator, a frequency integrator and a second encoder, wherein the output end of the second phase detector is connected with the input end of the second voter, the output end of the second voter is respectively connected with the input end of the second phase integrator and the input end of the frequency integrator, the output end of the second phase integrator and the output end of the frequency integrator are both connected with the input end of the second encoder, and the output end of the second encoder is connected with the phase interpolator.
4. The clock-data recovery circuit of claim 3, wherein the first encoder is to remove DC information in the phase of the first sampling instant.
5. The clock data recovery circuit of claim 3, wherein the first encoder is to convert a format of the first sample time phase to a format recognizable by the phase interpolator.
6. The clock data recovery circuit of claim 3, wherein the second encoder is to convert a format of the second sample time phase to a format recognizable by the phase interpolator.
7. The clock data recovery circuit according to any of claims 1-6, wherein the first clock data recovery unit is specifically configured to collect the high-order quantized data of the ADC after serial-to-parallel conversion.
8. The clock data recovery circuit of claim 7, wherein the high bit quantized data has a number of bits of at least two bits.
9. A serial receiver comprising a clock data recovery circuit as claimed in any one of claims 1 to 8.
10. The serial receiver of claim 9, wherein said serial receiver further comprises an analog front end, a serial-to-parallel conversion unit, a digital calibration unit, and an equalizer connected in sequence; the analog front end includes an ADC.
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|---|---|---|---|---|
| CN114615116A (en) * | 2022-05-13 | 2022-06-10 | 南京沁恒微电子股份有限公司 | Communication protocol self-adaptive channel equalizer and equalizing method thereof |
| CN114615116B (en) * | 2022-05-13 | 2022-09-06 | 南京沁恒微电子股份有限公司 | Communication protocol self-adaptive channel equalizer and equalization method thereof |
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