CN107528658A - A kind of clock recovery method and device - Google Patents
A kind of clock recovery method and device Download PDFInfo
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- CN107528658A CN107528658A CN201710652017.9A CN201710652017A CN107528658A CN 107528658 A CN107528658 A CN 107528658A CN 201710652017 A CN201710652017 A CN 201710652017A CN 107528658 A CN107528658 A CN 107528658A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0037—Delay of clock signal
Abstract
The disclosure is directed to a kind of clock recovery method and device.This method includes：Determine the trip point before present analysis point in measured signal；According to the half of the sampled point in cycle where the mark of present analysis point, the mark of trip point and present analysis point, current delay points are calculated；The difference of current delay points and the preceding delay points being once calculated of storage is calculated, obtains current phase increment；Present analysis point is adjusted according to current phase increment, using the analysis site after adjustment as new present analysis point；Compare current phase increment and the phase increment that is calculated of preceding preset times of storage, when identical, terminate clock recovery operation；When different, the step of above-mentioned clock recovery is repeated according to new present analysis point.The technical scheme eliminates influence of the hardware device to the clock recovery degree of accuracy, improves the degree of accuracy of clock recovery result, is realized completely using software, greatly reduces cost, the speed of clock recovery.
Description
Technical field
This disclosure relates to signal processing technology field, more particularly to a kind of clock recovery method and device.
Background technology
The method that clock-pulse component is regained from the signal sent, referred to as clock recovery.At present, gone here and there for high speed
The clock recovery of row signal, often realized by the way of hardware, such as Agilent company, Li Ke companies use and be based on hardware
The clock recovery method of phaselocked loop.This method shows as a close loop negative feedback phase control system, and it can make output signal
Keep synchronous in phase and frequency with input signal.In the locked state, output signal caused by voltage controlled oscillator is the same as input
The phase difference differed between signal is a constant.Figure 11 is the general principle figure that phaselocked loop is formed, as shown in figure 11,
The reponse system of phaselocked loop is made up of following three parts, is respectively：
(1) phase discriminator (Phase Detector, abbreviation PD)
(2) loop filter (Loop Filter, LF)
(3) voltage controlled oscillator (Voltage Controlled Oscillators, abbreviation VCO)
But the bottleneck of prior art maximum is that hardware phase-locked-loop clock recovery can produce shake in itself due to firmware
Composition, influence to recover the accuracy of clock.It is difficult precisely due to hardware phase-locked-loop clock recovery is by phase discriminator, loop filtering
Three device, voltage controlled oscillator hardware components compositions, are typically set by the control to resistance, electric capacity to realize to these parameters
Put.But inside circuit, due to being influenceed by the problems such as temperature, device aging, parameter can produce change to a certain extent,
Influence the accuracy of result.
The content of the invention
The embodiment of the present disclosure provides a kind of clock recovery method and device.The technical scheme is as follows：
According to the first aspect of the embodiment of the present disclosure, there is provided a kind of clock recovery method, including：
The trip point before present analysis point in measured signal is determined, the present analysis point is according to default sample rate pair
A sampled point in the multiple sampled points obtained after being sampled by side signal, the trip point are to be changed into 1 from 0 or become from 1
For 0 sampled point；
According to the cycle where the identifying of the present analysis point, the mark of the trip point and present analysis point
The half of sampled point, current delay points are calculated, it is described to be identified as the numerical value for representing sampled point position in all sampled points；
The difference of the current delay points and the preceding delay points being once calculated of storage is calculated, obtains current phase
Position increment；
According to the current phase increment present analysis point is adjusted, using the analysis site after adjustment as newly
Present analysis point；
Compare the phase increment that the preceding preset times of the current phase increment and storage are calculated, when identical, knot
Beam clock recovery operation；When different, the step of above-mentioned clock recovery is repeated according to new present analysis point.
Optionally, the trip point determined before present analysis point, including：
First number of the sampled point in cycle where determining the present analysis point；
First several sampled point is traveled through forward from the present analysis point, finds out trip point.
Optionally, methods described also includes：
The measured signal is sampled according to default sample rate, multiple sampled points are obtained, sequentially in time to be every
Individual sampled point addition mark, the integer being identified as since 1；
All pwm values of measured signal are traveled through, obtain most narrow spaces；
It is determined that the sampled point positioned at centre position most on narrow spaces is the first initial analysis site, by described first point
Analysis point is used as the present analysis point；
Second number of point is up-sampled according to the most narrow spaces, it is determined that initial first phase increment, by described first
Phase increment is as the current phase increment.
Optionally, methods described also includes：
According to working as after the initial present analysis point of first analysis site and the current phase increment determination
Preceding analysis site.
Optionally, the present analysis point is adjusted according to the current phase increment, including：
Second number of the sampled point in cycle according to where the current phase increment calculates the present analysis point；
Using the trip point as starting point, according to the half of second number, the position of institute's present analysis point is adjusted
It is whole.
Optionally, it is described when the current phase increment is identical with the phase increment being once calculated before storage
Method also includes：
According to the current phase increment and the default sample rate, the clock cycle of the measured signal is calculated.
According to the second aspect of the embodiment of the present disclosure, there is provided a kind of clock recovery device, including：
Trip point determining module, for determining the trip point in measured signal before present analysis point, the present analysis
Point is to a sampled point in multiple sampled points for being obtained after being sampled by side signal, the saltus step according to default sample rate
Point is to be changed into 1 from 0 or be changed into 0 sampled point from 1；
Delay computing module, for according to the identifying of the present analysis point, the mark of the trip point and described working as
The half of the sampled point in cycle where preceding analysis site, calculates current delay points, and described be identified as represents sampled point all
The numerical value of position in sampled point；
Phase increment computing module, for the delay for calculating the current delay points with being once calculated before storage
The difference of points, obtain current phase increment；
Analysis site adjusting module, for being adjusted according to the current phase increment to the present analysis point, it will adjust
Analysis site after whole is as new present analysis point；
Comparison module, the phase that the preceding preset times for the current phase increment and storage are calculated increase
Amount, when identical, terminate clock recovery operation；When different, by the trip point determining module, Delay computing module, phase
Incremental computations module, analysis site adjusting module repeat the operation of above-mentioned clock recovery according to new present analysis point.
Optionally, the trip point determining module includes：
Determination sub-module, first number for the sampled point in cycle where determining the present analysis point；
Submodule is searched, for traveling through first several sampled point forward from the present analysis point, finds out jump
Height.
Optionally, described device also includes：
Sampling module, for being sampled according to default sample rate to the measured signal, multiple sampled points are obtained, according to
Time sequencing is that the addition of each sampled point identifies, the integer being identified as since 1；
Spider module, for traveling through all pwm values of measured signal, obtain most narrow spaces；
First analysis site determining module, for determining that the sampled point positioned at centre position most on narrow spaces is initial
First analysis site, using first analysis site as the present analysis point；
Phase increment determining module, for second number according to the most narrow spaces up-sampling point, it is determined that initially the
One phase increment, using the first phase increment as the current phase increment.
Optionally, described device also includes：
Second analysis site determining module, for being determined initially according to first analysis site and the current phase increment
Present analysis point after the present analysis point.
Optionally, the adjusting module includes：
Calculating sub module, the sampled point for the cycle where calculating the present analysis point according to the current phase increment
Second number；
Submodule is adjusted, for using the trip point as starting point, according to the half of second number, to institute's present analysis
The position of point is adjusted.
Optionally, described device also includes：
Clock cycle computing module, for increasing when the current phase increment with the phase being once calculated before storage
When measuring identical, according to the current phase increment and the default sample rate, the clock cycle of the measured signal is calculated.
According to the third aspect of the embodiment of the present disclosure, there is provided a kind of clock recovery device, including：
Processor；
For storing the memory of processor-executable instruction；
Wherein, the processor is configured as：
The trip point before present analysis point in measured signal is determined, the present analysis point is according to default sample rate pair
A sampled point in the multiple sampled points obtained after being sampled by side signal, the trip point are to be changed into 1 from 0 or become from 1
For 0 sampled point；
According to the cycle where the identifying of the present analysis point, the mark of the trip point and present analysis point
The half of sampled point, current delay points are calculated, it is described to be identified as the numerical value for representing sampled point position in all sampled points；
The difference of the current delay points and the preceding delay points being once calculated of storage is calculated, obtains current phase
Position increment；
According to the current phase increment present analysis point is adjusted, using the analysis site after adjustment as newly
Present analysis point；
Compare the phase increment that the preceding preset times of the current phase increment and storage are calculated, when identical, knot
Beam clock recovery operation；When different, the step of above-mentioned clock recovery is repeated according to new present analysis point.
The technical scheme provided by this disclosed embodiment can include the following benefits：
In the present embodiment, influence of the hardware device to the clock recovery degree of accuracy is eliminated, improves clock recovery result
The degree of accuracy.In addition, being realized completely using software, cost is greatly reduced, also, the speed of clock recovery is with respect to hardware phase-locked-loop
Comparatively fast.
It should be appreciated that the general description and following detailed description of the above are only exemplary and explanatory, not
The disclosure can be limited.
Brief description of the drawings
Accompanying drawing herein is merged in specification and forms the part of this specification, shows the implementation for meeting the disclosure
Example, and be used to together with specification to explain the principle of the disclosure.
Fig. 1 is a kind of flow chart of clock recovery method according to an exemplary embodiment.
Fig. 2 is a kind of flow chart of clock recovery method according to another exemplary embodiment.
Fig. 3 is a kind of flow chart of clock recovery method according to another exemplary embodiment.
Fig. 4 is a kind of flow chart of clock recovery method according to another exemplary embodiment.
Fig. 5 is a kind of flow chart of clock recovery method according to another exemplary embodiment.
Fig. 6 is a kind of block diagram of clock recovery device according to an exemplary embodiment.
Fig. 7 is the block diagram of the trip point determining module 601 according to an exemplary embodiment.
Fig. 8 is a kind of block diagram of clock recovery device according to another exemplary embodiment.
Fig. 9 is the block diagram of the trip point adjusting module 605 according to an exemplary embodiment.
Figure 10 is a kind of block diagram of clock recovery device according to another exemplary embodiment.
Figure 11 is the general principle figure that phaselocked loop is formed.
Embodiment
Here exemplary embodiment will be illustrated in detail, its example is illustrated in the accompanying drawings.Following description is related to
During accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawings represent same or analogous key element.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the disclosure.On the contrary, they be only with it is such as appended
The example of the consistent apparatus and method of some aspects be described in detail in claims, the disclosure.
The embodiment of the present disclosure, for shaking interference problem caused by hardware phase-locked-loop clock recovery meeting, based on phaselocked loop
Phase differentiates principle, and clock recovery is realized using software.
The embodiment of the present disclosure, utilize present analysis point coordinates and initial phase increment size, it is proposed that a kind of delay phase
Computational methods, and then calculate new phase increment estimated value, draw actual clock signal standard point position and normal place
Phase delay relation, and present analysis point position is modified using phase is postponed, it is allowed to close to real signal.Finally,
The phase increment of locking can be utilized to obtain the clock information included in signal.
In addition, in another embodiment of the present disclosure, can more accurately be obtained by way of determining most narrow spaces length
The cycle of initial recovered clock.
Fig. 1 is a kind of flow chart of clock recovery method according to an exemplary embodiment, as shown in figure 1, the party
Method comprises the following steps：
Step S11, determines the trip point before present analysis point in measured signal, and present analysis point is according to default sampling
For rate to a sampled point in multiple sampled points for being obtained after being sampled by side signal, trip point is to be changed into 1 from 0 or become from 1
For 0 sampled point.
Fig. 2 is a kind of flow chart of clock recovery method according to another exemplary embodiment, as shown in Fig. 2
In step S11, the trip point before present analysis point is determined, including：
Step S21, first number of the sampled point in cycle where determining present analysis point；
Step S22, first several sampled point is traveled through forward from present analysis point, finds out trip point.
For example, the sampled point number in cycle where present analysis point is 200, because present analysis point is located at the place cycle
Center, i.e. the 100th point, then present analysis point travel through 200 points forward, one surely finds trip point, i.e., is changed into 1 from 0
Sampled point.
Step S12, according to the sampling in cycle where the mark of present analysis point, the mark of trip point and present analysis point
The half of point, current delay points are calculated, are identified as the numerical value for representing sampled point position in all sampled points.
For example, present analysis point is identified as 500, trip point is identified as 390, the sampled point in cycle where present analysis point
Half be 100, current delay points are 500-390-100=10.
Points in the pulsewidth length of current lock are determined by the value of initial phase increment, due to represented by the points
Pulsewidth and standard clock signal pulsewidth can there is certain deviation, it is therefore desirable to obtain determined by current phase increment value
The difference for the pulsewidth points that pulsewidth is counted and standard clock signal is included, as postpone the value of phase, in order to subsequently through this
Value verifies to the phase of locking.
Above-mentioned current delay points, actually represent measured signal current estimated position and actual clock signal position it
Between variation, the position of analysis site is adjusted on this basis, makes it closer to the position of actual clock signal.
Step S13, the difference of current delay points and the preceding delay points being once calculated of storage is calculated, is worked as
Preceding phase increment.
Step S14, present analysis point is adjusted according to current phase increment, using the analysis site after adjustment as new
Present analysis point.
Optionally, present analysis point is adjusted according to current phase increment, including：Calculated according to current phase increment
Second number of the sampled point in cycle where present analysis point；Using trip point as starting point, according to the half of second number, to working as
The position of preceding analysis site is adjusted.
The phase increment that the preceding preset times of step S15, more current phase increment and storage are calculated, when identical
When, terminate clock recovery operation；When different, repeat the step S11- of above-mentioned clock recovery according to new present analysis point
S15。
Phase increment value can be estimated according to the delay phase calculated, it is continuous with new phase increment estimated value
The position of present analysis point is corrected, is allowed to move closer to actual signal, is the deciding factor for verifying final result.It is in view of every
The secondary value for circulating the delay phase obtained is differed, therefore accurately the value of phase increment could be carried out using rational method
Verification, recalculates to the position of present analysis point, can just be allowed to close to actual signal, using obtaining what is included in signal
Clock information.Therefore, in above-mentioned steps S15, the phase increment being currently calculated preceding is calculated once or several times with preceding
To phase increment be compared, if all identical, illustrate measured signal be adjusted to reality clock signal it is identical,
Clock recovery operation can be stopped, if it is different, then also needing to continuing above-mentioned steps progress clock recovery.
Wherein, the preset times can be the integer more than or equal to 1, and staff can be according to the precision to clock recovery
Determine the preset times, if required precision is higher, the value of the preset times can be set to 2 times and more than, if to precision
It is required that it is relatively low, then preset times can be set to 1 time.
During software phase-lock loop clock recovery, most primary task seeks to determine the value of initial phase increment,
The accuracy that the selection of the value is estimated for clock signal period has very big influence.If the value chooses mistake, then whole
The process of individual lock phase all can be estimated that this can substantially reduce the accuracy of result, cause a deviation around the phase of mistake.This
Initial phase increment is determined by following steps in embodiment, Fig. 3 is a kind of clock according to another exemplary embodiment
The flow chart of restoration methods, as shown in figure 3, this method also includes：
Step S31, measured signal is sampled according to default sample rate, obtain multiple sampled points, sequentially in time
Add and identify for each sampled point, be identified as the integer since 1；
Step S32, all pwm values of measured signal are traveled through, obtain most narrow spaces；
Step S33, it is determined that the sampled point positioned at centre position most on narrow spaces is the first initial analysis site, by first point
Analysis point is used as present analysis point；
Step S34, second number of point is up-sampled according to most narrow spaces, it is determined that initial first phase increment, by first
Phase increment is as current phase increment.
In the present embodiment, by being traveled through to all pwm values of measured signal, the length of its most narrow spaces is found out, by
In in serial signal, the length of most narrow spaces is most close to its pwm clock signal included, therefore using the length as just
Beginning phase increment estimated value, initial phase increment size can with relatively more accurate be determined, so as to substantially increase subsequently to clock
The degree of accuracy of signaling protein14-3-3.
Optionally, this method also includes：Initial present analysis point is determined according to the first analysis site and current phase increment
Present analysis point afterwards.
Optionally, when current phase increment is identical with the phase increment being once calculated before storage, method is also wrapped
Include：
According to current phase increment and default sample rate, the clock cycle of measured signal is calculated.
For example, current phase increment is phase_current_increment, it is Fs to preset sample rate, represents per second and adopts
The clock cycle period_clock of sample how many times, then measured signal
In the present embodiment, based on the software phase-lock loop clock recovery of phase increment estimation, phase is increased by postponing phase
The value of amount is modified, and recycles revised value to rejudge present analysis point and next analysis site, and then to postponing phase
Again verified.Make phase increment stable in a standard value by this process verified repeatedly, pass through the value
The length of standard time clock pulsewidth is calculated, recovers clock information signal.
For prior art, the software phase-lock loop clock recovery based on phase increment estimation of the embodiment of the present disclosure
Method, influence of the hardware device to the clock recovery degree of accuracy is eliminated, improves the degree of accuracy of clock recovery result.It is in addition, complete
Realized entirely using software, greatly reduce cost, also, the speed of clock recovery is very fast with respect to hardware phase-locked-loop.
The method of the present embodiment is described in detail below.
Fig. 4 is a kind of flow chart of clock recovery method according to another exemplary embodiment, as shown in figure 4, should
Method includes the process of initial analysis, comprises the following steps that：
Step S41, measured signal is sampled according to default sample rate, obtain multiple sampled points, sequentially in time
Add and identify for each sampled point；
Step S42, all pwm values of measured signal are traveled through, obtain most narrow spaces；
Step S43, the number n1 of point is up-sampled according to most narrow spaces, it is determined that the first initial analysis site analysis_
Point1 and first phase increment phase_increment1；
Wherein, first phase increment
Step S44, the cycle according to where first phase increment phase_increment1 calculates the first analysis site are wrapped
Second number n2 of the sampled point contained；
Step S45, n2 sampled point is traveled through forward from the first analysis site analysis_point1, finds out the first saltus step
Point period_start_point1；
Step S46, according to the first analysis site analysis_point1 and the first trip point period_start_point1
Mark, and the half of second number, calculate the first delay points later_points1；
For example, the first analysis site analysis_point1's is identified as nanalysis_point1, the first trip point period_
Start_point1's is identified as nperiod_start_point1, then first postpones points
Fig. 5 is a kind of flow chart of clock recovery method according to another exemplary embodiment, as shown in figure 5, should
The overall step of method is as follows：
Step S501, initial analysis, i.e. above-mentioned steps S41~S46；
Step S502, the number n_ of the sampled point in cycle where determining present analysis point analysis_current_point
current；
Step S503, according to current phase increment phase_current_increment, determine currently to divide in measured signal
Analyse the trip point period_start_point before point analysis_current_point；
Step S504, according to adopting for cycle where the mark of present analysis point, the mark of trip point and present analysis point
The half of sampling point, calculate current delay points later_current_points；
Step S505, judge whether current be to analyze for the first time, if it is, step S506 is performed, if not, performing step
S511；
Step S506, current delay points later_current_points value is assigned to upper delay points later_
points_pre；
Step S507, next analysis site after present analysis point is determined according to present analysis point and current phase increment
analysis_next_point；
The mark of next analysis site
, i.e., next analysis site analysis_next_point is present analysis point analysis_current_point
N_current sampled point backward；
Step S508, next analysis site analysis_next_point is assigned to present analysis point analysis_
current_point；
Step S509, analysis times analysis_cuts is added 1；
Step S510, current phase increment phase_current_increment is stored in array phase_
Increment_test, return to step S502；
Step S511, counted by the upper delay for calculating current delay points later_current_points and prestoring
Later_points_pre difference, new current phase increment phase_current_increment is obtained,
Phase_current_increment=| later_current_points-later_points_pre |；
Step S512, according to trip point period_start_point and current phase increment phase_current_
Increment adjusts present analysis point analysis_current_point,
The present analysis point analysis_ is calculated according to current phase increment phase_current_increment
The number n_current of the sampled point in cycle where current_point；
Using trip point period_start_point as starting point, according to n_current half, to present analysis point
Analysis_current_point position is adjusted,
Present analysis point analysis_current_point's after adjustment is identified as
Step S513, according to present analysis point analysis_current_point and current phase increment phase_
Current_increment determines next analysis site analysis_next_point；
Step S514, next analysis site analysis_next_point is assigned to present analysis point
analysis_current_point；
Step S515, analysis times analysis_cuts is added 1；
Step S516, current phase increment phase_current_increment is stored in array phase_
increment_test；
Step S517, judge whether current phase increment and the preceding phase increment being calculated twice stored are identical, such as
Fruit is identical, terminates, if it is different, return to step S502.
Following is embodiment of the present disclosure, can be used for performing embodiments of the present disclosure.
Fig. 6 is a kind of block diagram of clock recovery device according to an exemplary embodiment, and the device can be by soft
Part, hardware or both are implemented in combination with as some or all of of electronic equipment.As shown in fig. 6, disclosure clock recovery
Device 600, including：
Trip point determining module 601, for determining the trip point in measured signal before present analysis point, present analysis point
For according to default sample rate to a sampled point in multiple sampled points for being obtained after being sampled by side signal, trip point be from
0 is changed into 1 or is changed into 0 sampled point from 1；
Delay computing module 602, for the mark according to present analysis point, the mark of trip point and present analysis point institute
In the half of the sampled point in cycle, current delay points are calculated, is identified as and represents sampled point position in all sampled points
Numerical value；
Phase increment computing module 603, for the delay for calculating current delay points with being once calculated before storage
The difference of points, obtain current phase increment；
Analysis site adjusting module 604, for being adjusted according to current phase increment to present analysis point, after adjustment
Analysis site is as new present analysis point；
Comparison module 605, the phase increment that the preceding preset times for comparing current phase increment and storage are calculated,
When identical, terminate clock recovery operation；When different, by the trip point determining module, Delay computing module, phase increment
Computing module, analysis site adjusting module repeat the operation of above-mentioned clock recovery according to new present analysis point.
Fig. 7 is the block diagram of the trip point determining module 601 according to an exemplary embodiment, as shown in fig. 7, optional
, trip point determining module 601 includes：
Determination sub-module 71, first number for the sampled point in cycle where determining present analysis point；
Submodule 72 is searched, for traveling through first several sampled point forward from present analysis point, finds out trip point.
Fig. 8 is a kind of block diagram of clock recovery device according to another exemplary embodiment, as shown in figure 8, the dress
Putting 600 also includes：
Sampling module 606, for being sampled according to default sample rate to measured signal, multiple sampled points are obtained, according to
Time sequencing is each sampled point addition mark, is identified as the integer since 1；
Spider module 607, for traveling through all pwm values of measured signal, obtain most narrow spaces；
First analysis site determining module 608, for determining that the sampled point positioned at centre position most on narrow spaces is initial
First analysis site, using the first analysis site as present analysis point；
Phase increment determining module 609, for second number according to most narrow spaces up-sampling point, it is determined that initial first
Phase increment, using first phase increment as current phase increment.
As shown in figure 8, the device 600 also includes：
Second analysis site determining module 610, for determining initially current according to the first analysis site and current phase increment
Present analysis point after analysis site.
Fig. 9 is the block diagram of the trip point adjusting module 605 according to an exemplary embodiment, as shown in figure 9, adjustment mould
Block 605 includes：
Calculating sub module 91, second for the sampled point in cycle where calculating present analysis point according to current phase increment
Number；
Submodule 92 is adjusted, for using trip point as starting point, according to the half of second number, to the position of institute's present analysis point
Put and be adjusted.
Figure 10 is a kind of block diagram of clock recovery device according to another exemplary embodiment, as shown in Figure 10, should
Device also includes：
Clock cycle computing module 611, for increasing when current phase increment with the phase being once calculated before storage
When measuring identical, according to current phase increment and default sample rate, the clock cycle of measured signal is calculated.
According to the third aspect of the embodiment of the present disclosure, there is provided a kind of clock recovery device, including：
Processor；
For storing the memory of processor-executable instruction；
Wherein, the processor is configured as：
The trip point before present analysis point in measured signal is determined, the present analysis point is according to default sample rate pair
A sampled point in the multiple sampled points obtained after being sampled by side signal, the trip point are to be changed into 1 from 0 or become from 1
For 0 sampled point；
According to the cycle where the identifying of the present analysis point, the mark of the trip point and present analysis point
The half of sampled point, current delay points are calculated, it is described to be identified as the numerical value for representing sampled point position in all sampled points；
The difference of the current delay points and the preceding delay points being once calculated of storage is calculated, obtains current phase
Position increment；
According to the current phase increment present analysis point is adjusted, using the analysis site after adjustment as newly
Present analysis point；
Compare the phase increment that the preceding preset times of the current phase increment and storage are calculated, when identical, knot
Beam clock recovery operation；When different, the step of above-mentioned clock recovery is repeated according to new present analysis point.
Optionally, the processor is additionally configured to：
The trip point determined before present analysis point, including：
First number of the sampled point in cycle where determining the present analysis point；
First several sampled point is traveled through forward from the present analysis point, finds out trip point.
Optionally, the processor is additionally configured to：
The measured signal is sampled according to default sample rate, multiple sampled points are obtained, sequentially in time to be every
Individual sampled point addition mark, the integer being identified as since 1；
All pwm values of measured signal are traveled through, obtain most narrow spaces；
It is determined that the sampled point positioned at centre position most on narrow spaces is the first initial analysis site, by described first point
Analysis point is used as the present analysis point；
Second number of point is up-sampled according to the most narrow spaces, it is determined that initial first phase increment, by described first
Phase increment is as the current phase increment.
Optionally, the processor is additionally configured to：
According to working as after the initial present analysis point of first analysis site and the current phase increment determination
Preceding analysis site.
Optionally, the processor is additionally configured to：
The present analysis point is adjusted according to the current phase increment, including：
Second number of the sampled point in cycle according to where the current phase increment calculates the present analysis point；
Using the trip point as starting point, according to the half of second number, the position of institute's present analysis point is adjusted
It is whole.
Optionally, the processor is additionally configured to：When the current phase increment before storage with being once calculated
Phase increment it is identical when, according to the current phase increment and the default sample rate, calculate the clock of the measured signal
Cycle.
Those skilled in the art will readily occur to the disclosure its after considering specification and putting into practice disclosure disclosed herein
Its embodiment.The application is intended to any modification, purposes or the adaptations of the disclosure, these modifications, purposes or
Person's adaptations follow the general principle of the disclosure and including the undocumented common knowledges in the art of the disclosure
Or conventional techniques.Description and embodiments are considered only as exemplary, and the true scope of the disclosure and spirit are by following
Claim is pointed out.
It should be appreciated that the precision architecture that the disclosure is not limited to be described above and is shown in the drawings, and
And various modifications and changes can be being carried out without departing from the scope.The scope of the present disclosure is only limited by appended claim.
Claims (13)
- A kind of 1. clock recovery method, it is characterised in that including：The trip point before present analysis point in measured signal is determined, the present analysis point is to by side according to default sample rate A sampled point in multiple sampled points that signal obtains after being sampled, the trip point are to be changed into 1 from 0 or be changed into 0 from 1 Sampled point；According to the sampling in cycle where the identifying of the present analysis point, the mark of the trip point and present analysis point The half of point, current delay points are calculated, it is described to be identified as the numerical value for representing sampled point position in all sampled points；The difference of the current delay points and the preceding delay points being once calculated of storage is calculated, current phase is obtained and increases Amount；The present analysis point is adjusted according to the current phase increment, using the analysis site after adjustment as newly current Analysis site；Compare the phase increment that the preceding preset times of the current phase increment and storage are calculated, when identical, at the end of Clock recovery operation；When different, the step of above-mentioned clock recovery is repeated according to new present analysis point.
- 2. according to the method for claim 1, it is characterised in that the trip point determined before present analysis point, including：First number of the sampled point in cycle where determining the present analysis point；First several sampled point are traveled through forward from the present analysis point, find out trip point.
- 3. method according to claim 1 or 2, it is characterised in that methods described also includes：The measured signal is sampled according to default sample rate, multiple sampled points is obtained, is adopted sequentially in time to be each Sampling point addition mark, the integer being identified as since 1；All pwm values of measured signal are traveled through, obtain most narrow spaces；It is determined that the sampled point positioned at centre position most on narrow spaces is the first initial analysis site, by first analysis site As the present analysis point；Second number of point is up-sampled according to the most narrow spaces, it is determined that initial first phase increment, by the first phase Increment is as the current phase increment.
- 4. according to the method for claim 3, it is characterised in that methods described also includes：Current minute after the initial present analysis point is determined according to first analysis site and the current phase increment Analysis point.
- 5. according to the method for claim 4, it is characterised in that according to the current phase increment to the present analysis point It is adjusted, including：Second of the sampled point in cycle according to where the current phase increment calculates the present analysis point；Using the trip point as starting point, according to the half of described second, the position of the present analysis point is adjusted.
- 6. according to the method for claim 3, it is characterised in that when the current phase increment before storage with once calculating When obtained phase increment is identical, methods described also includes：According to the current phase increment and the default sample rate, the clock cycle of the measured signal is calculated.
- A kind of 7. clock recovery device, it is characterised in that including：Trip point determining module, for determining the trip point in measured signal before present analysis point, the present analysis point is It is to a sampled point in multiple sampled points for being obtained after being sampled by side signal, the trip point according to default sample rate It is changed into 1 from 0 or is changed into 0 sampled point from 1；Delay computing module, for according to the identifying of the present analysis point, the mark of the trip point and described current minute The half of the sampled point in cycle where analysis point, calculates current delay points, and described be identified as represents sampled point in all samplings The numerical value of position in point；Phase increment computing module, counted for calculating the current delay points with the delay being once calculated before storage Difference, obtain current phase increment；Analysis site adjusting module, for being adjusted according to the current phase increment to the present analysis point, after adjustment Analysis site as new present analysis point；Comparison module, the phase increment that the preceding preset times for the current phase increment and storage are calculated, when When identical, terminate clock recovery operation；When different, by the trip point determining module, Delay computing module, phase increment meter Calculation module, analysis site adjusting module repeat the operation of above-mentioned clock recovery according to new present analysis point.
- 8. device according to claim 7, it is characterised in that the trip point determining module includes：Determination sub-module, first number for the sampled point in cycle where determining the present analysis point；Submodule is searched, for traveling through first several sampled point forward from the present analysis point, finds out trip point.
- 9. the device according to claim 7 or 8, it is characterised in that described device also includes：Sampling module, for being sampled according to default sample rate to the measured signal, multiple sampled points are obtained, according to the time Order identifies for the addition of each sampled point, the integer being identified as since 1；Spider module, for traveling through all pwm values of measured signal, obtain most narrow spaces；First analysis site determining module, for determining the sampled point positioned at centre position most on narrow spaces for initial first Analysis site, using first analysis site as the present analysis point；Phase increment determining module, for second number of the most narrow spaces up-sampling point according to, it is determined that the first initial phase Position increment, using the first phase increment as the current phase increment.
- 10. device according to claim 9, it is characterised in that described device also includes：Second analysis site determining module, for according to first analysis site and the current phase increment determination are initial Present analysis point after present analysis point.
- 11. device according to claim 10, it is characterised in that the adjusting module includes：Calculating sub module, for the sampled point in cycle where calculating the present analysis point according to the current phase increment Two numbers；Submodule is adjusted, for using the trip point as starting point, according to the half of second number, to institute's present analysis point Position is adjusted.
- 12. device according to claim 9, it is characterised in that described device also includes：Clock cycle computing module, for when the current phase increment and the phase increment phase that is once calculated before storing Meanwhile according to the current phase increment and the default sample rate, calculate the clock cycle of the measured signal.
- A kind of 13. clock recovery device, it is characterised in that including：Processor；For storing the memory of processor-executable instruction；Wherein, the processor is configured as：The trip point before present analysis point in measured signal is determined, the present analysis point is to by side according to default sample rate A sampled point in multiple sampled points that signal obtains after being sampled, the trip point are to be changed into 1 from 0 or be changed into 0 from 1 Sampled point；According to the sampling in cycle where the identifying of the present analysis point, the mark of the trip point and present analysis point The half of point, current delay points are calculated, it is described to be identified as the numerical value for representing sampled point position in all sampled points；The difference of the current delay points and the preceding delay points being once calculated of storage is calculated, current phase is obtained and increases Amount；The present analysis point is adjusted according to the current phase increment, using the analysis site after adjustment as newly current Analysis site；Compare the phase increment that the preceding preset times of the current phase increment and storage are calculated, when identical, at the end of Clock recovery operation；When different, the step of above-mentioned clock recovery is repeated according to new present analysis point.
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