CN1556603A - PHS system position synchronous method based on digital lock phase ring and realizing device - Google Patents
PHS system position synchronous method based on digital lock phase ring and realizing device Download PDFInfo
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- CN1556603A CN1556603A CNA2004100320114A CN200410032011A CN1556603A CN 1556603 A CN1556603 A CN 1556603A CN A2004100320114 A CNA2004100320114 A CN A2004100320114A CN 200410032011 A CN200410032011 A CN 200410032011A CN 1556603 A CN1556603 A CN 1556603A
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Abstract
The present invention discloses a PHS system position synchronous method based on digital lock phase ring and realizing device, wherein the method comprises steps of recovering synchronous clock by a lock phase ring, synchronizing constant-modulus character of points by using data in system, giving synchronous reference signal by quadratic sum calculation and zero crossing detection, synchronizing bit by using the synchronous reference. The device comprises a multiplier-adder unit, a synchronous reference generator, a local synchronous pulse generator, a digital loop filter, a synchronous mode estimator, a phase error register and a synchronous delay compensator. The method can give accuracy synchronous reference, and has large suitable area and good fault-tolerant capacity.
Description
Technical field
The invention belongs to digital communicating field, be specifically related to PHS (Personal Handyphone System Personal Handyphone System(PHS), i.e. " Personal Handyphone System ") system uplink bit synchronization method based on digital phase-locked loop.
Background technology
In digital communication system, bit synchronization is an important step before data demodulates, and inaccurate bit synchronization causes the decline of demodulation performance and the raising of the error rate possibly.For employing
The communication system of (orthogonal phase shift modulation) modulation system is an example with the PHS system, and common method for synchronous is by calculating the energy of the signal of each sampled point behind the differential decoding, determining sync bit according to the maximum principle of energy then.Resource required when this method hardware is realized is more, and owing to introduced two multiply operations that have noise signal in the differential decoding, not only reduced signal to noise ratio, and often will use more code element information to come completion bit synchronous, so processing delay is bigger.
Usually the bit synchronization in the legacy communications system is by clock recovery circuitry (often adopting phase-locked loop), recovers synchronised clock.This method adopts the mode that the input data in real time is handled, and data is not stored, so the processing delay of introducing is very little.But, because the locking of phase-locked loop needs certain hour, so the data before the pll lock often can not obtain correct demodulation result.In order to address this problem, actual communication systems often sent some temporal signatures known array clearly before sending business datum, with auxiliary phase locked loop fast lock, prefix SS+PR in the PHS system promptly aims at clock recovery and designs, and SS+PR is loop cycle " a 1001 " sequence.
The result for retrieval of relevant patent is being analyzed the back discovery, in the PHS system, conventional method for synchronous mainly contains two kinds: a kind of is to utilize this control word signal after demodulation maximum next as synchronization basic standard in the mould value at synchronous points place, this method has been introduced two multiplyings that have noise separating timing, and when the mark synchronous base, require the maximum of signal, hardware realizes that difficulty is big, exist under the situation of noise also bigger to the synchronous base influence; Another kind is to utilize the correlation of UW word in the PHS agreement (user's word) that it is asked relevant, and its relevant peaks is sync bit, and this method relates to asks relevant, and hardware resource takies bigger.
Summary of the invention
The technical problem to be solved in the present invention is that the proposition realization is easy, less to the synchronous base influence, and hardware takies the also less bit synchronization method of resource, has promptly proposed a kind of utilization warp
Data sync point constant modulus property behind modulation and the molding filtration, the PHS system uplink bit synchronization method based on digital phase-locked loop provides synchronous base by simple quadratic sum computing and zero passage detection.
On the basis that proposes said method, the present invention also proposes a kind of device of realizing said method.
Bit synchronization method provided by the invention recovers synchronised clock by phase-locked loop, utilizes the constant modulus property of data sync point in the system, provides synchronizing datum signal by quadratic sum computing and zero passage detection, utilizes this synchronous base to carry out bit synchronization.
The present invention can comprise the steps:
2.1 at first calculate process
Two-way orthogonal signalling I, the quadratic sum S=I of Q of modulation and formed filter output
2+ Q
2, suppose that here this signal rate is R times (being R times of over-sampling data) of symbol digit rate;
2.2 the quadratic sum signal of trying to achieve subtracted each other every R sampled point obtains signal D
n=S
N+R-S
n
2.3 to subtracting each other D as a result
nDo zero passage detection, its zero crossing is carried out mark, obtain synchronizing datum signal;
Obtaining taking following steps again on the basis of synchronous base:
3.1 produce local lock-out pulse, this pulse frequency and character rate are consistent; Lock-out pulse can produce by following method: can preset several counters by one and produce, arrive high level that width is a clock cycle of output after the maximum of its setting when count value;
3.2 whether current zero crossing be can be used for synchronous base is judged: push away before the zero crossing place
Individual sampled point, when
Handle (G value choose environmental correclation with practical application, generally choose the S signal maximum and multiply by coefficient k, k chooses) with follow-up described step between 0 to 1 during greater than the thresholding G that sets, and synchronous enabled flag F is changed to effectively; Otherwise, keep the constant clock cycle, the number that presets that is about to be used to produce the counter of local lock-out pulse is put back its initial value, and enable flag F is changed to invalid, and jumps to step 2.1;
3.3 control two counter C1, C2 jointly with zero crossing and local lock-out pulse, finish the loop filtering effect, wherein, count to C2 the next zero crossing by the lock-out pulse rising edge at zero crossing C1 counting between the next local lock-out pulse rising edge;
3.4 adding up its count value at each zero crossing place is N=C1-C2;
3.5 when synchronous enabled flag F is effective, calculate the initial value that presets counter according to the positive and negative and order of magnitude of N value at each zero crossing place:
(
Expression rounds downwards); T in the formula
nPreset the counter initial value for what needs upgraded; M is a constant, generally chooses 2 integral number power, as 16,32 equivalences 8,, this be for hardware realize convenient: remove M and round downwards, hardware can be finished by moving to right of data in realizing; The size of these values is the speed and the stability of influence tracking directly;
3.6 when the synchronous enabled flag F described in the step 3.2 is effective, preserves accumulative total by following formula and differ:
Accumulative total differs when this marked invalid: T
n'=T
N-1
3.7 synchronization delayed time is compensated, provides lock-out pulse.
The invention provides and be used to realize that the device of bit synchronization method comprises: adder and multiplier, synchronous base generator, local clock-pulse generator, digital loop filters, method of synchronization decision device, phase error register and synchronization delayed time compensator;
Described synchronous base generator further comprises sliding window subtraction device and zero-crossing detector;
Described loop filter further comprises forward counter and anti-phase counter;
Described method of synchronization decision device further comprises threshold compataror and synchro switch controller;
Described phase error register further comprises shift register and accumulator;
Described adder and multiplier mainly is responsible for calculating the quadratic sum that the up I/Q two-way of PHS base station system root is given birth to the cosine filter output signal;
Described synchronous base generator is slided window with the output of adder and multiplier and is subtracted each other, the width of window is consistent with the over-sampling multiple R of data, again the zero crossing that subtracts each other the result is carried out mark, and with this signal as synchronization basic standard, abbreviate this benchmark as crossover point signal among the present invention;
But described local clock-pulse generator is actually a counter that counting upper limit preset count initial value is arranged; When arriving counting, count value goes up in limited time the high level of a clock cycle of output; Also as the control signal of the counting initial value of itself packing into new, counter begins counting from new counting initial value in the back at this signal to this output signal from high to low simultaneously;
Described loop filter is responsible for phase error estimation and phase error, and wherein forward counter is used for writing down from the nearest zero crossing of local lock-out pulse to the working pulse number between this lock-out pulse; Backward counter is used for writing down lock-out pulse to the working pulse number between its nearest zero crossing;
Described method of synchronization decision device is according to the operating state that the comparative result of quadratic sum signal amplitude and thresholding is decided method for synchronous, and synchronous enabled flag F is effective when surpassing thresholding; Otherwise flag F is invalid;
Described phase error register is right at each zero crossing place, and the phase error N that loop filter is estimated adds up by following formula
In the formula,
Represent downward round numbers, choose less M value when being effective when flag F, to accelerate synchronizing speed, choose bigger M value when F is invalid, the reduction synchronizing speed improves anti-throat performance; Consider the hardware realization, M generally chooses 2 integral number power; The output of this phase error register is directly given local clock-pulse generator as the counting initial value, adjusts the phase place of local lock-out pulse;
Described synchronization delayed time compensator is to be used for compensating whole synchronous caused time delay, and this time delay is fixed, and mainly being has constant time delay caused by benchmark and actual synchronization position that synchronous base generator in this synchronizer produces; The output of this compensator is the lock-out pulse of this synchronizer output; By this lock-out pulse the I/Q two paths of data is extracted data after can obtaining synchronously.
The present invention utilizes the constant modulus property of data sync point in the PHS system, provided synchronous base by simple quadratic sum computing and zero passage detection, the characteristics of signals that is used for the control word " SS+PR " of assist in synchronization in the PHS system can draw synchronous base accurately through after such processing, simultaneously for other The data except this control word thresholding control, choose method such as different parameters under zero crossing screening and the different operating state under the prerequisite that does not influence synchronizing speed and synchronization accuracy, improved the suitable application area and the fault freedom of this method.
Description of drawings
Fig. 1 method flow diagram of the present invention;
Fig. 2 implement device structure chart of the present invention;
Embodiment
Accompanying drawing 1 is a method flow diagram of the present invention.Main points of the present invention are to calculate the synchronous tracking that is used for the zero crossing of synchronous base and utilizes digital phase-locked loop.Comprising whether zero crossing be can be used for the judgement of synchronous base, the control of synchronous working state.
Method set forth in the present invention can realize by following several steps:
The first step (101) is calculated the up quadratic sum S=I through the formed filter signal in I/Q two-way PHS base station
2+ Q
2, suppose that here this signal rate is R times (being R times of over-sampling data) of symbol digit rate.
Second goes on foot (102), the quadratic sum signal of trying to achieve is subtracted each other every R sampled point obtain signal D
n=S
N+R-S
n
The 3rd step (103) is to subtracting each other D as a result
nDo zero passage detection, its zero crossing is carried out mark, obtain synchronous base.
The 4th step (104) produced local lock-out pulse, and this pulse frequency and character rate are consistent.Lock-out pulse produces by following method: can preset several counters by one and produce, arrive high level that width is a clock cycle of output after the maximum of its setting when count value.
The 5th step (105), zero crossing and local lock-out pulse are controlled two counter C1, C2 jointly, finish the loop filtering effect, wherein, count to C2 next zero crossing by the lock-out pulse rising edge at zero crossing C1 counting between the next local lock-out pulse rising edge.
In the 6th step (106), adding up its count value at each zero crossing place is N=C1-C2.
In the 7th step (107), whether current zero crossing be can be used for synchronous base judge: before the zero crossing place, push away
Individual sampled point, when
Handle (G value choose environmental correclation with practical application, generally choose the S signal maximum and multiply by coefficient k, k chooses) with follow-up described step between 0 to 1 during greater than thresholding G, and synchronous enabled flag F is changed to effectively; Otherwise, keep the constant clock cycle, the number that presets that is about to be used to produce the counter of local lock-out pulse is put back its initial value, and it is invalid at this moment to need enable flag F is changed to.
In the 8th step (108), when synchronous enabled flag F is effective, calculate the initial value that presets counter according to the positive and negative and order of magnitude of N value:
(
Expression rounds downwards); T in the formula
nPreset the counter initial value for what needs upgraded, M is a constant.
In the 9th step (109), when the synchronous enabled flag F described in the step 5 is effective, preserves accumulative total by following formula and differ:
Accumulative total differs when this marked invalid: T
n'=T
N-1
The tenth step (110) compensated whole Synchronous Processing time delay, provided lock-out pulse.
Accompanying drawing 2 is synchronous implement device pie graphs provided by the present invention.Input signal input adder and multiplier 21 is sent into sliding window subtraction device 221 and zero-crossing detector 222 in the synchronous base generator 22 more successively; Produce local lock-out pulse by local clock-pulse generator 23 on the other hand, this signal and zero-crossing detector 222 unite to come the counting of forward counter 241 and backward counter 242 in the control loop filter 24, and count value is delivered to subtraction device 243 and obtained phase error separately at each zero crossing place.Method of synchronization decision device 25 comes the processing mode of shift register 261 in the control phase error register 26 and 262 pairs of phase error signals of accumulator according to the sliding window subtraction device 221 and the size of thresholding comparison.Synchronization delayed time compensator 27 is delivered in the output of accumulator, delivers to local clock-pulse generator 23 again, sends final lock-out pulse by it.
The present invention utilizes the PHS system uplink bit synchronization method of constant modulus property based on digital phase-locked loop, method uniqueness, novelty, described realization is simple, The Realization of Simulation with low cost, the development technique risk is little.The present invention has following characteristics:
1, before residing position is positioned at differential decoding in the PHS base station system, owing to do not need through differential ference spiral, thereby avoided introducing two multiply operations that have noise signal.
2, finish digital phase-locked loop (DPLL) by a counter group thus phase demodulation and loop filtering function control digital controlled oscillator (NCO) the phase place adjustment of finishing local lock-out pulse, reach the purpose with signal Synchronization, realize simple.
3, this method is utilized the characteristic of SS+PR control word in the up-link of PHS base station and is designed, but because method itself is by the screening to the data self character, make this method in whole communication process, to work always, further guaranteed tracking accuracy, avoided owing to the too short synchronous effect that influences of SS+PR control.
4, the related control signal of this method oneself is produced by it, and sequential cooperates upward simple than the method that generally is controlled by other signals again.
5, the hardware realization is convenient in the design of this method very much, and it is little to take resource.
In a word, adopt method provided by the invention and realization, not only improve the synchronization accuracy of PHS base station up-link, and simple in structure, very be convenient to hardware and realize that model can expand in other communication systems that adopt the QPSK modulation system.
Claims (7)
1, a kind of PHS system bits method for synchronous based on digital phase-locked loop, recover synchronised clock by phase-locked loop, it is characterized in that, utilize the constant modulus property of data sync point in the system, provide synchronizing datum signal by quadratic sum computing and zero passage detection, utilize this synchronous base to carry out bit synchronization.
2, the described PHS system bits method for synchronous based on digital phase-locked loop of claim 1 is characterized in that, describedly provides synchronizing datum signal by quadratic sum computing and zero passage detection, is meant:
2.1 at first calculate process
Two-way orthogonal signalling I, the quadratic sum S=I of Q of modulation and formed filter output
2+ Q
2
2.2 the quadratic sum signal of trying to achieve subtracted each other every R sampled point obtains signal D
n=S
N+R-S
n
2.3 to subtracting each other D as a result
nDo zero passage detection, its zero crossing is carried out mark, obtain synchronizing datum signal.
3, the described PHS system bits method for synchronous based on digital phase-locked loop of claim 2 is characterized in that the described bit synchronization benchmark that utilizes carries out bit synchronization, is meant:
3.1 produce local lock-out pulse, this pulse frequency and character rate are consistent;
3.2 whether current zero crossing be can be used for synchronous base is judged: push away before the zero crossing place
Individual sampled point, when
Handle with follow-up described step during greater than the thresholding G that sets, and synchronous enabled flag F is changed to effectively; Otherwise, keep the constant clock cycle, the number that presets that is about to be used to produce the counter of local lock-out pulse is put back its initial value, and enable flag F is changed to invalid, and jumps to step 2.1;
3.3 control two counter C1, C2 jointly with zero crossing and local lock-out pulse, finish the loop filtering effect, wherein, count to C2 the next zero crossing by the lock-out pulse rising edge at zero crossing C1 counting between the next local lock-out pulse rising edge;
3.4 adding up its count value at each zero crossing place is N=C1-C2;
3.5 when synchronous enabled flag F is effective, calculate the initial value that presets counter according to the positive and negative and order of magnitude of N value at each zero crossing place:
(
Expression rounds downwards); Tn presets the counter initial value for what need to upgrade in the formula, and M is a constant;
3.6 when the synchronous enabled flag F described in the step 3.2 is effective, preserves accumulative total by following formula and differ:
Accumulative total differs when this marked invalid:
3.7 synchronization delayed time is compensated, provides lock-out pulse.
4, the described PHS system bits method for synchronous of claim 3 based on digital phase-locked loop, it is characterized in that, the method that produces local lock-out pulse in the described step 3.1 is: can preset several counters by one and produce, arrive high level that width is a clock cycle of output after the maximum of its setting when count value.
5, the described PHS system bits method for synchronous based on digital phase-locked loop of claim 3 is characterized in that the M in the described step 3.5 chooses 2 integral number power.
6, a kind of bit synchronous device of realizing based on digital phase-locked loop of PHS system comprises: adder and multiplier (21), synchronous base generator (22), local clock-pulse generator (23), digital loop filters (24), method of synchronization decision device (25), phase error register (26) and synchronization delayed time compensator (27);
Described adder and multiplier (21) is responsible for calculating the quadratic sum of the up I of PHS base station system, Q two-way cosine filter output signal;
Described synchronous base generator (22) is slided window with the output of described adder and multiplier (21) and is subtracted each other, and again the zero crossing that subtracts each other the result is carried out mark, and with this signal as synchronization basic standard;
Described local clock-pulse generator (23) arrives on the counting in count value and prescribes a time limit, the high level of a clock cycle of output; Also as the control signal of the counting initial value of itself packing into new, counter begins counting from new counting initial value in the back at this signal to this output signal from high to low simultaneously;
Described loop filter (24) is responsible for phase error estimation and phase error;
Described method of synchronization decision device (25) is according to the operating state that the comparative result of quadratic sum signal amplitude and default thresholding is decided method for synchronous, and synchronous enabled flag F is effective when surpassing thresholding; Otherwise flag F is invalid;
Described phase error register (26) is right at each zero crossing place, and the phase error N that described loop filter (24) is estimated adds up by following formula
In the formula,
Represent downward round numbers, choose less M value when being effective,, when F is invalid, choose bigger M value, the reduction synchronizing speed to accelerate synchronizing speed when flag F;
Described synchronization delayed time compensator (27) is used for compensating whole synchronous caused time delay; The output of this compensator is the lock-out pulse of this synchronizer output; By this lock-out pulse I, Q two paths of data are extracted data after can obtaining synchronously.
7, the described realization of claim 6 is based on the bit synchronous device of PHS system of digital phase-locked loop, it is characterized in that, described synchronous base generator (22) comprises sliding window subtraction device (221) and zero-crossing detector (222), wherein, sliding window subtraction device (21) is slided window to the output of described adder and multiplier (21) and is subtracted each other, and zero-crossing detector (222) carries out mark to the zero crossing that subtracts each other the result; Described loop filter (24) comprises forward counter (241) and anti-phase counter (242), and wherein, forward counter (241) is used for writing down from the nearest zero crossing of local lock-out pulse to the working pulse number between this lock-out pulse; Backward counter (242) is used for writing down lock-out pulse to the working pulse number between its nearest zero crossing; Described method of synchronization decision device (25) comprises threshold compataror (251) and synchro switch controller (252), wherein, threshold compataror (251) compares quadratic sum signal amplitude and thresholding, and whether the synchro switch controller is to having effective according to comparative result to synchronous usage flag; Described phase error register (26) further comprises shift register (261) and accumulator (262), finishes the phase error that described loop filter (24) is estimated jointly and adds up.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101043259B (en) * | 2007-03-09 | 2010-05-19 | 武汉虹信通信技术有限责任公司 | Self-adapting method for little smart PHS RF signal enhancement equipment to synchronize PHS base station |
| CN101290655B (en) * | 2007-04-17 | 2010-05-26 | 中兴通讯股份有限公司 | Digital communication system bit synchronization restoration method and device |
| CN102164031A (en) * | 2011-03-16 | 2011-08-24 | 华为技术有限公司 | Link clock recovery method and device |
| CN101911493B (en) * | 2008-01-04 | 2013-06-05 | 高通股份有限公司 | Digital phase-locked loop with gated time-to-digital converter |
| CN106059975A (en) * | 2016-07-11 | 2016-10-26 | 天津中兴智联科技有限公司 | New method for inhibiting carrier synchronization and costas ring |
| CN110850151A (en) * | 2019-11-04 | 2020-02-28 | 易事特集团股份有限公司 | Zero-crossing determination method and zero-crossing determination device |
| CN110991609A (en) * | 2019-11-27 | 2020-04-10 | 天津大学 | Line buffer for improving data transmission efficiency |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2853491B2 (en) * | 1992-12-07 | 1999-02-03 | 株式会社村田製作所 | DQPSK delay detection circuit |
| US6016331A (en) * | 1997-08-05 | 2000-01-18 | Vlsi Technology, Inc. | Methods of synchronization, personal handy-phone system stations and phase lock loops |
| JP4178668B2 (en) * | 1999-06-18 | 2008-11-12 | 株式会社富士通ゼネラル | Digital demodulator |
| CN1329410A (en) * | 2001-01-18 | 2002-01-02 | 深圳市中兴集成电路设计有限责任公司 | Small region search method in code division multiple address communication system |
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2004
- 2004-03-25 CN CNB2004100320114A patent/CN1312875C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101043259B (en) * | 2007-03-09 | 2010-05-19 | 武汉虹信通信技术有限责任公司 | Self-adapting method for little smart PHS RF signal enhancement equipment to synchronize PHS base station |
| CN101290655B (en) * | 2007-04-17 | 2010-05-26 | 中兴通讯股份有限公司 | Digital communication system bit synchronization restoration method and device |
| CN101911493B (en) * | 2008-01-04 | 2013-06-05 | 高通股份有限公司 | Digital phase-locked loop with gated time-to-digital converter |
| CN102164031A (en) * | 2011-03-16 | 2011-08-24 | 华为技术有限公司 | Link clock recovery method and device |
| CN106059975A (en) * | 2016-07-11 | 2016-10-26 | 天津中兴智联科技有限公司 | New method for inhibiting carrier synchronization and costas ring |
| CN106059975B (en) * | 2016-07-11 | 2020-06-23 | 天津中兴智联科技有限公司 | Novel method for inhibiting carrier synchronization and costas ring |
| CN110850151A (en) * | 2019-11-04 | 2020-02-28 | 易事特集团股份有限公司 | Zero-crossing determination method and zero-crossing determination device |
| CN110850151B (en) * | 2019-11-04 | 2022-04-12 | 易事特集团股份有限公司 | Zero-crossing determination method and zero-crossing determination device |
| CN110991609A (en) * | 2019-11-27 | 2020-04-10 | 天津大学 | Line buffer for improving data transmission efficiency |
| CN110991609B (en) * | 2019-11-27 | 2023-12-26 | 天津大学 | Line buffer for data transmission |
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