CN1062392C - Synchro detection circuit - Google Patents
Synchro detection circuit Download PDFInfo
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- CN1062392C CN1062392C CN95118769A CN95118769A CN1062392C CN 1062392 C CN1062392 C CN 1062392C CN 95118769 A CN95118769 A CN 95118769A CN 95118769 A CN95118769 A CN 95118769A CN 1062392 C CN1062392 C CN 1062392C
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0032—Correction of carrier offset at baseband and passband
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0036—Correction of carrier offset using a recovered symbol clock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0046—Open loops
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0053—Closed loops
- H04L2027/0055—Closed loops single phase
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Abstract
A phase comparing means 1 obtains a momentary phase signal by comparing the phase of a generated carrier signal asynchronous with an input PSK-modulated signal with that of the input PSK-modulated signal and a clock regenerating means 6 regenerates and supplies a clock signal synchronized with the input PSK-modulated signal to respective parts. The momentary phase signal from the phase comparing means is supplied to carrier frequency difference component removing means 3-5 to remove error components corresponding to the carrier frequency difference between the transmitter and receiver, and phase shift component removing means 8-10 remove phase difference components from the phase reference axis of the receiver. Then data regenerating means 11 and 12 regenerate sent data on the basis of the momentary phase signal after at least the error components corresponding to the carrier frequency difference between the transmitter and receiver and the phase shift components from the phase reference axis of the receiver are removed.
Description
The present invention relates to the synchro detection circuit of psk modulation signal, for example relate to the synchro detection circuit of the detecting circuit that can be applied to pi/4 shift qpsk modulation signal and qpsk modulation signal.
Automobile telephone system and portable telephone system as the microcellulor mode have begun to turn to digital form from analog form, in addition, are that the personal handhold telephone system (below, abbreviate the PHS system as) of prerequisite also will begin utilization with the digital form.
The present invention is conceived to the detecting circuit in this digital mobile body communication system, the detecting circuit in the digital mobile body communication system that particularly is conceived to use under the decay environment of low speed relatively.For example, as the detection mode of this PHS system, the variety of way of being delivered as association all is to postpone the detection mode to the receiving system of PHS system usually under the decay environment that compares low speed.
But in radio communication, always to use very little transmitting power to prolong propagation distance as far as possible as purpose, therefore, just beginning one's study to adopt receives sensitivity characteristics in general than postponing the good synchronous detection mode (referring to document 1～4) of detection mode.
Document 1: " electronic intelligence Communications Society conference in autumn in 1993, B-300, "-プ Application Le-プ type detection same period mode " "
Document 2: " electronic intelligence Communications Society conference in autumn in 1992, B-241, " π/4 シ Off are foretold QPSK synchronous detection mode and examined " "
Document 3: " nineteen ninety national congress in autumn of electronic intelligence Communications Society, B-169, " land moving body satellite communication To is fitted the new same period of polyphony mode " "
Document 4: " letter is learned skill newspaper, DS94-18, RCS94-9 (1994-05), " パ-ソ Na Le communication low consumption electrification polyphony device LSI-high-performance detection same period polyphony device " "
In general, the synchronous detection mode under the decay environment of low speed relatively receiving sensitivity than postponing detection mode good (desirable C/N (signal to noise ratio) is little).But, because synchro detection circuit is than postponing the detecting circuit complexity, so, be difficult to realize that integrated (IC) changes and cheap, in addition, in synchro detection circuit, need carry out carrier regeneration, in general, owing to utilize feedback loop to come the regenerated carrier signal signal, so, exist high speed motion problem to burst.
The synchro detection circuit that above-mentioned document 1 and document 2 are put down in writing; be by using delay detection mode that temporary transient extraction the out through prediction processing of data component formed carrier signal; do not utilize the feedback loop just can the regenerated carrier signal signal; but; owing to utilized the delay detection mode of error ratio characteristic difference, so the precision of carrier regeneration reduces; the circuit that also needs protection simultaneously also differs and realizes miniaturization surely.
The synchro detection circuit that above-mentioned document 3 is put down in writing also is not utilize that feedback loop just can the regenerated carrier signal signal, still, owing to utilize double loop (feed-forward loop) to come the regenerated carrier signal signal, and so the revived structure complexity maximizes easily.
The synchro detection circuit that above-mentioned document 4 is put down in writing is to utilize by the carrier signal of feedback loop regeneration to carry out synchronous detection basically, when initial the introducing, is to think the application delay detection, so, the problem that exists structure to maximize easily.
Therefore, purpose of the present invention is exactly the wave detector at the digital mobile communication system of using under the decay environment of low speed relatively, and providing can high speed motion and can realize the high synchro detection circuit of practicality of miniaturization and ICization for burst.
In order to address this problem, in the present invention, the synchro detection circuit that psk modulation signal is carried out detection has following structural element (a)～(f) at least.
That is, synchro detection circuit of the present invention has (a) carrier generator, (b) phase comparator, (c) clock regenerator, (d) carrier frequency difference composition stripper, (e) phase deviation composition stripper and (f) data repeater at least.Carrier generator is used to take place the psk modulation signal carrier signal asynchronous with input; Phase comparator be used for will input psk modulation signal compare with carrier signal from the output of above-mentioned carrier generator, obtaining with the carrier signal is the instantaneous phase signal of psk modulation signal of input of benchmark; Clock regenerator is used to regenerate and the psk modulation signal clock signal synchronous of importing, and supplies with each several part; Carrier frequency difference composition stripper is used for the difference on the frequency corresponding error percentage of filtering from the carrier signal between the instantaneous phase signal of phase comparator output and the transceiver; Phase deviation composition stripper is used for the phase deviation composition of filtering from instantaneous phase signal and phase reference axle receiver of phase comparator output; Data repeater be used for according to filtering at least with transceiver between the corresponding error percentage of the difference on the frequency of carrier signal and with the phase deviation composition of the phase reference axle of receiver after instantaneous phase signal, regeneration sends data.
In synchro detection circuit of the present invention, the carrier signal that phase comparator carrier generator and the psk modulation signal of input takes place asynchronously and the psk modulation signal of input carry out bit comparison mutually, obtaining with the carrier signal is the instantaneous phase signal of P SK modulation signal of input of benchmark, in addition, clock regenerator regeneration and the psk modulation signal clock signal synchronous of importing, and supply with each several part.From the instantaneous phase signal of phase comparator output utilize carrier frequency difference composition stripper remove with transceiver between the corresponding error percentage of difference on the frequency, in addition, utilize phase deviation composition stripper to remove phase deviation composition with the phase reference axle of receiver.And, data repeater according to transceiver between the corresponding error percentage of the difference on the frequency of carrier signal and removed phase deviation composition with the phase reference axle of receiver at least after instantaneous phase signal regeneration transmission data.
Fig. 1 is the structured flowchart of embodiment.
Fig. 2 is the key diagram of the action and the output of phase comparator 1.
Fig. 3 be the error percentage that causes about carrier frequency difference key diagram (one of).
Fig. 4 is the key diagram of the input and output of π/4 backward shift position circuit 7.
Fig. 5 is the key diagram of the average necessity of phase deviation average circuit 8.
Fig. 6 is the block diagram of the detailed structure example of expression phase comparator 1.
Fig. 7 is the block diagram of the dual moving average filter of its inside.
Fig. 8 is the key diagram (two) of the error percentage that causes about carrier frequency difference.
Fig. 9 is the block diagram of the detailed structure example of expression difference on the frequency test section 4.
Figure 10 is the block diagram of the detailed structure example of expression clock regeneration portion 6.
Figure 11 be clock regeneration portion 6 action specification figure (one of).
Figure 12 is the action specification figure (two) of clock regeneration portion 6.
Below, detailed description is applicable to an embodiment of the synchro detection circuit of pi/4 shift qpsk modulation signal with reference to accompanying drawing.
Present embodiment is an object with the pi/4 shift qpsk modulation signal of deferring to so-called relative phase coded system.That is be object, with 2 intersymbol phase differences pi/4 shift qpsk modulation signal corresponding with sending data.(A-1) general structure of embodiment
Fig. 1 is the general structure block diagram of the synchro detection circuit of present embodiment.
In Fig. 1, the pi/4 shift qpsk modulation signal of input is supplied with phase comparator 1.In addition, the carrier signal of carrier generator 2 generations is also imported this phase comparator 1.Carrier generator 2 takes place with the pi/4 shift QP SK modulation signal of input asynchronous, but is the carrier signal of same frequency (being same frequency on the principle) substantially.The phase difference variable of 2 signals that phase comparator 1 will be imported changes the value that changes in per 2 π intervals linear shown in Fig. 2 (C) (no matter be digital value or direct voltage can) into.In other words, phase comparator 1 is the instantaneous phase of pi/4 shift qpsk modulation signal that detects with the carrier signal input that is benchmark.Instantaneous phase signal input delay arithmetic unit 3 and difference on the frequency filtering portion 5 from phase comparator 1 output.
In general synchronous detection mode, carrier generator is made of the PLL circuit, the phase locked carrier signal of pi/4 shift qpsk modulation signal with input takes place, but, in the present embodiment, for the simplification of structure and the high speed introducing of burst, adopted the pi/4 shift qpsk modulation signal carrier signal asynchronous that takes place with input.
Here, a certain symbol is with respect to the phase place of the carrier signal of transmitting end, can use according to by the phase component that sends the Q PSK modulation system that symbol string determines with to the accumulated value of π/4 of each symbol shifting function and represent.Also can consider by mould with respect to 2 π.
As everyone knows, according to by the phase component that sends the QPSK modulation system that symbol string determines by the modular representation with respect to 2 π be 0, pi/2, π, 3 pi/2s, so, a certain symbol is in the instantaneous phase of transmitting end, in order to carry out Ji/4 shifting functions, be taken as 0, π/4, pi/2,3 π/4, π, 5 π/4,3 pi/2s, 7 π/4.
In the present embodiment, owing to adopt the pi/4 shift qpsk modulation signal carrier signal asynchronous that takes place with input, so input modulating signal has the phase difference α of appointment with respect to carrier signal.In addition, when carrier frequency had difference between transceiver, then each symbol all produced the phase error β corresponding with this difference on the frequency.Therefore, the phase place of a certain symbol from the instantaneous phase signal of phase comparator 1 output is exactly the accumulation composition of adding phase difference α and phase error β in the instantaneous phase of transmitting end.
Postponing arithmetic unit 3, difference on the frequency test section 4 and difference on the frequency filtering portion 5 is for according to the carrier frequency difference between the transceiver from the instantaneous phase signal of phase comparator 1 output, removes the phase error composition and is provided with.
Postpone arithmetic unit 3 and detect from 2 intersymbol phase differences of the instantaneous phase signal of phase comparator 1 output, and incoming frequency difference test section 4 and difference on the frequency filtering portion 5.The output signal that postpones arithmetic unit 3 is that 2 intersymbol phase differences, π/4 according to the phase component of QPSK modulation system reach the phase error β sum during per 1 symbol that is caused by carrier frequency difference, if the phase error β that is caused by carrier frequency difference does not use the modular representation with respect to 2 π then to be taken as π/4,3 π/4,5 π/4,7 π.
If utilizing, difference on the frequency test section 4 do not have phase error β, the output signal that postpones arithmetic unit 3 just is taken as the fact of π/4,3 π/4,5 π/4,7 π/4, obtain with the carrier frequency difference between the transceiver is the phase error β of each symbol of basis, and to asking average back output (after, also represent mean value) during several symbols～dozens of symbol with β.
Calculating is accumulated to the phase error β of each symbol by difference on the frequency filtering portion 5, and by from the instantaneous phase signal of phase comparator 1, deducting this cumulative addition value, and, remove the phase error composition according to the carrier frequency difference between the transceiver that from the instantaneous phase signal of phase comparator 1 output, comprises.In addition, the instantaneous phase signal of phase comparator 1 output suitably can be postponed back incoming frequency difference filtering portion 5, also can not postpone and incoming frequency difference filtering portion 5.
In general synchronous detection mode, the carrier generator of receiving terminal is made of the PLL circuit, owing to take place and the phase locked carrier signal of input modulating signal, so the frequency of carrier signal and the input modulating signal carrier signal of transmitting terminal (thereby with) are consistent.But, in the present embodiment, owing to the generator of having used generation and input signal carrier signal asynchronous as carrier generator 2, so, the filtering structure of the above-mentioned error percentage of needs.
Fig. 3 utilizes the phase reference axle (I axle and Q axle) of virtual receiver one side to show symbol configuration in the instantaneous phase signal of phase comparator 1.Symbol configuration in the instantaneous phase signal of phase comparator 1, with transceiver between the corresponding direction of the difference on the frequency polarity of carrier signal on, the phase mass that each rotation of each symbol is corresponding with this frequency extent, because the accumulative effect of this rotation also can make it close to other character positions from original character position.Therefore, the error percentage that must the rejection frequency difference causes.
The error percentage β corresponding with the carrier frequency difference between the transceiver is in the output signal that postpones arithmetic unit 3, as mentioned above, fixing phase deviation as 1 symbolic unit shows, so, difference on the frequency test section 4 asks average by the error percentage that will obtain according to the output signal that postpones arithmetic unit 3 during to several symbols～dozens of symbol, can detect the phase error β corresponding with the difference on the frequency of having removed noise effect, thereby, just can utilize difference on the frequency filtering portion 5 that the difference on the frequency error percentage is removed.
Therefore, in the instantaneous phase signal stage of difference on the frequency filtering portion 5, the difference on the frequency of the carrier signal of input modulating signal and this synchro detection circuit is " 0 ", and the apparent carrier signal that goes up this synchro detection circuit is carried out automatic frequency control with respect to input modulating signal.
The output signal that postpones arithmetic unit 3 also flows to clock regeneration portion 6.If clock regeneration portion 6 is output signals of utilize postponing arithmetic unit 3 are original true regenerated clock signals that just are taken as π/4,3 π/4,5 π/4,7 π/4.The clock signal of regeneration is to the output of the outside of this synchro detection circuit, simultaneously, in the inside of this synchronous circuit, is defeated by the later each several part treatment circuit of difference on the frequency test section 4.In addition, be defeated by with clock signal as action at the synchronous high signal of frequency ratio carrier signal of carrier generator 2 inner that form and carrier signal and postpone arithmetic unit 3 and clock reproducing unit 6 etc.
Because in the output signal that postpones arithmetic unit 3, comprising the phase error composition β during per 1 symbol that causes by carrier frequency difference, so, the method (constituting other embodiment of the present invention) of being defeated by clock regeneration portion 6 after in addition the detection composition of difference on the frequency test section 4 being removed from the output signal that postpones arithmetic unit 3.But present embodiment is considered the high speed tracing property to burst, does not adopt such method.
π/4 backward shift position circuit 7 are by the circuit of 1 symbolic unit towards direction displacement π/4 phase places opposite with transmitter one side with respect to the instantaneous phase signal of difference on the frequency filtering portion 5.As everyone knows, in pi/4 shift QPSK modulation system, in transmitter one side, by per 1 symbol displacement π/4 phase places, π/4 backward shift position circuit 7 carry out its anti-operation independently in the phase deviation that causes with symbol code.Therefore, the instantaneous phase signal of π/4 backward shift position circuit 7 is just comprising the phase deviation composition that caused by symbol code and the information of the phase deviation α between input modulating signal and carrier signal, becomes the demodulation instantaneous phase signal in the QPSK modulation system just.The instantaneous phase signal of π/4 backward shift position circuit 7 is defeated by phase deviation average circuit 8 and memory circuitry 9.
Fig. 4 is by the symbol configuration of the virtual phase reference axle (I axle and Q axle) of receiver one side in the input signal of π/4 backward shift position circuit 7 and the output signal.As shown in Figure 4, the configuration of symbol in the output signal of π/4 backward shift position circuit 7 is to be shifted respectively differing between some phase place of pi/2, as mentioned above, becomes the restituted signal of QPSK modulation system just.
8 pairs of phase deviation average circuits carry out the modular arithmetic of pi/2 according to the instantaneous phase signal from the QPSK modulation system of π/4 backward shift position circuit, 7 outputs, promptly, ask the remainder that removes the output signal of π/4 backward shift position circuit 7 with pi/2, and this result of calculation asked average to the intersymbol designated duration of several symbol～dozens ofs, then, ask the pi/2 in the phase deviation α with input modulating signal and carrier signal integral multiple phase place depart from △ α, and to difference channel 10 outputs.
Memory circuit 9 is exported to difference channel 10 after departing from the instantaneous phase signal phase retardation of deferring to the QPSK modulation system of π/4 backward shift position circuit 7 outputs during average circuit 8 average.
After the output signal that difference channel 10 departs from phase average circuit 8 deducts from the instantaneous phase signal of deferring to the QPSK modulation system by memory circuit 9, be defeated by instantaneous phase and determine circuit 11.Therefore, the instantaneous phase signal of difference channel 10 just becomes the instantaneous phase signal on the phase reference axle (I axle and Q axle) of receiver one side.The instantaneous phase signal of this difference channel 10 is along the phase reference axle (I axle and Q axle) of receiver one side, but, do not limit along the phase reference axle of transmitter one side, from the phase reference axle of transmitter one side, might have 0, the departing from of pi/2, π or 3 pi/2s.
The instantaneous phase signal of π/4 backward shift position circuit 7 since as carrier generator 2 used with influence such as the asynchronous mode of input modulating signal might be inconsistent with the phase reference axle of receiver one side, so, can not carry out the phase place judgement for the instantaneous phase signal of π/4 backward shift position circuit 7.Therefore, the instantaneous phase signal of π/4 backward shift position circuit 7 must be modified to along the phase reference axle of receiver one side.
Shown in above-mentioned Fig. 4 (b), if abideing by the instantaneous phase signal of the QPSK modulation system of π/4 backward shift position circuit 7 is original at its phase place judging point, just with respect to the phase reference axle (I axle and Q axle) of receiver one side get 0, some in the pi/2, π, these 4 phase places of 3 pi/2s, but, if depart from phase place △ α with respect to this phase reference axle, then the instantaneous phase signal of π/4 backward shift position circuit 7 is got some in 0+ △ π, pi/2+△ α, these 4 phase places of π+△ α, 3 pi/2s+△ α at its phase place judging point with respect to the phase reference axle.Therefore, if the output signal of π/4 backward shift position circuit 7 is carried out the mould calculating of pi/2, just can obtain phase deviation composition △ α.
Fig. 5 represents the relation of the output signal of received electric field strength and π/4 backward shift position circuit 7.As shown in Figure 5, when receiving the electric field reduction, because the influence of receiver noise, the output signal of π/4 backward shift position circuit 7 will depart from above-mentioned 4 phase places 0, pi/2, π, 3 pi/2s in the phase place of phase place judging point.But, because the noise effect of regular distribution is deferred in the distribution of this phase deviation, so, become regular distribution, if ask average, then its value will become the phase reference axle basically.Therefore, phase deviation average circuit 8 is exactly that the phase deviation (△ α) that will above-mentioned 1 computing obtains is asked on average the intersymbol designated duration of several symbol～dozens ofs, so that the no received electric field strength of the acquisition phase deviation △ α with phase reference axle receiver one side that influence.
Remove from the instantaneous phase signal of the π/4 backward shift position circuit 7 by memory circuit 9 by the phase deviation △ α that will obtain like this by difference channel 10, on apparent, just can utilize the carrier signal of passing through phase control to obtain deferring to the instantaneous phase signal of the QPSK modulation system of passing through phase detection.That is, used the carrier signal of controlling automatically by the phase place of input modulating signal (staying the phase difference composition of the phase reference between centers between the transceiver).
Instantaneous phase determines that instantaneous phase signal that 11 pairs in circuit carries out the difference channel 10 of frequency correction and phase deviation correction carries out last phase place and judges, and its judged result is defeated by calculus of differences circuit 12.That is, judge that instantaneous phase at the phase place judging point is 0, in the pi/2, π, these 4 phase places of 3 pi/2s which, and with its judged result input difference computing circuit 12.
Calculus of differences circuit 12 is according to being determined that by instantaneous phase the difference of the phase place judged result of 2 symbols in 11 pairs of front and back of circuit carries out the inverse operation in the code of a side conversion of posting a letter (2 bit data), is transformed to behind the regular serial data as the output of this synchro detection circuit to launch.Instantaneous phase is determined the instantaneous phase during the output signal of circuit 11 is illustrated in this symbol, but, the situation of present embodiment is a prerequisite with the relative phase coded system, determine variable quantity to the instantaneous phase of next symbol according to the value that sends data, the instantaneous phase difference during 2 symbols is corresponding with the transmission data.Therefore, calculus of differences circuit 12 is according to being determined that by instantaneous phase the difference of the phase place judged result of 2 symbols in 11 pairs of front and back of circuit obtains data value and output.
Therefore, in the present embodiment, between transceiver, even also playback of data correctly of phase difference is arranged between the phase reference axle.(A-2) details of phase comparator 1
In phase comparator 1, input modulating signal is input to an input of "or" else circuit 22, and the carrier signal of 1/m frequency divider 21 is imported another input.After "or" else circuit 22 obtains the exclusive logic of these signals and signal (after, be called the 1st phase difference reflected signal), in the dual moving average filter 25 that input is moved by former oscillator signal.In addition, input modulating signal is input to an input of "or" else circuit 23, imports another input by the carrier signal of pi/2 phase shifter 24 after with the carrier signal phase shift pi/2 of 1/m frequency dividing circuit 21."or" else circuit 23 is imported dual moving average filter 26 after obtaining the exclusive logic of these signals and signal (after, be called the 2nd phase difference reflected signal).
It is corresponding with the phase difference of input modulating signal and carrier signal that the 1st phase difference reflected signal is got the ratio and cycle of " 1 " (inconsistent) or " 0 " (unanimity), the phase difference that the 2nd phase difference reflected signal is got the carrier signal behind the ratio of " 1 " (inconsistent) or " 0 " (unanimity) and cycle and input modulating signal and the phase shift pi/2 is corresponding, thereby corresponding with the phase difference of input modulating signal and carrier signal.
Dual moving average filter 25 is asked the moving average of the 1st phase difference reflected signal, and dual moving average filter 26 is asked the moving average of the 2nd phase difference reflected signal, has low-frequency filter characteristics respectively.
Relation shown in Fig. 2 (a) is arranged between the rolling average signal of dual moving average filter 25 and the phase difference.For example, the phase difference of supposing input modulating signal and carrier signal is 0, and then the 1st phase difference reflected signal of "or" else circuit 22 is " 0 " continuously, and its moving average just is 0; If the phase difference of input modulating signal and carrier signal is π, then the 1st phase difference reflected signal is " 1 " continuously, and its moving average just becomes maximum (if making " 1 " is 1, then becoming p); If the phase difference of input modulating signal and carrier signal is between between the two above-mentioned, then moving average is got the value between 0 and the maximum corresponding with its middle phase difference.As a result, by the phase characteristic of the input modulating signal of the function of "or" else circuit 22 and dual moving average filter 25 decision shown in Fig. 2 (a).On the other hand, because the 2nd phase difference reflected signal is being benchmark with the signal behind the carrier signal phase shift pi/2, so, the relation shown in Fig. 2 (b) is arranged between the rolling average signal of dual moving average filter 26 and the phase difference.
In Fig. 2, transverse axis is represented the phase difference (instantaneous phase) of input modulating signal and carrier signal.The moving average that the Fig. 2 (a) and the longitudinal axis (b) are represented to export (to the instantaneous phase of the modular representation of 2 π).
The rolling average signal input Polarity Control logical circuit 27 of each dual moving average filter 25,26.Logical circuit 27 is (bigger than central value according to the polarity of the rolling average signal of a dual moving average filter (being 26 here), be positive polarity, littler than central value, be negative polarity) determine to make the polarity of another dual moving average filter (being 25) not anti-phase or anti-phase here, the output signal of this logical circuit 27 is shown in Fig. 2 (c),-π～π, π～3 π, 3 π～5 π ... in 2 π scopes, phase place presents the characteristic of available straight-line detection.This output signal represents that the carrier signal with input modulating signal is the phase difference (instantaneous phase) of benchmark, as the output signal (instantaneous phase signal) of this phase comparator 1 and send.
Can application examples structure (referring to the fair 1-45097 communique of spy) as shown in Figure 7 as dual moving average filter 25 and 26.
Utilize the oscillator signal of former oscillator 20 to read in the shift register 30-1 from the phase difference reflected signal of "or" else circuit 22 or 23 outputs, the phase difference reflected signal that takes out from the previous stage of afterbody utilizes oscillator signal to read in the shift register 30-2.The progression of each shift register 30-1,30-2 (p+1) is selected by the following method.If the frequency of the oscillator signal of former oscillator 20 is f1, selected needed rolling average time τ makes p satisfy (1) formula.In other words, the value of rolling average is supplied with in storage before the selected p level, and afterbody is only stored the value above the rolling average time.
τ=p/f1…(1)
The value input logic circuit 31-1 of the elementary and afterbody of shift register 30-1 compares by the timing of oscillator signal.The value of up-down counter 32-1 becomes and is carved into moving average in the fixed time τ till moment before the designated duration from now.When elementary value was consistent with the value of afterbody (value of afterbody is not reflected in the middle of the moving average), logical circuit 31-1 just made moving average not change, thus the count value of inoperation up-down counter 32-1; When elementary value is " 1 ", when the value of afterbody is " 0 ", moving average is increased, thereby make upwards counting of up-down counter 32-1; When elementary value is " 0 ", when the value of afterbody is " 1 ", moving average is reduced, thereby up-down counter 32-1 is counted downwards.
The shift register 30-2 of another group, logical circuit 31-2 and up-down counter 32-2 equally also obtain the moving average of designated duration τ.But,, supply with this difference of selecting during the fixed time τ existence before this of moving average according to the above.
Register 35 is stored last moving average, and exports as the rolling average signal from lead-out terminal.Add circuit 33 is with the moving average of up-down counter 32-1 and the last moving average addition of register 35, and subtraction circuit 34 subtracts each other the moving average of up-down counter 32-2 and the last moving average of register 35.That is, being stored in last moving averages in the register 35 is to comprise present moment in the moving average of designated duration τ before the interior present moment and the revised one by one numerical value of difference of the moving average of the designated duration τ before with it.By after above-mentioned such processing, moving average just is reflected in the rolling average signal doubly.(A-3) details of difference on the frequency test section 4
Below, describe an example of difference on the frequency test section 4 in detail with reference to Fig. 8 and Fig. 9.
If carrier frequency does not have difference between transceiver, the output signal (delay rectified signal) that then postpones arithmetic unit 3 the moment Tn that the eyelet of eye pattern is opened maximumly get 3 π/4, π/4 ,-some phase places in π/4 ,-3 π/4.Here, carrier frequency has difference between transceiver, the frequency height of a side if post a letter, then eye pattern is shown in Fig. 8 (a), upwards departed from the stationary phase β corresponding than original eye pattern with its difference on the frequency, on the contrary, if the frequency of the side of posting a letter is low, then eye pattern is shown in Fig. 8 (b), than original eye pattern downward bias from the stationary phase β corresponding with its difference on the frequency.
For example, if the difference on the frequency of 5kHz is arranged, per 1 symbol departs from 10 degree, if the difference on the frequency of 10kHz is arranged, per 1 symbol departs from 20 degree, promptly departs from the stationary phase corresponding with the frequency extent.
Therefore, moment Tn at the regenerated clock signal of clock regeneration portion 6, extract the value of the output signal (instantaneous rectified signal) that postpones arithmetic unit 3 out, 4 value 3 π/4 that occur when frequency is consistent between transceiver, π/4 ,-immediate value in π/4 ,-3 π/4 compares, obtain both poor, and ask average several times back to extract out this difference as the difference on the frequency detection signal.
Can use internal structure shown in Figure 9 as difference on the frequency test section 4 with this function.Register 45 reads in the value of the output signal that postpones arithmetic unit 3 at moment Tn, by each difference channel 46 ..., 49 ask respectively this value and each fiducial value generating unit 41 ..., 44 fiducial value 3 π/4, π/4 ,-difference of π/4 ,-3 π/4, again by each absolute value circuit 50 ..., 53 be transformed to absolute value.Minimum value testing circuit 54 detects minimum numerical value from these difference absolute value after, to select control signal input selector 55, by selector 55 from the value of the output signal that postpones arithmetic unit 3 and fiducial value 3 π/4, π/4 ,-select the difference value of minimum the difference value of π/4 ,-3 π/4, and, obtain after the moving average as difference on the frequency signal incoming frequency difference filtering portion 5 with selected difference value input multidigit moving average filter 56.(A-4) details of clock regeneration portion 6
Below, with reference to an example (speciallyying permit out hope PCT/JP/01904 specification and accompanying drawing) of accompanying drawing detailed description clock regeneration portion 6 with reference to the world.
Clock regeneration portion 6 is used for regenerated clock signal, so that can carry out symbol decision at the open moment Tn of the eyelet of eye pattern, can use various structures, as an example, can enumerate structure shown in Figure 10.
Clock regeneration portion 6 by clock regeneration with signal generating circuit 61 and digital phase locked loop (after, abbreviate DPL L as) 62 formations, clock regeneration is extracted the clock regeneration signal out with signal generating circuit 61 from the output signal that postpones arithmetic unit 3, DPLL62 carries out the PLL action, so that the phase place of clock signal is consistent with signal with clock regeneration.
Use in the signal generator 61 at clock regeneration, transient pulse takes place respectively in each magnitude comparator 71,73 when detection level (detecting axle) by being set by the electric level predeterming circuit 72,74 of correspondence of the delay rectified signal of input, and timer 75 and timing control circuit 77 are defeated by in the pulse that takes place.Here, electric level predeterming circuit 72 set with the value of the delay rectified signal of 2 intersymbol phase differences of expression (after, be called phase difference) corresponding level 1 conduct detection level, another electric level predeterming circuit 74 is set the level corresponding with the phase difference pi/2 0 as detecting level (with reference to the described Figure 12 in back).
Timer 75 postpones rectified signal and picks up counting when detecting the pulse of level or reset or count value is imported decision circuitry 76 detecting from 71,72 inputs of each magnitude comparator, decision circuitry 76 is according to the output of this timer 75, calculate the variation track that postpones rectified signal, and form the timing adjustment signal of being defeated by timing control circuit 77.Timing control circuit 77 is adjusted signal according to the timing of decision circuitry 76, in the moment of pulse from each magnitude comparator 71,72 input, is taking place through the moment of fixed time as regeneration with the pulse (phase signal) of signal and import DPLL62.
Like this, clock regeneration portion 6 sets 2 and detects level, calculate by these two moment of detecting level postponing rectified signals along which type of track walks according to postponing rectified signal, in DPLL62, be presented on clock regeneration easily and the mode of the moment of carrying out well output pulse.Which type of track promptly allows to calculate is, because can not be in the moment output pulse of reviewing in the past, so, adopt a kind of like this method, the track sorting circuit 78 that promptly is made of timer 75 and decision circuitry 76 is calculated track in the past, and classifies, according to this categorizing selection output clock regeneration with the time before the pulse, timing control circuit 77 is selected according to this, the pulse that the output clock regeneration is used.
In fact, the start-up portion of burst signal is the preamble figure that occurs " 1001 " repeatedly, is " UW " of expression data header then, is data subject afterwards.Clock regeneration portion 6 must make the phase place of clock signal consistent with the phase place of input modulating signal during transmission preamble figure.
Figure 11 and Figure 12 are respectively the illustrations that this track of explanation is calculated and clock regeneration is adjusted with the output time of pulse.Time T is 1 symbol time (being equivalent to 360), and time T d for example is equivalent to for 150 time, and time t0 is for example to be equivalent to for 60 time.
In Figure 11, detect sequence number 1 expression detect postpone the pulse of rectified signal by level 0 (after, be called level 0 cross pulse) behind the input trajectory sorting circuit 78, at the appointed time in the Td, detect postpone the pulse of rectified signal by level 1 (after, be called level 1 cross pulse) situation of input trajectory sorting circuit 78, at this moment, track sorting circuit 78 (decision circuitry 76) is controlled timing control circuit 77, so that begin the pulse used to the moment output clock regeneration of elapsed time t0+T/2 from moment of incoming level 0 cross pulse.
After detection sequence number 2 is illustrated in level 1 cross pulse input trajectory sorting circuit 78, at the appointed time Td is with the situation of interior level 0 cross pulse input trajectory sorting circuit 78, at this moment, track sorting circuit 78 (decision circuitry 6) is also controlled timing control circuit 77, so that begin to export the pulse that clock regeneration is used to the moment of elapsed time t0+T/2 from the moment that level 1 cross pulse is imported.
After detection sequence number 3 is illustrated in level 1 cross pulse input trajectory sorting circuit 78, at the appointed time Td is with the situation of interior level 0 cross pulse end input trajectory sorting circuit 78, at this moment, track sorting circuit 78 (decision circuitry 76) is controlled timing control circuit 77, so that begin to export the pulse that clock regeneration is used to the moment of elapsed time T/2 from the moment that level 1 cross pulse is imported.
In Figure 12 (a) with the track shown in the thick line be in " 1001101 ... " preamble during track.Shown in Figure 12 (a), during preamble, behind level 0 cross pulse (moment 1) the input trajectory sorting circuit 78, at the appointed time in the Td, level 1 cross pulse (moment 2) input trajectory sorting circuit 78, so track sorting circuit 78 is adjusted signal incoming timing control circuit 77 with the timing corresponding with detecting sequence number 1.That is, shown in Figure 12 (b), from constantly 1 beginning to the moment of elapsed time t0+T/2, the pulse that clock regenerations are used takes place in control timing control circuit 77.Behind above-mentioned level 1 cross pulse (moment 2) the input trajectory sorting circuit 78,,, timing control circuit 77 is not carried out any control yet so at this moment timer 75 resets because the pulse of initial input is same level 1 cross pulse (moment 4).In addition, behind level 1 cross pulse (moment 4) input trajectory sorting circuit 78, because at the appointed time in the Td, level 0 cross pulse (moment 5) input trajectory sorting circuit 78, so track sorting circuit 78 is adjusted signal incoming timing control circuit 77 with the timing corresponding with detecting sequence number 2.That is, the pulse that clock regenerations are used so that from 4 moment 6 that begin to elapsed time t0+T/2 of the moment, takes place by timing control circuit 77 in controlling like that shown in Figure 12 (b).
After, equally during preamble, track sorting circuit 78 applying detection sequence numbers 1 and detect the timing adjustment of sequence number 2, shown in Figure 12 (b) like that, the pulse of using from timing control circuit 77 output clock regenerations in the moment that eyelet opens maximumly.As a result, just shown in Figure 12 (c), from the correct clock signals of DPLL62 generation with this impulsive synchronization.
During preamble, finish, enter UW and data subject during the time because bit pattern is fixing, so a certain delay rectified signal of getting in whole 16 kinds of tracks is input to clock regeneration with in the signal generating circuit 61.Above-mentioned detection sequence number 1 and to detect sequence number 2 are tracks of having considered especially during the preamble still, also can get during UW and data subject and detect sequence number 1 and detect the relevant track of sequence number 2.Corresponding during the track relevant and UW and the data subject with detecting sequence number 3, also can suitably utilize the timing adjustment of this detection sequence number 3.
For not elaborating during UW and the data subject, but, exported half of whole 16 kind tracks from clock regeneration with signal generating circuit 61 with signal according to the clock regeneration of the timing adjustment that detects sequence number 1～3,1/2 interior (4 kinds/8 kinds) of this pulse comprise having the pulse (not being correct phase angle) of beating.
But, when receiving the preamble graphic model, be defeated by DPLL62 owing to can 100% ground extract the pulse that the clock regeneration of not beating uses out, thereby can read in rapidly from the phase place of the clock signal of DPLL62 output with correct phase angle, so, import DPLL62 with pulse with 1/2 probability even after this have the clock regeneration of beating, also be enough to make regenerated clock signal to follow the tracks of input signal.(A-5) action of embodiment
Below, the action of embodiment is described.
In Fig. 1, the pi/4 shift qpsk modulation signal of input carries out phase detection by carrying out bit comparison mutually with the carrier signal that carrier generator 2 takes place as described above by phase comparator 1, is transformed into the carrier signal instantaneous phase signal of the pi/4 shift qpsk modulation signal that is benchmark.
2 intersymbol difference being obtained this instantaneous phase signal by delay arithmetic unit 3 are 2 intersymbol phase change.After these 2 the intersymbol phase signal input clock reproducing units 6, regenerated clock signal as described above.In addition, behind 2 intersymbol phase signal incoming frequency difference test sections 4, by this difference on the frequency test section 4 extract out with transceiver between the corresponding composition of difference of carrier frequency, then, remove this difference on the frequency composition that is included in the instantaneous phase signal by difference on the frequency filtering portion 5.
Removed with transceiver between the instantaneous phase signal of the corresponding composition of the difference of carrier frequency, by π/4 backward shift position circuit 7 towards with opposite direction phase shift π/4 of direction of displacement of π/4 of transmitting end, like this, just be transformed to the instantaneous phase signal of deferring to common QPSK modulation system, that is, be transformed to the instantaneous phase signal of getting the some phase places in original 0, pi/2, π, 3 pi/2s with respect to the phase reference axle of receiver one side.
If the phase reference axle with respect to receiver one side is original phase signal, then, obtain the phase deviation of instantaneous phase signal to the phase reference axle of receiver one side by this phase average circuit 8 according to the instantaneous phase signal input phase average circuit 8 of the QPS K modulation system of getting designated phase.Therefore, if with respect to the phase reference axle that was undertaken by memory circuitry 9 regularly adjusting is original phase signal, just from the instantaneous phase signal of getting designated phase, remove the phase deviation composition that this signal has by difference channel 10, be transformed to defer to respect to the phase reference axle of receiver one side get 0, the instantaneous phase signal of the QPSK modulation system of the some phase places in the pi/2, π, 3 pi/2s.
In the moment (phase place judging point) that the eyelet of this instantaneous phase signal opens maximumly, determine the phase place of circuit 11 definite these instantaneous phase signals by instantaneous phase, then, obtain 2 intersymbol definite phase differences by calculus of differences circuit 12, the code string (serial data) that to send and transmit of regenerating to external circuit.(A-6) effect of embodiment
If employing the foregoing description, because the detecting circuit of pi/4 shift qpsk modulation signal adopts the synchronous detection mode, so, compare with delay detection mode, even transmitting power or receiver noise index are identical, also receiving sensitivity can be improved number dB, thereby can prolong propagation distance.
In addition, if adopt present embodiment, because carrier generator adopts the form that does not have feedback loop, so, can make simple in structurely, simultaneously, when the input burst, there is not the problem of tracing property yet.Although carrier generator has been used the form that does not have feedback loop, owing to be provided with the structure of the difference that compensates the carrier frequency between transceiver and make the structure synchronous with input modulating signal, so, can not reduce the detection precision.
In addition, if adopt present embodiment, as shown in the above description, all structural elements can be realized digitlization, so, realize ICization and miniaturization easily.For the situation that is loaded into the detecting circuit on the mobile terminal device, the meaning of this effect is very big.
Owing to can obtain above effect, so the practicality of the synchro detection circuit of present embodiment is very high.(B) other embodiment
In the above-described embodiments, provide be according to the removing of difference on the frequency, π/4 backward shift positions and phase deviation remove this in sequence, still, also can change this order.For example, can carry out π/4 backward shift positions after removing phase deviation, at this moment, phase deviation average circuit 8 can not carry out modular arithmetic to pi/2, and carries out the modular arithmetic to π/4 in inside yet.
In addition, in the above-described embodiments, the modulation system that provides is a pi/4 shift PSK modulation system, still, the invention is not restricted to this, go for the synchro detection circuit of various PSK modulation systems such as BPSK modulation system, QPSK modulation system, 8 phase PSK modulation systems and compensation QPSK modulation system.For example, if the synchro detection circuit corresponding with the QPSK modulation system then can omit the π/4 backward shift position circuit 7 among Fig. 1.
The suitable devices of synchro detection circuit of the present invention is not limited to mobile terminal apparatus, can be various receiving systems, all, transmission line also is not limited to wireless.
As mentioned above, if employing the present invention, owing to have the carrier generator that takes place with input psk modulation signal carrier signal asynchronous, acquisition is the phase comparator of instantaneous phase signal of the input psk modulation signal of benchmark with the carrier signal, regeneration and the clock regenerator of importing the psk modulation signal clock signal synchronous, remove in the instantaneous phase signal of phase comparator with transceiver between the carrier frequency difference composition stripper of the corresponding error percentage of the difference on the frequency of carrier signal, remove in the instantaneous phase signal of phase comparator with the phase deviation composition stripper of the phase deviation composition of the phase reference axle of receiver with according to the data repeater of the instantaneous phase signal playback of data of having removed various error percentages, so, the synchro detection circuit that can improve the detection precision and can realize miniaturization and ICization can be provided.
Claims (3)
1. synchro detection circuit is characterised in that: have carrier generator, phase comparator, clock regenerator, clock frequency difference composition stripper, phase deviation composition stripper and data repeater at least, carrier generator is used to take place the psk modulation signal carrier signal asynchronous with input;
Phase comparator be used for will input psk modulation signal compare with carrier signal from the output of above-mentioned carrier generator, and to obtain with the carrier signal be the instantaneous phase signal of the psk modulation signal of benchmark;
Clock regenerator is used to regenerate and the psk modulation signal clock signal synchronous of importing, and supplies with each several part;
Carrier frequency difference composition stripper, by postponing arithmetic unit, the difference on the frequency detector be configured in the instantaneous phase signal of the above-mentioned phase comparator of filtering with transceiver between the corresponding error percentage of difference on the frequency of carrier signal;
Phase deviation composition stripper, by π/4 backward shift position circuit, memory, difference channel and phase deviation average circuit constitute, and are used for the instantaneous phase signal of the above-mentioned phase comparator of filtering and the phase deviation composition of the phase reference axle of receiver;
Data repeater, determine circuit by instantaneous phase, the calculus of differences circuit constitutes, be used for according to removed at least with transceiver between the corresponding error percentage of the difference on the frequency of carrier signal and the instantaneous phase signal of the phase deviation composition of the phase reference axle of receiver, regeneration sends data.
2. by the described synchro detection circuit of claim 1, it is characterized in that: above-mentioned clock regenerator is according to the output signal regenerated clock signal of above-mentioned delay arithmetic unit.
3. by claim 1,2 described synchro detection circuits, it is characterized in that: phase deviation composition stripper is made of phase deviation circuit, delayer and difference channel, and the phase deviation circuit is used to obtain the modular arithmetic result's at the corresponding designated phase angle of the instantaneous phase signal with this phase deviation composition stripper of input during a plurality of symbols mean value;
Delayer be used for will this phase component stripper of input instantaneous phase signal postpone an above-mentioned phase deviation average circuit of confession average handle usefulness during;
Difference channel is used for deducting from the output signal of this delayer the output signal of above-mentioned phase deviation average circuit.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27652494A JP3390272B2 (en) | 1994-11-10 | 1994-11-10 | Synchronous detection circuit |
| JP276524/1994 | 1994-11-10 | ||
| JP276524/94 | 1994-11-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1128433A CN1128433A (en) | 1996-08-07 |
| CN1062392C true CN1062392C (en) | 2001-02-21 |
Family
ID=17570680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95118769A Expired - Fee Related CN1062392C (en) | 1994-11-10 | 1995-11-07 | Synchro detection circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5574399A (en) |
| JP (1) | JP3390272B2 (en) |
| CN (1) | CN1062392C (en) |
| GB (1) | GB2295071B (en) |
| SG (1) | SG52178A1 (en) |
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| JPH09266499A (en) * | 1996-01-26 | 1997-10-07 | Oki Electric Ind Co Ltd | Digital demodulating circuit, maximum detecting circuit, and reception device |
| JPH09219693A (en) * | 1996-02-09 | 1997-08-19 | Mitsubishi Electric Corp | Digital broadcast receiver |
| US5892797A (en) * | 1996-07-17 | 1999-04-06 | Jay Deng | System and method for recovering data encoded using manchester code and other bi-phase level codes |
| JPH1093646A (en) * | 1996-09-12 | 1998-04-10 | Pacific Commun Res:Kk | Digital orthogonal detector circuit |
| US5960040A (en) * | 1996-12-05 | 1999-09-28 | Raytheon Company | Communication signal processors and methods |
| JP3088359B2 (en) * | 1997-09-30 | 2000-09-18 | 埼玉日本電気株式会社 | π / 4 shift DQPSK digital demodulator |
| FI105751B (en) * | 1998-05-29 | 2000-09-29 | Nokia Networks Oy | demodulation |
| FI106502B (en) * | 1998-05-29 | 2001-02-15 | Nokia Networks Oy | Symbol synchronization method |
| FI106501B (en) * | 1998-05-29 | 2001-02-15 | Nokia Networks Oy | Method and system for detecting carrier frequency |
| DE69927957T2 (en) * | 1999-01-06 | 2006-07-27 | Koninklijke Philips Electronics N.V. | Demodulator with rotation means for frequency offset correction |
| KR100333704B1 (en) * | 1999-06-21 | 2002-04-24 | 박종섭 | modified circuit of decision region for phase rotation error caused by phase noise |
| US6606357B1 (en) | 1999-09-10 | 2003-08-12 | Harris Corporation | Carrier injecting waveform-based modulation scheme for reducing satellite transponder power requirements and earth terminal antenna size |
| US20010031023A1 (en) * | 1999-10-28 | 2001-10-18 | Kin Mun Lye | Method and apparatus for generating pulses from phase shift keying analog waveforms |
| US8385476B2 (en) | 2001-04-25 | 2013-02-26 | Texas Instruments Incorporated | Digital phase locked loop |
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| US7075948B2 (en) * | 2002-05-22 | 2006-07-11 | Stmicroelectronics, Inc. | Frequency offset estimator |
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| US7336705B2 (en) * | 2003-03-18 | 2008-02-26 | Microsoft Corporation | Smart receiver for wireless peripherals |
| JP4306515B2 (en) * | 2003-08-29 | 2009-08-05 | 株式会社デンソー | Synchronous detection method and apparatus |
| US7428273B2 (en) * | 2003-09-18 | 2008-09-23 | Promptu Systems Corporation | Method and apparatus for efficient preamble detection in digital data receivers |
| JP2005210330A (en) * | 2004-01-21 | 2005-08-04 | Nec Compound Semiconductor Devices Ltd | Binary fsk modulated wave data generation circuit and method |
| CN101040437B (en) * | 2004-10-13 | 2010-05-12 | 联发科技股份有限公司 | Filters for communication systems and filtering method thereof |
| US20060078068A1 (en) * | 2004-10-13 | 2006-04-13 | Aiguo Yan | Methods and apparatus for wireless communication |
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| SG126808A1 (en) * | 2005-05-05 | 2006-11-29 | Oki Techno Ct Singapore Pte | Frequency offset estimation for dpsk |
| CN1968235B (en) * | 2005-11-15 | 2010-05-05 | 凌阳科技股份有限公司 | Preorder detection and symbol time sequence recovery system and method |
| SG133422A1 (en) * | 2005-12-14 | 2007-07-30 | Oki Techno Ct Singapore Pte | A system and method for estimating phase offset in a communication system |
| US9094266B2 (en) * | 2013-05-03 | 2015-07-28 | Gilat Satellite Networks Ltd. | Efficient de-spreading |
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- 1995-10-30 US US08/544,977 patent/US5574399A/en not_active Expired - Lifetime
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- 1995-11-07 CN CN95118769A patent/CN1062392C/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| GB2295071A (en) | 1996-05-15 |
| US5574399A (en) | 1996-11-12 |
| JP3390272B2 (en) | 2003-03-24 |
| JPH08139778A (en) | 1996-05-31 |
| CN1128433A (en) | 1996-08-07 |
| SG52178A1 (en) | 1998-09-28 |
| GB9522046D0 (en) | 1996-01-03 |
| GB2295071B (en) | 1998-12-02 |
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