CN101290655B - Digital communication system bit synchronization restoration method and device - Google Patents
Digital communication system bit synchronization restoration method and device Download PDFInfo
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Abstract
The invention discloses a method and a device for restoring bit synchronization of a digital communication system. The invention makes the best test of signals in advance by utilizing the matched filtering principle and reduces influences of noises or disturbance on bit synchronization property; moreover, a synchronous judgment process and a corresponding implementation module are introduced in asynchronous loop; based on present integral results of a noninverting integrator module and a cross integrator module, whether the synchronization is realized at the moment is judged; when the judgment is that the synchronization is realized, bit synchronous signals are not subject to phasing adjustment; when the judgment is that the synchronization is not realized, bit synchronous signals are allowed to take phasing adjustment; based on pre-pulse signals and lagging pulse signals, phases of bit synchronous signals are adjusted, thereby effectively limiting the oscillation caused by the lagging of the loop feedback during the tracking process.
Description
Technical field
The present invention relates to digital communication technology field, relate in particular to a kind of bit synchronization restoration method and device of digital communication system.
Background technology
In radio-frequency recognition system, in order to realize base band demodulating, reader need extract bit synchronization from received signal, and the bit synchronization error has very big influence to the base band demodulating performance.In the radio-frequency recognition system, generally adopt asynchronous communication means, require reader in several signal periods, to set up bit synchronization rapidly.On the other hand, owing to reasons such as label itself and environmental factors, the frequency jitter scope of baseband signal is bigger, about the tag reflection signal errors of ISO18000-6 (comprising Type A, Type B and Type C) regulation is generally.Bit synchronous Time Created and synchronization bandwidth all are inversely proportional to regulating step-length, and this two aspect all needs the synchronous device of reader to have bigger bit synchronization adjusting step-length.Find that by emulation and practice because the hysteresis quality of feedback regulation, bit synchronizer is adjusted under the bigger situation of step-length in bit synchronization producing vibration in the tracing process synchronously, can cause the bit synchronization strategy fails, correctly demodulation of signal.
Summary of the invention
The present invention proposes a kind of bit synchronization restoration method and device of digital communication system, can solve bit synchronization adjusts under the bigger situation of step-length, because the hysteresis quality of Bit-synchronous Circle feedback regulation, in tracing process, vibrate easily, cause synchronization policy to lose efficacy, signal is the problem of demodulation correctly.
For this reason, the present invention takes following technical scheme:
A kind of bit synchronization restoration method of digital communication system may further comprise the steps:
A, noninverting integrator module and orthogonal integration device module are carried out respectively with phase integral and orthogonal integration the baseband signal of input simultaneously;
B, first sampling keep module that described noninverting integrator module integral result is sampled and polarity is judged maintenance, and second sampling keeps module that described orthogonal integration device module integral result is sampled and polarity is judged maintenance; Wherein, first sampling keeps module to sample before described noninverting integrator module integral result is eliminated and polarity is judged maintenance, and remain to next sampling maintenance constantly; Second sampling keeps module to sample before described orthogonal integration device module integral result is eliminated and polarity is judged maintenance, and remain to next sampling maintenance constantly;
C, synchronization decisions module judge according to the integral result of described noninverting integrator module and described orthogonal integration device module whether the baseband signal of bit synchronization signal and input has realized synchronously, and the output synchronous indicating signal;
D, lead and lag pulse generator module keep module and described second sampling to keep the output of module and the synchronous indicating signal of described synchronization decisions module output to judge the phase relation of the baseband signal of current time bit synchronization signal and input according to described first sampling, and send phase adjustment signal; Wherein, the phase adjustment signal of described lead and lag pulse generator module output prepulsing if described bit synchronization signal phase place is leading, if described bit synchronization signal lags behind then the phase adjustment signal of described lead and lag pulse generator module lag output pulse, when the synchronous indicating signal of synchronization decisions module output when realizing bit synchronization, output phase adjustment signal not then;
E, phase regulator module are adjusted the bit synchronization signal phase place according to the phase adjustment signal of described lead and lag pulse generator module output;
F, described bit synchronization signal are controlled the integral result of described noninverting integrator module and are removed, and the orthogonal signal of described bit synchronization signal are controlled the integral result of described orthogonal integration device module and removed, and form the dynamic feedback loop.
Further, said method also can comprise: among the step C, when the absolute value of the integral result of described noninverting integrator module during greater than pre-set threshold, described synchronization decisions module judges that the baseband signal of bit synchronization signal and input has realized synchronously.
Further, said method also can comprise: among the step C, when the absolute value of the integral result of described orthogonal integration device during less than pre-set threshold, described synchronization decisions module judges that the baseband signal of bit synchronization signal and input has realized synchronously.
Further, said method also can comprise: among the step C, when the absolute value of the integral result of described noninverting integrator than the absolute value of the integral result of last orthogonal integration device during greater than pre-set threshold, described synchronization decisions module judges that the baseband signal of bit synchronization signal and input has realized synchronously.
Further, said method also can comprise: among the step D, when the synchronous indicating signal of described synchronization decisions module output when being unrealized bit synchronization, keep module and described second sampling to keep the sampling maintenance result of module to judge phase relation between the baseband signal of described bit synchronization signal and described input by described first sampling.
Further, said method also can comprise: in the step e, when described phase regulator module was received the prepulsing signal, one of bit synchronization signal phase lag was regulated step-length, when described phase regulator module was received the hysteresis pulse signal, the bit synchronization signal phase place was put forward previous adjusting step-length.
Further, said method also can comprise: in the step F, the orthogonal signal of described bit synchronization signal postpone half synchronizing cycle by described bit synchronization signal and obtain.
A kind of bit synchronization restoration device of digital communication system comprises that noninverting integrator module, orthogonal integration device module, first sampling keep module, second sampling to keep module, synchronization decisions module, lead and lag pulse generator module, phase regulator module and bit synchronization signal control module; Wherein,
Described noninverting integrator module is used for the baseband signal of input is carried out with phase integral and integral result is issued described first sampling keeping module and described synchronization decisions module;
Described orthogonal integration device module is used for the baseband signal of input is carried out orthogonal integration and integral result is issued described second sampling keeping module and described synchronization decisions module;
Described first sampling keeps module, is used for the integral result of described noninverting integrator module is sampled and polarity judgement maintenance; Wherein, described first sampling keeps module to sample before described noninverting integrator module integral result is eliminated and polarity is judged maintenance, and remains to next sampling maintenance constantly;
Described second sampling keeps module, is used for the integral result of described orthogonal integration device module is sampled and polarity judgement maintenance; Wherein, described second sampling keeps module to sample before described orthogonal integration device module integral result is eliminated and polarity is judged maintenance, and remains to next sampling maintenance constantly;
Described synchronization decisions module, whether the baseband signal that is used to judge bit synchronization signal and input has realized synchronously and has exported synchronous indicating signal and give described lead and lag pulse generator module;
Described lead and lag pulse generator module, be used for keeping module and described second sampling to keep the output of module and the synchronous indicating signal of described synchronization decisions module output to judge the phase relation of the baseband signal of current bit synchronization signal and input, and send phase adjustment signal according to described first sampling; Wherein, the phase adjustment signal of described lead and lag pulse generator module output prepulsing if described bit synchronization signal phase place is leading, if described bit synchronization signal lags behind then the phase adjustment signal of described lead and lag pulse generator module lag output pulse, when the synchronous indicating signal of synchronization decisions module output when realizing bit synchronization, output phase adjustment signal not then;
Described phase regulator module is used to receive the output of described lead and lag pulse generator module, and the bit synchronization signal phase place is adjusted;
Described bit synchronization signal control module is used to control the integral result removing of described noninverting integrator module, and the integral result removing of controlling described orthogonal integration device module, forms the dynamic feedback loop.
Further, said apparatus also can comprise: described device also comprises Postponement module; Wherein,
Described Postponement module is used for described bit synchronization signal is postponed half synchronizing cycle and obtains the orthogonal signal of described bit synchronization signal.
Adopt technical scheme of the present invention, had following beneficial effect:
1, utilizes the matched filtering principle in advance signal to be carried out optimum detection, can farthest reduce the influence of noise or interference contraposition net synchronization capability;
2, introduce synchronization decisions process and realize module accordingly in the synchronous feedback loop on the throne, when judgement for realizing when synchronous, no longer the phase place of bit synchronization signal is adjusted, the oscillatory occurences that has effectively suppressed loop also can obtain good synchronous effect in the adjusted in concert step-length during bigger or little signal to noise ratio (S/N ratio);
3, owing under the prerequisite that guarantees net synchronization capability, can use bigger adjusted in concert step-length,, reduced bit synchronization and caught the needed time, can set up bit synchronization more rapidly with less that the adjusted in concert step-length is compared;
4, by under the prerequisite that guarantees net synchronization capability, can use bigger adjusted in concert step-length, thereby increase the synchronization bandwidth of system, make system can adapt to the wider frequency jitter of baseband signal, improve the adaptive faculty of system;
5, can utilize hardware or software mode to realize, have bigger dirigibility, and realize integratedly easily, reduce cost of products.
Description of drawings
Fig. 1 is the structural scheme of mechanism of bit synchronization recovery device in this embodiment;
Fig. 2 is the process flow diagram of bit synchronization restoration in this embodiment;
Fig. 3 is the signal timing diagram of noninverting integrator module, orthogonal integration device module and sampling retainer module;
Fig. 4 is when not adopting this method, and the design sketch of loop oscillation takes place in the bit synchronization tracing process;
Fig. 5 adopts this method, to the inhibition design sketch of loop oscillation.
Embodiment
Below in conjunction with accompanying drawing, and technical scheme of the present invention is described further by embodiment.
The present invention utilizes the matched filtering principle in advance signal to be carried out optimum detection, farthest reduce the influence of noise or interference contraposition net synchronization capability, and in synchronization loop, introduce synchronization decisions process and the corresponding module that realizes, integral result according to current noninverting integrator module and orthogonal integration device module, judge whether current time has been realized synchronously, realize when synchronous when being judged as, bit synchronization signal does not carry out the phase place adjustment, when judged result is synchronous for being unrealized, allow bit synchronization signal to carry out the phase place adjustment, according to the phase place of prepulsing signal and hysteresis pulse signal adjustment bit synchronization signal.
Fig. 1 is the structural scheme of mechanism of bit synchronization recovery device in this embodiment.As shown in Figure 1, the bit synchronization restoration device comprises noninverting integrator module 101, orthogonal integration device module 102, first sampling keeps module 103, second sampling keeps module 104, synchronization decisions module 105, lead and lag pulse generator module 106, phase regulator module 107 and Postponement module 108, the baseband signal of 101 pairs of inputs of noninverting integrator module carries out with phase integral and integral result is issued first sampling keeping module 103 and synchronization decisions module 105, orthogonal integration device module 102 is used for the baseband signal of input is carried out orthogonal integration and integral result is issued second sampling keeping module 104 and synchronization decisions module 105, first sampling keeps the module 103 and second sampling to keep module 104 to be respectively applied for the integral result of noninverting integrator module 101 and orthogonal integration device module 102 is sampled and polarity is judged and kept, synchronization decisions module 105 judges whether the baseband signal of bit synchronization signal and input has realized synchronously and export synchronous indicating signal and give lead and lag pulse generator module 106, lead and lag pulse generator module 106 keeps the module 103 and second sampling to keep the sampling of module 104 to keep the synchronous indicating signal of result and 105 outputs of synchronization decisions module to judge the phase relation of the baseband signal of bit synchronization signal and input according to first sampling, phase regulator module 107 is used to receive the prepulsing or the hysteresis pulse of the output of lead and lag pulse generator module 106, and the bit synchronization signal phase place adjusted, 108 pairs of bit synchronization signals of Postponement module postpone to obtain the orthogonal signal of bit synchronization signal, the integral result of bit synchronization signal control noninverting integrator module 101 is removed, and the integral result of orthogonal signal control orthogonal integration device module 102 is removed.
Fig. 2 is the process flow diagram of bit synchronization restoration in this embodiment.As shown in Figure 2, bit synchronization restoration may further comprise the steps:
Step 201, noninverting integrator module and orthogonal integration device module are carried out with phase integral and orthogonal integration respectively the baseband signal of input simultaneously.
Step 202, first sampling keep module to sample before noninverting integrator module integral result is eliminated and polarity is judged maintenance, and remain to next sampling maintenance constantly, second sampling keeps module to sample before orthogonal integration device module integral result is eliminated and polarity is judged maintenance, and remain to next sampling maintenance constantly.
Step 203, synchronization decisions module are according to the integral result of noninverting integrator module and orthogonal integration device module, whether the baseband signal of judging bit synchronization signal and input has realized bit synchronization, and the output synchronous indicating signal, synchronous indicating signal comprises realizes bit synchronization signal and the bit synchronization signal of being unrealized.
Judging whether in this step to have realized synchronously can be according to one of following condition, or wherein combination arbitrarily: a) absolute value of the integral result of noninverting integrator module is greater than a certain fixing or dynamic threshold, b) absolute value of the integral result of orthogonal integration device is less than a certain fixing or dynamic threshold, and c) absolute value of the integral result of noninverting integrator is fixed or dynamic threshold greater than a certain than the absolute value of the integral result of last orthogonal integration device.
Step 204, when the synchronous indicating signal of synchronization decisions module output when being unrealized bit synchronization, keep the module and second sampling to keep the sampling of module to keep the result to judge phase relation between the baseband signal of bit synchronization signal and input by first sampling, the phase adjustment signal of lead and lag pulse generator module output prepulsing if the bit synchronization signal phase place is leading, the phase adjustment signal of lead and lag pulse generator module lag output pulse if bit synchronization signal lags behind, when the synchronous indicating signal of synchronization decisions module output when realizing bit synchronization, output phase adjustment signal not then.
Step 205, when the phase regulator module is received the prepulsing signal, one of bit synchronization signal phase lag is regulated step-length, when the phase regulator module was received the hysteresis pulse signal, the bit synchronization signal phase place was put forward previous adjusting step-length.
Step 206, bit synchronization signal postpone half synchronizing cycle to obtain the orthogonal signal of bit synchronization signal, the integral result of bit synchronization signal control noninverting integrator module is removed, the integral result of the orthogonal signal control orthogonal integration device module of bit synchronization signal is removed, and forms the dynamic feedback loop.
The signal sequence of noninverting integrator module, orthogonal integration device module and sampling retainer module as shown in Figure 3.
The design sketch of loop oscillation takes place when not adopting this method in Fig. 4 in the bit synchronization tracing process.After synchronous some Time Created, bit synchronization signal since the accurate edge of locking signal of loop oscillation swing at ideal position.Fig. 5 is for adopting this method, to the inhibition design sketch of loop oscillation.After putting Time Created synchronously, bit synchronization signal is the locking signal edge accurately, realizes synchronously.
This embodiment has been utilized the matched filtering principle, at first signal is carried out optimum detection, has reduced and has disturbed bit synchronous influence.And introduce synchronous judgment mechanism, no longer the phase place of bit synchronization signal is adjusted when having obtained bit synchronization judging, thereby eliminated because the hysteresis quality of Bit-synchronous Circle feedback regulation, the oscillatory occurences that takes place in tracing process synchronously.
The present invention can be applicable to the bit synchronization restoration of electronic tag to reader signal, also can be applied to the digital communication system that other needs bit synchronization restoration.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and those skilled in the art is in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the definition of claim.
Claims (9)
1. the bit synchronization restoration method of a digital communication system is characterized in that, may further comprise the steps:
A, noninverting integrator module and orthogonal integration device module are carried out respectively with phase integral and orthogonal integration the baseband signal of input simultaneously;
B, first sampling keep module that described noninverting integrator module integral result is sampled and polarity is judged maintenance, and second sampling keeps module that described orthogonal integration device module integral result is sampled and polarity is judged maintenance; Wherein, first sampling keeps module to sample before described noninverting integrator module integral result is eliminated and polarity is judged maintenance, and remain to next sampling maintenance constantly; Second sampling keeps module to sample before described orthogonal integration device module integral result is eliminated and polarity is judged maintenance, and remain to next sampling maintenance constantly;
C, synchronization decisions module judge according to the integral result of described noninverting integrator module and described orthogonal integration device module whether the baseband signal of bit synchronization signal and input has realized synchronously, and the output synchronous indicating signal;
D, lead and lag pulse generator module keep module and described second sampling to keep the output of module and the synchronous indicating signal of described synchronization decisions module output to judge the phase relation of the baseband signal of current time bit synchronization signal and input according to described first sampling, and send phase adjustment signal; Wherein, the phase adjustment signal of described lead and lag pulse generator module output prepulsing if described bit synchronization signal phase place is leading, if described bit synchronization signal lags behind then the phase adjustment signal of described lead and lag pulse generator module lag output pulse, when the synchronous indicating signal of synchronization decisions module output when realizing bit synchronization, output phase adjustment signal not then;
E, phase regulator module are adjusted the bit synchronization signal phase place according to the phase adjustment signal of described lead and lag pulse generator module output;
F, described bit synchronization signal are controlled the integral result of described noninverting integrator module and are removed, and the orthogonal signal of described bit synchronization signal are controlled the integral result of described orthogonal integration device module and removed, and form the dynamic feedback loop.
2. the bit synchronization restoration method of a kind of digital communication system according to claim 1, it is characterized in that, among the step C, when the absolute value of the integral result of described noninverting integrator module during greater than pre-set threshold, described synchronization decisions module judges that the baseband signal of bit synchronization signal and input has realized synchronously.
3. the bit synchronization restoration method of a kind of digital communication system according to claim 1, it is characterized in that, among the step C, when the absolute value of the integral result of described orthogonal integration device during less than pre-set threshold, described synchronization decisions module judges that the baseband signal of bit synchronization signal and input has realized synchronously.
4. the bit synchronization restoration method of a kind of digital communication system according to claim 1, it is characterized in that, among the step C, when the absolute value of the integral result of described noninverting integrator than the absolute value of the integral result of last orthogonal integration device during greater than pre-set threshold, described synchronization decisions module judges that the baseband signal of bit synchronization signal and input has realized synchronously.
5. the bit synchronization restoration method of a kind of digital communication system according to claim 1, it is characterized in that, among the step D, when the synchronous indicating signal of described synchronization decisions module output when being unrealized bit synchronization, keep module and described second sampling to keep the sampling maintenance result of module to judge phase relation between the baseband signal of described bit synchronization signal and described input by described first sampling.
6. the bit synchronization restoration method of a kind of digital communication system according to claim 1, it is characterized in that, in the step e, when described phase regulator module is received the prepulsing signal, one of bit synchronization signal phase lag is regulated step-length, when described phase regulator module was received the hysteresis pulse signal, the bit synchronization signal phase place was put forward previous adjusting step-length.
7. the bit synchronization restoration method of a kind of digital communication system according to claim 1 is characterized in that, in the step F, the orthogonal signal of described bit synchronization signal postpone half synchronizing cycle by described bit synchronization signal and obtain.
8. the bit synchronization restoration device of a digital communication system, it is characterized in that, comprise that noninverting integrator module, orthogonal integration device module, first sampling keep module, second sampling to keep module, synchronization decisions module, lead and lag pulse generator module, phase regulator module and bit synchronization signal control module; Wherein,
Described noninverting integrator module is used for the baseband signal of input is carried out with phase integral and integral result is issued described first sampling keeping module and described synchronization decisions module;
Described orthogonal integration device module is used for the baseband signal of input is carried out orthogonal integration and integral result is issued described second sampling keeping module and described synchronization decisions module;
Described first sampling keeps module, is used for the integral result of described noninverting integrator module is sampled and polarity judgement maintenance; Wherein, described first sampling keeps module to sample before described noninverting integrator module integral result is eliminated and polarity is judged maintenance, and remains to next sampling maintenance constantly;
Described second sampling keeps module, is used for the integral result of described orthogonal integration device module is sampled and polarity judgement maintenance; Wherein, described second sampling keeps module to sample before described orthogonal integration device module integral result is eliminated and polarity is judged maintenance, and remains to next sampling maintenance constantly;
Described synchronization decisions module, whether the baseband signal that is used to judge bit synchronization signal and input has realized synchronously and has exported synchronous indicating signal and give described lead and lag pulse generator module;
Described lead and lag pulse generator module, be used for keeping module and described second sampling to keep the output of module and the synchronous indicating signal of described synchronization decisions module output to judge the phase relation of the baseband signal of current time bit synchronization signal and input, and send phase adjustment signal according to described first sampling; Wherein, the phase adjustment signal of described lead and lag pulse generator module output prepulsing if described bit synchronization signal phase place is leading, if described bit synchronization signal lags behind then the phase adjustment signal of described lead and lag pulse generator module lag output pulse, when the synchronous indicating signal of synchronization decisions module output when realizing bit synchronization, output phase adjustment signal not then;
Described phase regulator module is used to receive the output of described lead and lag pulse generator module, and the bit synchronization signal phase place is adjusted;
Described bit synchronization signal control module is used to control the integral result removing of described noninverting integrator module, and the integral result removing of controlling described orthogonal integration device module, forms the dynamic feedback loop.
9. the bit synchronization restoration device of a kind of digital communication system as claimed in claim 8 is characterized in that, also comprises Postponement module; Wherein,
Described Postponement module is used for described bit synchronization signal is postponed half synchronizing cycle and obtains the orthogonal signal of described bit synchronization signal.
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| CN1556603A (en) * | 2004-01-05 | 2004-12-22 | 中兴通讯股份有限公司 | PHS system position synchronous method based on digital lock phase ring and realizing device |
| CN1825471A (en) * | 2005-02-04 | 2006-08-30 | 因芬尼昂技术股份公司 | Synchronization and data recovery device |
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| CN1556603A (en) * | 2004-01-05 | 2004-12-22 | 中兴通讯股份有限公司 | PHS system position synchronous method based on digital lock phase ring and realizing device |
| CN1825471A (en) * | 2005-02-04 | 2006-08-30 | 因芬尼昂技术股份公司 | Synchronization and data recovery device |
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