CN1539113A - 层次集成电路设计和分析系统中对子模块设计的表达 - Google Patents
层次集成电路设计和分析系统中对子模块设计的表达 Download PDFInfo
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- CN1539113A CN1539113A CNA028152786A CN02815278A CN1539113A CN 1539113 A CN1539113 A CN 1539113A CN A028152786 A CNA028152786 A CN A028152786A CN 02815278 A CN02815278 A CN 02815278A CN 1539113 A CN1539113 A CN 1539113A
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US29679701P | 2001-06-08 | 2001-06-08 | |
US60/296,797 | 2001-06-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1539113A true CN1539113A (zh) | 2004-10-20 |
Family
ID=23143594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA028152786A Pending CN1539113A (zh) | 2001-06-08 | 2002-06-10 | 层次集成电路设计和分析系统中对子模块设计的表达 |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1407391A2 (fr) |
JP (1) | JP2005518002A (fr) |
KR (1) | KR20040032109A (fr) |
CN (1) | CN1539113A (fr) |
CA (1) | CA2450143A1 (fr) |
IL (1) | IL159224A0 (fr) |
WO (1) | WO2002101601A2 (fr) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100461189C (zh) * | 2005-01-21 | 2009-02-11 | 国际商业机器公司 | 电路设计方法及系统 |
CN102160055B (zh) * | 2009-07-28 | 2014-03-12 | 新诺普系统公司 | 电子电路阶层级数的排序仿真 |
CN103678760A (zh) * | 2012-09-21 | 2014-03-26 | 波音公司 | 建模数据和逻辑数据的显示 |
CN105612520A (zh) * | 2013-08-06 | 2016-05-25 | Ess技术有限公司 | 连接的元件的约束性布置 |
CN106777441A (zh) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | 时序约束管理方法及装置 |
CN107797051A (zh) * | 2016-08-30 | 2018-03-13 | 联发科技股份有限公司 | 自动测试样式生成的电路建模方法以及自动测试样式生成电路 |
CN112395431A (zh) * | 2021-01-18 | 2021-02-23 | 北京晶未科技有限公司 | 用于构建行为模型的方法、电子装置和电子设备 |
CN113642280A (zh) * | 2020-04-27 | 2021-11-12 | 中国科学院上海微系统与信息技术研究所 | 超导集成电路的布局方法 |
CN117436379A (zh) * | 2023-12-21 | 2024-01-23 | 成都行芯科技有限公司 | 一种通孔压缩方法、装置、电子设备及存储介质 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100382085C (zh) * | 2004-07-07 | 2008-04-16 | 华为技术有限公司 | 一种印制电路板中集成设计元件的版图设计方法和装置 |
US7752588B2 (en) | 2005-06-29 | 2010-07-06 | Subhasis Bose | Timing driven force directed placement flow |
WO2007002799A1 (fr) | 2005-06-29 | 2007-01-04 | Lightspeed Logic, Inc. | Procedes et systemes de placement |
US8332793B2 (en) | 2006-05-18 | 2012-12-11 | Otrsotech, Llc | Methods and systems for placement and routing |
US7840927B1 (en) | 2006-12-08 | 2010-11-23 | Harold Wallace Dozier | Mutable cells for use in integrated circuits |
CN102339342B (zh) * | 2010-07-27 | 2013-06-05 | 中国科学院微电子研究所 | 一种参数化器件单元的快速实体化方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5598344A (en) * | 1990-04-06 | 1997-01-28 | Lsi Logic Corporation | Method and system for creating, validating, and scaling structural description of electronic device |
US5644498A (en) * | 1995-01-25 | 1997-07-01 | Lsi Logic Corporation | Timing shell generation through netlist reduction |
US5844818A (en) * | 1996-05-10 | 1998-12-01 | Lsi Logic Corporation | Method for creating and using design shells for integrated circuit designs |
US5920484A (en) * | 1996-12-02 | 1999-07-06 | Motorola Inc. | Method for generating a reduced order model of an electronic circuit |
US5878053A (en) * | 1997-06-09 | 1999-03-02 | Synopsys, Inc. | Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs |
US6072945A (en) * | 1997-06-26 | 2000-06-06 | Sun Microsystems Inc. | System for automated electromigration verification |
US6457159B1 (en) * | 1998-12-29 | 2002-09-24 | Cadence Design Systems, Inc. | Functional timing analysis for characterization of virtual component blocks |
-
2002
- 2002-06-10 CA CA002450143A patent/CA2450143A1/fr not_active Abandoned
- 2002-06-10 WO PCT/US2002/018424 patent/WO2002101601A2/fr active Application Filing
- 2002-06-10 IL IL15922402A patent/IL159224A0/xx unknown
- 2002-06-10 KR KR10-2003-7016097A patent/KR20040032109A/ko not_active Application Discontinuation
- 2002-06-10 JP JP2003504290A patent/JP2005518002A/ja active Pending
- 2002-06-10 EP EP02739817A patent/EP1407391A2/fr not_active Withdrawn
- 2002-06-10 CN CNA028152786A patent/CN1539113A/zh active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100461189C (zh) * | 2005-01-21 | 2009-02-11 | 国际商业机器公司 | 电路设计方法及系统 |
CN102160055B (zh) * | 2009-07-28 | 2014-03-12 | 新诺普系统公司 | 电子电路阶层级数的排序仿真 |
CN103678760A (zh) * | 2012-09-21 | 2014-03-26 | 波音公司 | 建模数据和逻辑数据的显示 |
CN103678760B (zh) * | 2012-09-21 | 2018-06-05 | 波音公司 | 建模数据和逻辑数据的显示 |
CN105612520A (zh) * | 2013-08-06 | 2016-05-25 | Ess技术有限公司 | 连接的元件的约束性布置 |
CN106777441A (zh) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | 时序约束管理方法及装置 |
CN106777441B (zh) * | 2015-11-24 | 2020-04-21 | 龙芯中科技术有限公司 | 时序约束管理方法及装置 |
CN107797051A (zh) * | 2016-08-30 | 2018-03-13 | 联发科技股份有限公司 | 自动测试样式生成的电路建模方法以及自动测试样式生成电路 |
CN113642280A (zh) * | 2020-04-27 | 2021-11-12 | 中国科学院上海微系统与信息技术研究所 | 超导集成电路的布局方法 |
CN112395431A (zh) * | 2021-01-18 | 2021-02-23 | 北京晶未科技有限公司 | 用于构建行为模型的方法、电子装置和电子设备 |
CN117436379A (zh) * | 2023-12-21 | 2024-01-23 | 成都行芯科技有限公司 | 一种通孔压缩方法、装置、电子设备及存储介质 |
CN117436379B (zh) * | 2023-12-21 | 2024-04-09 | 成都行芯科技有限公司 | 一种通孔压缩方法、装置、电子设备及存储介质 |
Also Published As
Publication number | Publication date |
---|---|
KR20040032109A (ko) | 2004-04-14 |
IL159224A0 (en) | 2004-06-01 |
WO2002101601A2 (fr) | 2002-12-19 |
CA2450143A1 (fr) | 2002-12-19 |
JP2005518002A (ja) | 2005-06-16 |
EP1407391A2 (fr) | 2004-04-14 |
WO2002101601A3 (fr) | 2003-12-11 |
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