CN1525187A - Apparatus for testing semiconductor integrated circuit - Google Patents

Apparatus for testing semiconductor integrated circuit Download PDF

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Publication number
CN1525187A
CN1525187A CNA2003101036093A CN200310103609A CN1525187A CN 1525187 A CN1525187 A CN 1525187A CN A2003101036093 A CNA2003101036093 A CN A2003101036093A CN 200310103609 A CN200310103609 A CN 200310103609A CN 1525187 A CN1525187 A CN 1525187A
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CN
China
Prior art keywords
test
signal
test pattern
semiconductor integrated
circuit
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Application number
CNA2003101036093A
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Chinese (zh)
Inventor
ɭ��Ҳ
森长也
船仓辉彦
花井寿佳
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Renesas Technology Corp
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Renesas Technology Corp
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Publication of CN1525187A publication Critical patent/CN1525187A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

An apparatus for testing a semiconductor integrated circuit has a test circuit board and an ancillary test device. The ancillary test device can test a digital circuit. The ancillary test device has test pattern memory, a test pattern signal generator, and a control section for controlling an operation for the test pattern data selected from among the plurality of test pattern data sets stored in the test pattern memory and an operation for writing the selected test pattern data into the test pattern signal generator. The ancillary test device generates a test input pattern signal on the basis of test pattern data written in the test pattern signal generator and determines a test output pattern signal output from the semiconductor integrated circuit on the basis of the test input pattern signal, thereby testing a digital circuit.

Description

Semiconductor integrated circuit testing apparatus and SIC (semiconductor integrated circuit) manufacture method
Technical field
The present invention relates to carrying out near the testing circuit board of signal exchange the proving installation of the SIC (semiconductor integrated circuit) of testing auxiliary device being set, and use the manufacture method of the SIC (semiconductor integrated circuit) of this device with tested SIC (semiconductor integrated circuit).
Background technology
In general, by using the test of the large-scale semiconductive integrated circuit (hereinafter referred to as LSI) that the simulation special tester simulates.The structure of this simulation special tester is designed to: can provide Test input signal to DUT, and analyze from DUT acceptance test output signal via carrying out the testing circuit board of signal exchange with tested SIC (semiconductor integrated circuit) (hereinafter referred to as DUT).But, in nearest SIC (semiconductor integrated circuit), on the LSI of simulation, added the LSI of digital circuit, be exactly that the mixed type LSI that has added logical circuit and memory circuit increases specifically.In this mixed type LSI; if the small scale of the digital circuit that is coupled with; and low speed action; functional test function by the low performance of establishing in the simulation special tester so; can test digital circuit, still, nearest development rapidly along with system's singualtion; simulation LSI goes up added digital circuit and changes on a large scale, therefore is difficult to test with traditional test function.
As the countermeasure of improving this situation that is difficult to test, can consider to expand the digital function test function that inside had of simulation special tester, but in the expansion of this digital function test function, need the special tester of indivedual exploitations for the expansion purpose.In addition, as another countermeasure, can consider respectively to mimic channel and DLC (digital logic circuit) and the special-purpose test machine of number storage preparation, but, need carry out equipment investment to logical circuit special tester and storer special tester, and the test duration that need increase during test is also worrying.In addition, also can consider to prepare mixed signal type test machine, but need carry out the great number investment this special test machine to mixed type LSI.
On the other hand, in the test to digital LSI, the logical circuit of interior dress, memory circuit are also changed on a large scale, and, in the test machine of the special use corresponding, also there is same problem to produce with logical circuit and memory circuit.In addition, on digital LSI, add in the test of mixed type LSI of mimic channel, also have same problem.
Open in flat 8-179013 communique and the Te Kai 2001-83216 communique the spy, disclose the inner test machine that mode generator is housed and has the digital function test function.But, these are relevant test machines with digital function test function, and are the test machines that is provided with the digital function test function at so-called special tester certainly on one's body, so, for the expansion of this digital function test function, also need other exploitation as hereinbefore.In addition, in the test machine that can not expand such digital function test function, just need transform test machine significantly, therefore, from easiness two aspects of cost and expansion, all have problems.
The inventor waits the spy who has filed an application to open in 2002-236143 number before the application, be provided with proving installation near the testing auxiliary device that has proposed testing circuit board, to dispose, as the proving installation of the SIC (semiconductor integrated circuit) that contains A/D change-over circuit and D/A change-over circuit to the test circuit of A/D change-over circuit and D/A change-over circuit.This device to mixed the mixed type LSI of mimic channel on digital LSI, is tested the A/D change-over circuit and the D/A change-over circuit that are comprised in this mimic channel by testing auxiliary device.By near the testing auxiliary device of test being located at testing circuit board with A/D change-over circuit and test with the D/A change-over circuit is set, do not need test machine is carried out big transformation, and, can eliminate the simulated determination line between test machine and the testing circuit board, eliminate the influence of noise to this simulated determination line, near by being provided with testing circuit board testing auxiliary device can effectively be tested simultaneously.But, even the test machine of this last application also still is not enough to further expand its test function.
Summary of the invention
The objective of the invention is to, provide a kind of do not need the too big expense of flower just can realize simply to the expansion of the test function of the digital circuit of SIC (semiconductor integrated circuit), and the proving installation of SIC (semiconductor integrated circuit) test, of combine digital circuit promptly through improveing.
In addition, the present invention also aims to, provide a kind of do not need the too big expense of flower just can realize simply to the expansion of the test function of the digital circuit of SIC (semiconductor integrated circuit), promptly the combine digital circuit test, and test pattern data that can test is required easily and the proving installation of SIC (semiconductor integrated circuit) that prepare fully, through improveing.
In addition, the present invention also aims to, provide a kind of do not need the too big expense of flower just can realize simply to the transmission of test pattern data expansion, that can carry out the self-testing mode storer efficiently of the test function of the digital circuit of SIC (semiconductor integrated circuit), and the proving installation of the SIC (semiconductor integrated circuit) through improveing of combine digital circuit test rapidly.
In addition, the present invention also aims to, provide a kind of do not need the too big expense of flower just can realize simply to the function expansion of the digital circuit test of the SIC (semiconductor integrated circuit) in the test step of SIC (semiconductor integrated circuit), and can implement the manufacture method of the SIC (semiconductor integrated circuit) through improveing of its test rapidly.
Description of drawings
Fig. 1 is the structural drawing of embodiment 1 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of SIC (semiconductor integrated circuit) of the present invention.
Fig. 2 is a block diagram of representing the major part of embodiment 1 in detail.
Fig. 3 is the sequential chart of the operation of expression embodiment 1.
Fig. 4 is the BOST control part among the embodiment 2-1 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention and the block diagram of PG portion.
Fig. 5 is the sequential chart of the operation of expression embodiment 2-1.
Fig. 6 is the sequential chart of the operation of expression embodiment 2-1.
Fig. 7 is the sequential chart of the operation of expression embodiment 2-1.
Fig. 8 is the sequential chart of the operation of expression embodiment 2-1.
Fig. 9 is the BOST control part among the embodiment 2-2 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention and the block diagram of PG portion.
Figure 10 is this figure of detailed structure of a part of circuit of expression embodiment 2-2.
Figure 11 is a block diagram of representing the programmable counter among the embodiment 2-2 in detail.
Figure 12 is the sequential chart of the operation of expression embodiment 2-2.
Figure 13 is the chart of the expression control routine corresponding with the sequential chart of Figure 12.
Figure 14 is the sequential chart of the operation of expression embodiment 2-2.
Figure 15 is the chart of the expression control routine corresponding with the sequential chart of Figure 14.
Figure 16 is the sequential chart of the operation of expression embodiment 2-2.
Figure 17 is the chart of the expression control routine corresponding with the sequential chart of Figure 16.
Figure 18 is the sequential chart of the operation of expression embodiment 2-2.
Figure 19 is the chart of the expression control routine corresponding with the sequential chart of Figure 18.
Figure 20 is the block diagram of the BOST control part among the embodiment 2-3 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention.
Figure 21 is a block diagram of representing the serializer among the embodiment 2-3 in detail.
Figure 22 is the sequential chart of the operation of expression embodiment 2-3.
Figure 23 is the block diagram of the embodiment 2-4 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention.
Figure 24 is the block diagram of the embodiment 2-5 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention.
Figure 25 is the block diagram of the embodiment 2-6 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention.
Figure 26 is a block diagram of representing the main circuit part of embodiment 2-6 in detail.
Figure 27 is the sequential chart of the operation of expression embodiment 2-6.
Figure 28 is the block diagram of the DUT-BOST I/F portion among the embodiment 2-7 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention.
Figure 29 is the output detection unit among the embodiment 2-8 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention and the block diagram of error message storage part.
Figure 30 is the stretch-out view of BOST combination among the embodiment 3-1 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention.
Figure 31 is the outboard profile of the BOST combination among the expression embodiment 3-1.
Figure 32 is the key diagram of the data writing system of medium among the embodiment 3-1.
Figure 33 is the block diagram of BOST control part, TPM portion and PG portion among the embodiment 3-2 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention.
Figure 34 is a block diagram of representing embodiment 3-2 in detail.
Figure 35 is the process flow diagram of the testing sequence among the expression embodiment 3-2.
Figure 36 is the sequential chart of the operation of expression embodiment 3-2.
Figure 37 is the process flow diagram of the testing sequence among the expression embodiment 3-2.
Figure 38 is the sequential chart of the operation of expression embodiment 3-2.
Figure 39 is the block diagram of the PG portion among the embodiment 3-3 of the proving installation of the SIC (semiconductor integrated circuit) of the present invention used in the manufacture method of expression SIC (semiconductor integrated circuit) of the present invention.
Embodiment
Embodiment 1
Fig. 1 is the block diagram of circuit structure of embodiment 1 of the proving installation of expression SIC (semiconductor integrated circuit) of the present invention.Fig. 2 is the block diagram of circuit structure of the testing auxiliary device of expression embodiment 1.Fig. 3 is the sequential chart of the test operation of expression embodiment 1.In the test step of the manufacture method of SIC (semiconductor integrated circuit) of the present invention, adopted the proving installation of present embodiment 1.
At first, describe with regard to the integrated circuit structure of embodiment 1 with reference to Fig. 1.The proving installation of the SIC (semiconductor integrated circuit) of present embodiment 1 is the proving installation at tested SIC (semiconductor integrated circuit) 10, wherein is provided with testing circuit board 11, external testing machine 18 and testing auxiliary device 20.Tested SIC (semiconductor integrated circuit) 10 also can be called DUT (Device Under Test).In this DUT10, can adopt various types of LSI, but in the present embodiment 1, imagination adopt in simulation LSI, added digital circuit, be exactly mixed type LSI or the digital LSI that has added logical circuit and memory circuit specifically.Testing circuit board 11 is also referred to as the DUT plate.External testing machine 18 is also referred to as test machine.In addition, testing auxiliary device 20 is also referred to as the BOST device.
In addition, in Fig. 1, add the signal wire presentation address signal wire of hatched IR intermediate rough, the black signal line of IR intermediate rough is represented data signal line, and thin signal wire is represented control signal wire.In addition, black thick signal wire is provided by the input pattern signal wire to DUT to DUT10 that provides from BOST device 20, the thick signal wire that adds reticulate pattern represents to offer from DUT10 the DUT output signal line of BOST device 20, and the thick signal wire of adding some points is represented the expectancy model signal wire with respect to DUT10.
DUT plate 11 is to be configured near the circuit board of DUT10, is the test machine-DUT interface board that carries out signal exchange between DUT10 and test machine 18.
In Fig. 1, DUT10 is depicted in the DUT plate 11, but this DUT plate 11 and DUT10 are separated from each other formation, and, between them, directly carry out signal exchange.
BOST device (Built Off Self Test device) the 20th, a kind of testing auxiliary device that does not rely on test machine 18, its purpose is the test function of carrying out self-test (Built In SelfTest) of auxiliary DUT10, and the test function of extend testing machine 18.
This BOST device 20 comprises circuit board 201.Circuit board 201 is also referred to as BOST (Built OffSelf Test) plate.This plate is to constitute the circuit board that BOST device 20 occasions adopt with a circuit board.
Among Fig. 1, bost board 201 is depicted in the DUT plate 11, the expression bost board 201 be configured in DUT plate 11 near.
Below, be described in detail with regard to BOST device 20.BOST device 20 has at the hardware configuration shown in Fig. 1, specifically, wherein be provided with: (1) BOST communication interface part (BOST communication I/F portion) 30, (2) CPU portion 33, (3) reference clock portion 38, (4) the BOST control part 40, (5) test pattern storage part (Test Pattern Memory/TPM portion) 50, (6) test pattern signal generator (Pattern Generator/PG portion) 60, (7) timing generator (Timing Generator/TG portion) 70, (8) wave shaping portion (WaveForm/WF portion) 80, (9) output detection unit 85, (10) the error message storage part 90, (11) DUT-BOST interface portion (DUT-BOST I/F portion) 95, (12) power supply unit 99.
BOST communication I/F portion 30 is used for the interface that communicates between test machine 18 and BOST device 20, between the TPM portion 50 of BOST device 20 inside and test machine 18, communicate, promptly write test pattern data TPD to TPM portion 50, read test pattern data TPD to test machine 18 from TPM portion 50 from test machine 18.BOST communication I/F portion 30 receives the address signal ATP that these are used to the test pattern data TPD that writes and read from test machine 18.Simultaneously, BOST communication I/F portion 30 communicates between the CPU of BOST device 20 one 33 and test machine 18, specifically, provide test code (Test No.) TCD and test commencing signal TST from test machine 18 to CPU portion 33, and provide error code (Pass/Fail information) ECD to test machine 18 from CPU portion 33.
In addition, can not use test machine 18, and other test data source beyond test machine 18 writes and therefrom reads test pattern data TPD to TPM portion 50.
CPU portion 33 is principal computers of BOST device 20, is made of digital signal processor (DSP) or microprocessor.This CPU portion 33 is according to test code (Test No.) TCD and test commencing signal TST that provide via BOST communication I/F portion 30 from test machine 18, each several part to BOST device 20 carries out initial setting, and carry out self diagnosing of BOST device 20, also test result is analyzed.CPU portion 33 provides selection indicator signal SIS according to test code TCD to control part 40.This selection indicator signal SIS is in order to from a plurality of test pattern data TPD corresponding to a plurality of test events that are stored in TPM portion 50, the test pattern data TPD that selection will be carried out.
Reference clock signal SCK take place in reference clock portion 38, and this reference clock signal SCK offered comprise CPU portion 33 each circuit part at interior BOST device 20.
The indication that BOST control part 40 receives from CPU portion 33, and each circuit part of control BOST device 20.Simultaneously, to the TPM portion 50 and PG portion 60 calculated addresses of BOST device 20.
TPM portion 50 is storeies of the test pattern data TPD of storage numeral.This test pattern data TPD becomes in order to take place at the test input pattern signal TIP of DUT10, from the test output mode signal TOP of DUT10 and the master data of other test mode signals.Correspond respectively to a plurality of test pattern data TPD of the needed various test events of digital circuit test of various SIC (semiconductor integrated circuit), be stored in this TPM portion 50.
There is the promptly lower frequency of operation than low speed in this TPM portion 50, and it is made of the semiconductor memory with large storage capacity.Constitute the large storage capacity of the semiconductor memory of this TPM portion 50, required a lot of test pattern data TPD are tested in storage effectively, and it is the lower frequency of operation of low speed relatively, is effective for cost degradation, the miniaturization of the semiconductor memory that constitutes TPM portion 50.Because BOST device 20 is configured on the DUT10 DUT plate 11 nearby, therefore, its size is subjected to the system limit, but the miniaturization of TPM portion 50, is effective for the further miniaturization of whole BOST device 20.
Specifically, TPM portion 50 is made of the semiconductor memory system of the large storage capacity of 10 gigabits (G) byte to 20 gigabits (G) byte.In addition, constitute the semiconductor memory of TPM portion 50, constitute by the semiconductor memory that hangs down frequency of operation with 10 megahertz to 20 megahertzes.As semiconductor memory, for example can adopt dynamic RAM (DRAM), static RAM (SRAM), flash memory etc., combine by these storeies are a plurality of.
Then, PG portion 60 is from the every a plurality of test pattern data TPD that correspond respectively to a plurality of test events that are stored in TPM portion 50, download the test pattern data TPD corresponding, and, test mode signal TPS takes place at a high speed based on this test pattern data TPD that is downloaded with the test that will carry out.And test input/determinating mode signal JPS takes place based on the test pattern data TPD that is downloaded to this PG portion 60 in this PG portion 60.These test mode signals TPS and test input/determinating mode signal JPS are the signals that test pattern data TPD is comprised, and take out by read the test pattern data TPD that downloads from TPM portion 50 by PG portion 60.
This PG portion 60 is by constituting than the semiconductor memory that constitutes TPM portion 50 semiconductor memory at a high speed.Constitute the semiconductor memory of this PG portion 60, compare with the semiconductor memory that constitutes TPM portion 50, have higher frequency of operation, ETPD reads with the high speed test mode data.This frequency of operation for example is to 250 megahertzes from 100 megahertzes.The high speed of this test pattern takes place, and with shortening readout time of test pattern data ETPD, and shortens the test required time effectively.The memory capacity of this PG portion 60 for example has the memory capacity of 256 megabits to 1 gigabit (G) bit less than the memory capacity of TPM portion 50.
Mensuration commencing signal MST, external timing signal OCK that TG portion 70 receives from test machine 18, and, receive reference clock signal SCK from reference clock portion 38, the needed various timing signals of test take place.This timing signal comprises: with the mensuration commencing signal MST test cycle signal TCY of synchronous and definite test period, the clock signal clk of the timing of the rise and fall of the test input pattern signal TIP that setting provides to DUT10, and the test output mode signal TOP from DUT10 set judge gating signal (gating periodic signal) STB regularly.In these timing signals, test cycle signal TCY also offers the trigger 803 (Fig. 2) of the leading portion of BOST control part 40 and WF portion 80, and clock signal clk offers WF portion 80, and gating signal STB offers output detection unit 85.
This WF portion 80 again from 70 acceptance test periodic signal TCY of TG portion and clock signal C TK, and generates the test input pattern signal TIP that gives DUT10 from 60 acceptance test mode signal TPS of PG portion and test input/determinating mode signal JPS.This test input pattern signal TIP offers DUT10 via DUT-BOST I/F portion 95.
The test output mode signal TOP that provides via DUT-BOST I/F portion 95 from DUT10 is provided output detection unit 85.Specifically, in the timing of the gating signal STB of TG portion 70 output, judge this test output mode signal TOP and from the test input pattern signal TPS of PG portion 60.From PG portion 60 to the test mode signal TPS that provides of output detection unit 85, be and the corresponding expectancy model signal of test output mode signal TOP from DUT10, if the test output mode signal TOP from DUT10 is identical with this test mode signal TPS, just be judged to be inerrancy, if value from the test output mode signal TOP of DUT10, with the expectancy model signal is that test mode signal TPS is different, just exports the error data signal.
Error message storage part 90 storage is from the error data signal of output detection unit 85, and stores the address of the test pattern vector of this mistake when taking place.The address of this test pattern vector is the vector address of PG portion 60, is the vector address value of the PG portion 60 of output detection unit 85 when being judged to be mistake.Have, the vector address of test pattern vector means the group unit of a succession of address of test pattern data TPD again.
DUT-BOST I/F portion 95 provides test input pattern signal TIP to DUT10, and receives the test output mode signal TOP from DUT10, offers output detection unit 85.Simultaneously, these input and output voltage level of testing input pattern signal TIP and test output signal TOP are mated, adjust, and, carry out connection switching to the input/output signal line of DUT10.The connection of this input/output signal line is switched, and is in the switching of carrying out between being connected of the connection of test machine 18 and DUT10 and BOST device 20 and DUT10.
The power supply that power supply unit 99 receives from external power source, and generation is to the various supply voltages of BOST device 20.The function of this power supply unit 99 comprises conversion from AC to DC and the voltage transitions between the DC-DC.
Fig. 2 is the BOST control part 40, TG portion 70, WF portion 80 in the BOST device 20 shown in the detailed presentation graphs 1, the block diagram of output detection unit 85, error message storage part 90 and DUT-BOST I/F portion 95.In addition, in Fig. 2, the thin signal wire that is added with bullet is represented data bus, and the signal wire that is added with the IR intermediate rough of bullet is represented the initial setting line.
Be provided with memory address counter 401,402 in the BOST control part 40.Memory address counter 401 will advance to the memory address signal MAD (in Fig. 3 (a) expression) of PG portion 60 when the test cycle signal TCY (in Fig. 3 (d) expression) that at every turn receives from TG portion 70.This memory address signal MAD is and test vector address corresponding address signal.This memory address signal MAD offers PG portion 60, also offers the DATA terminal of error message storage part 90 simultaneously.If memory address counter 402 receives storer when writing signal MWR (shown in Fig. 3 (k)) from the phase inverter 855 that is connected of output stage with output detection unit 85, provide to error message storage part 90 and to specify the address specification signal MIS (in Fig. 3 (m), representing) that writes the address that error data signal EDT uses.
Be provided with in the TG portion 70: the test cycle signal generation circuit 700 that test cycle signal TCY (shown in Fig. 3 (d)) takes place, the clock generating circuit 710 of clock signal clk (shown in Fig. 3 (e)) takes place, and the gating signal generation circuit 715 that gating signal STB (shown in Fig. 3 (f)) takes place.
Be provided with in the test cycle signal generation circuit 700: select circuit 701, selection circuit 702, PLL circuit 703, AND circuit 704 and trigger 705.Selecting has in the circuit 701: receive the input end A from the reference clock signal SCK of reference clock portion 38, reception is from the input end B of the external timing signal OCK (in Fig. 3 (b) expression) of test machine 18, reception is from the selection input end S of the selection signal S of BOST control part 40, and output terminal F.This selects the output F of circuit 701, equates with reference clock signal SCK when selecting input S to be low level L, equates with external timing signal OCK when selecting input S to be high level H.The output F of this selection circuit 701 offers the input end A that selects circuit 702 via PLL circuit 703.703 couples of reference clock signal CLK of PLL circuit or external timing signal OCK carry out phase-locked, by BOST control part 40 initial setting in addition.
Selecting has in the circuit 702: input end A, and the input end B of reception reference clock signal SCK, the input end C of reception external timing signal OCK (shown in Fig. 3 (b)) receives the selection input end of selecting signal S0/S1, and output terminal F.This selects the output F of circuit 702, select input S0 be low level L and when selecting input S1 also for low level L with import A and equate, in addition, in that to select input S0 be high level H and import B with reference clock when selecting input S1 to be low level L and equate, in addition, in that to select input S0 be low level L and import C with external clock when selecting input S1 to be high level H and equate.The output terminal F of this selection circuit 702 becomes an input end in the AND circuit 704.
Have in the trigger 705: receive input end of clock, the input end D that is connected with supply voltage, and output terminal Q from the mensuration commencing signal MST (shown in Fig. 3 (c)) of test machine 18; The output terminal Q of this trigger 705 is as another input end of AND circuit 704.The output of AND circuit 704 is output F of selecting circuit 702 with the output Q of trigger 705 between AND export.The output of this AND circuit 704 is test cycle signal TCY.This test cycle signal TCY is shown in Fig. 3 (d), and it is provided for memory address counter 401 and advances its memory address count value, also is provided for clock generating circuit 710 and gating signal generation circuit 715 simultaneously.
Clock generating circuit 710 comprises delay circuit 711.This delay circuit 711 will postpone tclk time delay of initial setting from the test cycle signal TCY that test cycle signal generation circuit 700 provides, and the clock signal clk shown in Fig. 3 (e) takes place.Time delay, tclk was by BOST control part 40 initial settings.
Gating signal generation circuit 715 comprises delay circuit 716.This delay circuit 716 will postpone tstb time delay of initial setting from the test cycle signal TCY that test cycle signal generation circuit 700 provides, and the gating signal STB shown in Fig. 3 (f) takes place.Time delay, tstb was by BOST control part 40 initial settings.
As shown in Figure 2, WF portion 80 comprises trigger 801 and AND circuit 802, and its prime is connected with trigger 803.Trigger 803 is imported determinating mode signal JPS at the test mode signal TPS of input end D1 reception from PG portion 60 in input end D2 acceptance test, and at the test cycle signal TCY of its input end of clock C reception from test cycle signal generation circuit 700.Trigger 803 makes the test input/determinating mode signal JPS shown in the test mode signal TPS shown in Fig. 3 (h) and Fig. 3 (g), and TCY is synchronous with test cycle signal, exports from output terminal Q1, Q2.Offer the input end D of the trigger 801 of WF portion 80 from the test mode signal TPS of trigger 803, and test input determinating mode signal JPS offers an input end (inverting input) of AND circuit 802.
This tests in input/determinating mode signal JPS AND circuit 802 in reception, at the clock signal clk of another input end reception from clock generating circuit 710, and, its AND is exported the input end of clock that offers trigger 801.The output Q of trigger 801, when the test input/determinating mode signal JPS shown in Fig. 3 (g) was low level L, when promptly test input/determinating mode signal JPS represented input state, output was at the rising test mode signal TPS regularly of clock signal clk.When the test input/determinating mode signal JPS shown in Fig. 3 (g) was high level H, when promptly test input/determinating mode signal JPS represented decision state, the output Q of trigger 801 did not change, the state before keeping.The output Q of this trigger 801, result become test input pattern signal TIP, and, offer DUT10 via the three-state buffer 951 of DUT-BOST I/F portion 95.
Output detection unit 85 comprises: EX-OR circuit 851, AND circuit 852, trigger 853 and pulse generation circuit 854.EX-OR circuit 851 is on an one input end, reception is from the test mode signal TPS (shown in Fig. 3 (h)) of trigger 803, on its another input end, receive test output mode signal TOP (shown in Fig. 3 (i)) from the input buffer circuit 952 of DUT-BOST I/F portion 95.EX-OR circuit 851 pairs of tests output mode signal TOP and test mode signal TPS compare, if its value is consistent, and with regard to output low level L, if the inconsistent high level H that just exports, the expression error condition.
The output of this EX-OR circuit 851 becomes the input D of trigger 853.AND circuit 852 receives the test input/determinating mode signal JPS from trigger 803 on an one input end, on its another input end, receive the gating signal STB from gating signal generation circuit 715.The output of this AND circuit 852 becomes the clock input C of trigger 853.In addition, in output detection unit 85, when test input/determinating mode signal JPS represented input state, clock signal clk was made as effectively, and gating signal STB is made as invalid; When test input/determinating mode signal JPS represented decision state, clock signal C TK was made as invalid, and gating signal STB is made as effectively, and in the timing of this gating signal STB, test mode signal TPS and test output mode signal TOP are carried out comparison.
The output Q of trigger 853, when the test input/determinating mode signal JPS shown in Fig. 3 (g) is high level H, when promptly test input/determinating mode signal JPS represented decision state, output was the output valve of AND circuit 852 at the input D of the timing of gating signal STB.When test input/determinating mode signal JPS was low level L, when promptly test input/determinating mode signal JPS represented input state, the output Q of trigger 853 did not change, the state before keeping.As a result, the output of trigger 853 becomes the error data signal EDT shown in Fig. 8 (j).
In the action timing diagram of Fig. 3, memory address signal MAD shown in the figure (a) is address 1,2,3,5,6 o'clock, test input/determinating mode signal JPS shown in the figure (g) represents input state, clock signal clk is made as effectively, gating signal STB is made as invalid, and test input pattern signal TIP is input to DUT10.When memory address MAD was address 4, test input/determinating mode signal JPS represented decision state.At this moment, clock signal clk is invalid, and gating signal STB is effective, judges in the timing of this gating signal STB.Among Fig. 3, when memory address signal MAD was address 4, test mode signal TPS was 0, was 0 to the desired value of testing output mode signal TOP.On the contrary, because the test output mode signal TOP shown in figure this moment (i) represents 1, therefore, the output Q of the trigger 853 of output detection unit 85 becomes high level H, and the error data signal EDT shown in the figure (j) rises.
This error data signal EDT is provided for the DATA input end of error message storage part 90, is provided for pulse generation circuit 854 simultaneously.Pulse generation circuit 854 provides the pulse input to phase inverter 855, storer shown in Fig. 3 (k) takes place and writes signal MWR in phase inverter 855, and this signal is offered the input end of clock of memory address counter 402 and the WR input end of error message storage part 90.Error message storage part 90 writes the timing of signal MWR at storer, storage error data signal EDT and from the memory address signal MAD (shown in Fig. 3 (a)) of memory address counter 401.Address specification signal MIS from memory address counter 402 specifies its memory address.
DUT-BOST I/F portion 95 is provided with: input and output commutation circuit 950, interface voltage level shifting circuit 955 and test machine/BOST commutation circuit 960.Three-state buffer 951 and impact damper 952 are arranged in the input and output commutation circuit 950.Three-state buffer 951 comprises: receive the control input end from the test input/determinating mode signal JPS of trigger 803, the output Q that receives trigger 801 promptly tests the input end of input pattern signal TIP and output terminal.When this three-state buffer 951 is low level L at test input/determinating mode signal JPS, when promptly test input/determinating mode signal JPS represents input state, output test input pattern signal TIP.And when test input/determinating mode signal JPS is high level H, when promptly testing input/determinating mode signal indication decision state, three-state buffer 951 no-outputs.
Impact damper 952 is in order to the impact damper with the input signal shaping, and its output offers another input end of the EX-OR circuit 851 of output detection unit 85.Interface voltage level shifting circuit 955 is provided with MOS transistor 956.The grid of this MOS transistor 956 is from the analog output reception reference voltage V S of D/A converting circuit 957.The drain electrode of MOS transistor 956 is connected with the output terminal of three-state buffer 951 and the input end of impact damper 952, and its source electrode is connected with test machine/BOST commutation circuit 960.This MOS transistor 956 will be changed the voltage of its source electrode, drain electrode according to the reference voltage V S that offers grid voltage.For example, the supply voltage of DUT10 is the low-voltage of 3V series etc., and when the voltage of BOST device 20 was 5V, the level conversion of the test input pattern signal TIP that will provide to DUT10 became 3V, and, will convert 5V to from 3V from the test output mode signal TOP of DUT10.On D/A converting circuit 957, provide voltage, and this D/A converting circuit 957 carries out initial setting by BOST control part 40 from power supply unit 99.
Test machine/BOST commutation circuit 960 is provided with change-over switch 961.This change-over switch 961 comprises the terminal B that the shared terminal C that is connected with DUT10, the terminal A that is connected with test machine 18 are connected with source electrode with MOS transistor 956.Under the state that terminal B, C connect, the source electrode of MOS transistor 956 is connected with DUT10, is tested by BOST device 20.Under the state that terminal A, C connect, test machine 18 directly is connected with DUT10, is tested by test machine 18.
In the embodiment shown in Fig. 1,2,31, carry out general description with regard to its action.
At first the initial setting action comprises following (1), (2), (3), (4) four steps.
(1) test pattern data TPD's writes
(2) transmission of test code code T CD
(3) initial setting in the BOST device 20
(4) starting condition in the BOST device 20 is set
Below for the action of these initial settings with being illustrated successively.
(1) test pattern data TPD's writes
From test machine 18 or other data source,, the test pattern data TPD corresponding with the needed a plurality of test events of test of the digital circuit of various SIC (semiconductor integrated circuit) write TMP portion 50 via BOST communication I/F portion 30.In addition, also the TMP portion 50 that has write test pattern data TPD in advance can be loaded on BOST device 20, replace writing of this test pattern data TPD.
(2) transmission of test code code T CD
From test machine 18 will with the suitable test code TCD of test event that implements, send to CPU portion 33 via BOST communication I/F portion 30.
(3) initial setting in the BOST device 20
Received the CPU portion 33 of test code TCD, TMP portion 50, PG portion 60, TG portion 70 have been carried out initial setting.In the initial setting of TMP portion 50,, the storer of TMP portion 50 is set start address and the halt address of the test pattern data TPD that will carry out corresponding to test code TCD.
In initial setting, the storer of PG portion 60 is set start address and halt address in order to the test pattern data TPD that writes execution to PG portion 60.To the initial setting of TG portion 70,, set the timing of test cycle signal TCY on the basis of reference signal that will use as reference clock signal CLK.After the initial setting of finishing these TMP portions 50, PG portion 60, TG portion 70,, download the test pattern data TPD that will carry out that from a plurality of test pattern data TPD, selects from 50 to PG portions 60 of TMP portion.
(4) starting condition in the BOST device 20 is set
After the initial setting of finishing (3), error message storage part 90, TG portion 70, DUT-BOST I/F portion 95 are carried out following starting condition again set.
In the starting condition setting to error message storage part 90, set start address and halt address for error message storage part 90.The starting condition of TG portion 70 is set, selected the reference clock signal CLK and the external timing signal OCK that are used to test exactly, and set timing data in order to generation test cycle signal TCY, clock signal clk and gating signal STB.
Starting condition to DUT-BOST I/F portion 95 is set, and is exactly to set reference voltage V S for the grid of MOS transistor 956.
After above initial setting and starting condition setting, test operation is carried out in following (1), (2), (3), (4) four actions.Successively test operation (1), (2), (3), (4) are described.
(1) read the test pattern data that downloads to PG portion 60 from PG portion 60, and test mode signal TPS that will wherein comprise and test input/determinating mode signal JPS, TCY synchronously exports with test cycle signal.
(2) in WF portion 80, output face is to the test input pattern signal TIP of DUT10.This test input pattern signal TIP offers DUT10 via DUT-BOST I/F portion 95.
(3) from the test output mode signal TOP of DUT10, send to output detection unit 85 via DUT-BOST I/F portion 95.In output detection unit 85, this test output mode signal TOP is that test mode signal TPS compares with expectancy model signal from the output signal of DUT10, and whether wrong generation of affirmation.Make a mistake if be confirmed to be, the test pattern vector address MAD during so wrong the generation, EDT deposits error message storage part 90 in its error data signal.
(4) repeat test operation, up to finishing test pattern data TPD the reading that to carry out from PG portion 60 from (1) to (3).
In the acts of determination of test result, address MAD when reading the error data signal EDT that is stored in error message storage part 90 and wrong the generation by CPU portion 33, and make the judgement that test result is an acceptance or rejection, subsequently its result is sent to test machine 18 via BOST communication I/F portion 30.In addition, also can carry out various error analyses based on the data of error message storage part 90.
In embodiment 1, the TPM portion 50 storages a plurality of test pattern data TPDs corresponding with a plurality of test events of the digital circuit test that is used for DUT10, and also the test pattern data that will select from these a plurality of test pattern data TPD writes PG portion 60.According to this structure, do not need to develop especially special tester, by the test pattern data of extension storage, can expand test function simply to the digital circuit of DUT10 in TPM portion 50.Simultaneously, by storing required test pattern data in advance, can promptly carry out the test of digital circuit by testing auxiliary device 20 in TPM portion 50.
In addition, in embodiment 1, the semiconductor memory that constitutes TPM portion 50 has than the bigger memory capacity of semiconductor memory that constitutes PG portion 60, can store more test pattern data in TPM portion 50, therefore, BOST device 20 can be corresponding the kind of functional test just become many, thereby can in the more function test, effectively test by BOST device 20.
In addition, in embodiment 1, the semiconductor memory that constitutes PG portion 60 moves more at high speed than the semiconductor memory that constitutes TPM portion 50.That is to say that the semiconductor memory that constitutes PG portion 60 is with the bigger frequency of operation high speed motion of semiconductor memory than formation TPM portion 50.This has improved the speed of reading test pattern data from PG portion 60 effectively, and its result can make BOST device 20 carry out the test of the digital circuit of DUT10 with higher speed, and shorten the test duration.In addition, though the responsiveness of the semiconductor memory of TPM portion 50 is slow, this is effective for making the semiconductor memory cost degradation, the miniaturization that constitute TPM portion 50.
In addition, in embodiment 1, in order to select to be stored in a plurality of test pattern datas of TPM portion 50, CPU portion 33 provides to BOST control part 40 and selects indicator signal SIS.By this structure, the test pattern data corresponding with selecting indicator signal SIS correctly is sent to PG portion 60.
Then, just describe about embodiment 2-1 to the embodiment 2-8 of the test function of embodiment 1 proving installation expansion, SIC (semiconductor integrated circuit) of the present invention.These embodiment 2-1 to 2-8 are to have added the function and the structure of explanation from now on the function of embodiment 1 more basically.These embodiment 2-1 to 2-8 also are used in the test step that manufacture method comprised of SIC (semiconductor integrated circuit) of the present invention.
Embodiment 2-1
Present embodiment 2-1 is the embodiment that can carry out proving installation instruction control, SIC (semiconductor integrated circuit) of the present invention of its test vector to test mode signal TPS.The hardware configuration of in Fig. 4, having represented present embodiment 2-1, and represent test operation according to this structure with the sequential chart of Fig. 5 to Fig. 8.
At first, with reference to Fig. 4 the hardware configuration of present embodiment 2-1 is described.The structure of the BOST control part 40 of Fig. 4 (a) expression present embodiment 2-1, the memory construction of the PG portion 60 that Fig. 4 (b) expression is corresponding with present embodiment 2-1, Fig. 4 (c) is the pulse generation circuit 417 shown in the presentation graphs 4 (a) in detail.
In present embodiment 2-1, the PG portion 60 of the BOST device 20 shown in Fig. 1 has the memory construction shown in Fig. 4 (b).This PG portion 60 is provided with the storage area 614 of storage test vector address control routine TBAC and the storage area 613 of storage test vector address control data TBAD; With this test vector address control routine TBAC and test vector address control data TBAD accordingly, test input/determinating mode signal JPS is stored in storage area 612, test mode signal TPS is stored in storage area 611.Here, test vector means the group of bit about comprising of test mode signal TPS of continuous predetermined number.These control routines TBAC, control data TBAD, test input pattern signal JPS, test mode signal TPS are included among the test pattern data TPD that downloads to PG portion 60, and according to test vector address N, N+1, N+2, N+3 ..., N+M stores.
In present embodiment 2-1, test vector address control routine TBAC comprises: five codes such as code REP of the code JMP of the code SJP of code NOP, the subroutine jump SJP of common mode NOP, code RET, the unconditional transfer JMP that subroutine is returned RET, repetition REP.
Code NOP is the code of specifying common mode, shown in the memory address signal MAD of Fig. 3 (a), in this common mode NOP, in turn add on the last address value of test vector address+1.Code SJP is meant the code that the stator routine shifts, and indication is shifted to the description address of storing in the control data TBAD of test vector address accordingly with this code SJP.Code RET is meant the code that the stator routine is returned, indication and this code RET accordingly to add on the description address of in the control data TBAD of test vector address, describing+address after 1 is returned.Code JMP is the code of specifying unconditional transfer, and indication is shifted to the description address of describing in the control data TBAD of test vector address accordingly with this code JMP.Code REP is the code of specifying same vector to repeat, and indication is used in accordingly on the description number of times of describing among the control data TBAD of test vector address with this code REP and adds+and the number of times of 1 gained carries out repetition to same test vector address.
Test vector address control data TBAD, with each test vector address control routine TBAC accordingly, store above-mentioned description address and describe number of times.
In embodiment 2-1, shown in Fig. 4 (a), the BOST control part 40 of the embodiment 1 shown in Fig. 1 is provided with programmable counter 410.Be provided with in this programmable counter 410: instruction control selector switch 411, trigger 412, initial value register circuit 413, totalizer 414, subroutine return address latch circuit 415, multiplicity down counter 416, pulse generation circuit 417,418, and AND circuit 419,420,421.
Have in the instruction control selector switch 411: the control terminal of input terminal A0 to A6 and lead-out terminal F and reception control input S0-S2.The test vector address TBA that provides to PG portion 60 takes place in this instruction control selector switch 411 on the lead-out terminal Q of the trigger 412 that is connected with its lead-out terminal F.Figure in Fig. 5 to figure (i) represents this test vector address TBA.Initial value register 413 contains the output terminal Q that the input terminal A0 of the input end D, the input end of clock C that are connected with the internal bus 40B of BOST control part 40 and and instruction control selector switch 411 connects, and on the input terminal A0 of instruction control selector switch 411, provide initial value register output INR.This initial value register output INR is shown in the figure of Fig. 5 (a).
Totalizer 414 contains the lead-out terminal OUT that the input terminal A1 of the input terminal IN that is connected with the output terminal Q of trigger 412 and and instruction control selector switch 411 is connected, and produces totalizer export ADO=IN+1 on its lead-out terminal OUT.Figure (b) in each figure of Fig. 5 to Fig. 8 has represented this totalizer output ADO.On input terminal A2, the A4 of instruction control selector switch 411, provide transfer destination address date JAD from the test vector address control data TBAD of PG portion 60.Figure among Fig. 6,29 (c) represents this transfer destination address date JAD.Subroutine address latch circuit 415 contains the output terminal Q that the input terminal A3 of the input end D, the input end of clock C that are connected with the lead-out terminal OUT of totalizer 414 and and instruction control selector switch 411 connects, and produces at this output terminal Q and returns destination address signal RAS.Fig. 6 (d) represents that this returns destination address signal RAS.The input terminal A5 of instruction control selector switch 411, A6 ground connection.
Have in the multiplicity down counter 416: the input end D that receives the repeating data RPD of multiplicity setting value+1 that the test vector address control data TBAD of the storage area 613 be stored in PG portion 60 comprised, the LOAD input end, input end of clock C, and output terminal B0.Fig. 8 (c) expression repeating data RPD.The LOAD input end of multiplicity down counter 416 is connected with the terminal 4 of pulse generation circuit 417, and receives multiplicity setting trigger pip RCT.Fig. 8 (e) represents this multiplicity setting trigger pip RCT.At the input end of clock C of multiplicity down counter 416, provide test cycle signal TCY from the TG portion 70 of BOST device 20.Represented this test cycle signal TCY at the figure of Fig. 5 to Fig. 8 (h).At the output terminal B0 of multiplicity down counter 416, produce down counter borrow signal DCB.Fig. 8 (k) represents this down counter borrow signal DCB.This down counter borrow signal DCB becomes high level H when resetting, become low level L during LOAD.
Pulse generation circuit 417 is provided with four terminals 1,2,3,4. Terminal 1,2,3 is an input terminal, and the test vector address control routine TBAC of PG portion 60 is provided on terminal 1.The figure of Fig. 5 to Fig. 8 (j) represents this test vector address control routine TBAC.On terminal 2, provide down counter borrow signal DCB from the output terminal B0 of multiplicity down counter 416.On terminal 3, provide test cycle signal TCY from TG portion 70.Import S0-S2, offer the down counter borrow signal DCB of terminal 2 and the test cycle signal TCY that offers terminal 3 based on the control that offers terminal 1, when control input S0-S9=5, pulse generation circuit 417 produces multiplicity and sets trigger pip RCT, offers the LOAD terminal of multiplicity down counter 416.
Shown in Fig. 4 (c), pulse generation circuit 417 is provided with demoder 423, trigger 424 and AND circuit 425.423 pairs of demoders decode for the control input S0-S2 of terminal 1, offer the input end of clock C of trigger 424 then.AND circuit 425 will offer the RESET input R of trigger 424 to the down counter borrow signal DCB of terminal 2 with to the output of the AND between the test cycle signal TCY of terminal 3.The output terminal Q of trigger 424 is connected with terminal 4, provides multiplicity to set trigger pip RCT to terminal 4.
Pulse generation circuit 418 is provided with terminal 1 that receives control input S0-S2 and the lead-out terminal 2 that produces the signal generation stop signal TGS of TG portion that gives TG portion 70, S0-S2 decodes to the control input, when S0-S2=6, produce the TG signal generation stop signal TGS of portion, make TG portion 70 stop to produce test cycle signal TCY.TG portion 70 provides and measures commencing signal MST (shown in the figure (g) of Fig. 5 to Fig. 8), and measures commencing signal MST generation test cycle signal TCY based on this.
AND circuit 419 is on one input end, receive control input S0-S2, and on another input end (inverting input), get high level H when being received in initial setting, between the normal epoch beyond the initial setting, get low level mode signal (mode signal) MDS.This AND circuit 419 is provided with three altogether, and corresponding with each control input S0, S1, S2, their output becomes the control input S0-S2 of instruction control selector switch 411.AND circuit 420 is being received in the down counter borrow signal DCB that produces on the output terminal B0 of multiplicity down counter 416 on the one input end, and on another input end acceptance test periodic signal TCY.The output of this AND circuit 420 is supplied to an input end of OR circuit 421.In another input of OR circuit 421, be provided at the test vector address initial setting trigger pip TBAIT shown in the figure (f) of Fig. 5 to Fig. 8.At the output terminal of OR circuit 421, generate the test vector address final breech lock trigger pip TBAFR shown in Fig. 8 (m), offer the input end of clock C of trigger 412.
Below, carry out general description with regard to the selection action of instruction control selector switch 411.During control input S0-S2=0, selected to the input of input terminal A0.During control input S0-S2=0, output F becomes initial value register output INR (shown in the figure (a) of Fig. 5 to Fig. 8).During control input S0-S2=1, selected to the input of input terminal A1.At this moment, output F becomes totalizer output ADO (shown in the figure (b) of Fig. 5 to Fig. 8); BOST device 20 moves in the common mode of being indicated by code NOP, and, with address value+1, NOP action in due form simultaneously.During control input S0-S2=2, input terminal A2 is selected, and output F becomes transfer destination address JAD.At this moment, BOST device 20 carries out the action of subroutine jump SRJ, and carries out description address, the i.e. action of the test vector address transfer corresponding with transfer destination address date JAD to test vector address control data TBAD is comprised.
During control input S0-S2=3, it is selected that the input of input terminal A3 is promptly selected to return destination address signal RAS, and export from output terminal F.At this moment, BOST device 20 carries out the action that subroutine is returned SRR, and carries out the action returned to the test vector address corresponding with returning destination address signal RAS.During control input S0-S2=4, the input signal that output F becomes input terminal A4 is transfer destination address date JAD, and BOST device 20 carries out unconditional transfer NCJ action, transfers to the test vector address TBA corresponding with transfer destination address date JAD.During control input S0-S2=5, it is ground signalling that output F becomes input terminal A5, BOST device 20 carries out the action of same vector repetitive operation SBR, and based on the output of multiplicity down counter 416, until its count value becomes till 0, repeat to be back to the action of last test vector address.
Fig. 5 is each signal when making 20 actions of BOST device according to embodiment 2-1 with the code NOP that advances test vector address TBA in due form, the sequential chart of data.Suppose that the test vector address control routine TBAC shown in the figure (j) is set as follows with test vector address N, N+1, N+2, N+3, N+4, N+5 accordingly.
N:NOP (mode usually) complys with code 0x1
N+1:NOP complys with code 0x1
N+2:NOP complys with code 0x1
N+3:NOP complys with code 0x1
N+4:NOP complys with code 0x1
N+5:STOP (stopping) complying with code 0x6
With common mode NOP accordingly, among Fig. 5, figure (a) expression initial value register output INR, figure (b) expression totalizer output ADO, figure (f) expression test vector address initial setting trigger pip TBAIT, commencing signal MST is measured in figure (g) expression, figure (h) expression test cycle signal, figure (i) expression test vector address TBA, figure (j) expression test vector address control routine TBAC.
In the example of Fig. 5, the totalizer output ADO of figure shown in (b) is selected, and becomes on the test vector address TBA shown in the figure (i) and sequentially add+1 common mode NOP.The test vector address TBA of figure (i) enters N+1, N+2, N+3, N+4, N+5 from N when every generation test cycle signal TCY.Test vector address control routine TBAC during 0x1, promptly at test vector address TBA during the N to N+4, NOP moves in due form, and stops action when test vector address TBA becomes N+5.
To be expression advance the action of test vector address TBA with NOP in due form and sequential chart when shifting and returning RET and carry out return action by subroutine by subroutine jump SRJ according to embodiment 2-1 to Fig. 6.Suppose that test vector address control routine TBAC is set as follows accordingly with N, N+1, N+2, N+3, N+100, the N+101 of test vector address TBA respectively.
N:NOP complys with code 0x1
N+1:[SJP N+100] comply with code 0x2
N+100:NOP complys with code 0x1
N+101:RET complys with code 0x3
N+2:NOP complys with code 0x1
N+3:STOP complys with code 0x6
[the SJP N+100] of N+1 complys with code 0x2 in the N+1 of test vector address, means to test vector address N+100 to shift; The RET of N+101 complys with code 0x3 in the N+101 of test vector address, means to be back to test vector address N+3.Move accordingly with this, figure (a) expression initial value register output INR among Fig. 6, figure (b) expression totalizer output ADO, figure (c) expression transfer destination address JAD, destination address RAS is returned in figure (d) expression, figure (f) expression test vector address initial setting trigger pip TBAIT, commencing signal MST is measured in figure (g) expression, figure (h) expression test cycle signal TCY, figure (i) expression test vector address TBA, figure (j) expression test vector address control routine TBAC.
In example shown in Figure 6, when the test vector address TBA shown in the figure (i) becomes N+1, carry out subroutine jump SJP, and carry out transfer action to test vector address N+100.In addition, when test vector address TBA becomes N+101, carry out returning the action of RET to the subroutine of test vector address N+3.
By the action shown in this Fig. 6, in different test vector addresses, can specify identical transfer destination address mutually, thereby can reduce the test vector number.
Fig. 7 is the sequential chart of expression when advancing the action of test vector address TBA according to embodiment 2-1 with NOP in due form and carrying out transfer action by unconditional transfer JMP.Test vector address control routine TBAC and test vector address N, N+1, N+2, N+100, N+101, N+102, N+103, the following accordingly setting of N+104.
N:NOP (mode usually) complys with code 0x1
N+1:NOP complys with code 0x1
N+2:[JMP N+100] comply with code 0x4
N+100:NOP complys with code 0x1
N+101:NOP complys with code 0x1
N+102:NOP complys with code 0x1
N+103:STOP (stopping) complying with code 0x6
Address N+2 [JMP N+100] complys with code 0x4, means to test vector address N+100 to shift in the N+2 of test vector address, and in addition, the STOP of address N+103 complys with code 0x6, means to stop (STOP) in the N+103 of test vector address.Move accordingly with this, among Fig. 7, figure (a) expression initial value register output INR, figure (b) expression totalizer output ADO, figure (c) expression transfer destination address JAD, figure (f) expression test vector address initial setting trigger pip TBAIT, commencing signal MST is measured in figure (g) expression, figure (h) expression test cycle signal, figure (i) expression test vector address TBA, figure (j) expression test vector address control routine TBAC.
In the example of Fig. 7, when the test vector address TBA shown in the figure (i) becomes N+2, carry out unconditional transfer JMP to test vector address N+100.
By the action of this Fig. 7, in different test vector addresses, can specify identical transfer destination address mutually, can reduce the test vector number.
Fig. 8 is the sequential chart of expression when advancing the action of test vector address TBA and carrying out repetition REP action with NOP in due form according to embodiment 2-1.N, N+1, N+2, the N+3 of test vector address control routine TBAC and test vector address TBA are set as follows accordingly.
N:NOP (mode usually) complys with code 0x1
N+1:[REP 2] comply with code 0x5
N+2:NOP complys with code 0x1
N+3:STOP (stopping) complying with code 0x6
Address N+1 [REP 2] comply with code 0x5, and the multiplicity that means test vector address N+1 in the N+1 of test vector address is 2, promptly makes it twice of repetition.Move accordingly with this, figure (a) expression initial value register output INR among Fig. 8, figure (b) expression totalizer output ADO, the repeating signal RPD of figure (c) expression multiplicity setting value+1, figure (e) expression multiplicity is set trigger pip RCT, figure (k) expression down counter borrow signal DCB, figure (m) expression test vector address final breech lock trigger pip TBAFR, figure (f) expression test vector address initial setting trigger pip TBAIT, commencing signal MST is measured in figure (g) expression, figure (h) expression test cycle signal, figure (i) expression test vector address TBA, figure (j) expression test vector address control routine TBAC.
In the example of Fig. 8, when the test vector address TBA shown in the figure (i) becomes N+1, carry out twice repetition REP of test vector address N+1, its result has carried out test vector address N+1 three times.
By the action of this Fig. 8, can repeat to take place same test pattern by repeating REP, can reduce the test vector number.
In present embodiment 2-1, can access on the basis of the effect identical with embodiment 1, based on test vector address control routine TBAC and test vector address control data TBAD, can comprise that subroutine jump SJP, subroutine return the diversified control that RET, unconditional transfer JMP and same vector repeat REP etc., and can realize test pattern data TPD modularization, reduce the test vector number.In addition, by producing diversified test pattern data, can carry out diversified functional test.
Embodiment 2-2
Present embodiment 2-2 is the proving installation that is suitable for SIC (semiconductor integrated circuit) of the present invention that the digital circuit of matrix form configuration is tested about semiconductor memory etc., especially in present embodiment 2-2, PG portion 60 has the function that produces the test of heuristics pattern by instruction control.The BOST control part 40 of Fig. 9,32,33 expression present embodiment 2-2 and the structure of PG portion 60, Figure 12, Figure 14, Figure 16 and Figure 18 represent the action timing diagram of present embodiment 2-2.
In the semiconductor memory as DUT10, to line matrix form configuration mutual vertically, their each intersection point place has storage unit respectively to line and many Y for many X.Select many X to line by the X demoder, select many Y to line by the Y demoder.This semiconductor memory selecteed X to line and Y on the storage unit at the intersection point place of line, input is according to the test input pattern signal of test pattern data, therefore test is carried out, so that the test output mode signal that obtains from DUT10 is judged.
The structure of the PG portion 60 of Fig. 9 (a) expression embodiment 2-2 and registers group A430, the B460 that BOST control part 40 is comprised, the structure of C465.Comparand register A451, B451 that Fig. 9 (b) expression registers group A430, B460 are comprised and the structure of significance bit register A452, B452.Figure 10 (a) is illustrated in the structure of the data scrambler 471,472 that the BOST control part 40 shown in Fig. 9 (a) comprised, the structure of Figure 10 (b) expression registers group C465, in addition, the memory address structure of Figure 10 (c) expression data scrambler 466.Figure 11 is illustrated in the structure of the programmable counter 410A that uses among the embodiment 2-2.
In embodiment 2-2, shown in Fig. 9 (a), PG portion 60 comprises that six storage areas are that storage area 611 is to storage area 616.Storage algorithm data generation register control routine ADRC in storage area 616, storage algorithm data generation register control data ADRD in storage area 615, storage test vector address control routine TBAC in storage area 614, storage test vector address control data TBAD in storage area 613, storage A/B/C register switch data RSD in storage area 612, storage test input/determinating mode signal JPS in storage area 611.These codes, data and signal are included in from the test pattern data TPD that TPM portion 50 downloads, and deposited in respectively PG portion 60 address N, N+1 ..., N+M.
The address of PG portion 60 is advanced by the test vector address TBA (by the figure among Figure 12, Figure 14, Figure 16, Figure 18 (i) expression) from programmable counter 410A.Be stored in the algorithm data generation register control routine ADRC (by the figure among Figure 12, Figure 14, Figure 16, Figure 18 (n) expression) of storage area 616, be provided for registers group A430, B450, C460, and the algorithm data generation register that is stored in storage area 615 is provided for registers group A, B with control data ADRD (by the figure among Figure 12, Figure 14, Figure 16, Figure 18 (o) expression).Be stored in the test vector address control routine TBAC (by the figure among Figure 12, Figure 14, Figure 16, Figure 18 (j) expression) of storage area 614 and be stored in the test vector address control data TBAD of storage area 613, be provided for programmable counter 410A.The A/B/C register switch data RSD that is stored in storage area 612 is provided for selector switch 473, and the test input/determinating mode signal JPS that is stored in storage area 611 is provided for WF portion 80.
The BOST control part 40 of embodiment 2-2 is made of a plurality of passages of 0-N passage, each passage with as the semiconductor memory of DUT10, for example many X are corresponding to each bar of line.On this each passage, be respectively equipped with registers group A430, the B460 shown in Fig. 9 (a), C465 and data scrambler 471,472, and selector switch 473.In addition, in this multi-channel structure, be provided with BOST control part 40, PG portion 60 on each passage, and as illustrated in Fig. 4, embodiment 1-1 shown in Figure 5, also set up TMP portion 50, TG portion 70, WF portion 80, output detection unit 85, error message storage part 90 and DUT-BOST I/F portion 95.
Registers group A430 is provided with: control circuit 431, master register A440, comparand register A451, significance bit register A452 and bit comparison portion 456.Control circuit 431 is provided with: AND circuit 432, OR circuit 433 and AND circuit 434.On the input end of AND circuit 432, be supplied to the control routine SA0 that algorithm data generation register is comprised with control routine ADRC.On the input end of OR circuit 433, be supplied to the control routine SA1 that algorithm data generation register is comprised with control routine ADRC.On the input end of AND circuit 434, be supplied to the control routine SA2 that algorithm data generation register is comprised with control routine ADRC.On another input end of AND circuit 434, be supplied to totalizer carry output BAC, and another input end (inverting input) of AND circuit 431 and another input end of OR circuit 433 are supplied with in the output of AND circuit 434 from the carry terminal C0 of registers group B.AND circuit 432 produces control signal S0, and OR circuit 433 produces control signal S1.
Master register A440 is provided with: logic and circuit 441, A+B adding circuit 442, selector switch 443, logic integrated circuit 444, trigger 445, demoder 446, OR circuit 447, AND circuit 448 and phase inverter 449 by turn by turn.Logic and circuit 441 will be imported the logic of A, B and the input A that output offers A+B adding circuit 442 by turn.The input end A of logic and circuit 441 is connected with the output terminal Q of trigger 445 by turn, is supplied on the lead-out terminal 4 that makes significance bit register A452 the output of the anti-phase phase inverter 449 of the output EBA (figure among Figure 12, Figure 14, Figure 16, Figure 18 (p) expression) of significance bit register A452 of output on its input end B.On the input end B of A+B adding circuit 442, be supplied to algorithm data generation register controlled audio data AD RD, this A+B adding circuit 442 will be imported the input end C of the additive operation output F supply selector switch 443 of A, B.On the input end A of selector switch 443, be supplied to algorithm data generation register controlled audio data AD RD, be supplied to the master register B440 output MRB of registers group B460 on its input end B.In the figure of the figure of the figure of the figure of Figure 12 (r2), Figure 14 (r), Figure 16 (r2) and Figure 18 (r), represented the output MRB of this master register B440.
The A+B totalizer 442 of master register A440, the totalizer carry signal AAC of generation registers group A (as the figure among Figure 16 (t) expression) on its carry terminal C0.The totalizer carry signal AAC of this registers group A offers registers group R460.
According to control signal S0-S1, selector switch 443 is selected input A, B, C, and exports at output terminal F.The output F of this selector switch 443 is supplied to the input end A of logic integrated circuit 444 by turn.The input end B of logic integrated circuit 444 by turn is supplied to the output EBA of the lead-out terminal 4 of significance bit register A452, and this by turn the output of logic integrated circuit 444 be supplied to the input end D of trigger 445.
446 couples of control signal S0-S1 of demoder decode, and its output is supplied to the input end of OR circuit 447.The output of OR circuit 447 is supplied to an input end of AND circuit 448.Another input end at this AND circuit 448 is supplied to test cycle signal TCY, and the input end of clock C of trigger 445 is supplied with in the output of AND circuit 448.At the output terminal Q of this trigger 445, the output MRA of output master register A.The figure (r1) of figure (r), Figure 16 of the figure of Figure 12 (r1), Figure 14 and the figure (r) of Figure 18 have represented the output MRA of this master register A440.
The following formation of output F of selector switch 443.Control routine SA0, the SA1 that algorithm data generation register controlled code ADRC is comprised, when SA2 is SA0=0, SA1=0, SA2=0, A is selected in input, algorithm data generation register is used as immediate data with control data ADRD and exports.When control routine SA0=1, control routine SA1=0, control routine SA2=0, B is selected in input, and the output MRB of the master register B of registers group B is used as the output terminal F that data are sent to selector switch 443.When control routine SA0=0, control routine SA1=1, control routine SA2=0, C is selected in input, and the operational data that input end C is imported is output at the output terminal F of selector switch 443.When control routine SA0=X, control routine SA1=X, control routine SA2=1, C is selected in input, from the operational data (concatenation operation: link computation) in the output terminal F of selector switch 443 output of input end C.The output F of this selector switch 443 is via logic integrated circuit and trigger by turn, as the output MRA output of master register A.
Comparand register A451 and significance bit register A452 have the structure shown in Fig. 9 (b) respectively.These registers 451,452 are provided with demoder 453, AND circuit 454 and trigger 455, and comprise 1,2,3 and lead-out terminals 4 of three input terminals.The input end of demoder 453 is connected with input terminal 2, and the output terminal of this demoder 453 is connected with an input end of AND circuit 454.Another input end of AND circuit 454 is connected with input terminal 3, and the output terminal of this AND circuit 454 is connected with the input end of clock C of trigger 455.The input end D of trigger 455 is connected with input terminal 1, and its output terminal Q is connected with lead-out terminal 4.
The terminal 1 of comparand register A451 and significance bit register A452 is supplied to algorithm data generation register control data ADRD respectively, and its terminal 2 is supplied to control signal S0-S1 respectively.The terminal 3 of comparand register A451 and significance bit register A452 is supplied to test cycle signal TCY respectively.On the terminal 4 of comparand register A451, produce the output CRA (by figure (q) expression of Figure 14, Figure 16, Figure 18) of comparand register A.The output CRA of this comparand register A451 is sent to the input end B of bit comparator 456, and the input end A of this bit comparator 456 is supplied to the output MRA of master register A440.Bit comparator 456 compares by turn to these inputs A, B, and produces the consistent signal CCA of comparison (by figure (s) expression of Figure 14, Figure 16, Figure 18) of registers group A.This more consistent signal CCA becomes high level H when input A=input B.
Significance bit register A452 produces output EBA.The figure of Figure 12, Figure 14, Figure 16, Figure 18 (p) represents this output EBA.This output EBA is the output that the significance bit place becomes high level H, and this output is sent to the input end B of a logic integrated circuit 444.
The demoder 453 of the demoder 446 of master register A440, the demoder 453 of comparand register 451 and significance bit register 452 is all decoded to control signal S0-S1.The structure of these demoders is designed to can be by different mutually control signal S0-S1 output high level; As a result, at control signal S0-S1 mutually not simultaneously, any one among master register A440, comparand register A451 and the significance bit register A452 will be moved selectively.
Registers group B460 and registers group A430 similarly constitute.In registers group B460, the master register A440 of registers group A, comparand register A451, significance bit register A452, be called master register B, comparand register B, significance bit register B, A452 is identical but its structure is with master register A440, comparand register A451, significance bit register.In addition, the control circuit 431 outside these registers, bit comparator 456 also are contained in registers group B460 with identical structure.The A+B totalizer 442 of registers group B produces carry output BAC on carry terminal C0, this output is supplied to the AND circuit 434 of registers group A430.The significance bit register B452 of registers group B460 produces output EBB.This output EBB represents in the figure of Figure 12, Figure 14, Figure 16, Figure 18 (p) with output EBA.The comparand register B451 of registers group B produces output CRB.This output CRB represents in the figure of Figure 14, Figure 16, Figure 18 (q) with output CRA.The bit comparator 456 of registers group B460 produces the same more consistent signal CCB of output with the bit comparator 456 of registers group A.This more consistent signal CCB represents in the figure of Figure 14, Figure 16, Figure 18 (s).
The output MRA of the master register A440 of registers group A430 offers data scrambler 471, and the output MRB of the master register B of registers group B460 offers data scrambler 472.Figure 10 (a) is for being drawn out of the data scrambler 471,472 of independent expression, this data scrambler 471,472 is made of semiconductor memory, input end IN is supplied to the memory address of its semiconductor memory, and the memory data corresponding with its memory address exported from output terminal OUT.By in the semiconductor memory of composition data scrambler 471,472, writing translation data in advance, will make the output OUT after the conversion to input IN according to translation data again and exported.By input IN is periodically changed, output OUT is changed on algorithm based on translation data.
Registers group C465 is provided with data scrambler 466 and trigger 467,478.Represented this registers group C465 among Figure 10 (b).Data scrambler 466 constitutes master register C, and, comprise 1,2,3 and output terminals 4 of three input ends.At the output MRA of input end 1 input, at the output MRB of input 2 inputs from the master register B of registers group B460 from the master register A of registers group A430.At the input end D of trigger 467, provide algorithm data generation register to count SCN with the scrambling that control routine ADRC is comprised.An input end of AND circuit 469 is supplied to algorithm data generation register and sets a startup yard SCNE with the scrambler numbering that control routine ADRC is comprised, and its another input end is supplied to test cycle signal TCY.The output terminal of this AND circuit 469 is connected with the input end of clock C of trigger 467, and the output terminal Q of this trigger 467 is connected with the input end 3 of data scrambler 466.
Data scrambler 466 is by to constitute the input of input end 1,2,3 semiconductor memory as the address.Shown in Figure 10 (c), count SCN for the scrambling of input end 3, give the output MRB of master register B of input end 2 and the output MRA that gives the master register A of input end 1, be used as the address number of distributing to data scrambler 466.In data scrambler 466, write translation data in advance, and based on the output MRA of master register A, B, the combination of MRB, the data output that output changes on algorithm.The call number of the data algorithm that SCN is equivalent to be output is counted in scrambling.When a scrambling number setting startup sign indicating number SCNE was high level H, this scrambling was counted SCN and is passed through test cycle signal TCY by trigger 467 breech locks.Count the breech lock of SCN by this scrambling, just need not set scrambling on each test vector address counts SCN.
Have, the output terminal 4 of data scrambler 466 is connected in the input end D of trigger 468 again, and its input end of clock C is supplied to test cycle signal TCY.The output MRC of registers group C465 is (by Figure 18 (v) expression), the output terminal Q output of slave flipflop 468.
Selector switch 473 is provided with input end A, B, C and output terminal F, and control input end S *In the output of input end A input data scrambler 471, in the output of input end B input data scrambler 472, and at the register output MRC of input end C input from registers group C465.At the control input end of selector switch 473 S *, input is stored in the A/B/C register switch data RSD of storage area 612 of PG portion 60, selects among input A, B, the C any one based on this data selector 473, simultaneously to output terminal F output test mode signal TPS.
As previously mentioned, the circuit of the BOST control part 40 of Fig. 9 (a) is made of a plurality of passages such as 0-N passages, and Fig. 9 (a) represents one of them passage.Passage 0-N many X with the storer of DUT10 respectively is corresponding to line.That is to say, from as each X of the semiconductor memory of DUT10 to each corresponding passage of line, a plurality of test mode signal TPS are by simultaneously and line output.Each test mode signal TPS is converted into test input pattern signal TIP in the WF of each passage portion 80, and each X is supplied with DUT10 concurrently to the test input pattern signal TIP of line.Test input/determinating mode signal JPS, supplied with the output detection unit 85 of each passage from the storage area 611 of the PG portion 60 of each passage, with compare and the test address signal MAD when in the error message storage part 90 of each passage setting, depositing wrong the generation in to the test output mode signal TOP of each passage output from DUT10.
With reference to Figure 11, just the programmable counter 410A of embodiment 2-2 is elaborated.This programmable counter 410A is similar to the programmable counter 410 of Fig. 4 (a), but also is provided with selector switch 426, control circuit 427 on the basis of this programmable counter 410.Other structure is identical with programmable counter 410 shown in Figure 4.
Selector switch 426 is arranged between the input end A1 of totalizer 414 and selector switch 411.This selector switch 426 is provided with the input end A and the input end B of reception from the test vector address control data TBAD of the storage area 613 of PG portion 60 that is connected with the OUT terminal of totalizer 414; And, select their input A, B based on the more consistent signal CCA of registers group A, B, the CCB that give control terminal S (by figure (s) expression of Figure 14, Figure 16, Figure 18).
Control circuit 427 is provided with: OR circuit 428 and AND circuit 429a, 429b, 429c, and demoder 429d.Demoder 429d decodes to the control signal S3-S4 that test vector address control routine TBAC is comprised, and in its terminal 1 to 4 output.The input end of AND circuit 429a is connected with the terminal 1 of demoder 429d, is supplied to the bit comparison output CCA of the bit comparator A456 of registers group A430 on its another input end.The input end of AND circuit 429b is connected with the terminal 2 of demoder 429d, is supplied to the bit comparison output CCB of the bit comparator B456 of registers group B on its another input end.AND circuit 429c is three input AND circuit, is supplied to bit comparison output CCA on an one input end, and its another input end is provided bit comparison output CCB, and its 3rd input end is connected with the terminal 3 of demoder 429d.OR circuit 428 is supplied to the output of AND circuit 429a, 429b, 429c, and is provided the output of the terminal 0 of demoder 429d.The output of OR circuit 428 (anti-phase output) becomes the more consistent signal CCS of registers group A, B.When the more consistent signal CCS of registers group A, B that supplies with control terminal S became low level L, selector switch 426 offered the test vector address control data TBAD that is added to input end B the input end A1 of selector switch 411.
Figure 12 is expression, produces test vector address TBA with common mode NOP in embodiment 2-2, and with import immediately and register between the combination that transmits produce master register A440 and master register B440 output the time action timing diagram.
Among Figure 12, the output INR of figure (a) expression initial value register 413, the totalizer output ADO of figure (b) expression totalizer 414, figure (c) expression transfer destination address JAD, figure (f) expression test vector address initial setting triggers TBAIT, commencing signal MST is measured in figure (g) expression, figure (h) expression test cycle signal TCY, figure (i) expression test vector address TBA, figure (j) expression test vector address control routine TBAC, figure (n) expression algorithm data generation register controlled code ADRC, figure (o) expression algorithm data generation register controlled audio data AD RD, output EBA and the EBB of figure (p) expression significance bit register A452 and B452, the output MRA of figure (r1) expression master register A440, the output MRB of figure (r2) expression master register B440.
In Figure 12, with respect to address value N, N+1, N+2, the N+3 of test vector address TBA, test vector address control routine TBAC and algorithm data generation control routine ADRC such as Figure 13 set.
In Figure 13, NOP means common mode, and code is made as 0x1.In addition, STOP means the mode of stopping, and code is made as 0x6.
When test vector address TBA was N, test vector address control routine TBAC became the 0x1 that means common mode NOP, set initial value simultaneously in initial value register 413, and algorithm data generation control routine ADRC becomes EA=0xFF, EB=0xFF.EA=0xFF means 4 of significance bit register A452 each under is thereon set 1111 respectively.When test vector address TBA was N, algorithm data generation register controlled audio data AD RD was 0xFF, and this audio data AD RD is located at the significance bit register A452 of registers group A430, and significance bit register A452 also is set in 0xFF.Similarly, EB=0xFF means that significance bit register B452 is set in 0xFF, and the significance bit register B452 of registers group B460 also is set in 0xFF.Its result, the position 0～7 of master register A440, B440 becomes significance bit.
When test vector address TBA is N+1, test vector address control routine TBAC is the 0x1 of the common mode NOP of indication, algorithm data generation register controlled code ADRC becomes MA=0x00, MB=0xFF, with respect to master register A440, algorithm data generation register controlled audio data AD RD becomes 0x00; With respect to master register B460, algorithm data generation register controlled audio data AD RD becomes 0xFF.As a result, the output MRA of master register A440 becomes 0x00, simultaneously master register A440 up and down each 4 all become 0000.The output MRB of master register B440 becomes 0xFF, master register B440 up and down each 4 all become 1111.
When test vector address TBA is N+2, test vector address control routine TBAC is the 0x1 that means common mode NOP, algorithm data generation register controlled code ADRC becomes MA=MB (MB → MA transmits), MB=MA (MA → MB transmits), the output MRA of master register A440 becomes 0xFF, and the output MRB of master register B440 becomes 0x00.
When test vector address TBA was N+2, test vector address control routine TBAC became and means the 0x6 that stops STOP, thereby stopped action.
Figure 14 is expression, produces test vector address TBA with the combination of common mode, register comparison, and the action timing diagram during with register is imported immediately, the combination of register computing produces master register A440, B440 output.In the action of this Figure 14, with respect to address value N, N+1, N+2, N+3, N+4, the N+5 of test vector address TBA, test vector address control routine TBAC and algorithm data generation register controlled code ADRC are set as shown in figure 15.[MAB/CAB N+3] at the test vector address control routine TBAC shown in Figure 15, mean to transfer to and specify transfer destination address N+3, output valve with comparand register A451, B451 is consistent respectively up to the output valve of master register A440, B440, as then entering next test vector address for unanimity.
In Figure 14, the output INR of figure (a) expression initial value register 413, the additive operation output ADO of figure (b) expression totalizer 414, figure (c) expression transfer destination address JAD, figure (f) expression test vector address initial setting triggers TBAIT, commencing signal MST is measured in figure (g) expression, figure (h) expression test cycle signal TCY, figure (i) expression test vector address TBA, figure (j) expression test vector address control routine TBAC, figure (n) expression algorithm data generation register controlled code ADRC, figure (o) expression algorithm data generation register controlled audio data AD RD, figure (p) expression significance bit register A452, the output EBA of B452, EBB, figure (q) expression comparand register A451, the output CRA of B451, CRB, figure (r) expression master register A440, the output MRA of B440, MRB, figure (s) expression registers group A, the consistent signal CCA of the comparison of B, CCB.
When test vector address TBA was N, algorithm data generation register controlled code ADRC became EA=0xFF, EB=0xFF, carries out the initial setting identical with the occasion of Figure 12 on significance bit register A452, B452.
When test vector address TBA was N+1, algorithm data generation register controlled code ADRC became CA=0xFF, CB=0xFF.This means on comparand register A451, B451 and set 0xFF, the immediate value of algorithm data generation register controlled audio data AD RD is imported into comparand register A451, B451, and 0xFF is imported into comparand register A451, B451.
As test vector address TBA is N+2, and algorithm data generation register controlled code ADRC just becomes MA=0x00, MB=0x00.This means on master register A440, B440 and set 0x00 that the immediate value of algorithm data generation register controlled audio data AD RD is imported into master register A440, B440, sets 0x00 on master register A440, B440.
If test vector address TBA is N+3, algorithm data generation register controlled code ADRC just becomes MA=MA+1, MB=MB+1.This means on the output valve of master register A440, the B440 in last cycle to add 1, and its result be set on master register A440, the B440 that output MRA, the MRB of master register A440, B440 become 0x01.
If test vector address TBA is N+4, just become the action of MAB/CAB N+3, this means that test vector address TBA transfers to appointment transfer destination address N+3, output valve up to master register A440, B440 is consistent with the output valve of comparand register A451, B451, and test vector address TBA transfers to N+3 once more.In addition, algorithm data generation register controlled code ADRC becomes MA=MA+1, MB=MB+1.This means on the output valve of master register A440, the B440 in last cycle to add 1, and its result is set in master register A440, B440, output MRA, the MRB of master register A440, B440 become 0x02.
Repeat this action, become the output 0xFF of comparand register A451, B451 up to output MRA, the MRB of master register A440, B440.Output MRA, MRB as master register A440, B440 are consistent with the output of comparand register A451, B451, just produce more consistent signal CCA, CCB from bit comparator 456, and add 1 on the output 0xFF of master register A440, B440.If the output 0xFF at master register A440, B440 adds 1, then output MRA, the MRB of master register A440, B440 just become 0x100, but, because output EBA, the EBB of significance bit register A452, B452 are set at 0xFF, therefore, output MRA, the MRB of master register A440, B440 are back to 0x00.
Like this, as shown in figure 14, output MRA, the MRB of master register A440, B440 import immediately with the combination of register computing based on register and produce, and change to 0xFF from 0x00.
Figure 16 is that expression produces test vector address TBA with the combination of common mode and register comparison, and the action timing diagram when importing combination with the register concatenation operation immediately and produce output MRA, the MRB of master register A440, B440 with register.In the action of this Figure 16,, set test vector address control routine TBAC and algorithm data generation register controlled code ADRC as shown in figure 17 with respect to address value N, N+1, N+2, N+3, the N+4 of test vector address TBA.In Figure 17, the code [MAB/CAB N+3] of the test vector address control routine TBAC corresponding with the address value N+3 of test vector address TBA means: test vector address TBA transfers to and specifies transfer destination address N+3, output valve with comparand register A451, B451 is consistent respectively up to the output valve of master register A440, B440, if unanimity then enter into next test vector address.In this Figure 16, when test vector address TBA became N+3, the action of MAB/CAB N+3 took place, test vector address TBA repeats N+3.
In Figure 16, the output INR of figure (a) expression initial value register 413, the additive operation output ADO of figure (b) expression totalizer 414, figure (c) expression transfer destination address JAD, figure (f) expression test vector address initial setting triggers TBAIT, commencing signal MST is measured in figure (g) expression, figure (h) expression test cycle signal TCY, figure (i) expression test vector address TBA, figure (j) expression test vector address control routine TBAC, figure (n) expression algorithm data generation register controlled code ADRC, figure (o) expression algorithm data generation register controlled audio data AD RD, figure (p) expression significance bit register A452, the output EBA of B452, EBB, figure (q) expression comparand register A451, the output CRA of B451, CRB, the output MRA of figure (r1) expression master register A440, the output MRB of figure (r2) expression master register B440, the carry output AAC that represents the A+B totalizer 422 of registers group A at figure (t), figure (s) expression registers group A, the consistent signal CCA of the comparison of B, CCB.
Action when test vector address TBA is N, N+1, N+2 is identical with the action shown in Figure 13.When test vector address TBA became N+3, with the action of MAB/CAB N+3, algorithm data generation register controlled code ADRC indicated MA=MA+1, LMB+1.MA=MA+1 means on the output valve of the master register A440 in last cycle and adds 1, and whenever test vector address TBA becomes N+3, master register A440 adds 1 in its output.LMB+1 means, when the A+B of master register A440 totalizer 442 produces carry output AAC, adds 1 on master register B440.Therefore, when test vector address TBA repeated N+3, master register B440 repeated the concatenation operation of the output in last cycle, when producing carry output AAC when the output of master register A440 becomes 0xFF, added 1 in the output of master register B440.
This action is carried out always, becomes 0xFF up to the output MRA of master register A440, and the output MRB of master register B440 also becomes 0xFF.If output MRA, the MRB of master register A440, B440 all become 0xFF, so because from output CCA, the CCB of the bit comparator 456 of registers group A, B, output MRA, the MRB of master register A440, B440 all are back to 0x00.
Figure 18 is expression, produces test vector address TBA with the combination of common mode and register comparison, and the action timing diagram when importing combination with the register computing immediately and produce output MRA, the MRB of master register A440, B440 with register.In the action of this Figure 18,, set test vector address control routine TBAC and algorithm data generation register controlled code ADRC as shown in figure 19 with respect to address value N, N+1, N+2, N+3, N+4, the N+5 of test vector address TBA.In Figure 19, the code [MAB/CAB N+3] of the test vector address control routine TBAC corresponding with the address value N+4 of test vector address TBA means, transfer to and specify transfer destination address N+3, the output valve with comparand register A451, B451 is consistent respectively up to the output valve of master register A440, B440; If become unanimity then enter next test vector address.In Figure 18, when test vector address TBA became N+4, the action of [MAB/CAB N+3] took place, test vector address TBA repeats to be back to the action of N+3.
In Figure 18, the output INR of figure (a) expression initial value register 413, the additive operation output ADO of figure (b) expression totalizer 414, figure (c) expression transfer destination address JAD, figure (f) expression test vector address initial setting triggers TBAIT, commencing signal MST is measured in figure (g) expression, figure (h) expression test cycle signal TCY, figure (i) expression test vector address TBA, figure (j) expression test vector address control routine TBAC, figure (n) expression algorithm data generation register controlled code ADRC, figure (o) expression algorithm data generation register controlled audio data AD RD, figure (p) expression significance bit register A452, the output EBA of B452, EBB, figure (q) expression comparand register A451, the output CRA of B451, CRB, figure (r) expression master register A440, the output MRA of B440, MRB, figure (the output MRC that v) represents master register C466, figure (s) expression registers group A, the consistent signal CCA of the comparison of B, CCB.
When test vector address TBA was N, algorithm data generation register controlled code ADRC was set as EA=0xFF, EB=0xFF, MC=0x00.That is to say that significance bit register A452, B452 are set in 0xFF, master register C465 is set in 0x00.In master register C465, scrambling is counted SCN and is set at 0x00, and the data algorithm that master register C465 counts 0x00 with scrambling produces output MRC.If test vector address TBA becomes N+1, algorithm data generation register controlled code ADRC just becomes CA=0xFF, CB=0xFF, all is set at 0xFF on comparand register A451, the B451.If test vector address TBA becomes N+2, algorithm data generation register controlled code ADRC becomes MA=0x00, MB=0x00, is set at 0x00 on master register A440, the B440.If test vector address TBA becomes N+3, algorithm data generation register controlled code ADRC just becomes MA=MA+1, MB=MB+1, add 1 respectively on the output valve of master register A440, the B440 in last cycle, output MRA, the MRB of master register A440, B440 all become 0x01.
TBA becomes N+4 as the test vector address, then test vector address control routine TBAC becomes 0018, action by MAB/CAB N+3 forms and makes test vector address TBA be back to the indication of N+3, algorithm data generation register controlled code ADRC becomes MA=MA+1, MB=MB+1 simultaneously, adds 1 again in the output of master register A440, B440.TBA is back to N+3 as the test vector address, then algorithm data generation register controlled code ADRC just becomes MA=MA+1, MB=MB+1, add 1 respectively on the output valve of master register A440, the B440 in last cycle, output MRA, the MRB of master register A440, B440 all in turn is increased to 0xFF.Output MRA, MRB as master register A440, B440 become 0xFF, and then by output CCA, the CCB of bit comparator 456, output MRA, the MRB of master register A440, B440 are back to 0x00.
In action shown in Figure 180, can therefore, can reduce the test vector number with different test mode signals with transfer destination address pattern sharing.
In present embodiment 2-2, can access the effect identical with embodiment 1, the test mode signal TPS of algorithm can also take place to produce with register controlled data RDRD with register controlled code ADRC and algorithm data generation in addition based on algorithm data, thereby, can reduce the test vector number, and can produce multiple test pattern data and carry out multiple functional test.In addition, by means of multi-channel structure, can in each passage 0～N, walk abreast and produce test mode signal TPS, and can provide concurrently a plurality of for example respectively with X to the corresponding test mode signal TPS of line, thereby can be to the digital circuit that for example DUT10 comprised, particularly memory circuit is effectively tested.
Embodiment 2-3
Present embodiment 2-3 relates to and is provided with proving installation serializer 475, SIC (semiconductor integrated circuit) of the present invention that the parallel test mode signal TPS that takes place is converted to the serial test signal.Figure 20 represents the structure of the BOST control part 40 of present embodiment 2-3, and Figure 21 represents the detailed structure of these BOST control part 40 employed serializers, and Figure 22 represents the action timing diagram of this serializer.
In present embodiment 2-3, be provided with serializer 475 and test pattern generator 619.Serializer 475 is comprised by BOST control part 40, and test pattern generator 619 is comprised by PG portion 60.Serializer 475 is provided with a plurality of input terminal IN1 to INN at input side, is provided with a plurality of lead-out terminal OUT1 to OUTN at outgoing side.Test pattern generator 619 is multi-channel structures, at a plurality of channel C H (1) side by side parallel test pattern data TPD that produces to the CH (N).The test pattern data that these are parallel is represented with symbol P-TPD especially.Serializer 475 has such function: convert these to serial test data S-TPD from channel C H (1) to the parallel test mode data P-TPD of CH (N), and export at each lead-out terminal OUT1 to OUTN.But serializer 475 also can intactly be exported parallel test mode data P-TPD.
As shown in figure 21, serializer 475 is multi-channel structures, promptly comprises a plurality of channel C H1 to CHN.Each self-forming input terminal IN1 to INN on these channel C H1 to CHN, and form lead-out terminal OUT1 to OUTN.On the channel C H1 to CHN-1 of serializer 475, connect selector switch 476 and trigger 477 respectively.On the channel C HN of serializer 475, only connect trigger 477.Selector switch 476 is provided with input end A, B and control terminal S, and output F.On the input end A of each selector switch 476 that is provided with on the channel C H1 to CHN-1, be connected with input terminal IN1 to INN-1 respectively.And the input end B of each selector switch 476, the output terminal Q with the trigger 477 that is provided with at next channel C H2 to CHN is connected respectively.
The output F of each trigger 477 of channel C H1 to CHN is connected with lead-out terminal OUT1 to OUTN respectively.On the input end of clock of these triggers 477, be supplied to test cycle signal TCY.
Serializer 475 also comprises set-reset flip-floop 478.This set-reset flip-floop 478 comprises set input S and the RESET input R, and its output terminal O is connected with the control terminal S of each selector switch 476.In this set-reset flip-floop 478, owing to conversion ON signal CON becomes high level H, its output O just becomes high level H so as set input S, and the input end B of each selector switch 476 is connected with output terminal F.If the input R that resets of set-reset flip-floop 478 is owing to conversion OFF signal COF becomes high level H, its output O just becomes low level L, and each selector switch 476 switches, and supplies with output F will import A.
Figure 22 (e) expression conversion OFF signal COF, Figure 22 (f) expression conversion ON signal CON.Receive conversion OFF signal COF at set-reset flip-floop 478, under the input end A of each selector switch 476 and the state that output terminal F is connected, on each lead-out terminal OUT1 to OUTN of serializer 475, output Figure 22 (a) is (c) parallel test pattern data P-TDP shown in (d) (b).Test pattern data P-TDP that should be parallel, the first test period TA (TA=N * TCY), supply with input terminal IN1 to INN test pattern data DA (1) ..., DA (N-2), DA (N-1), DA (N) be by intactly and line output.And with the continuous second test period TB of test period TA (TB=N * TCY), intactly and line output test pattern data DB (1) ..., DB (N-2), DB (N-1), DB (N).
As change ON signal CON and become high level H, the input end B of each selector switch 476 is connected with output terminal F, the test pattern data S-TPD of the serial shown in Figure 22 (g) occurs.Shown in Figure 22 (g), in the test pattern data S-TPD of this serial, with the test cycle signal TCY shown in Figure 22 (h) synchronously, the output of lead-out terminal OUT1 to OUTN is switched successively.Figure 22 (g) illustration appear at the test pattern data TPDS of the serial of lead-out terminal OUT1, wherein, at the first test period TA, test data DA (1), DA (2) ..., DA (N-1), DA (N) and test cycle signal TCY synchronously, output serially successively.Similarly, at the second test period TB, test data DB (1), DB (2) ..., DB (N-1), DB (N) exported successively.
According to present embodiment 2-3, can access the effect identical with embodiment 1, in addition, because BOST control part 40 is provided with serializer 475, therefore, the parallel test mode data-switching can be become the serial test pattern data export, and need be at pack into the test pattern data of the mode data that is used to produce serial of TPM portion 50.In addition, therefore PG portion 60 can reduce its required memory capacity, can carry out the functional test based on the test pattern data of serial simultaneously, does not obtain special test pattern data, also can carry out the functional test project that can adapt.
Embodiment 2-4
Embodiment 2-4 to embodiment 2-1, embodiment 2-2, embodiment 2-3 made up, the embodiment of the proving installation of SIC (semiconductor integrated circuit) of the present invention.Figure 23 represents the structure of present embodiment 2-4.Present embodiment 2-4 is provided with: PG portion 60, programmable counter 410 or 410A, registers group 430,460,465, data scrambler 471,472, selector switch 480, and serializer 475.PG portion 60 constitutes as embodiment 2-2, and programmable counter 410,410A constitute as embodiment 2-1,2-2.Registers group 430,460,465 and data scrambler 471,472 constitute as embodiment 2-2.Serializer 475 constitutes as embodiment 2-3.
Selector switch 480 has the N channel architecture that a plurality of passages constitute, and each passage is disposed.Selector switch 480 usefulness are switched input end A that is connected with PG portion 60 and the input end B that is connected with data scrambler 471,472 from the control signal S of PG portion 60.Serializer 475 will convert the test pattern data S-TPD of serial on demand from the parallel test pattern data P-TPD of selector switch 480.
In present embodiment 2-4, can obtain the effect identical with embodiment 1, can produce multiple test pattern data in addition, and adapt to multiple functional test easily digital circuit.
Embodiment 2-5
Present embodiment 2-5 has the structure of each circuit shown in Figure 23 being concentrated by processor P RS.Figure 24 represents the structure of present embodiment 2-5.Processor P RS has gathered following each functions of components: PG portion 60 shown in Figure 23, TG portion 70, programmable counter 410,410A, registers group 430,460,465, data scrambler 471,472, selector switch 480, and serializer 475.This processor P RS is made of CPU, DSP etc.
In present embodiment 2-5, can access the effect identical with embodiment 2-4, can further simplify BOST device 20 simultaneously.
Embodiment 2-6
Among the present embodiment 2-6, the proving installation of SIC (semiconductor integrated circuit) of the present invention has been expanded the function of TG portion 70, and done the improvement make timing condition variable.Figure 25 represents the one-piece construction according to the proving installation of present embodiment 2-6, and Figure 26 represents its BOST control part 40 and TG portion 70, WF portion 80 and output detection unit 85, and the detailed structure of DUT-BOST I/F portion 95.Figure 27 is the action timing diagram of present embodiment 2-6.
In Figure 25, the one-piece construction of present embodiment 2-6 is described, but its one-piece construction is very similar to the one-piece construction of the embodiment 1 shown in Fig. 1.In the one-piece construction of present embodiment 2-6, TG portion 70 also provides set clock signal SCLK and reset clock signal RCLK to BOST control part 40 providing beyond test cycle signal TCY, the gating signal STB.Set clock signal SCLK and reset clock signal RCLK replace the clock signal clk of embodiment 1 and produce.Other structure is identical with Fig. 1, and identical part is omitted its explanation with identical symbolic representation.
The detailed circuit of Figure 26, also similar to the detailed circuit of Fig. 2.In this detailed circuit, TG portion 70 is provided with test cycle signal generation circuit 700A, set clock signal generating circuit 710A, reset clock signal generation circuit 710B and gating signal generation circuit 715A, and the structure of these signal generating circuits 700A, 710A, 710B, 715A is different with the detailed circuit of Fig. 2.In addition, except memory address counter 401,402, BOST control part 40 also is provided with and begins to trigger generation circuit 403.Other structure is identical with the detailed circuit of Fig. 2, and identical part is omitted its explanation with identical symbolic representation.
Test cycle signal generation circuit 700A shown in Figure 26 is provided with: timing data storer 720, a pair of trigger 721 and 722, a pair of delay circuit 723 and 724, pair of O R circuit 725 and 726 and OR circuit 727.Timing data storer 720 receives from PG portion 60 and regularly organizes signal TGS.This is regularly organized signal TGS and is formed by the test pattern data TPD that downloads to PG portion 60 from TPM portion 50.This is regularly organized signal TGS and gives test cycle signal TCY with the timing changeable.Timing data signal TDS shown in Figure 27 (b) takes place in timing data storer 720.This timing data signal TDS offers the memory address signal (by the figure (a) of Figure 27 expression) of PG portion 60 based on memory address counter 402, reads from timing data storer 720.
Trigger 721,722 is respectively equipped with: receive the input end D and the output terminal Q that is connected with delay circuit 723,724 of timing data signal TDS, and input end of clock C.Delay circuit 723,724 is provided with in terminal and Out terminal and control input end S, and the output terminal Q of trigger 721,722 is connected with the control input end S of delay circuit 723,724 respectively.The Out terminal of delay circuit 723,724 is connected with each input end of OR circuit 727, and the output of this OR circuit 727 becomes test cycle signal TCY.OR circuit 725 is OR circuit that an input end is only arranged, and this input end is connected with the Out terminal of delay circuit 724, and the output terminal of OR circuit 725 is connected with the in terminal of delay circuit 723.OR circuit 726 has two input ends, on input end, receive from beginning and trigger the beginning trigger pip STS that circuit 403 takes place, and its another one input end is connected with the Out terminal of delay circuit 723 therein.
Test cycle signal generation circuit 700A receives beginning trigger pip STS and moves, and, after the time delay of delay circuit 723,724, produce test cycle signal TCY.This time delay can be by the timing data signal TDS change from timing data storer 720.Test cycle signal TCY also offers set clock signal generating circuit 710A, reset clock signal generation circuit 710B and gating signal generation circuit 715A except offering memory address counter 401.
Set clock signal generating circuit 710A, reset clock signal generation circuit 710B and gating signal generation circuit 715A, has identical structure with test cycle signal generation circuit 700A, they are respectively equipped with: timing data storer 720, a pair of trigger 721,722, a pair of delay circuit 723,724, and OR circuit 725,726,727.
Set clock signal generating circuit 710A acceptance test periodic signal TCY and moving after the time delay of delay circuit 723,724, produces set clock signal SCLK.This set clock signal SCLK represents in Figure 27 (d), it have tsc0 time delay, tsc1 with respect to test cycle signal TCY ..., tsc6.Can change these time delays in each cycle of test cycle signal TCY, tsc0 time delay, the tsc1 in these each cycles ..., tsc6, can be adjusted by timing data storer 720 at the interior dress of set clock signal generating circuit 710A.This timing data storer 720 is supplied to and regularly organizes signal TGS.
Reset clock signal generation circuit 710B acceptance test periodic signal TCY and moving after the time delay of delay circuit 723,724, produces reset clock signal RCLK.This reset clock signal RCLK represents in Figure 27 (e), it have trc0 time delay, trc1 with respect to test cycle signal TCY ..., trc6.Can change these time delays in each cycle of test cycle signal TCY, trc0 time delay, the trc1 in these each cycles ..., trc6, can be adjusted by timing data storer 720 at the interior dress of reset clock signal generation circuit 710B.This timing data storer 720 is supplied to and regularly organizes signal TGS.
Similarly, gating signal generation circuit 715A acceptance test periodic signal TCY and moving, and, after the time delay of delay circuit 723,724, produce gating signal STB.This gating signal STB represents in Figure 27 (f), it have tst0 time delay, tst1 with respect to test cycle signal TCY ..., tst6.Can change these time delays in each cycle of test cycle signal TCY, tst0 time delay, the tst1 in these each cycles ..., tst6, can be adjusted by timing data storer 720 at the interior dress of gating signal generation circuit 715A.This timing data storer 720 is supplied to and regularly organizes signal TGS.
In the action timing diagram of embodiment 2-6 shown in Figure 27, test output mode signal TOP shown in the figure (i) is 1 o'clock at the test mode signal TPS shown in Figure 27 (h), response set clock signal SCLK becomes high level H, and response reset clock signal RCLK becomes low level L.In addition, this test output mode signal TOP is 0 o'clock at test mode signal TPS, even exist set clock signal SCLK also to maintain low level L.The timing of this test output mode signal TOP, can be made as by timing set clock signal SCLK and reset clock signal RCLK variable become variable.Concerning test input pattern signal TIP too.In addition, when the test input/determinating mode signal JPS shown in Figure 27 (g) was decision state, output decision circuit 85 was implemented to judge that the timing of this gating signal STB also can change by gating signal STB.
Like this, in embodiment 2-6, can change the timing of test input pattern signal TIP and test output mode signal TOP, also can change output and judge the timing of the gating signal STB of usefulness, therefore, can adapt to multiple functional test, make more effective test become possibility digital circuit.
Embodiment 2-7
Among the present embodiment 2-7, the proving installation of SIC (semiconductor integrated circuit) of the present invention can change the voltage level of the test input pattern signal TIP of output test mode signal TPS of detection unit 85 and DUT-BOST I/F portion 95.Figure 28 has at length represented output detection unit 85 and the DUT-BOST I/F portion 95 of present embodiment 2-7.
At first, DUT-BOST I/F portion 95 is provided with: driver 965, high-side voltage generator 966, low level side voltage generator 967, input and output change-over switch 968, judgement high-side comparer 969, judgement low level side comparer 970, judgement high-side voltage generator 971 and judgement low level side voltage generator 972.High-side voltage generator 966, low level side voltage generator 967, judgement are made of digital to analog converter (DAC) respectively with high-side voltage generator 971 and judgement low level side voltage generator 972.
Driver 965 is provided with IN terminal and OUT terminal and Vh terminal and Vl terminal.The IN terminal of this driver 965, be supplied to test input pattern signal TIP from WF portion 80, its VH terminal is supplied to the high level voltage VH from high-side voltage generator 966, and its Vl terminal is supplied to the low level voltage VL from low level side voltage generator 967.The OUT terminal of driver 965 is connected with input and output change-over switch 968.High-side voltage generator 966 can do to provide high level voltage VH after voltage changes, and low level side voltage generator 967 can do to provide low level voltage VL after voltage changes.Therefore, on the OUT of driver 965 terminal, can change high level voltage VH and the low level voltage Vl of test input pattern signal TIP, this test input pattern signal TIP supplies with DUT10 via input and output change-over switch 968.Input and output change-over switch 968 conducting when test input pattern signal TIP is provided to DUT10 disconnects when output detection unit 80 usefulness test mode signal TPS judge test output mode signal TOP.
Judge to be provided with "+" input end, "-" input end and OUT terminal, anti-phase comparison is carried out in "+" input and "-" input with high-side comparer 969."+" input end of this comparer 969 is supplied to from the judgement high level voltage VOH that judges with high-side voltage generator 971; Its "-" input end is connected with the outgoing side of input and output change-over switch 968, is supplied to the test input pattern signal TIP that VIN promptly tests output mode signal TOP or exported by input and output change-over switch 968.Judge also to be provided with "+" input end, "-" input end and OUT terminal, noninverting comparison is carried out in "+" input and "-" input with low level side comparer 970."+" input end of this comparer 970 is supplied to the test input pattern signal TIP that VIN promptly tests output mode signal TOP or exported by input and output change-over switch 968; Its "-" input end is supplied to from the judgement low level voltage VOL that judges with low level side voltage generator 972.
Judge with 969 couples of VIN of high-side comparer and detect than VOH is high still low that if VIN＞VOH just is judged as normally, its output becomes low level L, if VIN＜VOH just is judged as mistake, its output becomes high level H.And, judge with 970 couples of VIN of low level side comparer and detect that if VIN＜VOL just is judged as normally, its output becomes low level L than the low still height of VOL, if VIN＞VOL just is judged as mistake, its output becomes high level H.
Output detection unit 85 is provided with: three AND circuit 860,861,862, NAND circuit 863, trigger 864, and decoder circuit 865.NAND circuit 863 receives the output of comparer 969,970 at two input terminal.AND circuit 860,861 has three input terminals respectively.AND circuit 862 has two input terminals.An input end of AND circuit 860 is connected with judging the OUT terminal with low level side comparer 970, and its another input end is supplied to determinating mode signal TPS.An input end of AND circuit 861 is connected with judging the OUT terminal with high-side comparer 969, and its another input end is supplied to test mode signal TPS.Two input ends of NAND circuit 863 are connected with the OUT terminal of judgement with low level side comparer 970 with judging the OUT terminal with high-side comparer 969 respectively, and the output terminal of this NAND circuit 863 is connected with an input end of AND circuit 862.Trigger 864 is provided with: three input end D1, D2 that connect with each lead-out terminal of AND circuit 860,861,862, D3 and with they corresponding three output terminal Q1, Q2, Q3.Output terminal Q1 output high-side error data signal HES, output terminal Q2 output low level side error data signal LES, error data signal HLES between output terminal Q3 output high-low level.
Decoder circuit 865 is provided with output terminals A 0, A1, B0, and receives the input and output switch-over control signal S0-S2 from PG portion 60.Output terminals A 0 is connected with the another input end of AND circuit 860, and output terminals A 0 also is connected with the another input end of AND circuit 861, and output terminals A 1 is connected with another input end of AND circuit 862.By these output terminals A 0, A1, control the operating state of AND circuit 860,861,862, and input and output change-over switch 968 is switched by output terminal B0.Output A0, the A1 of decoder circuit 865, B0 become as follows according to control signal S0-S2.
At first, as S0=0, S1=0, S2=0, then output becomes A0=L, output A1=L, B0=H.That is to say that output A0, A1 become low level L simultaneously, the judgement of AND circuit 860,861,862 is stopped.Output B0 becomes high level H, therefore, 968 conductings of input and output change-over switch, test input pattern signal TIP offers DUT10.
When S0=1, S1=0, S2=0, output becomes A0=H, A1=L, B0=L.That is to say that A0 becomes high level H by output, carries out the judgement of AND circuit 860,861, promptly compares the output of device 969,970 and the judgement of test mode signal TPS.In other words, when test mode signal TPS is high level H, compare the judgement of device 969,970 outputs, if comparer 969 is output as high level H, then high-side error data signal HES becomes high level H; If comparer 970 is output as high level H, then low level side error data signal LES just becomes high level H.Because output A1 is low level L, therefore, the judgement of AND circuit 862 is stopped.Because output B0 is low level L, therefore, input and output change-over switch 968 disconnects, the test output mode signal TOP that comparer 969,970 obtains from DUT10.
When S0=0, S1=1, S2=0, output becomes A0=L, A1=H, B0=L.At this moment, the judgement of AND circuit 860,861 is stopped, and the judgement of AND circuit 862 is performed.The judgement of this AND circuit 862 is at high-side or in the judgement of low level side, if there is mistake, error data signal HLES just becomes high level between high-low level to test mode signal TPS and test output mode signal TOP.Output B0 is low level L, and input and output change-over switch 968 disconnects, and is compared device 969,970 from the test output mode signal TOP of DUT10 and obtains.
When S0=1, S1=1, S2=0, output becomes A0=H, A1=L, B0=H.At this moment, the judgement of AND circuit 860,861 is performed, but because 968 conductings of input and output change-over switch, therefore, test input pattern signal TIP is compared device 969,970 and obtains, the result, and driver 965 is judged certainly.
When S0=1, S1=1, S2=1, output becomes A0=L, A1=H, B0=H.At this moment, the judgement of AND circuit 860,861 is stopped, and the judgement of AND circuit 862 is performed, but because 968 conductings of input and output change-over switch, therefore, test input pattern signal TIP is compared device 969,970 and obtains, the result, and driver 965 is judged certainly.
According to present embodiment 2-7, can obtain the effect identical with embodiment 1, and can change the voltage level of testing input pattern signal TIP, and to testing the judgement voltage level of output mode signal TOP, therefore, can when test, change voltage level, carry out multiple functional test effectively digital circuit.
Embodiment 2-8
Among the present embodiment 2-8, for and embodiment 2-7 adopt accordingly that error data signal HLES has made proving installation improved, SIC (semiconductor integrated circuit) of the present invention between high-side error data signal HES, low level side error data signal LES and high-low level.Figure 29 represents the structure of output detection unit 85 and the error message storage part 90 of present embodiment 2-8.
Among the present embodiment 2-8, as shown in figure 29, the output detection unit 85 of BOST device 20 also is provided with OR circuit 866.This OR circuit 866 has three input ends, and these three input ends are connected with output terminal Q1, Q2, the Q3 of trigger 864 respectively.The output terminal of this OR circuit 866 is connected with pulse generating circuit 854, and the output terminal of this pulse generating circuit 854 is connected with the terminal WR that writes of error message storage part 90 via phase inverter 855.From error data signal HLES between high-side error data signal HES, the low level side error data signal LES of output terminal Q1, the Q2 of trigger 864, Q3, high-low level, offer the DATA terminal of error message storage part 90.
According to present embodiment 2-8, when error data signal HLES becomes high level H whenever between high-side error data signal HES, low level side error data signal LES and high-low level, pulse generating circuit 854 just produces storer and writes signal MWR, and this signal MWR offers via phase inverter 855 and writes terminal WR; Therefore, when error data signal HLES became high level H whenever between high-side error data signal HES, low level side error data signal LES and high-low level, these error datas just deposited error message storage part 90 in memory address signal MAD.The canned data of this error message storage part 90 is read by CPU portion 33, and carries out the error analysis of DUT10.
In present embodiment 2-8, can obtain the effect identical with embodiment 1, and, by error data signal HLES between storage high-side error data signal HES, low level side error data signal LES and high-low level, error message is enriched, the error analysis ability can be improved, and the function of its logic analyzer can be enriched.
Then, just embodiment 3-1 to 3-6 describes, and they relate to has made up PC card etc. and can plug proving installation medium, SIC (semiconductor integrated circuit) of the present invention on BOST device 20.These embodiment 3-1 to 3-6 are that beyond the function that possesses embodiment 1, additional respectively structure, the function that illustrates later constitutes.These embodiment 3-1 to 3-6 also are used in the test step that manufacture method comprised of SIC (semiconductor integrated circuit) of the present invention.
Embodiment 3-1
Figure 30 is illustrated in and makes up the embodiment 3-1 that can plug medium in the TPM portion 50.An embodiment of the BOST device 20 of this array configuration is adopted in Figure 30 (a) expression, Figure 30 (b) represents other embodiment about the medium that is combined, Figure 30 (c) expression is about other embodiment of the BOST device 20 of having set up the circuit board that is used for making up medium, also have, other embodiment of the BOST device 20 of medium array mode is adopted in Figure 30 (d) expression.
In present embodiment 3-1, the pluggable medium of combination on Figure 11, embodiment 1-7 shown in Figure 12.In the embodiment of Figure 30 (a), be formed on and make up the BOST combination 210K that can plug medium 230 on the circuit board 215 shown in Figure 11,12.Can plug medium 230 as this, the interface specification such as PC card, small-sized sudden strain of a muscle card (registered trademark) storer, smart media card, small card, multimedia card, memory stick that can use PC card ATA specification is by standardized pluggable medium.In the combination of the BOST shown in Figure 30 (a) 210K, the retaining member 231 that is provided with card insertion slot is installed in the one side of circuit board 215.On this retaining member 231, use PC card, and guarantee plug property as medium 230.The medium 230 that this PC card forms, the storer of the TPM portion 50 of formation BOST device 20.The medium 230 that this PC card forms can constitute the whole storer of TPM portion 50 voluntarily; But also can adopt another kind of mode, be exactly the semiconductor memory that TPM portion 50 is housed on the circuit board 215, adds that then the medium 230 that is formed by this PC card increases the memory capacity of TPM portion 50.In general, PC card operating rate is low, but it is a kind of small-sized and jumbo medium, therefore, is particularly suitable for the storer as the TPM portion 50 that constitutes BOST device 20 of the present invention.
In the combination of the BOST shown in Figure 30 (a) 210K, the medium 230 that is formed by the PC card directly is inserted in retaining member 231, but shown in Figure 30 (b), also can adopt such structure, promptly prepare the adaptive cover 232 of card that medium 230 can plug in advance thereon.In the embodiment of Figure 30 (b), block adaptive cover 232 and can be inserted into retaining member 231 with plugging.In the embodiment of Figure 30 (b),, can adopt small-sized sudden strain of a muscle card (registered trademark) storer, smart media card etc. as medium 230.
The embodiment of Figure 30 (c), employing is provided with retaining member 231 on circuit board 215, the BOST in abutting connection with this circuit board 215 extension circuit plate 215A makes up 210L simultaneously.Its result in the BOST of this Figure 30 (c) combination 210L, has also added an extension circuit plate 215A on five circuit boards 211 to 215.For example, this extension circuit plate 215A and circuit board 215 configured in parallel, on this extension circuit plate 215A, retaining member 231 is set also, and inserts the medium 230 that forms by the PC card shown in Figure 30 (a) or at the adaptive cover 232 of card shown in Figure 30 (b) at this retaining member 231.
In the BOST of Figure 30 (d) combination 210M, be provided with the retaining member 231A of reduced size on the circuit board 215.At this retaining member 231A, insert little the plugged medium 230 shown in Figure 30 (b).
Figure 31 is the outboard profile of expression based on the BOST combination 210N of embodiment 3-1.On this BOST combination 210N, set up circuit board 215A, 215B, and on these extension circuit plates 215A, 215B, set up retaining member 231 respectively, other structure in addition and the combination of the BOST shown in Figure 11,12 210B are basic identical.Circuit board 213,214,215,215A, 215B are with circuit board 211,212 arranged perpendicular.On circuit board 215A, 215B, set up respectively and medium 230 corresponding connector 233.
System architecture example when Figure 32 represents that medium 230 write test pattern data TPD.In Figure 32 (a),, write test pattern data TPD to medium 230 using personal computer terminal 15 and inserting under the state of medium 230 in this terminal 15.The medium 230 that writes the test pattern data TPD that finishes is inserted into retaining member 231, the 231A of BOST device 20.
In Figure 32 (b), in the retaining member 231 of BOST device 20,231A, insert under the state of medium 230, write test pattern data TPD from personal computer terminal 15 to medium 230.At this moment, write test pattern data TPD via I/F portion 17 to medium 230.
According to present embodiment 3-1, on the circuit board that constitutes BOST device 20, mediums 230 such as PC card can be installed with plugging, and constitute TPM portions 50 with this medium 230, therefore, the memory capacity of TPM portion 50 can be easily increased, more test pattern data can be stored by this medium 230, thereby, strengthened the test function of BOST device 20.In addition, medium 230 can plug, and this medium 230 can be inserted into other terminal and wait and store test pattern data, therefore, can not use BOST device 20 and easily stores test pattern data.
Embodiment 3-2
Among the present embodiment 3-2, the proving installation of SIC (semiconductor integrated circuit) of the present invention has been done improvement, the dual-ported memory of the enough PG of energy portion 60, in the test mode signal TPS, the test input/determinating mode signal JPS that read out from PG portion 60, download test pattern data TPD from TPM portion 50.In present embodiment 3-2, use pluggable medium 230, particularly the PC card based on PC card ATM specification is used as medium 230 uses.Figure 33 represents the signal input-output system of BOST control part 40, TPM portion 50 and the PG portion 60 of present embodiment 3-2.In addition, Figure 34 has represented signal input-output system shown in Figure 33 in detail.
Among the present invention, deposited in TMP portion 50 corresponding to a plurality of test pattern data TPD of a plurality of test events of digital circuit, and from these a plurality of test pattern datas, downloaded and the corresponding test pattern data of execution test pattern to PG portion 60.By this structure, can carry out simple and effectively test to digital circuit by BOST device 20n.But downloading the execution test pattern data from TPM portion 50 to PG portion 60 needs the time.In present embodiment 3-2, PG portion 60 uses dual-ported memory, therefore, PG portion 60 is downloaded the execution test pattern data can carry out concurrently with the action of reading test pattern data TPD from PG portion 60, downloads the needed time thereby effectively reduced.
As shown in figure 33, PG portion 60 is provided with dual-ported memory 620.This PG portion 60 is made of a plurality of passages, for example, with each passage be 32 kilobyte 16 passages promptly 0 to 15 passage constitute.
The dual-ported memory 620 of each passage is provided with two input/output port 621,622.Input/output port 621 is left port (a L port), and input/output port 622 is right output port (a R port).These left port 621, right output port 622 comprise separately that again four port PO 1 are to PO4.Port PO 1 is for reading the input port of write signal R/W, and port PO 2 is the input/output port of data-signal DQ, and port PO 3 is the input port of address signal ADD, and port PO 4 is the input port of clock CLK.
BOST control part 40 and PG portion 60 between carry out the exchange of signal, and and constitute the exchange of carrying out signal between the medium 230 of TPM portion 50.In present embodiment 3-2, this medium 230 is the PC card 230A of PC card ATA specification, and its signal is for pressing the signal of PC card ATA specification specifies.Comprise to the signal that PC card 230A provides from BOST control part 40: signal A[0..10], card is selected signal/CE1/CE2, register controlled signal/OE, the ATASEL signal in attribute zone and assignment file zone, register input signal/the WE in attribute zone and assignment file zone, the data output signal IORD of the register in assignment file zone, the data input signal IOWR of the register in assignment file zone, give the assignment file zone access signal/REG, RESET ,/RESET signal, CSEL signal.
The signal that carries out two-way exchange between BOST control part 40 and PC card 230A comprises: D[0..15], the BVD1 signal ,/STSCHG ,/PDIAG signal, BVD2 signal ,/SPKR ,/the DASP signal.230A comprises to the signal that BOST control part 40 provides from the PC card: RDY ,/the BSY signal; / IREQ ,/the INTRQ signal; write protect signal WP; / IOIS16 signal; / INPAC signal ,/WAIT signal, IORDY signal; supply voltage setting signal/VS1 ,/VS2, and card detection signal/CD1 ,/CD2.
BOST control part 40 is connected to CPU portion 33 and PC card ata interface 17.
In Figure 34, represented BOST control part 40 and the CPU portion 33 of embodiment 3-2 in detail.This BOST control part 40 is provided with: outer/inner signal switching circuit 480, attribute access circuit and assignment file access circuit 481, the generative circuit 482 that resets, clamp appropriate testing circuit 483, R/W control circuit 484, address generator circuit 485, address instruction generation circuit 486, clock circuit 487 and interrupt identification control circuit 488.CPU330 and OR circuit 331 are arranged in the CPU portion 33.
Outer/inner signal switching circuit 480 carries out the switching between the internal circuit of the PC card ata interface 17 of BOST control part 40 outsides and BOST control part 40.Address instruction generation circuit 486 carries out signal exchange with CPU330 and address generator circuit 485, provide signal A[0..10 to outside/internal signal commutation circuit 480], A[1..10], and provide signal ADD[0..14 to the port PO 3 of the L of dual-ported memory 620 port].Address generator circuit 485 provides signal A[0..14 to the port PO 3 of the R of dual-ported memory 620 port].R/W control circuit 484 provides to the port PO 1 of the R of dual-ported memory 620 port and reads write signal R/W.Test cycle signal TCY offers R/W control circuit 484, address generator circuit 485, and provides clock CLK to the port PO 4 of the R of dual-ported memory 620 port.Outer/inner signal switching circuit 480 is with signal DQ[0..15] offer the R of dual-ported memory 620, the port PO 2 of L port.
Attribute circuit and assignment file access circuit 481, port PO 4, the PO1 to the L of dual-ported memory 620 port provides clock CLK, reads write signal R/W respectively.And, this attribute circuit and assignment file access circuit 481, carry out and CPU330 between signal exchange, to outside/internal signal commutation circuit 480 provide signal A0 ,/REG ,/CE1 ,/CE2 ,/OE ,/WE ,/IORD and/signals such as IOWR.The generative circuit 482 that resets provides RESET signal.Clamp appropriate testing circuit 483, be supplied to signal/CD1 ,/CD2, this output that clamps appropriate testing circuit 483 offers interrupt identification control circuit 488.This interrupt identification control circuit 488, be supplied to RDY ,/BSY signal and address instruction signal.The output of this interrupt identification control circuit 488 (anti-phase output) is supplied to OR circuit 331.
Constitute the BOST control part 40 shown in Figure 34 and the dual-ported memory 620 of PG portion 60, be contained on the circuit board 490.This circuit board 490 each passage in passage 0 to 15 has identical structure, reads test pattern data TPD from the dual-ported memory 620 of each circuit board 490.
Flowcharting shown in Figure 35: according to embodiment 3-2, transmit test pattern data TPD to PG portion 60, produce test mode signal TPS and test input/determinating mode signal JPS in PG portion 60 from TMP portion 50, and the basic order of carrying out the DUT10 test.
The process flow diagram of this Figure 35 comprises 13 step S10 to S22 from start to end.These steps S10 to S22 is all carried out continuously.After just having begun, in step S10, send the test code TCD that is consistent with the test that will carry out via BOST communication I/F portion 30 to the CPU of BOST device 20 one 33 from test machine 18.In next step S11, the CPU portion 33 of BOST device 20 is made as high level H with ready/busy flag signal from low level L, and should send to test machine 18 by ready/busy flag signal.In the step S12 that follows, CPU portion 33 is based on the test code TCD that receives, and carries out initial setting via each circuit parts of 40 pairs of BOST devices 20 of BOST control part.In the step S13 that follows, BOST control part 40 sends with the test code TCD that will carry out corresponding test pattern data TPD from TPM portion 50 to PG portion 60 according to the indication of CPU portion 33.
In step S14, BOST control part 40 passes on the transmission of test pattern data TPD to finish to CPU portion 33.In next step S15, CPU portion 33 allows, and ready/busy flag signal is got back to low level L from high level H, and communicates this signal of transmission via BOST communication I/F portion 30 with test machine 18.In step S16, test machine 18 will be measured commencing signal MST and send to CPU portion 33 based on this ready/busy flag signal that receives.In the step S17 that follows, CPU portion 33 makes once more, and ready/busy flag signal becomes high level H from low level L, and should send test machine 18 to by ready/busy flag signal, indicates BOST control part 40 to read test pattern data TPD from PG portion 60 simultaneously.
Read indication by this, in step S18, BOST control part 40 is read the test pattern data TPD that will carry out from PG portion 60, reads PG portion 60 by this and produces test mode signal TPS and test input/determinating mode signal JPS.This test mode signal TPS is shaped to test input pattern signal TIP in WF portion 80, and sends to DUT10 via DUT-BOST I/F portion 95, and DUT10 is tested.In step S19, output detection unit 85 utilizes the test output mode signal TOP of test mode signal TPS judgement from DUT10, and when whenever making a mistake, this error message is deposited in error message storer 90.In the step S20 that follows, to CPU portion 33 reading error information, error message is judged, analyzed from error message storer 90.In step S21, CPU portion 33 makes, and ready/busy flag signal becomes low level L from high level H, and BOST communication I/F portion 30 conveys to test machine 18 with this variation.In follow-up step S22, the error code ECD that CPU portion 33 will obtain by the analysis to error message sends to test machine 18.
Figure 36 represents in detail, transmits the action of test pattern data TPD and read out action from the test pattern data TPD of PG portion 60 among step S18 to PG portion 60 from TPM portion 50 in the step S13 of Figure 35.The read operation of (1) PC card has been represented on top at Figure 36.This PC card read operation, expression is from the read operation of the test pattern data TPD of PC card 230A, (2) PG write operation below it, the action that the test pattern data TPD that expression is read from PC card 230A writes to dual-ported memory 620, in addition, Xia Mian (3) PG read operation again, expression is from the read operation of the test pattern data TPD of dual-ported memory 620.
In Figure 36 (1) PC card read operation, figure (a) expression is for the signal A[0..10 of PC card 230A], figure (b) expression card is selected signal/CE1 signal, figure (c) expression card is selected signal/CE2, data output control signal/the IORD of the register in figure (d) expression assignment file zone, the data input control signal IOWR of the register in figure (e) expression assignment file zone, figure (f) expression signal D[0..15], figure (g) expression/IREQ signal.In addition, in Figure 36 (2) PG write operation and (3) PG read operation, figure (a) expression clock CLK, write signal R/W is read in figure (b) expression, figure (c) expression signal A[0..14], figure (d) expression signal DQ[0..15].
Below, just (1) PC read operation of Figure 36 describes.This PC read operation, that represents on the top of Figure 36 carries out from the step of step S101 to S109.At first in step S101, set following 8 (lower eight bits) of the cylinder number that transmits the beginning sector.This sets action, for example corresponding to A[0..10]=the 4h execution.In next step S102, set last 8 (higher eight bits) of the cylinder number that transmits the beginning sector.This sets action, for example corresponding to A[0..10]=the 5h execution.In next step S103, set the drive letter of card and the head number of beginning sector transmission, this sets action for example corresponding to A[0..10]=the 6h execution.In step S104, the sector number that transmit setting beginning sector, this sets action for example corresponding to A[0..10]=the 3h execution.
In step S105, set between principal computer and the card and carry out the sector number that read/write transmits.These set action, for example corresponding to A[0..10]=the 2h execution, set D[0..15]=" 00h ": 256 times, " 01h ": initial value.This means and set 256 times read.In step S106, carry out the setting of order register.This sets action, for example corresponding to A[0..10]=the 7h execution, set D[0..15]=" 20h ": read the sector.In step S107, carry out reading of status register.This sets action, for example corresponding to A[0..10]=the 0h execution, repeat to read and move to 58h from 80h up to the address.In the reading step S107 of this status register, the card inter-process becomes seizure condition at address 80h place, and the card inter-process finishes at address 58h place, and can accept next access, the driver tracking is finished, and what the data between main frame and the data register transmitted is ready to complete.
In step S108, carry out reading to the data register.In this example, carry out 256 times read, and carry out reading of 256 * 16=512 bytes/sector.In the step S109 that follows, once more status register is read.Repeat reading of status register, move to 58h from 80h up to the address.In the reading step S109 of this status register, the card inter-process becomes seizure condition at address 80h place, and the card inter-process finishes at address 58h place, can accept the access of next time, and the driver tracking is finished.
In Figure 36 (2) PG write operation, according to the step S108 of (1) PC read operation from the data that PC card 230A reads, be written into the left side port 621 of the dual-ported memory 620 of PG portion 60.Arrow A 1 expression is downloaded to the left side of dual-ported memory 620 port 621 from PC card 230A, and the arrow A 2 expressions end of downloading.Between arrow A 1 and arrow A 2, have a plurality of clock signals, but each clock signal by each cycle, will be from D[0..15] data as DQ[0..15] be written to the port PO 2 of left side port 621.In Figure 36 (3) PG read operation,, read test pattern data TPD from the right side port 622 of dual-ported memory 620 according to the step S18 of Figure 35.In this example, be read out in step S18 at the test pattern data TPD that right side port 622 writes before.
Figure 37 is a process flow diagram of representing concurrently to transmit to PG portion 60 from TPM portion 50 test pattern data TPD and the order when test pattern data TPD reads in PG portion 60.Be step S18A and step 23A, 23B with difference in the basic order shown in Figure 35.In step S18A, read test pattern data TPD from PG portion 60, produce test mode signal TPS and test input/determinating mode signal JPS, and DUT10 is tested based on this, but walk abreast with read test pattern data TPD from PG portion 60, transmit test pattern data TPD from TPM portion 50 to PG portion 60 simultaneously.
Follow step S18A, step S23A, S23B are carried out simultaneously concurrently.Step S23A is the step that comprises from step S13 to step S15, transmits test pattern data TPD from TPM portion 50 to PG portion 60.Step S23B is based on the step that writes, reads and analyze that test mode signal TPS that PG portion 60 produced and test input/determinating mode signal JPS carry out error message, and it comprises step S19 among Figure 35 to step S22.
Figure 38 is the sequential chart of detailed action of the step S18A of Figure 37, and is identical with Figure 36, the figure shows (1) PC read operation, (2) PG write operation and (3) PG read operation.(2) the PG write operation is that left port 621 to dual-ported memory 620 writes the action from the test pattern data of PC card 230A.(3) the PC read operation is to the read operation from the test pattern data of the right output port 622 of dual-ported memory 620.As shown in Figure 38, dual-ported memory 620 is carried out concurrently write operation and the read operation of test pattern data TPD.
In embodiment 3-2, by using dual-ported memory 620 in PG portion 60, can make from TPM portion 50 to the transmission of the test pattern data TPD of PG portion 60 with carry out from the reading concurrently of test pattern data TPD of PG portion 60, thereby, can shorten from TPM portion 50 and transmit the required special time of test pattern data TPD to PG portion 60.In addition, in embodiment 3-2, also use pluggable mediums 230 such as PC card 230A, so, can increase the memory capacity of TPM portion 50, can store the more test pattern data TPD that is adapted to more test events in this TPM portion 50.Therefore, by the test pattern data of in more test event, selecting to adapt, can tackle multiple functional test effectively with the test event that will carry out.In addition, PC card 230A can plug, so, can take out from BOST device 20, write test pattern data in another terminal, therefore, in this write operation, can shorten the time of using BOST device 20, and can shorten the stand-by period that is used for this BOST device 20 that writes.
Embodiment 3-3
Among the present embodiment 3-3, the structure of the proving installation of SIC (semiconductor integrated circuit) of the present invention is designed to: use two memory bank A, B in PG portion 60, and can carry out multiple functional test effectively in the same manner with embodiment 3-2.Figure 39 represents the detailed structure of the PG portion 60 among the embodiment 3-3.Among the present embodiment 3-3, also use PC card 230A in TPM portion 50.
In present embodiment 3-3, PG portion 60 is provided with: two memory bank A630, B631, and commutation circuit 632, commutation circuit 633, and switch initialization circuit 634.Memory bank A630, B631 are provided with separately: RW terminal, CLK terminal, ADD terminal and DQ terminal.
Read write signal R/W, clock signal clk and the address signal ADD of commutation circuit 632 couples of memory bank A630, B631 switch, wherein be provided with: receive the input end A0, the A1 that read write signal R/W, input end B0, the B1 of receive clock signal CLK, receiver address signal ADD[0..14] input end C0, C1, output terminal FA0, FA1, FB0, FB1, FC0, the FC1 corresponding, and control input end S with them.Reading write signal R/W and address signal ADD is provided by the BOST control part 40 of Figure 35, and clock signal clk obtains based on test cycle signal TCY.
If control input S is low level L, then importing A0 becomes output FA0, and input A1 becomes output FA1, and input B0 becomes output FB0, and input B1 becomes output FB1, and input C0 becomes output FC0, and input C1 becomes output FC1; And, if control input S is high level H, then imports A0 and switch to FA1, input A1 switches to output FA0, and input B0 switches to output FB1, and input B1 switches to output FB0, and input C0 switches to output FC1, and input C1 switches to output FC0.Control input S provides by switching initialization circuit 634, and this switches initialization circuit 634 by 33 controls of CPU portion.
Output terminal FA0, the FA1 of commutation circuit 632, be connected with the RW terminal of memory bank A630, B631 respectively, output terminal FB0, FB1 are connected with the CLK terminal of memory bank A630, B631 respectively, and output terminal FC0, FC1 are connected with the ADD terminal of memory bank A630, B631 respectively.
Commutation circuit 633 is provided with input and output terminal A, B, lead-out terminal F0 and input terminal F1.Input and output terminal A, B are connected with the DQ terminal of memory bank A630, B631 respectively.Input terminal F1 is supplied to the DQ[0..15 from PC card 230A] signal.Control terminal S is connected with switching initialization circuit 634.
In the commutation circuit 633, S is low level L as the control input, and input and output terminal A, B are connected with terminal F0, F1 respectively.In addition, S is high level H as the control input, and input and output terminal A, B switch to respectively and be connected with terminal F1, F2.
If control input S is low level L, then input and output terminal A is connected with lead-out terminal F0, and input terminal F1 is connected with input and output terminal B.Under this state, what memory bank A630 received output FA0, FB0 from commutation circuit 632, FC0 reads write signal R/W, clock signal clk and address signal ADD[0..14], carry out read operation, and on lead-out terminal F0, read output.On the other hand, the data DQ[0..15 that provides to input terminal F1] be connected with the DQ of memory bank B631, what this memory bank B631 received output FA1, FB1 from commutation circuit 632, FC1 reads write signal R/W, clock signal clk and address signal ADD, carries out write operation.
If control input S is high level H, then input and output terminal B is connected with lead-out terminal F0, and input terminal F1 is connected with input and output terminal A.Under this state, what memory bank B631 received output FA0, FB0 from commutation circuit 632, FC0 reads write signal R/W, clock signal clk and address signal ADD[0..14], carry out read operation, and on lead-out terminal F0, read output.On the other hand, the data DQ[0..15 that provides to input terminal F1] be connected with the DQ of memory bank A630, what this memory bank A630 received output FA1, FB1 from commutation circuit 632, FC1 reads write signal R/W, clock signal clk and address signal ADD, carries out write operation.
As mentioned above, in embodiment 3-3, according to control input S, switch that memory bank A630 reads and state that memory bank B631 writes and on the contrary memory bank A630 write and state that memory bank B631 reads, promptly memory bank A630, B631 hocket read, write operation; Therefore, identical with the situation of the dual-ported memory 620 that uses embodiment 3-2, can be with reading and carry out simultaneously concurrently to the transmission of the test pattern data of PG portion 60 from the test pattern data TPD of PG portion 60 from TPM portion 50.In addition, in embodiment 3-2, also use pluggable mediums 230 such as PC card 230A, thereby can increase the memory capacity of TPM portion 50, and can store a plurality of test pattern data TPD that adapt with more test event in this TPM portion 50; Therefore, by in more test event, selecting and the corresponding test pattern data of carrying out of test event, can tackle multiple functional test effectively.In addition, because PC card 230A can plug, can take out from BOST device 20, available other terminal writes test pattern data, therefore, in this write operation, can shorten the time of using BOST device 20, and can shorten the stand-by period that this writes used BOST device 20.
As mentioned above, the proving installation of SIC (semiconductor integrated circuit) of the present invention, do not need to develop especially special tester, and can expand the test function corresponding simply by the test pattern data of extension storage at the test pattern storer with the digital circuit of tested SIC (semiconductor integrated circuit).Simultaneously, at the needed test pattern data of test pattern data memory stores, can promptly implement digital circuit test by enough testing auxiliary devices by in advance.
In addition, in the manufacture method of SIC (semiconductor integrated circuit) of the present invention, need not to spend excessive expense and just can in the test step of SIC (semiconductor integrated circuit), realize test function expansion simply, and can realize the high speed of this test the digital circuit of SIC (semiconductor integrated circuit).

Claims (15)

1. the proving installation of a SIC (semiconductor integrated circuit) is characterized in that:
Be provided with and carry out the testing circuit board of signal exchange with tested SIC (semiconductor integrated circuit) and be configured near this testing circuit board and the testing auxiliary device that is connected with described testing circuit board;
This testing auxiliary device has the digital circuit test function that digital circuit that tested SIC (semiconductor integrated circuit) is comprised is tested;
Described testing auxiliary device is provided with,
Store the test pattern storer of a plurality of test pattern datas corresponding with a plurality of test events of the test that is used for described digital circuit,
Be written into the test pattern signal generator of the test pattern data of from a plurality of test pattern datas that described test pattern storer is stored, selecting, and
Handle is read the operation of selecteed test pattern data and the control part that the operation that this selecteed test pattern data is written to described test pattern signal generator is controlled from a plurality of test pattern datas that described test pattern storer is stored;
Described testing auxiliary device, based on the test pattern data that is written to described test pattern signal generator, generation is to the test input pattern signal of tested SIC (semiconductor integrated circuit), and judge from the test output mode signal of tested SIC (semiconductor integrated circuit) output, thereby carry out the test of the digital circuit of tested SIC (semiconductor integrated circuit) based on this test input pattern signal.
2. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 1 is characterized in that:
Described testing auxiliary device also is provided with CPU portion, and this CPU portion takes place in order to read the selection indicator signal of the test pattern data of selecting from a plurality of test pattern datas that are stored in described test pattern storer; Described control part is read selecteed test pattern data based on this selection indicator signal from a plurality of test pattern datas that are stored in described test pattern storer, and this selecteed test pattern data is written to described test pattern signal generator.
3. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 1 is characterized in that:
Described control part is read the test pattern data that is written to described test pattern signal generator, and described test pattern signal generator is read based on this test pattern data, produces test mode signal and test input/determinating mode signal.
4. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 3 is characterized in that:
Described testing auxiliary device also is provided with wave shaping portion, and this wave shaping portion carries out shaping based on described test mode signal to test input pattern signal, and this test input pattern signal is imported into tested SIC (semiconductor integrated circuit).
5. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 4 is characterized in that:
Described testing auxiliary device also is provided with the output detection unit, and this output detection unit is exported the error data signal then making comparisons from the test output mode signal and the described test mode signal of tested SIC (semiconductor integrated circuit) output.
6. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 3 is characterized in that:
Described testing auxiliary device also is provided with the error message storage part, this error message storage part constitutes in order to the address information of reading the test pattern data that is written to described test pattern signal generator for receiving, and the address information when its also produces described error data signal to described output detection unit is simultaneously stored.
7. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 1 is characterized in that:
Described testing auxiliary device also is provided with timing generator, and this timing generator produces test cycle signal, clock signal and gating signal; Described clock signal and gating signal are respectively the signals that described test cycle signal produces after postponing sometime, the rising that this clock signal is used to set described test input pattern signal regularly and descend regularly, and described gating signal in order to based on described test input pattern signal sets to regularly from the judgement of the test output mode signal of tested SIC (semiconductor integrated circuit) output.
8. the proving installation of a SIC (semiconductor integrated circuit) is characterized in that:
Be provided with and carry out the testing circuit board of signal exchange with tested SIC (semiconductor integrated circuit) and be configured near this testing circuit board and the testing auxiliary device that is connected with described testing circuit board;
This testing auxiliary device has the digital circuit test function that digital circuit that tested SIC (semiconductor integrated circuit) is comprised is tested;
Described testing auxiliary device is provided with,
Store the test pattern storer of a plurality of test pattern datas corresponding with a plurality of test events of the test that is used for described digital circuit,
Be written into the test pattern signal generator of the test pattern data of from a plurality of test pattern datas of described test pattern memory stores, selecting, and
Handle is read the operation of selecteed test pattern data and the control part that the operation that this selecteed test pattern data is written to described test pattern signal generator is controlled from a plurality of test pattern datas of described test pattern memory stores;
Described test pattern signal generator is stored test vector address control routine, test vector address control data and test pattern data according to the test vector address;
Described control part is provided with the programmable counter that produces the test vector address signal based on described test vector address control routine and test vector address control data;
Described test pattern signal generator advances the test vector address according to described test vector address signal, and produces test mode signal based on described test pattern data;
Described testing auxiliary device, produce the test input pattern signal of supplying with tested SIC (semiconductor integrated circuit) based on this test mode signal, and based on the test output mode signal of this test input pattern signal determining, thereby the digital circuit of tested SIC (semiconductor integrated circuit) is tested from tested SIC (semiconductor integrated circuit) output.
9. the proving installation of a SIC (semiconductor integrated circuit) is characterized in that:
Be provided with and carry out the testing circuit board of signal exchange with tested SIC (semiconductor integrated circuit) and be configured near this testing circuit board and the testing auxiliary device that is connected with described testing circuit board;
This testing auxiliary device has the digital circuit test function that digital circuit that tested SIC (semiconductor integrated circuit) is comprised is tested;
Described testing auxiliary device is provided with,
Store the test pattern storer of a plurality of test pattern datas corresponding with a plurality of test events of the test that is used for described digital circuit,
Be written into the test pattern signal generator of the test pattern data of from a plurality of test pattern datas that described test pattern storer is stored, selecting, and
Handle is read the operation of selecteed test pattern data and the control part that the operation that this selecteed test pattern data is written to described test pattern signal generator is controlled from a plurality of test pattern datas that described test pattern storer is stored;
Described test pattern signal generator comes storage algorithm data generation register control routine, algorithm data generation register control data, test vector address control routine and test vector address control data according to the test vector address;
Described control part is provided with, based on the programmable counter of described test vector address control routine and test vector address control data generation test vector address signal, and a plurality of registers group that produce the test of heuristics mode signal based on described algorithm data generation register with control routine and algorithm data generation register with control data;
Described testing auxiliary device, produce the test input pattern signal of supplying with tested SIC (semiconductor integrated circuit) based on this test mode signal, and based on the test output mode signal of this test input pattern signal determining, thereby carry out test to the digital circuit of tested SIC (semiconductor integrated circuit) from tested SIC (semiconductor integrated circuit) output.
10. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 1 is characterized in that:
Described test pattern signal generator is provided with a plurality of passages, has the structure of reading test pattern data from each passage; Described control part is provided with the serializer that is transfused to the test pattern data of reading from each passage, and this serializer has the function of exporting the test pattern data of reading from each passage in each test period serially.
11. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 1 is characterized in that:
Described testing auxiliary device also is provided with timing generator, and this timing generator produces test cycle signal, set clock signal, reset clock signal and gating signal; Described set clock signal, reset clock signal and gating signal are produced through a certain variable time delay by described test cycle signal respectively; Described set clock signal is used to set the rising timing of described test input pattern signal; Described reset clock signal is used to set the decline timing of described test input pattern signal; Described gating signal is in order to set based on described test input pattern signal from the judgement of the test output mode signal of tested SIC (semiconductor integrated circuit) output regularly.
12. the proving installation of SIC (semiconductor integrated circuit) as claimed in claim 1 is characterized in that:
Described testing auxiliary device also be provided with and tested SIC (semiconductor integrated circuit) between interface circuit and output detection unit;
Described interface circuit is provided with high level voltage generator and low level voltage generator, from the high level voltage of high level voltage generator be set as variablely from the low level voltage of low level voltage generator, described test input pattern signal produces with these high level voltages and low level voltage;
Described output detection unit has to be used from judging with the judgement of high level voltage generator with high level voltage with from judging the structure of being judged with low level voltage, to the level of the test output mode signal exported from tested SIC (semiconductor integrated circuit) with the judgement of low level voltage generator, its generation with this test the relevant error data signal of the high level voltage of output mode signal, the error data signal relevant with its low level voltage and and its high level voltage and low level voltage between the relevant error data signal of voltage.
13. the proving installation of a SIC (semiconductor integrated circuit) is characterized in that:
Be provided with and carry out the testing circuit board of signal exchange with tested SIC (semiconductor integrated circuit) and be configured near this testing circuit board and the testing auxiliary device that is connected with described testing circuit board;
This testing auxiliary device has the digital circuit test function that digital circuit that tested SIC (semiconductor integrated circuit) is comprised is tested;
Described testing auxiliary device is provided with,
Store the test pattern storer of a plurality of test pattern datas corresponding with a plurality of test events of the test that is used for described digital circuit,
Be written into the test pattern signal generator of the test pattern data of from a plurality of test pattern datas that described test pattern storer is stored, selecting, and
To the operation of from a plurality of test pattern datas of described test pattern memory stores, reading selecteed test pattern data, this selecteed test pattern data is written to the operation of described test pattern signal generator and reads the control part that the operation of test pattern data is controlled from this test pattern signal generator;
Described testing auxiliary device, based on the test pattern data of reading from described test pattern signal generator, generation is to the test input pattern signal of tested SIC (semiconductor integrated circuit), and judge from the test output mode signal of tested SIC (semiconductor integrated circuit) output, thereby carry out test to the digital circuit of tested SIC (semiconductor integrated circuit) based on this test input pattern signal;
This testing auxiliary device constitutes by comprising a plurality of circuit boards that the circuit board of medium can be installed with plugging, constitutes described mode data storer with described medium.
14. the proving installation of a SIC (semiconductor integrated circuit) is characterized in that:
Be provided with and carry out the testing circuit board of signal exchange with tested SIC (semiconductor integrated circuit) and be configured near this testing circuit board and the testing auxiliary device that is connected with described testing circuit board;
This testing auxiliary device has the digital circuit test function that digital circuit that tested SIC (semiconductor integrated circuit) is comprised is tested;
Described testing auxiliary device is provided with,
Store the test pattern storer of a plurality of test pattern datas corresponding with a plurality of test events of the test that is used for described digital circuit,
The test pattern signal generator that contains first, second storer that is written into the test pattern data of from a plurality of test pattern datas of described test pattern memory stores, selecting, and
To from a plurality of test pattern datas that described test pattern storer is stored, reading the operation of selecteed test pattern data, this selecteed test pattern data being written to the operation of first, second storer of described test pattern signal generator and the control part of being controlled from the operation that described first, second storer of this test pattern signal generator is read test pattern data;
Described testing auxiliary device, based on the test pattern data of reading from described test pattern signal generator, generation is to the test input pattern signal of tested SIC (semiconductor integrated circuit), and based on the test output mode signal of this test input pattern signal determining, thereby carry out test to the digital circuit of tested SIC (semiconductor integrated circuit) from tested SIC (semiconductor integrated circuit) output;
When reading first test pattern data of the described first memory that is written to described test pattern signal generator, second test pattern data of selecting from a plurality of test pattern datas that are stored in described test pattern storer is written to described second memory.
15. the manufacture method of the SIC (semiconductor integrated circuit) of a test step that comprises the measuring semiconductor integrated circuit is characterized in that:
In described test step, near use comprises the testing circuit board that carries out signal exchange with described SIC (semiconductor integrated circuit) and is configured in this testing circuit board and the proving installation of the testing auxiliary device that is connected with described testing circuit board, described testing auxiliary device has the digital circuit test function that digital circuit that described SIC (semiconductor integrated circuit) is comprised is tested;
This testing auxiliary device is provided with,
Store the test pattern storer of a plurality of test pattern datas corresponding with a plurality of test events of the test that is used for described digital circuit,
Be written into the test pattern signal generator of the test pattern data of from a plurality of test pattern datas that are stored in described test pattern storer, selecting, and
Handle is read the operation of selecteed test pattern data and the control part that the operation that this selecteed test pattern data is written to described test pattern signal generator is controlled from a plurality of test pattern datas that described test pattern storer is stored;
In described test step, described testing auxiliary device is based on the test pattern data that writes described test pattern signal generator, generation is to the test input pattern signal of the digital circuit of described SIC (semiconductor integrated circuit), and based on the test output mode signal of this test input pattern signal determining, thereby carry out test to the digital circuit of described SIC (semiconductor integrated circuit) from described SIC (semiconductor integrated circuit) output.
CNA2003101036093A 2003-02-26 2003-10-27 Apparatus for testing semiconductor integrated circuit Pending CN1525187A (en)

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JP2004257898A (en) 2004-09-16

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