CN1514481A - Technology of manufacturing high voltage semiconductor device - Google Patents
Technology of manufacturing high voltage semiconductor device Download PDFInfo
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- CN1514481A CN1514481A CNA021605610A CN02160561A CN1514481A CN 1514481 A CN1514481 A CN 1514481A CN A021605610 A CNA021605610 A CN A021605610A CN 02160561 A CN02160561 A CN 02160561A CN 1514481 A CN1514481 A CN 1514481A
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Abstract
The invention includes following steps: (1) growing oxide layer on substrate, and photo etching pattern forms N trap area; (2) coating photoresist layer on oxide layer, and photo etching pattern forms P area; (3) depositing silicon nitride on oxide layer grown on silicon chip, photo etching pattern forms field area and P area; (4) field oxidation is grown on silicon chip, then etching layers of silicon oxynitride, silicon nitride and dioxide in active area in sequence; (5) step for forming capacitance area and grid oxide layer; (6) depositing polysilicon on silicon chip, and photo etching pattern on silicon chip forms polycrystal area; (7) etching pattern forms N+ area and P+ area; (8) etching pattern on silicon chip forms contact hole area; (9) step for forming aluminum wiring and passive film.
Description
Technical field
The present invention relates to a kind of technology of semiconductor device, relate in particular to a kind of technology of making high-voltage semi-conductor device.
Background technology
In the prior art semiconductor device manufacturing process, in order to reach the logic function of high pressure low on-resistance (LDMOS) and circuit (BICMOS), traditional and known method be with (LDMOS) and (BICMOS) these two kinds of devices separately make.
The technology of the conventional and the simplest manufacturing of prior art BICMOS is, needs that growth one 10um make nmos device to the thick P epitaxial loayer of 15um on the P+ backing material, makes PMOS device and NPN transistor in the dark n trap of 4um to 5um; And prior art is made the LDMOS power tube, and it is withstand voltage, and the highest can only accomplishing lied prostrate 100 more.
This shows, prior art manufacturing (LDMOS) and (BICMOS) device, not only manufacturing process is loaded down with trivial details, and the waste raw material, and the device volume of making is big, therefore can not satisfy the demand of information and electronics industry develop rapidly.
Summary of the invention
The object of the present invention is to provide a kind of technology of making high-voltage semi-conductor device, it can not only lump together manufacturing with LDMOS and these two kinds of devices of BICMOS, and the device volume of making is little.
The object of the present invention is achieved like this:
A kind of technology of making high-voltage semi-conductor device is characterized in may further comprise the steps:
The first, the N trap forms step, and the oxide layer of growing on the high resistant backing material through photoetching composition, forms the N well area;
The second, the P-layer forms step, and coating one photoresist layer on oxide layer then through photoetching composition, forms the P-zone;
The 3rd, place and territory, P place form step, and growth oxide layer deposit silicon nitride through photoetching composition, forms place and territory, P place on silicon chip;
The 4th, a growth oxidation and corrosion step, a growth oxidation is corroded the silicon oxynitride on the active area respectively, silicon nitride and dioxide layer then successively on silicon chip;
The 5th, form capacitor regions and gate oxide step, the pre-grid oxide of growing on silicon chip earlier through photoetching composition, forms knot, and regrowth one gate oxide;
The 6th, the polycrystalline zone forms step, deposit polysilicon on silicon chip, and, form the polycrystalline zone through photoetching composition;
The 7th, N+, the P+ zone forms step, through photoetching composition, forms N+ zone and P+ zone respectively on silicon chip;
The 8th, contact hole forms step, and photoetching composition on silicon chip forms the contact hole zone;
The 9th, aluminium wiring and passivating film form step, with conventional method cloth aluminum strip, growth of passivation layer.
In the technology of above-mentioned manufacturing high-voltage semi-conductor device, wherein, described step 1 comprises: 1) on the high resistant backing material 1 of resistivity 100～200 ohmcms, growth one deck is greater than the oxide layer of 5000A; 2) coating one photoresist layer on this oxide layer carries out photoetching composition, then to expose N well area to be formed; 3) oxide layer of exposed region is clean with the corrosive liquid corrosion, and remove the photoresist layer; 4) this exposed region is carried out phosphonium ion and inject, under greater than 1000 ℃ of temperature, in the atmosphere of nitrogen and oxygen, advance about about 7～8 hours, thereby form the N trap about the about 6.5～7.0um of junction depth then; Grow simultaneously oxide layer about 5000A.
In the technology of above-mentioned manufacturing high-voltage semi-conductor device, wherein, described step 2 comprises: 1) coating one photoresist layer on oxide layer, carry out photoetching composition then, expose P-layer region to be formed, and the silicon dioxide of exposed region is clean with the corrosive liquid corrosion; 2) remove the photoresist layer; 3) the pre-injection oxide layer about the about 500A of growth one deck is carried out the boron ion to this exposure territory and is injected; 4) coating one photoresist layer on silicon chip carries out photoetching composition then, to expose zone, base to be formed, exposed region is carried out the boron ion inject; 5) under greater than 1100 ℃ of temperature, in the atmosphere of nitrogen and oxygen, advance about about 1.5～2.5 hours, thereby form the P-layer about the about 0.5～1.5um of junction depth, float all oxide layers of light with the hydrofluoric acid corrosive liquid at last.
In the technology of above-mentioned manufacturing high-voltage semi-conductor device, wherein, described step 3 comprises 1) in the oxide layer about growth one deck 400A on the silicon chip, and then the silicon nitride about deposit 600A; 2) coating one photoresist layer on silicon chip carries out photoetching composition, then to expose zone, place to be formed.And remove silicon nitride and oxide layer on the place with dry etching; 3) remove the photoresist layer; 4) coating one photoresist layer on silicon chip carries out photoetching composition then, exposing territory, P place to be formed, and with boron difluoride ion injection exposed region.
In the technology of above-mentioned manufacturing high-voltage semi-conductor device, wherein, described step 5 comprises 1) at the pre-grid oxide about growth one deck 400A on the silicon chip; 2) face figure one deck photoresist structurally carries out photoetching composition then, exposing capacitor regions to be formed, and injects exposed region with the boron ion; 3) remove the photoresist layer, last under temperature greater than 1000C, advance about 1 hour with N2, form the junction depth about 2um; 4) float the pre-grid oxide layer with the hydrofluoric acid corrosive liquid, again the gate oxide about regrowth one deck 500～1000A.
In the technology of above-mentioned manufacturing high-voltage semi-conductor device, wherein, described step 6 comprises, 1) coating one photoresist layer on silicon chip carries out photoetching composition, then to expose NMOS raceway groove control band to be formed, and inject exposed region with phosphonium ion, remove the photoresist layer then; 2) coating one photoresist layer on silicon chip carries out photoetching composition then, exposing PMOS raceway groove control band to be formed, and with boron ion injection exposed region, removes the photoresist layer then; 3) at the polysilicon about deposit one deck 5000A on the silicon chip, and under the temperature greater than 900C, logical phosphorus oxychloride gas mixes to polysilicon; 4) coating one photoresist layer on silicon chip carries out photoetching composition, then to expose polycrystalline zone to be formed; 5) with the method for dry etching the polycrystalline of exposed region is removed, removed the photoresist layer then.
In the technology of above-mentioned manufacturing high-voltage semi-conductor device, wherein, described step 7 comprises 1) coating one photoresist layer on silicon chip, carry out photoetching composition then, exposing N+ zone to be formed, and inject exposed region with arsenic ion; 2) remove the photoresist layer, coating one photoresist layer (1100) carries out photoetching composition then on silicon chip, exposing P+ zone to be formed, and with boron ion injection exposed region; 3) remove the photoresist layer, at the phosphorosilicate glass about deposit one deck 10000A on the silicon chip, and under the temperature greater than 900C, logical nitrogen refluxed to phosphorosilicate glass in about 20 minutes, formed N+12 and P+ knot.
In the technology of above-mentioned manufacturing high-voltage semi-conductor device, wherein, described step 8 comprises, coating one photoresist layer on silicon chip, carry out photoetching composition then, exposing contact hole zone to be formed, and all remove the exposed region oxide layer clean with the method for wet method and dry method successively.
The present invention makes the technology of high-voltage semi-conductor device, owing to adopted above-mentioned technical scheme, makes it to compare with the prior art manufacturing process, has tangible advantage and good effect.
1. the present invention is in process for fabrication of semiconductor device, at first be the resistivity that changes backing material, next has omitted extension, at last at the N trap, concentration and the junction depth of P-have been done adjustment, the circuit of making LDMOS and these two kinds of functions of BICMOS is integrated on the chip piece, and saves semi-conducting material, and the device volume of making is little.
2. the present invention is by (concentration and) junction depth of control N trap, and (concentration and) junction depth of P-makes the high withstand voltage and low on-resistance of having of power LDMOS pipe.
The present invention since the special construction of LDMOS be the N trap as drain-drift region, polycrystalline is done a version and is helped improving withstand voltage, the P-layer in the N trap also has contribution to improving withstand voltage and reducing conducting resistance in addition.
Description of drawings
To the description of one embodiment of the invention, can further understand purpose of the present invention, specific structural features and advantage by following in conjunction with its accompanying drawing.Wherein, accompanying drawing is:
Fig. 1, the 2nd, the present invention makes the schematic diagram of N well area in the technology of high-voltage semi-conductor device;
Fig. 3, the 4th, the present invention makes the schematic diagram of P-layer region in the technology of high-voltage semi-conductor device;
Fig. 5 is the schematic diagram that the present invention makes active area in the technology of high-voltage semi-conductor device;
Fig. 6 is the schematic diagram that the present invention makes P place in the technology of high-voltage semi-conductor device;
Fig. 7 is that the present invention makes the schematic diagram that floats denitrification silica-silicon nitride-oxide layer after the technology midfield oxidation of high-voltage semi-conductor device;
Fig. 8 is the schematic diagram that the present invention makes capacitor regions in the technology of high-voltage semi-conductor device;
Fig. 9 is the schematic diagram that the present invention makes gate oxidation in the technology of high-voltage semi-conductor device;
Figure 10, the 11st, the present invention makes the schematic diagram in polycrystalline zone in the technology of high-voltage semi-conductor device;
Figure 12 is the schematic diagram that the present invention makes N+ zone in the technology of high-voltage semi-conductor device;
Figure 13 is the schematic diagram that the present invention makes contact hole zone in the technology of high-voltage semi-conductor device;
Embodiment
See also shown in the accompanying drawing, the present invention makes the technology of high-voltage semi-conductor device, may further comprise the steps:
The first, the N trap forms step (seeing also illustrated in figures 1 and 2), comprising:
1) on the high resistant backing material 1 of resistivity 100～200 ohmcms, growth one deck is greater than the oxide layer 2 of 5000A;
2) coating one photoresist layer 100 on this oxide layer carries out photoetching composition, then to expose N well area (3) to be formed;
3) oxide layer of exposed region is clean with the corrosive liquid corrosion, and remove photoresist layer 100;
4) this exposed region is carried out phosphonium ion and inject, under greater than 1000 ℃ of temperature, in the atmosphere of nitrogen and oxygen, advance about 7～8 hours, thereby form the N trap junction depth of 6.5～7.0um then.Grow simultaneously oxide layer (2-1) about 5000A.
The second, the P-layer region forms step (seeing also shown in Fig. 3 and 4), and coating one photoresist layer 200 on oxide layer 2-1 carries out photoetching composition then earlier, exposes P-zone to be formed, and the oxide layer of exposed region is clean with the corrosive liquid corrosion;
1) removes photoresist layer 200;
2) grow then pre-injection oxide layer about the about 500A of one deck is carried out the boron ion to this exposure territory and is injected;
3) coating one photoresist layer 250 (not showing this structure among the figure) on silicon chip carries out photoetching composition then, to expose zone, base to be formed, exposed region is carried out the boron ion inject, and ion injects;
3) under greater than 1100 ℃ of temperature, in the atmosphere of nitrogen and oxygen, advance about about 1.5～2.5 hours, thereby form the P-layer 4 about the about 0.5～1.5um of junction depth.Float all oxide layers of light with the hydrofluoric acid corrosive liquid.
The 3rd, place and territory, P place form step (seeing also Fig. 5 and shown in Figure 6), comprising:
1) in the oxide layer 5 about growth one deck 400A on the silicon chip, and then the silicon nitride about deposit 600A 6;
2) coating one photoresist layer 300 on silicon chip carries out photoetching composition then, exposing zone, place to be formed, and removes silicon nitride and oxide layer (see figure 5) on the place with dry etching;
3) remove photoresist layer 300;
4) coating one photoresist layer 400 on silicon chip carries out photoetching composition then, exposing territory, P place to be formed, and with boron difluoride ion injection exposed region (see figure 6).
The 4th, a growth oxidation and corrosion step (seeing also shown in Figure 7), a growth oxidation (7) on silicon chip is earlier corroded the silicon oxynitride on the active area respectively, silicon nitride and dioxide layer then successively;
The 5th, form capacitor regions and gate oxide step (seeing also Fig. 8 and shown in Figure 9), comprising:
1) at the pre-grid oxide about growth one deck 400A on the silicon chip;
2) face figure one deck photoresist 500 structurally carries out photoetching composition then, exposing capacitor regions to be formed, and injects exposed region with the boron ion.(see figure 8);
3) remove photoresist layer 500; Last under temperature greater than 1000C, advance about 1 hour with N2, form the junction depth 9 about 2um;
4) float the pre-grid oxide layer with the hydrofluoric acid corrosive liquid, again the gate oxide about regrowth one deck 500～1000A.(see figure 9).
The 6th, the polycrystalline zone forms step (seeing also Figure 10 and shown in Figure 11), comprising:
1) coating one photoresist layer 600 (not showing this structure among Figure 10) on silicon chip carries out photoetching composition then, exposing NMOS raceway groove control band to be formed, and injects exposed region with phosphonium ion, removes photoresist layer 600 then;
2) coating one photoresist layer 700 (not showing this structure among Figure 10) on silicon chip carries out photoetching composition then, exposing PMOS raceway groove control band to be formed, and with boron ion injection exposed region, removes photoresist layer 700 then;
3) at the polysilicon 10 about deposit one deck 5000A on the silicon chip, and under the temperature greater than 900C, logical phosphorus oxychloride gas mixes to polysilicon.
4) coating one photoresist layer 900 on silicon chip carries out photoetching composition, then to expose polycrystalline zone to be formed.
5) with the method for dry etching the polycrystalline of exposed region is removed, removed photoresist layer 900 (seeing Figure 11) then;
The 7th, N+, the P+ zone forms step (seeing also shown in Figure 12), comprising:
2) coating one photoresist layer 1000 on silicon chip carries out photoetching composition then, exposing N+ zone to be formed, and injects exposed region (seeing Figure 12) with arsenic ion.
3) remove photoresist layer 1000; Coating one photoresist layer 1100 (not showing this structure among Figure 13) carries out photoetching composition then on silicon chip, exposing P+ zone to be formed, and with boron ion injection exposed region.
4) remove photoresist layer 1100; At the phosphorosilicate glass 11 about deposit one deck 10000A on the silicon chip, and under the temperature greater than 900C, logical nitrogen refluxed to phosphorosilicate glass in about 20 minutes, formed N+12 and P+ knot;
The 8th, contact hole forms step (seeing also shown in Figure 13), comprising:
1) coating one photoresist layer 1200 on silicon chip carries out photoetching composition then, exposing contact hole zone to be formed, and all removes the exposed region oxide layer clean with the method for wet method and dry method successively.
2) remove photoresist layer 1200 earlier;
The 9th, aluminium wiring and passivating film form step, comprising:
1) with conventional method cloth aluminum strip, growth of passivation layer.
In sum, the present invention makes the technology of high-voltage semi-conductor device, having done some at the manufacturing semiconductor device technology and changed, at first is the resistivity that changes backing material, and next has omitted extension, at last at the N trap, concentration and the junction depth of P-have been done adjustment, and the circuit of making LDMOS and these two kinds of functions of BICMOS is integrated on the chip piece, and economical with materials, the device volume of making is little, to be fit to the needs of electronics industry development.
Claims (8)
1. technology of making high-voltage semi-conductor device is characterized in that may further comprise the steps:
The first, the N trap forms step, goes up growth oxide layer (2) at high resistant backing material (1), through photoetching composition, forms the N well area;
The second, the P-layer forms step, goes up coating one photoresist layer (200) in oxide layer (2), then through photoetching composition, forms the P-zone;
The 3rd, place and territory, P place form step, and growth oxide layer deposit silicon nitride (6) on silicon chip through photoetching composition, forms place and territory, P place;
The 4th, a growth oxidation and corrosion step, a growth oxidation (7) is corroded the silicon oxynitride on the active area respectively, silicon nitride and dioxide layer then successively on silicon chip;
The 5th, form capacitor regions and gate oxide step, the pre-grid oxide of growing on silicon chip earlier through photoetching composition, forms knot (9), and regrowth one gate oxide;
The 6th, the polycrystalline zone forms step, deposit polysilicon (10) on silicon chip, and, form the polycrystalline zone through photoetching composition;
The 7th, N+, the P+ zone forms step, through photoetching composition, forms N+ zone and P+ zone respectively on silicon chip;
The 8th, contact hole forms step, and photoetching composition on silicon chip forms the contact hole zone;
The 9th, aluminium wiring and passivating film form step, with conventional method cloth aluminum strip, growth of passivation layer.
2. the technology of manufacturing high-voltage semi-conductor device as claimed in claim 1 is characterized in that: described step 1 comprises:
1) on the high resistant backing material 1 of resistivity 100～200 ohmcms, growth one deck is greater than the oxide layer (2) of 5000A;
2) coating one photoresist layer (100) on this oxide layer carries out photoetching composition, then to expose N well area (3) to be formed;
3) oxide layer of exposed region is clean with the corrosive liquid corrosion, and remove photoresist layer (100);
4) this exposed region is carried out phosphonium ion and inject, under greater than 1000 ℃ of temperature, in the atmosphere of nitrogen and oxygen, advance about about 7～8 hours, thereby form the N trap about the about 6.5～7.0um of junction depth then; Grow simultaneously oxide layer (2-1) about 5000A.
3. the technology of manufacturing high-voltage semi-conductor device as claimed in claim 1 is characterized in that: described step 2 comprises:
1) go up coating one photoresist layer (200) in oxide layer (2), carry out photoetching composition then, expose P-layer region to be formed, and the silicon dioxide of exposed region is clean with the corrosive liquid corrosion;
2) remove photoresist layer 200;
3) the pre-injection oxide layer about the about 500A of growth one deck is carried out the boron ion to this exposure territory and is injected;
4) coating one photoresist layer (250) on silicon chip carries out photoetching composition then, to expose zone, base to be formed, exposed region is carried out the boron ion inject;
5) under greater than 1100 ℃ of temperature, in the atmosphere of nitrogen and oxygen, advance about about 1.5～2.5 hours, thereby form the P-layer (4) about the about 0.5～1.5um of junction depth, float all oxide layers of light with the hydrofluoric acid corrosive liquid at last.
4. the technology of manufacturing high-voltage semi-conductor device as claimed in claim 1 is characterized in that: described step 3 comprises,
1) in the oxide layer (5) about growth one deck 400A on the silicon chip, and then the silicon nitride about deposit 600A (6);
2) coating one photoresist layer (300) on silicon chip carries out photoetching composition, then to expose zone, place to be formed.And remove silicon nitride and oxide layer on the place with dry etching;
3) remove photoresist layer (300);
4) coating one photoresist layer (400) on silicon chip carries out photoetching composition then, exposing territory, P place to be formed, and with boron difluoride ion injection exposed region.
5. the technology of manufacturing high-voltage semi-conductor device as claimed in claim 1 is characterized in that: described step 5 comprises,
1) at the pre-grid oxide about growth one deck 400A on the silicon chip;
2) face figure one deck photoresist (500) structurally carries out photoetching composition then, exposing capacitor regions to be formed, and injects exposed region with the boron ion;
3) remove photoresist layer (500), last under temperature greater than 1000C, advance about 1 hour with N2, form the junction depth (9) about 2um;
4) float the pre-grid oxide layer with the hydrofluoric acid corrosive liquid, again the gate oxide about regrowth one deck 500～1000A.
6. the technology of manufacturing high-voltage semi-conductor device as claimed in claim 1 is characterized in that: described step 6 comprises,
1) coating one photoresist layer (600) on silicon chip carries out photoetching composition then, exposing NMOS raceway groove control band to be formed, and injects exposed region with phosphonium ion, removes photoresist layer (600) then;
2) coating one photoresist layer (700) on silicon chip carries out photoetching composition then, exposing PMOS raceway groove control band to be formed, and with boron ion injection exposed region, removes photoresist layer (700) then;
3) at the polysilicon (10) about deposit one deck 5000A on the silicon chip, and under the temperature greater than 900C, logical phosphorus oxychloride gas mixes to polysilicon;
4) coating one photoresist layer (900) on silicon chip carries out photoetching composition, then to expose polycrystalline zone to be formed;
5) with the method for dry etching the polycrystalline of exposed region is removed, removed photoresist layer (900) then.
7. the technology of manufacturing high-voltage semi-conductor device as claimed in claim 1 is characterized in that: described step 7 comprises,
1) coating one photoresist layer (1000) on silicon chip carries out photoetching composition then, exposing N+ zone to be formed, and injects exposed region with arsenic ion;
2) remove photoresist layer (1000), coating one photoresist layer (1100) carries out photoetching composition then on silicon chip, exposing P+ zone to be formed, and with boron ion injection exposed region;
3) remove photoresist layer (1100), at the phosphorosilicate glass (11) about deposit one deck 10000A on the silicon chip, and under the temperature greater than 900C, logical nitrogen refluxed to phosphorosilicate glass in about 20 minutes, formed N+12 and P+ knot.
8. the technology of manufacturing high-voltage semi-conductor device as claimed in claim 1, it is characterized in that: described step 8 comprises, coating one photoresist layer (1200) on silicon chip, carry out photoetching composition then, exposing contact hole zone to be formed, and all remove the exposed region oxide layer clean with the method for wet method and dry method successively.
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| CNB021605610A CN100447982C (en) | 2002-12-31 | 2002-12-31 | Technology of manufacturing high voltage semiconductor device |
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| CNB021605610A CN100447982C (en) | 2002-12-31 | 2002-12-31 | Technology of manufacturing high voltage semiconductor device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100428492C (en) * | 2005-09-20 | 2008-10-22 | 联华电子股份有限公司 | Ultrahigh voltage metal oxide semiconductor transistor component |
| CN100594591C (en) * | 2007-10-17 | 2010-03-17 | 中国科学院微电子研究所 | Method for improving performance of gallium nitride-based field effect transistor |
| CN102184897A (en) * | 2011-03-28 | 2011-09-14 | 上海贝岭股份有限公司 | Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit |
| CN102361035A (en) * | 2011-10-21 | 2012-02-22 | 昆山华太电子技术有限公司 | Structure of RF-LDMOS (radio frequency laterally double-diffused metal oxide semiconductor) device without epitaxial layer |
| WO2012031546A1 (en) * | 2010-09-07 | 2012-03-15 | Csmc Technologies Fab1 Co., Ltd | Mos device and fabricating method thereof |
| CN103956318A (en) * | 2014-05-21 | 2014-07-30 | 上海华力微电子有限公司 | Method for avoiding film poisoning caused by ion implantation layer rear photoresist |
| CN105097570A (en) * | 2014-05-21 | 2015-11-25 | 北大方正集团有限公司 | Passivation layer manufacturing method and high-voltage semiconductor power device |
| CN105810583A (en) * | 2014-12-30 | 2016-07-27 | 无锡华润上华半导体有限公司 | Horizontal insulated gate bipolar transistor production method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP0610599A1 (en) * | 1993-01-04 | 1994-08-17 | Texas Instruments Incorporated | High voltage transistor with drift region |
| CN1110098C (en) * | 1999-07-27 | 2003-05-28 | 北京工业大学 | High-speed high-voltage power IC device |
| US20020053695A1 (en) * | 2000-11-07 | 2002-05-09 | Chorng-Wei Liaw | Split buried layer for high voltage LDMOS transistor |
| CN1149658C (en) * | 2001-04-18 | 2004-05-12 | 上海贝岭股份有限公司 | Process for preparing bipolar IC |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428492C (en) * | 2005-09-20 | 2008-10-22 | 联华电子股份有限公司 | Ultrahigh voltage metal oxide semiconductor transistor component |
| CN100594591C (en) * | 2007-10-17 | 2010-03-17 | 中国科学院微电子研究所 | Method for improving performance of gallium nitride-based field effect transistor |
| WO2012031546A1 (en) * | 2010-09-07 | 2012-03-15 | Csmc Technologies Fab1 Co., Ltd | Mos device and fabricating method thereof |
| CN102403335A (en) * | 2010-09-07 | 2012-04-04 | 无锡华润上华半导体有限公司 | MOS (metal oxide semiconductor) device and manufacturing method for same |
| CN102184897A (en) * | 2011-03-28 | 2011-09-14 | 上海贝岭股份有限公司 | Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit |
| CN102184897B (en) * | 2011-03-28 | 2013-11-06 | 上海贝岭股份有限公司 | Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit |
| CN102361035A (en) * | 2011-10-21 | 2012-02-22 | 昆山华太电子技术有限公司 | Structure of RF-LDMOS (radio frequency laterally double-diffused metal oxide semiconductor) device without epitaxial layer |
| CN103956318A (en) * | 2014-05-21 | 2014-07-30 | 上海华力微电子有限公司 | Method for avoiding film poisoning caused by ion implantation layer rear photoresist |
| CN105097570A (en) * | 2014-05-21 | 2015-11-25 | 北大方正集团有限公司 | Passivation layer manufacturing method and high-voltage semiconductor power device |
| CN105097570B (en) * | 2014-05-21 | 2017-12-19 | 北大方正集团有限公司 | Manufacturing method of passivation layer and high-voltage semi-conductor power device |
| CN105810583A (en) * | 2014-12-30 | 2016-07-27 | 无锡华润上华半导体有限公司 | Horizontal insulated gate bipolar transistor production method |
| CN105810583B (en) * | 2014-12-30 | 2019-03-15 | 无锡华润上华科技有限公司 | The manufacturing method of landscape insulation bar double-pole-type transistor |
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| CN100447982C (en) | 2008-12-31 |
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