CN1149658C - Process for preparing bipolar IC - Google Patents
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- CN1149658C CN1149658C CNB011126620A CN01112662A CN1149658C CN 1149658 C CN1149658 C CN 1149658C CN B011126620 A CNB011126620 A CN B011126620A CN 01112662 A CN01112662 A CN 01112662A CN 1149658 C CN1149658 C CN 1149658C
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Abstract
The present invention relates to a manufacturing method of a bipolar integrated circuit. The method comprises: preparing a silicon substrate; communicating and separating; extending a thin layer; shallowly forming a base region; injecting phosphor into an emitting region. The present invention also describes the technological characteristics of a full plane technology, a TEOS/Si3N4/LTO three-layer structure, a dry-dry-wet hole carving technology, a Si3N4/TEOS dielectric capacitor, double-layer metal wirings, etc.
Description
The present invention relates to a kind of integrated circuit fabrication process, relate in particular to the manufacturing process of bipolar integrated circuit.
As everyone knows, the development of integrated circuit processing technique is maked rapid progress.Its development doubles every 18 months parts numbers basically according to More's law, and chip area reduces 1/3.Comparatively speaking, the technological level of China's integrated circuit manufacturing is also backward relatively.
The objective of the invention is to improve the craft precision of integrated circuit, reduce chip area, improve device performance.
According to one aspect of the present invention, a kind of method of making bipolar integrated circuit is provided, may further comprise the steps the preparation Semiconductor substrate; In described Semiconductor substrate, form buried regions; Optionally in described Semiconductor substrate, form isolated area; At described Semiconductor substrate growing epitaxial layers; In described Semiconductor substrate, form the base; Remove all oxide layers on the described Semiconductor substrate, deposit TEOS layer; In described Semiconductor substrate, form the emitter region; On described TEOS layer, form the Si3N4 layer; On described Si3N4 layer, form low temperature oxide layer; Etching contact hole optionally in described TEOS layer/described Si3N4 layer/described low temperature oxide layer structure; And on the structure that obtains, form metal line.
To the description of preferred embodiment of the present invention and in conjunction with the accompanying drawing that technological process of the present invention is shown, advantage of the present invention, feature and purpose will be become more obviously from following.Wherein:
Fig. 1 is the schematic diagram that original silicon chip is shown;
Fig. 2 illustrates according to the present invention to carry out the schematic diagram of oxygen just;
Fig. 3 illustrates according to the present invention to carry out the schematic diagram that buried regions injects;
Fig. 4 illustrates according to the present invention to carry out the schematic diagram that buried regions advances;
Fig. 5 is the schematic diagram that illustrates according to the present invention descends separator to inject and following separator advances;
Fig. 6 is the schematic diagram that illustrates according to grown epitaxial layer of the present invention;
Fig. 7 illustrates according to the present invention to carry out the schematic diagram that dark phosphorus district is injected and dark phosphorus district advances;
Fig. 8 illustrates according to the present invention to go up the schematic diagram that separator injects and goes up the separator propelling;
Fig. 9 illustrates the schematic diagram that carries out resistance and base injection and resistance and base propelling according to the present invention;
Figure 10 illustrates according to the present invention to form the schematic diagram that TEOS (TEOS) layer, emitter region injection and emitter region advance;
Figure 11 is the schematic diagram that illustrates according to deposit Si3N4/LTO of the present invention (low temperature oxide layer) layer, etching contact hole;
Figure 12 illustrates the schematic diagram that forms the ground floor metal line according to the present invention;
Figure 13 is the schematic diagram that illustrates according to deposit PSG of the present invention (phosphorosilicate glass)/BSG (Pyrex)/PSG and etching through hole;
Figure 14 is the schematic diagram that forms the second layer metal wiring according to the present invention;
Figure 15 A-15D is the schematic diagram that illustrates according to the whole plane metallization processes of one embodiment of the present of invention;
Figure 16 A-16C is according to an alternative embodiment of the invention, is illustrated in the schematic diagram of etching contact hole in the whole plane TEOS/Si3N4/LTO structure shown in Figure 15 D; And
Figure 17 is the frequency characteristic figure that illustrates according to the device that process for preparing bipolar IC of the present invention obtained.
Below with reference to accompanying drawing preferred embodiment of the present invention is described in detail.Those skilled in that art are appreciated that these accompanying drawings just schematically, but not limitation of the present invention.
As described below, referring to figs. 1 to 14 manufacturing process of describing according to bipolar integrated circuit of the present invention.
Fig. 1 is the schematic diagram that original silicon chip 1 is shown.In Fig. 1, it is the silicon polished of 8.0-12 ohmcm that original silicon substrate 1 can adopt P (100) crystal orientation and resistivity.But other silicon chip is known to those skilled in the art.
As shown in Figure 2, at first in the pre-injection oxide layer 2 that forms on the silicon substrate about about 50 of one deck-Yue 200 (preferably about 135 ).
Then, as shown in Figure 3, coating one photoresist layer 100 carries out photoetching composition then on this oxide layer 2, to expose the zone of N+ buried regions to be formed, area exposed is carried out the Sb ion inject, to form Sb (N+) buried regions 3.Certainly, also can use other known in this area ion.
Then, as shown in Figure 4, remove photoresist layer 100.Under the temperature about about 500 ℃ to about 2000 ℃ (preferably about 1225 ℃), carrying out about about 4 hours buried regions propelling under N2 and the O2 atmosphere, thereby the junction depth of buried regions 3 is reached about about 4.5 μ m then.Meanwhile, 3 form thickness and be about oxide layer about 2000 -3500 (being generally about 2700 ) in Sb buried regions district.This is the enhancing oxidation effect of locating because of heavy doping N+ district (Sb buried regions district 3), so the oxidated layer thickness in the buried regions district 3 is greater than the oxidated layer thickness on the place.
Then, as shown in Figure 5, oxide layer is carried out full wafer float light, stay about 200-600 .Then, apply a photoresist layer 200, and carry out photoetching composition,, in area exposed, inject boron ion (for example, B then to expose the zone of separator down to be formed
11), to form down isolated area 4.Then, after removing photoresist and cleaning, under the temperature about about 500 ℃ to about 1500 ℃ (preferably 1120 ℃), at N
2And O
2Carrying out about 2 hours following separator in the atmosphere advances.Similar to the situation during buried regions advances, after following separator advances, on isolated area 4 down, form the oxide layer (not shown) of about 4000 to about about 6000 (being generally 5000 ).
Then, float oxide layer on the total that light obtains.Then, as shown in Figure 6, growth one deck is mixed the N type epitaxial loayer 5 of arsenic on whole surface.The thickness of epitaxial loayer 5 is for about the about 5.0 μ m of about 3.0-, and resistivity is about 1 ohmcm.
Then, as shown in Figure 7,, on this oxide layer 6, apply a photoresist layer 300, and carry out photoetching composition, to expose the zone in dark phosphorus to be formed district in the oxide layer 6 of growth one deck about 250 on the epitaxial loayer to about about 450 (being preferably about 350 ).In this zone, inject phosphonium ion (for example, P then
31).Then, after removing photoresist and cleaning, under the temperature about about 500 ℃ to about 1500 ℃ (preferably about 1125 ℃), at N
2And O
2Atmosphere in carry out about 1 hour dark phosphorus district and advance, to form dark phosphorus district 7.Dark phosphorus district 7 junction depths are about about 2.3 μ m.The effect in this dark phosphorus district 7 is to reduce collector series resistance, reduces the pipe forward voltage drop, improves pipe output driving force.Be similar to the situation that above-mentioned buried regions advances, when carrying out the propelling of dark phosphorus district, in dark phosphorus district 7, form the oxide layer (not shown) of about 3000 -Yue 4500 (being generally about 3800 ).
Subsequently, full wafer corrosion (floating light) oxide layer stays about 550 of about 250-.Then, as shown in Figure 8, be coated with last layer photoresist layer 400 again, and carry out photoetching composition, to expose zone (upper and lower area of isolation corresponds to each other) of going up separator to be formed.Then boron ion (for example, B is carried out in this zone
11) inject.After removing photoresist, cleaning, under the temperature about about 500 ℃ to about 1500 ℃ (being preferably about 1100 ℃), at N
2And H
2/ O
2Carry out about about 2 hours last separator under the atmosphere and advance, separator 8 formations in, and with following separator 4 connection-meanings to leading to isolation.In the progradation of last separator 8, on last separator 8, also form thicker oxide layer (not shown).Then, full wafer corrosion (floating light) oxide layer stays about 200-400 .
Then, as shown in Figure 9, as known in this area, utilize resistance (P-), base (intrinsic base region), P+ (extrinsic base region) mask (not shown), carry out P-district, base, the injection of P+ district boron ion respectively, and under the temperature about about 500 ℃ to 1500 ℃ (preferably about 950 ℃), at N
2And H
2/ O
2Advance about 1 hour in the atmosphere.Thereby, form P district 9, base 10 and P+ district 11 respectively.The junction depth of formed base 10 is about about 0.5 μ m.Meanwhile, on base 10, form the oxide layer of about 1000 to about 2000 (being generally 1700 ).
Then, as shown in figure 10, remove the whole oxide layer on the silicon chip.Then, TEOS (TEOS) layer 14 (or the SiO of about 300 of low temperature deposition one deck to about about 700 (being preferably about 500 )
2).Deposition temperature is about 500 ℃ to about 900 ℃, preferably about 700 ℃.Utilize known emitter region mask (illustrating), carry out radiation zone glue and inject.Then, under the temperature about about 450 ℃ to about 1200 ℃ (being preferably about 850 ℃), at N
2Advance about 30 minutes in the atmosphere, thereby form emitter region 12.Can regulate the junction depth size of emitter region 12 according to the β that wants, generally about 0.2-0.5 μ m.As known in this area, when forming the emitter region, also form collector region 13.Below will be explained in more detail forming the TEOS layer.
Subsequently, as shown in figure 11, at the silicon nitride (Si of about 300 of deposit one deck on the whole surface of formed structure to about about 700 (being preferably 500 )
3N
4) layer 15, the low temperature oxide layer (LTO) 16 of about 2500 of deposit one deck to about about 4500 (being preferably about 3500 ) more thereon then.Deposition temperature is about 250 ℃ to about 550 ℃, preferably about 400 ℃.Utilize known contact hole mask version (not shown) respectively LTO layer 16, silicon nitride layer 15 to be carried out dry etching and TEOS layer 14 is carried out wet etching, thereby form each contact hole 17.Below will be explained in more detail forming silicon nitride layer and low temperature oxide layer.
Then, as shown in figure 12, the sputter first metallization aluminium lamination 18 on the total that obtains.By the known first aluminium mask (not shown), form the first metal composition, and it is carried out dry etching then, form first metal wiring pattern 18.
Then, as shown in figure 13, about 9000 of deposit are to first phosphorosilicate glass (PSG) layer 20 of about 15000 (being preferably about 11000 ) on the surface of acquired structure, apply the photoresist (not shown) of about 9000 of one deck more thereon to about 15000 (preferably about 12000 ), to carry out large-area complanation etching, realize relative complanation.Then, second phosphorosilicate glass layer 22 of about 1500 of deposit one deck to the Pyrex (BSG) of about 2500 (being preferably about 2000 ) layer 21 and about 6500 to about 8500 (preferably about 7500 ) again, utilize known via mask version (not shown), form the through hole composition and the 2nd PSG layer 22, bsg layer 21 and a PSG layer 20 are carried out wet method and add dry etching, thereby form the passage of through hole 19-between connecting up as ground floor metal line and second layer metal.
Then, as shown in figure 14, on total, (comprise in the through hole) sputtered aluminum, and utilize the known second aluminium mask (not shown), and form the second metallization aluminium composition, it is carried out dry etching, form the second metallization aluminium wiring figure 23, realize device interconnection.Again on whole surface deposit one deck 9000 to the Si of about 15000 (preferably about 12000 )
3N
4The passivation layer (not shown).By the pressure point mask, carve the passivation layer that goes to the pressure point place.But form the weld zone (pad) 24 of device.Also need alloy at last, make its contact good.
Formed bipolar integrated circuit technology by above processing step referring to figs. 1 to 14.
Then, describe according to the whole plane metallization processes in the manufacturing process of the bipolar integrated circuit of one embodiment of the invention to 15D with reference to figure 15A.Here, the whole plane metallization processes was meant before the etching contact hole, made the total surface not have tangible step, was the whole plane state.
Figure 15 A illustrates the profile after resistance, the base propelling.Shown in Figure 15 A, dark phosphorus district 7 is heavy doping N+ districts, and there is the enhancing oxidation in heavy doping N+ district.Specifically, about 1000 of the oxide layer on the base are thick to about 2000 (being generally 1700 ), and the oxidated layer thickness in dark phosphorus district 7 is that about 2000 are to about 3000 (being generally 2500 ).Difference between these two thickness depends on concentration, oxidizing temperature and the oxidation model in dark phosphorus district 7.In general, N+ concentration is high more, and long oxide layer is fast more, and dry-oxygen oxidation is bigger than wet oxygen oxidation difference, and low-temperature oxidation is bigger than high-temperature oxydation difference.
Then, shown in Figure 15 B, float all oxide layers on the total that is obtained.The TEOS layer 14 of about 700 of the about 300-of deposit one deck (preferably about 500 ) under the temperature about about 500-900 ℃ (preferably being about 700 ℃) then, thus realize the whole planeization of silicon chip surface.Certainly need to be grasped process detail.Deal with improperly and will produce the PN junction electric leakage.
Then, shown in Figure 15 C, inject (for example, P at the emitter region ion
31) after, carry out emitter region annealing and advance the formation emitter region.But, do not use the high temperature oxygen-containing atmosphere in order to guarantee the whole plane structure.Otherwise will exceed a step at 7 places, dark phosphorus district.This process adopts N
2Annealing, propelling way.Only the have an appointment TEOS layer 14 of 300-700 of the surface of guaranteeing total, preferably about 500 .TEOS layer 14 is by fine and close in annealing process.The density of the TEOS layer 14 after the annealing is significantly improved.
Then, shown in Figure 15 D, after the emitter region advances, the low temperature silicon nitride (Si of about 700 of the about 300-of deposit one deck (preferably about 500 ) again on total
3N
4) layer 15 and the LTO (SiO of the about 2500-4500 of one deck (preferably about 3500 )
2) layer 16.It is not enough that the TEOS layer 14 of 300-700 is only arranged on the PN junction face, because can produce serious wiring capacitance and low field breakdown voltage like this.In order to ensure the whole plane structure, must adopt the method for chemical vapor deposition.For example, can adopt PECVD deposit Si
3N
4Layer 15, and can adopt APCVD deposit LTO.About the nearly 250-550 of deposition temperature ℃, preferably about 400 ℃.
Adopt the advantage of aforesaid whole plane metallization processes to be:
1. simplified etching contact hole technology.Because whole planeization eliminated non-planar surfaces, so that the required degree of depth of etching is identical.
2. reduced the PN junction electric leakage.Because the All Ranges of contact hole such as base, emitter region, collector region etc. all have identical oxidated layer thickness, eliminated because each regional oxidated layer thickness difference is (common, oxide layer on the emitter region is the thinnest, the thickest on the base) the over etching that causes to place, emitter region silicon, thereby avoid producing the PN junction electric leakage, the PN junction electric leakage tends to cause circuit malfunction.
3. the whole plane structure does not have step, thus improved the step hiding power greatly, thus improved the reliability of device.
Below, describe according to the LTO/Si in the manufacturing process of the bipolar integrated circuit of another embodiment of the present invention with reference to figure 15D
3N
4/ TEOS three-decker technology.
LTO/Si before etching contact hole shown in Figure 15 D
3N
4/ TEOS three-decker.Shown in Figure 15 D, before etching contact hole as shown in figure 11, at first form LTO/Si
3N
4Three layers of dielectric structure of/TEOS.Wherein, TEOS layer 14 is to float all SiO of light after advancing through the base
2Afterwards, thermal decomposition under the temperature about about 500 ℃-900 ℃ (preferably about 700 ℃) and the TEOS layer of the about 300-700 of one deck of deposit, its performance (vacuum density, dielectric constant) is between the SiO of high-temperature thermal oxidation and low temperature deposition
2Between; Si
3N
4Layer 15 is after the emitter region advances, and uses the method such as chemical vapor depositions such as PECVD, the Si under low temperature (about about 250 ℃-550 ℃, preferably about 400 ℃) about the about 300-700 of one deck of deposit
3N
4LTO layer 16 is to follow Si closely
3N
4After layer 15 deposit at once under the low temperature about about 250-550 ℃ (preferably about 400 ℃), the low temperature oxide layer about the about 2500-4500 of one deck (preferably about 3500 ℃) of deposits such as employing APCVD method.
Adopt this LTO/Si
3N
4The advantage of/TEOS three-decker technology is:
1. guarantee whole plane metallization processes structure.Do not adopt high temperature, oxygen-containing atmosphere.
2.TEOS the effect of layer is to adopt the low-temperature epitaxy thermal oxidation and form, thereby its quality height and compactness are good.
3.Si
3N
4The effect of layer is:
(1). improved the puncture voltage of dielectric layer.This is because Si
3N
4Dielectric constant big, pinhold density is little, thereby the puncture voltage height, thereby makes the withstand voltage increase of integrated circuit.
(2). reduced the PN junction electric leakage.Because Si
3N
4Film compactness compares SiO
2Good, the interfacial state and the movable charge at the topped place of PN junction are wanted much less.In addition, because Si
3N
4Topped, improve the surface state that finishes, significantly reduced surface recombination velocity.Si is arranged
3N
4The β ratio of topped LPNP does not have Si
3N
4Topped wanting is big more than 50%, thereby the sensitivity of integrated circuit is improved, and leakage current reduces, withstand voltage raising.
(3). this also is needs of making the capacitor dielectric layer in the integrated circuit.The structure of capacitor dielectric layer is generally Si
3N
4/ TEOS.Therefore, form Si
3N
4Layer need not to increase processing step.
4. because etching LTO/Si
3N
4With etching Si
3N
4The selection of/TEOS is higher frequently.Therefore, the repeatability of etching contact hole technology can be done finely.
5.LTO the effect of layer is that it has enough thickness, thereby can reduce parasitic capacitance.
Subsequently, describe according to the contact hole etching technology in the manufacturing process of the bipolar integrated circuit of another embodiment of the present invention to 16C with reference to figure 16A.
At the first time shown in Figure 16 A contact hole etching, i.e. etching LTO.For example, can adopt Teg11-2# program reactive ion etching (anisotropy) LTO layer 16.Has the control of automatic process terminal during etching.Etching LTO layer 16 and etching Si
3N
4Selection than＞4.That is to say when etching into Si
3N
4In time, can stop automatically.This dry etching can adopt CF
4, SF
6, HCl or CHF
3Deng special gas.
Then, go on foot at second of etching contact hole shown in Figure 16 B, i.e. etching Si
3N
4For example, can adopt Teg01,2# program reactive ion etching Si
3N
4Layer 15.This etching has the automatic process terminal control function equally.Etching Si
3N
4With etching TEOS speed ratio greater than 4.That is can stop automatically when, etching into TEOS.This dry etching can adopt CF
4, SF
6, HCl or CHF
3Deng special gas.
Subsequently, shown in Figure 16 C, carry out the 3rd step of etching contact hole, promptly TEOS is carried out wet etching.Before wet etching TEOS, can carry out post bake, the stripping counterdie.The purpose of post bake is further to reinforce the bonding force of photoresist and silicon dioxide, is unlikely when wet etching to come unstuck.The polymer that the purpose of stripping counterdie stays when being to remove preceding twice dry etching.For example, wet etching can adopt 7: 1 BOE (buffered oxide etch agent, for example HF+HN
3F: H
2O) solution.Corrosion temperature is about about 10-30 ℃ (being preferably 23 ℃).When corrosion, control etching time.Because the TEOS corrosion rate is very fast.Not so can influence the section of contact hole.
The specific example of foundation process for preparing bipolar IC of the present invention has been described as mentioned above.But those skilled in the art know that above various sizes and temperature range only are schematically, can carry out various modifications to it.In addition, the technology that those skilled in the art also can other identical effect substitutes above-described special process.
This technology is with the difference of common process, for all adopting full wet processing more than or equal to the lines common process about 6 μ m.For the many employings dried humidification process of lines about smaller or equal to 4 μ m.And common process adopts first wet etching more, the method for back dry etching.Because dry etching can cause the over etching of silicon, thereby makes the out-of-flatness of knot face, bring the PN junction electric leakage, and process tolerant is very little thereupon.And the present invention adopts distinguished secondary dry method, the hole etching technology of a wet method, i.e. and wet etching is adopted in etching contact hole final step, and abandons dry etching.The effect of this dry-dry-wet hole etching technology method is very obvious, because wet etching has prevented over etching to silicon, thereby makes the knot face smooth and avoided the PN junction electric leakage.Use wet etching, technology is simple, process tolerant is very big.
As mentioned above, have according to the characteristics and the innovation part of process for preparing bipolar IC of the present invention with respect to prior art:
(1). shallow junction: base junction depth is about 0.52 μ m, and the emitter region junction depth is about 0.3 μ m.Inject realization shallow junction like this with phosphorus, also nobody reported at least at home.The present invention advances the back to carry out full chilling process by the base and realizes.
(2). the whole plane metallization processes: the whole plane metallization processes is meant that the etching contact hole does not have the technology step on the silicon chip before, has only the TEOS (cryogenic oxidation silicon) of 300-700 .Its advantage is significantly-simplified the etching contact process, reduced the PN junction electric leakage.
(3). adopt TEOS/SI
3N
4/ LTO three-decker.Adopt the advantage of three-decker to be: the first, be low temperature process entirely, be no more than about 250-900 ℃.Established PN junction is not produced passing; The second, it is the dielectric capacitance needs that silicon nitride is arranged, and improves again and finishes the topped mass of medium of face, has improved field breakdown, has reduced junction leakage.
(4). wet etching is adopted in the final step of etching contact hole, and abandons dry etching.This also is an innovation.Effect is very obvious.Because dry etching can cause the over etching of silicon, the out-of-flatness of knot face.Bring the PN junction electric leakage thereupon.And process tolerant is very little.Use wet etching, technology is simple, process tolerant is very big.
Figure 17 illustrates the frequency characteristic according to the device that process for preparing bipolar IC of the present invention obtained.In Figure 17, transverse axis is represented emitter current (μ A), and vertical pivot is represented frequency (MHz).Shown in the frequency characteristics of Figure 17, this device has reached higher frequency.Method of the present invention is particularly useful for the bipolar integrated circuit that characteristic size is about 1.5 μ m * 1.5 μ m-2.0 μ m * 2.0 μ m.
More than, preferred embodiment of the present invention has been described in conjunction with the accompanying drawings.But those skilled in the art should be understood that and the invention is not restricted to above-described specific examples, and can revise separately and change it.
Claims (8)
1. method of making bipolar integrated circuit may further comprise the steps:
The preparation Semiconductor substrate;
In described Semiconductor substrate, form buried regions;
Optionally in described Semiconductor substrate, form isolated area;
At described Semiconductor substrate growing epitaxial layers;
In described Semiconductor substrate, form the base;
Remove all oxide layers on the described Semiconductor substrate, deposit TEOS layer;
In described Semiconductor substrate, form the emitter region;
On described TEOS layer, form Si
3N
4Layer;
At described Si
3N
4Form low temperature oxide layer on the layer;
At described TEOS layer/described Si
3N
4Etching contact hole optionally in the layer/described low temperature oxide layer structure; And
On the structure that obtains, form metal line.
2. the method for claim 1, in the scope of 700 , deposition temperature is in 500-900 ℃ scope at 300 for the thickness that it is characterized in that described TEOS layer.
3. method as claimed in claim 2 is characterized in that described Si
3N
4In the scope of 700 , deposition temperature is in 250-550 ℃ scope at 300 for the thickness of layer.
4. method as claimed in claim 3, in the scope of 4500 , deposition temperature is in 250-550 ℃ scope at 2500 for the thickness that it is characterized in that described low temperature oxide layer.
5. method according to any one of claims 1 to 4, the step that it is characterized in that the etching contact hole also comprise with dry etch process optionally the described low temperature oxide layer of etching, with the dry etch process described silicon nitride layer of etching and optionally with the wet-etching technology step of the described TEOS of etching optionally.
7. method according to any one of claims 1 to 4 is characterized in that also comprising and carries out rinsing to forming buried regions, form isolated area, form the base and forming the oxide layer that forms in the step of emitter region, to form the step of planar structure.
8. method according to any one of claims 1 to 4, the step that it is characterized in that forming isolated area also comprise and form the following isolated area that corresponds to each other and connect and the step of last isolated area respectively.
9. method according to any one of claims 1 to 4 is characterized in that the step that forms metal line also comprises the step that forms two-layer wiring.
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|---|---|---|---|
| CNB011126620A CN1149658C (en) | 2001-04-18 | 2001-04-18 | Process for preparing bipolar IC |
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|---|---|---|---|
| CNB011126620A CN1149658C (en) | 2001-04-18 | 2001-04-18 | Process for preparing bipolar IC |
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| CN1149658C true CN1149658C (en) | 2004-05-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013023528A1 (en) * | 2011-08-12 | 2013-02-21 | 无锡华润上华半导体有限公司 | Capacitor and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100337323C (en) * | 2002-12-31 | 2007-09-12 | 上海贝岭股份有限公司 | Manufacturing technology of high voltage integrated circuit |
| CN100447982C (en) * | 2002-12-31 | 2008-12-31 | 上海贝岭股份有限公司 | Technology of manufacturing high voltage semiconductor device |
| CN100367477C (en) * | 2004-05-12 | 2008-02-06 | 上海先进半导体制造有限公司 | Technique for fabricating bipolar device under improved two-layer wiring |
| CN101017809B (en) * | 2007-02-16 | 2011-08-31 | 上海集成电路研发中心有限公司 | Structure for forming dual-pole integrated circuit contact hole and contact hole making method |
| CN102931063B (en) * | 2011-08-10 | 2016-05-11 | 无锡华润上华半导体有限公司 | The preparation method of double grid dielectric layer |
| CN103177958B (en) * | 2011-12-22 | 2016-08-03 | 北大方正集团有限公司 | A kind of integrated Schottky diode and manufacture method thereof |
| CN110739205B (en) * | 2019-10-24 | 2022-01-11 | 苏师大半导体材料与设备研究院(邳州)有限公司 | Surface passivation method of semiconductor material |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013023528A1 (en) * | 2011-08-12 | 2013-02-21 | 无锡华润上华半导体有限公司 | Capacitor and preparation method thereof |
| US9391133B2 (en) | 2011-08-12 | 2016-07-12 | Csmc Technologies Fab1 Co., Ltd. | Capacitor and preparation method thereof |
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