CN101043023A - Method for forming a 3d integrated circuit - Google Patents
Method for forming a 3d integrated circuit Download PDFInfo
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- CN101043023A CN101043023A CNA2006101118190A CN200610111819A CN101043023A CN 101043023 A CN101043023 A CN 101043023A CN A2006101118190 A CNA2006101118190 A CN A2006101118190A CN 200610111819 A CN200610111819 A CN 200610111819A CN 101043023 A CN101043023 A CN 101043023A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention provides a method for forming a three dimensional integrated circuit, comprising: a first wafer with a silicon layer is provided, a second wafer, the top surface of which is provided with a silicon monoxide layer, is arranged on the top surface of the first wafer. A pressure, preferably a low pressure, is applied to the top surface of the silicon monoxide layer which is in corresponding to the top surface of the silicon layer. The first and the second wafer are connected to form a contact plug for electrically connecting integrated circuits in the first and the second wafers. Before connecting the first and the second wafers, the surface of the silicon monoxide is preferably to be leveled off by chemical mechanical polishing and plasma disposal. The method for forming the three dimensional integrated circuit provided by the invention, which makes use of a covalent bond between a silicon atom and an oxygen atom to carry out joining process under low pressure and low temperature and to keep the porosity and dielectric constant of a low dielectric constant, is applicable to form three dimensional integrated circuits with low dielectric capacity.
Description
Technical field
The present invention is relevant for a kind of integrated circuit, and is particularly to a kind of 3D integrated circuit structure and forming method thereof.
Background technology
Since the invention of integrated circuit since the increase of bulk density and various electronic component (for example: transistor, diode, resistor and electric capacity etc.) development, semiconductor industry has experienced the process of one section fast development.Generally speaking, semi-conductor industry can have development so fast depend on critical size continue dwindle, therefore can in limited zone, pile up more circuit.
Development of integrated circuits comes down to two-dimensional structure, integrated circuit is the surface that is deposited in semiconductor crystal wafer, make two-dimentional integrated circuit that very big progress be arranged though photoetching technique is progressive fast, but bulk density still has many physical restriction in the development of two-dimensional structure, one of them is exactly to need minimum size to form these elements, when more multicomponent is formed on wafer, then need more complicated design.
When number of elements increased, the quantity of interelement lead and length also can produce extra processing procedure restriction, and capacitance-resistance sluggishness and energy consumption also can increase thereupon simultaneously.
For solving the restriction of above-mentioned processing procedure, thereby develop and three-dimensional integrated circuit structure.In the processing procedure of typical three dimensional integrated circuits, form two wafers that have integrated circuit separately earlier.Then, behind the element alignment two wafers are connected.Afterwards, form the element that dark contact plunger connects first and second substrate.
Utilize the three-dimensional structure integrated circuit technique can reach higher component density, reached the connection of six wafer at present, therefore, can effectively reduce the length of lead.The number of contact plunger also can reduce.Learn that by above-mentioned the three dimensional integrated circuits technology will have an opportunity to become the mainstream technology in next epoch.
The method that tradition is used for connecting two wafers comprises: adhesion connects, directly copper connects (direct copper bonding) and the direct oxidation thing connects (direct oxidebonding), wherein the adhesion connection is with binding agent two wafers to be connected, the simple and lower cost of this method, but its subject matter is its thermally-stabilised lower and ductility.When the 3rd wafer be connected to two bondd wafer the time, the sticker between first and second wafer can shrink because of heating, and the uneven contraction of sticker can produce stress, makes the connection of follow-up more polycrystalline circle produce difficulty.
Directly to connect be that two wafers with the surface has a copper packing apply a high pressure to copper, 80 pounds to 100 pounds approximately per square inch of general applied pressures, so that two wafers are connected, but the dielectric material on the wafer can cause its density to increase under this high pressure, and its dielectric constant is increased.
Connecting as for the direct oxidation thing, is two wafers that the surface had oxide layer, with oxide oxide is engaged.Then, form contact plunger and extend through oxide layer to connect wafer.The direct oxidation thing connects its process temperatures approximately between 400 to 500 ℃, and the highest about 900 ℃, and the while also imposes 40 to 50psi pressure.Yet the high temperature of processing procedure and high pressure also cause the increase of advanced low-k materials dielectric constant.
Tradition adhesion processing procedure, directly copper connects and the direct oxidation thing connects and all is fit to be used for forming the three dimensional integrated circuits with high dielectric constant material, for example: comprise that dielectric constant is approximately greater than the integrated circuit of 3.5 dielectric material.Yet these methods equally also can cause the increase of porousness dielectric materials dielectric constant, or cause the problem of ductility.Therefore, existing joining technique also is not suitable for the three dimensional integrated circuits with advanced low-k materials, so the formation method that industry is needed a kind of new three dimensional integrated circuits badly is improved the problem that traditional combination process produces.
Summary of the invention
In view of this, the invention provides a kind of formation method of three dimensional integrated circuits, comprising: one first wafer is provided, comprises that a silicon layer is positioned at the top surface of this first wafer; One second wafer is provided, comprises that one silica layer is positioned at the top surface of this second wafer; The top surface of this silicon oxide layer is corresponded to the top surface of this silicon layer, and apply a pressure with engage this first and this second wafer; And the formation contact plunger, in order to connect this first and the integrated circuit of this second wafer.
The formation method of three dimensional integrated circuits of the present invention more comprised before engaging this first wafer and this second wafer this silicon oxide layer is carried out a cmp processing procedure.
The formation method of three dimensional integrated circuits of the present invention comprised more that before engaging this first wafer and this second wafer one of them carries out a plasma processing procedure to this silicon layer and this silicon oxide layer at least.
The formation method of three dimensional integrated circuits of the present invention, wherein this pressure is less than 20 pounds/square inch (psi).
In addition, the present invention still provides a kind of formation method of three dimensional integrated circuits, comprising: one first wafer is provided, comprises that one first internal connection-wire structure is positioned on one first substrate; One second wafer is provided, comprises that one second internal connection-wire structure is positioned on one second substrate, wherein this second substrate comprises silicon; On this first internal connection-wire structure, form one silica layer; Applying one handle wafer on this second internal connection-wire structure; With this second substrate of thinning processing procedure thinning; The top surface of this silicon oxide layer is corresponded to the surface that this second substrate one is exposed, and apply a pressure with engage this first and this second wafer; Remove this handle wafer; And form contact plunger in order to connect this first and this second internal connection-wire structure.
The formation method of three dimensional integrated circuits of the present invention, wherein this second substrate comprises semi-conductor layer, one insulating barrier is positioned on this semiconductor layer, and a silicon layer is positioned on this insulating barrier, and wherein this thinning processing procedure comprises and removes this semiconductor layer and this insulating barrier.
The formation method of three dimensional integrated circuits of the present invention more comprises and utilizes the cmp processing procedure on the whole with the surface evening of this silicon oxide layer.
The formation method of three dimensional integrated circuits of the present invention more comprises before engaging this first wafer and this second wafer this silicon oxide layer is carried out a plasma treatment.
The formation method of three dimensional integrated circuits of the present invention, wherein this pressure is less than 20 pounds/square inch.
The formation method of three dimensional integrated circuits of the present invention comprises more after engaging this first wafer and this second wafer and carries out an annealing process that its annealing temperature is less than about 400 ℃.
The formation method of three dimensional integrated circuits of the present invention, wherein one of them comprises that a dielectric constant is lower than about 3.1 dielectric material at least for this first intraconnections and this second internal connection-wire structure.
The formation method of three dimensional integrated circuits of the present invention, behind this thinning processing procedure, the gross thickness of this second internal connection-wire structure and this second substrate is approximately between 10-15 μ m.
The formation method of three dimensional integrated circuits of the present invention, wherein before engaging this first wafer and this second wafer, this silicon oxide layer and this second substrate have the uneven surface of difference of height less than about 10 dusts.
The present invention still provides a kind of formation method of three dimensional integrated circuits, comprising: one first wafer is provided, comprises one first internal connection-wire structure, be positioned on one first substrate, wherein this first internal connection-wire structure comprises one first advanced low-k materials; Utilize the plasma-enhanced chemical vapor deposition PECVD method on this first internal connection-wire structure, to form one silica layer; On this silicon oxide layer, carry out a cmp processing procedure; On this silicon oxide layer, carry out first-class ion processing; One second wafer is provided, comprises one second internal connection-wire structure, be positioned on one second substrate, wherein this second substrate is a silicon base, and wherein this second internal connection-wire structure comprises one second advanced low-k materials; Applying one handle wafer on this second internal connection-wire structure; Carry out this second substrate of thinning processing procedure thinning; The top surface of this silicon oxide layer is corresponded to one of this second substrate surface and applies a pressure, with connect this first and this second wafer; Remove this handle wafer; And form contact plunger connect this first and this second internal connection-wire structure.
The formation method of three dimensional integrated circuits provided by the present invention, utilize the covalent bond between silicon atom and oxygen atom, can under low pressure and low temperature, carry out connection process, can keep the porousness and the dielectric constant thereof of low-k, be applicable to form three dimensional integrated circuits with low-k.
Description of drawings
Fig. 1 to Fig. 8 is the processing procedure profile of the wafer joint of preferred embodiment of the present invention.
Embodiment
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below:
The invention provides a kind of formation method with three dimensional integrated circuits of advanced low-k materials.Identical symbology components identical in the different diagrams and in the various embodiments of the present invention.As shown in Figure 1, provide one first wafer, in a preferred embodiment, first wafer is a silicon base 40, has element 41 on it, and as shown, internal connection-wire structure 42 is formed on the silicon base 40.Internal connection-wire structure 42 comprises the formation of dielectric layer 43, metal layer and contact plunger, for simplicity of illustration, can not show dielectric layer 43 in subsequent figures.In addition, in the preferred embodiment, the unprotect layer is formed on the internal connection-wire structure 42.In a preferred embodiment, dielectric layer comprises that dielectric constant is lower than 3.1 dielectric material, and it is 2.5 better that its dielectric constant is lower than.Porousness in the advanced low-k materials is preferable greater than 0%, and better greater than 25%.Wherein advanced low-k materials for example is: doping carbon silica, spin coating organic material or porous material.
As shown in Figure 2, behind the contact plunger that forms required metal layer and correspondence, on internal connection-wire structure 42, form etching stopping layer (etch stop layer, ESL) 48.Then, form silicon oxide layer 50.In a preferred embodiment, metal layer is approximately between the 3-5 layer.Etching stopping layer 48 is preferably carborundum, but also can be other etching stopping layer materials commonly used, for example: silicon oxide carbide, silicon oxynitride or silicon nitride.In addition, also can the metal cladding (not shown) replace etching stopping layer 48, metal cladding for example is cobalt, cobalt-tungsten or cobalt-silicon, is formed on the metal layer.Because it is to stop at metal cladding and expose metal cladding that subsequent etch forms the contact plunger open end process, so it can be used as etching stopping layer.
Silicon oxide layer is preferable to comprise that (Tetraethoxysilane TEOS), and preferablely forms silicon oxide layer 50 with low heat budget method (Low ThermalBudget) to the silicyl oxide tetraethoxysilane.In a preferred embodiment, silicon oxide layer is to utilize plasma-enhanced chemical vapor deposition PECVD method (PECVD), but also can other low heat budget methods (Low Thermal Budget), for example: carbon doped silicon oxide and spin coating oxide.The process temperatures of above-mentioned the whole bag of tricks is less than about 400 ℃, and preferred temperature is less than about 250 ℃.The preferred thickness of silicon oxide layer 50 is approximately between the 100-5000 dust.
After forming silica 50, preferablely flatten its surface with cmp processing procedure (CMP).The surface of CMP rear oxidation silicon layer 50 is on the whole smooth, and the preferable difference of height that peak and minimum point are gone up in its surface is less than about 10 dusts.
Then, plasma treatment is carried out on the surface of silicon oxide layer 50, be used for the bond between silicon atom and other atoms is interrupted, for example the Si-O bond among the Si-O-Si is interrupted to form dangling bonds, for example: Si-O-is formed on the silicon oxide layer 50.In one embodiment, the process conditions of plasma treatment comprises: pressure 1mtorr to 10mtorr, the about 20-400 of temperature ℃ and handle 2-30 second, and preferable at N
2, NH
3With and/or Ar atmosphere under carry out.In another embodiment, the process conditions of plasma treatment comprises: under an atmospheric pressure, the about 20-200 of temperature ℃ and handle 2-30 second, and preferable at Ar or H
2Carry out under the atmosphere.
Fig. 3 A shows one second wafer, comprises one second substrate 52, comprises element 53 on it.Then, form internal connection-wire structure 54 in substrate 52, wherein internal connection-wire structure 54 comprises metal layer and the contact plunger that is arranged in dielectric layer.Preferable dielectric layer comprises that dielectric constant is lower than 3.1 advanced low-k materials, goodly is lower than 2.5.
In other embodiments, shown in Fig. 3 B, the substrate in second wafer has insulation layer structure on the silicon, and wherein silicon base 52 is positioned on the insulating barrier 58, and wherein insulating barrier 58 is positioned on the semi-conducting material 56.Substrate 52 is preferable approximately between 10-15 μ m with the gross thickness T of internal connection-wire structure 54, also can greater than 15 μ m or less than 10 μ m, its gross thickness depends on wafer sum and process technique.
Then, as shown in Figure 4, with the binding agent (not shown) handle wafer 59 is pasted to internal connection-wire structure 54, handle wafer 59 can be glass, silica or aluminium oxide.In one embodiment, binding agent is ultraviolet glue, promptly loses its viscosity after it is exposed to ultraviolet ray.Then, from substrate 52 limit thinnings second wafer.The gross thickness of substrate 52 and internal connection-wire structure 54 is preferable between about 10-15 μ m after the thinning.
In another embodiment, second wafer has insulation layer structure on the silicon shown in Fig. 3 B, and semiconductor material layer is removed, and then insulating barrier 58 is removed to expose silicon base 52.
In a preferred embodiment, the surface that substrate 52 is exposed also can impose plasma treatment.The pollutant on the removable surface of plasma treatment, for example fine particle or moisture.In one embodiment, the condition of plasma treatment comprises: at Ar or H
2Under the atmosphere, the about 1mtorr to 10mtorr of pressure, the about 20-200 of temperature ℃ and handle about 2-40 second.
As shown in Figure 5, second wafer shown in Figure 4 is placed on the first wafer top shown in Figure 2, two wafers are alignd.Then carry out a connection process, execute a pressure first and second wafer is engaged, the time of exerting pressure is preferable lasting approximately above 0.5 second.In connection process, the atom on the silicon oxide layer 50, for example: oxygen atom, with the silicon atom formation covalent bond on the silicon base 52, therefore in conjunction with silicon oxide layer 50 and silicon base 52.Silicon oxide layer 50 lip-deep dangling bonds can improve the chance that forms covalent bond, can make that combining of 52 of silicon oxide layer 50 and silicon base is more stable.
Because bond only is formed on silicon oxide layer 50 and silicon base 52 contacted places, therefore, must be with the planarization as far as possible of two-phase contact plane, to increase the contact area on two planes.
The advantage of preferred embodiment of the present invention is that wafer is obviously little than conventional method in conjunction with required pressure, and for example, pressure required for the present invention is less than about 20psi (pounds persquare inch), and is preferable less than about 10psi.In one embodiment, two wafers successful combination under the about 5-10psi of pressure.Under so little pressure, on the whole the advanced low-k materials in first and second wafer can not be compressed, so its dielectric constant can obviously not increase.
Then, will in conjunction with after wafer anneal, in a preferred embodiment, annealing temperature is approximately less than 400 ℃, and is preferable approximately between 250-400 ℃, in this temperature range, can avoid causing the rising of advanced low-k materials dielectric constant.Compared to traditional joining technique, for example: directly copper engages or direct oxidation thing joint, and process temperatures of the present invention is obviously lower.And the about 10-60 of preferable annealing time minute.
Fig. 6 demonstration removes handle wafer 59.Handle wafer 59 is to utilize ultraviolet glue bonding with internal connection-wire structure 54 in one embodiment, is exposed to make it lose its viscosity under the ultraviolet light, therefore can easily wafer 59 be removed.
Fig. 7 shows the formation of metal layer, and metal layer can be pre-formed when internal connection-wire structure 54 forms.Metal layer comprises metal wire 60.As prior art, can utilize double-insert process to form metal layer, wherein double-insert process comprises: form dielectric layer on internal connection-wire structure 54, form opening in dielectric layer, then fill up metal-containing material in the opening, be preferably copper or copper alloy.Then remove unnecessary metal-containing material with the cmp processing procedure again.
Fig. 8 shows the formation of contact plunger 62.The preferable top surface from top metallization layer of contact plunger 62 openings extends to the metal wire 66 in the internal connection-wire structure 42.The preferable side 64 that exposes metal wire 60 from opening.Then fill up opening, in order to connect metal wire 66 and metal wire 60 with metal material.Remove unnecessary metal material with the cmp processing procedure again, and remaining metal material promptly forms contact plunger 62.
The integrated circuit of first and second wafer is promptly finished connection thus.Can be if the final structure of Fig. 8, repeats the processing procedure of Fig. 2 to Fig. 8 as first wafer in conjunction with polycrystalline circle more to the structure of Fig. 8.
The above-mentioned joint that is a kind of back side to the front that is to say that the back side of second wafer engages with the front of first wafer, and those skilled in the art also can carry out other as the back side and engaging of the back side or positive with positive engaging according to preferred embodiment of the present invention.Preferable one side at a wafer forms silicon oxide layer among these embodiment, forms silicon layer on one side of another wafer, two wafers is engaged with covalent bond between silicon layer by silica.
Utilize the covalent bond between silicon atom and oxygen atom, can carry out connection process under low pressure and low temperature, can keep the porousness and the dielectric constant thereof of low-k, therefore, preferred embodiment of the present invention is applicable to and forms the three dimensional integrated circuits with low-k.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
Substrate: 40,52
Element: 41,53
Internal connection-wire structure: 42,54
Silicon oxide layer: 50
Etching stopping layer: 48
Semi-conducting material: 56
Insulating barrier: 58
Wafer: 59
Metal wire: 60,66
Contact plunger: 62
Side: 64
Claims (13)
1. the formation method of a three dimensional integrated circuits is characterized in that, the formation method of described three dimensional integrated circuits comprises:
One first wafer is provided, comprises that a silicon layer is positioned at the top surface of this first wafer;
One second wafer is provided, comprises that one silica layer is positioned at the top surface of this second wafer;
The top surface of this silicon oxide layer is corresponded to the top surface of this silicon layer, and apply a pressure to engage this first wafer and this second wafer; And
Form contact plunger, in order to connect the integrated circuit of this first wafer and this second wafer.
2. the formation method of three dimensional integrated circuits according to claim 1 is characterized in that, more comprised before engaging this first wafer and this second wafer this silicon oxide layer is carried out a cmp processing procedure.
3. the formation method of three dimensional integrated circuits according to claim 1 is characterized in that, comprises more that before engaging this first wafer and this second wafer one of them carries out a plasma processing procedure to this silicon layer and this silicon oxide layer at least.
4. the formation method of three dimensional integrated circuits according to claim 1 is characterized in that, this pressure is less than 20psi.
5. the formation method of a three dimensional integrated circuits is characterized in that, the formation method of described three dimensional integrated circuits comprises:
One first wafer is provided, comprises that one first internal connection-wire structure is positioned on one first substrate;
One second wafer is provided, comprises that one second internal connection-wire structure is positioned on one second substrate, wherein this second substrate comprises silicon;
On this first internal connection-wire structure, form one silica layer;
Applying one handle wafer on this second internal connection-wire structure;
With this second substrate of thinning processing procedure thinning;
The top surface of this silicon oxide layer is corresponded to the surface that this second substrate one is exposed, and apply a pressure to engage this first wafer and this second wafer;
Remove this handle wafer; And
Form contact plunger in order to connect this first intraconnections and this second internal connection-wire structure.
6. the formation method of three dimensional integrated circuits according to claim 5, it is characterized in that this second substrate comprises semi-conductor layer, an insulating barrier is positioned on this semiconductor layer, and one silicon layer be positioned on this insulating barrier, wherein this thinning processing procedure comprises and removes this semiconductor layer and this insulating barrier.
7. the formation method of three dimensional integrated circuits according to claim 5 is characterized in that, more comprises utilizing the cmp processing procedure on the whole with the surface evening of this silicon oxide layer.
8. the formation method of three dimensional integrated circuits according to claim 5 is characterized in that, more comprises before engaging this first wafer and this second wafer this silicon oxide layer is carried out a plasma treatment.
9. the formation method of three dimensional integrated circuits according to claim 5 is characterized in that, this pressure is less than 20 pounds/square inch.
10. the formation method of three dimensional integrated circuits according to claim 9 is characterized in that, more comprises after engaging this first wafer and this second wafer and carries out an annealing process, and its annealing temperature is lower than 400 ℃.
11. the formation method of three dimensional integrated circuits according to claim 10 is characterized in that, one of them comprises that a dielectric constant is lower than 3.1 dielectric material at least for this first intraconnections and this second internal connection-wire structure.
12. the formation method of three dimensional integrated circuits according to claim 5 is characterized in that, behind this thinning processing procedure, the gross thickness of this second internal connection-wire structure and this second substrate is between 10-15 μ m.
13. the formation method of three dimensional integrated circuits according to claim 5 is characterized in that, before engaging this first wafer and this second wafer, this silicon oxide layer and this second substrate have the uneven surface of difference of height less than 10 dusts.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/385,968 | 2006-03-21 | ||
| US11/385,968 US7371662B2 (en) | 2006-03-21 | 2006-03-21 | Method for forming a 3D interconnect and resulting structures |
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| CN101043023A true CN101043023A (en) | 2007-09-26 |
| CN100561709C CN100561709C (en) | 2009-11-18 |
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| US (1) | US7371662B2 (en) |
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| FR2978295A1 (en) * | 2011-07-18 | 2013-01-25 | St Microelectronics Sa | Method for forming bearing structure of interconnection levels, involves forming openings in bearing structure from side to boundary by etching, and covering bottom part and sides of openings by layer of conductive material |
| US9111912B2 (en) | 2013-05-30 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
| US9929050B2 (en) * | 2013-07-16 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure |
| US9437484B2 (en) * | 2014-10-17 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
| US11094613B2 (en) * | 2019-08-22 | 2021-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
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| JPH09331049A (en) * | 1996-04-08 | 1997-12-22 | Canon Inc | Pasted soi substrate and its production |
| SE511721C2 (en) * | 1997-06-18 | 1999-11-15 | Ericsson Telefon Ab L M | Substrates for integrated high frequency circuits and method for substrate production |
| US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
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- 2006-07-13 TW TW095125639A patent/TWI309433B/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102738026A (en) * | 2011-03-31 | 2012-10-17 | 索泰克公司 | Methods of forming bonded semiconductor structures and semiconductor structures formed by such methods |
| CN102738026B (en) * | 2011-03-31 | 2014-11-05 | 索泰克公司 | Methods of forming bonded semiconductor structures and semiconductor structures formed by such methods |
| CN104617101A (en) * | 2013-11-05 | 2015-05-13 | 台湾积体电路制造股份有限公司 | Systems and methods for a semiconductor structure having multiple semiconductor-device layers |
| CN104934365A (en) * | 2014-03-20 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN104934365B (en) * | 2014-03-20 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN106356370A (en) * | 2015-07-13 | 2017-01-25 | 爱思开海力士有限公司 | Switched-capacitor dc-to-dc converters and methods of fabricating the same |
| CN106356370B (en) * | 2015-07-13 | 2020-08-18 | 爱思开海力士有限公司 | Switched capacitor DC-DC converter and method of manufacturing the same |
| CN106365115A (en) * | 2015-07-23 | 2017-02-01 | 上海丽恒光微电子科技有限公司 | MEMS sensor and preparation method thereof |
| CN106365115B (en) * | 2015-07-23 | 2019-08-23 | 上海丽恒光微电子科技有限公司 | MEMS sensor and preparation method thereof |
| CN111477603A (en) * | 2019-01-23 | 2020-07-31 | 联华电子股份有限公司 | Three-dimensional integrated circuit and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200737285A (en) | 2007-10-01 |
| US20070224776A1 (en) | 2007-09-27 |
| CN100561709C (en) | 2009-11-18 |
| TWI309433B (en) | 2009-05-01 |
| US7371662B2 (en) | 2008-05-13 |
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