FR2978295A1 - Method for forming bearing structure of interconnection levels, involves forming openings in bearing structure from side to boundary by etching, and covering bottom part and sides of openings by layer of conductive material - Google Patents

Abstract

The method involves forming interconnection levels (3, 5) on two sides of a silicon wafer (1). Openings are formed in a bearing structure from a side to a boundary by etching, where the boundary is formed between the silicon wafer and the interconnect levels of a face of the bearing structure. A bottom part and sides of the openings are covered by a layer of a conductive material (57). A polymer layer (58) is deposited over the layer of conductive material to fill the openings formed in the bearing structure. An insulating layer (56) is formed on walls of the openings. An independent claim is also included for a device for forming a bearing structure of interconnection levels.

Description

B11044 - 11-GR1-0322EN01 1 METHOD FOR FORMING A STRUCTURE HAVING INTERCONNECTION LEVELS ON BOTH SIDES AND VIAS TRAVERSAN'T'S

FIELD OF THE INVENTION The present invention relates to a method of forming a structure carrying interconnection levels on its front face and on its rear face and comprising through-nodes.

DISCUSSION OF THE PRIOR ART In certain applications, it is desired to form assemblies of integrated circuits intended to be connected to printed circuits. One way to obtain a high density of integrated circuits is to assemble them on both sides of a semiconductor wafer, itself arranged above a printed circuit and at a distance from it. It is desired to form an integrated circuit assembly of the type illustrated, in sectional view, in FIG. 1. FIG. 1 represents a silicon wafer 1 on both sides of which integrated circuits are assembled. Slice 1 carries interconnection levels 3 on its front face and interconnect levels 5 on its rear face. The interconnection levels 3 and 5 consist of several levels of conductive tracks separated by insulating layers, each of these insulating layers being traversed by B11044 - 11-GR1-0322EN01

2 conductive nias connecting conductive tracks of different levels. The conductive tracks are for example copper. Integrated circuit chips are connected to the wafer 1 by means of conductive balls 9. For example, two integrated circuits 7 and 8 have been represented on the side of the front face of the wafer 1 and an integrated circuit 13 on the side of its back side. Through-holes 15, comprising at least one conductive layer, for example made of copper, have been represented in slot 1. They make it possible to electrically connect the interconnection levels 3 of the front face of slot 1 to the interconnection levels 5. from its back side. By way of example, there is shown a set 11 of conductive tracks and conductive nias connecting a ball 9 of the integrated circuit chip 7 to a ball 9 of the integrated circuit chip 8. Two sets 16 and 17 conductive tracks and conductive nias connecting, via a via via 15, a ball 9 of the integrated circuit chip 7 of the front face to a ball 9 of the integrated circuit chip 13 of the rear face . In addition, there is shown partially a set 23 of conductive tracks and conductive nias, connecting a ball 9 of an integrated circuit chip of the rear face not shown, to a pad 22 of a printed circuit 21, by via a contact socket 19 below the interconnection levels 5 and a conductive ball 20 disposed between the contact 19 and the stud 22. Finally, two sets 25 and 26 of FIG. conductor tracks and conductive nias, connecting through a through via 15, a ball 9 of an integrated circuit chip of the not shown front face, a contact 19 and a ball 20 of a stud 22 In an integrated circuit assembly of the type illustrated in FIG. 1, in practice at least four interconnection levels are required on the front face of the wafer, and two to four levels of interconnection on the front face of the wafer are required. its back side, for B11044 - 11-GR1-0322EN01

3 make the desired connections between the various integrated circuit chips. There is a problem to form several levels of interconnection on the rear face of a silicon wafer comprising traversing nias and carrying several levels of interconnection on its front face. SUMMARY Thus, an object of an embodiment of the present invention is to provide a method of forming a structure comprising a silicon wafer carrying interconnection levels on its front face and on its rear face and comprising niases. through. To achieve this object, an embodiment of the present invention provides a method of forming a structure carrying interconnection levels on its front face and on its back face and comprising a plurality of through-nodes, said method comprising the steps following forms interconnect levels on both sides of a silicon wafer; forming, by etching, openings in the structure from one of its faces until reaching the limit between the silicon wafer and the interconnection levels of the other face of the structure; and covering the bottom and the walls of the openings with at least one layer of a conductive material.

According to one embodiment of the present invention, the structure carries at least four interconnection levels on its front face, and two to four levels of interconnection on its rear face. According to one embodiment of the present invention, the method comprises, after step c), a step of depositing a layer of polymer above said at least one layer of conductive material so as to fill the openings formed in step b). According to an embodiment of the present invention, the method comprises, between step b) and step c), a step B11044 - 11-GR1-0322EN01

4 consisting of forming an insulating layer on the walls of the openings. According to one embodiment of the present invention, the silicon wafer has a thickness between 200 and 300 micrometers. According to an embodiment of the present invention, in step b), the diameter of the openings formed is between 100 and 150 micrometers. According to an embodiment of the present invention, in step c), the bottom and the walls of the openings are covered with a stack of first and second layers of conductive material. According to one embodiment of the present invention, the first layer of conductive material is of a material selected from the group consisting of Ti, TiN, Ta and TaN. According to an embodiment of the present invention, the second layer of conductive material is made of a material selected from the group consisting of Cu, W, Al and AlSiCu. According to one embodiment of the present invention, the polymer layer is of a material selected from the group consisting of polyimide, benzocyclobutene (BCB) and epoxy. According to one embodiment of the present invention, the polymer layer is based on an alumina compound (Al-X). According to one embodiment of the present invention, the insulating layer is of a material selected from the group consisting of SiO 2 and Si 3 N 4. According to one embodiment of the present invention, the insulating layer is a polymer layer. The present invention further provides a device 30 comprising a silicon wafer carrying interconnection levels on its front face and on its rear face and comprising a plurality of traversing nias, said traversing nias stopping at the boundary between the wafer. silicon and interconnection levels of one of the two faces, and crossing the interconnection levels of the other side.

B11044 - 11-GR1-0322EN01

According to one embodiment of the present invention, the silicon wafer carries at least four interconnection levels on its front face, and two to four levels of interconnection on its rear face. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, features, and advantages will be set forth in detail in the following description of particular embodiments in a non-limitative manner with reference to the accompanying drawings in which: FIG. previously, is a sectional view of an integrated circuit assembly connected to a printed circuit; FIGS. 2A to 2D are cross-sectional views illustrating successive steps of a method of forming a structure comprising a silicon wafer carrying interconnection levels on its front face and on its rear face and comprising traversing nias; Figures 3A-3D are sectional views of a through-hole forming method; and Fig. 4 is a sectional view illustrating an exemplary via via an integrated circuit assembly of the type shown in Fig. 1, according to an embodiment of the present invention. As is usual in the representation of integrated circuits, the various figures are not drawn to scale. DETAILED DESCRIPTION FIGS. 2A-2D are sectional views illustrating successive steps of an exemplary method of forming a structure comprising a silicon wafer having interconnection levels on its front face and on its back face and including traversing nias. Figure 2A shows a portion of a silicon wafer 31 carrying interconnection levels 33 on its front face. The interconnection levels 33 consist of B11044 - 11-GR1-0322EN01

6 several levels of conductive tracks, for example copper, separated by insulating layers, each of these insulating layers being traversed by conductive nias connecting conductive tracks of different levels.

FIG. 2B illustrates a step of forming an opening 35 in the silicon wafer 31, previously turned over, from its rear face, until reaching the limit between its front face and the interconnection levels 33. FIG. 2C illustrates a step of completely filling the aperture 35 formed in the previous step. The walls of the opening 35 are first covered with an insulating layer 36. Then, a layer of a conductive material 37, for example a copper layer, is formed, generally by electrolytic growth, from the bottom of the opening and the layer 36, so as to completely fill the opening 35. As illustrated in Figure 2D, it is then possible to form interconnection levels 39 on the flat rear face of the wafer 31 The interconnection levels 39, like the interconnection levels 33, consist of several levels of conductive tracks, for example made of copper, separated by insulating layers, each of these insulating layers being crossed by conductive nias connecting tracks. drivers of different levels. A disadvantage of the methods of the type described above is that they involve completely filling the apertures 35 with the conductive material 37. For small apertures, for example 80 μm deep and 10 μm wide, the time for filling openings is reasonable, of the order of two hours by electrolytic growth. In the case where it is desired to use a thick silicon wafer, for example with a thickness greater than 200 μm, it is necessary to form openings with a diameter greater than 100 μm. The full filling time of such openings would then be too long. A method as described in connection with FIGS. 2A to 2D is therefore not B11044 - 11-GR1-0322EN01

7 can be used in practice to form large diameter through nias in thick silicon wafers of a structure carrying interconnection levels on both sides. FIGS. 3A to 3D illustrate successive steps of a through-hole forming method adapted to silicon wafers with a thickness greater than 200 μm and openings of more than 100 μm in diameter. As shown in FIG. 3A, inter-connection levels 33 are first formed on one of the faces of a silicon wafer 31. FIG. 3B illustrates, after flipping of the wafer 31, the formation of FIG. an opening 35 in the slice 31 from its other side. FIG. 3C illustrates a step of depositing a stack of several layers of different materials in the opening 35 of the wafer 31 and above the upper face of the wafer 31. A layer of an insulating material 36, for example, a layer of SiO 2, Si 3 N 4 or a polymer is formed on the walls of the opening 35. A barrier and hooking layer of a first conductive material 41, for example a layer of Ti, TiN, Ta or TaN, is formed above the insulating layer 36 and at the bottom of the opening 35. Above the layer of conductive material 41, is deposited a layer of a second conductive material 43, for example a layer of Copper, tungsten, aluminum or AlSiCu. As shown, the layers 41 and 43 present on the surface are then etched in a chosen pattern. Thus, the via via is constituted by the conductive layers 41 and 43 which line the walls and the bottom of the opening 35 but do not fill it. It remains an opening 44. It is then desired to form interconnection levels on the upper face of the wafer 31. For this, it is necessary to deposit insulating layers and conductive layers 35. Because of the presence of the opening 44, this B11044 - 11-GR1-0322EN01

8 proves difficult because some of these layers will be found at the bottom of the opening 44. In addition, in general, it is preferred to avoid leaving openings in integrated circuits. For these two reasons, it is desired to fill the opening 44. The simplest solution is to fill the opening 44 with a polymeric material. FIG. 3D illustrates a step of depositing a polymer layer 45 over the layer of conductive material 43, so as to fill the opening 44.

Even after the step illustrated in FIG. 3D of deposition of the polymer layer 45 making it possible to fill the opening 44, it is difficult to form interconnection levels on the upper face of the wafer 31. First, it It would be necessary to obtain a planar upper surface, comprising for example copper 43 and a polymer 45. However, there is no reliable method for simply smoothing the surface of a structure comprising a layer of conductive material and a layer of polymer. In addition, the subsequent steps of forming the interconnection levels would be difficult to achieve because of the presence, on the same wafer, of the polymer of the layer 45, which is an organic material, and other materials of mineral nature. In practice, the insufficient planarization of the upper face of the wafer 31 limits the photolithography processes used to form the interconnection levels to the production of patterns of large width and limits the number of interconnection levels. It is therefore not possible to achieve on the upper face of the wafer 31 high density interconnection levels, which increases the size and cost of a circuit assembly as illustrated in FIG. reduces performance. A method of forming a structure comprising a silicon wafer carrying interconnection levels on its front face and on its rear face and comprising traversing niases that overcomes the disadvantages of the B11044 - 11-GR1-0322EN01 is proposed here.

9 processes described above. A structure obtained by such a method is shown partially in section in FIG. 4. FIG. 4 illustrates a portion of a structure as illustrated in FIG. 1, and more specifically a particular example of through-holes 15 that can be formed in such a structure. structure. The elements common with Figure 1 are designated by the same references. To achieve this structure, one starts from a silicon wafer 1, for example with a thickness greater than 200 μm, for example between 200 and 300 μm, carrying interconnection levels 3, 5 on both sides. Apertures, of diameter for example between 100 and 150 μm, are then formed by etching from one of the faces of the wafer 1, until reaching the limit between the wafer 1 and the interconnection levels of the wafer. 'other face. After forming the openings in the wafer 1, the walls of the openings are covered with a layer of an insulating material 56, for example a layer of SiO 2, Si 3 N 4 or polymer. Then, a stack of conductive layers 57, for example a stack of a barrier layer and Ti, TiN, Ta or TaN, and a layer of copper, tungsten, aluminum or AlSiCu, is formed above the layer 56 and at the bottom of the openings. The traversing nias consist of the stack of conductive layers 57 which line the bottom and the walls of the openings. A polymer layer 58, for example a layer of polyimide, benzocyclobutene (BCB), epoxy, or a layer based on aluminum compounds (Al-X), is then deposited on top of the stack of conductive layers 57, so as to fill the openings, either partially, as shown in Figure 4, or completely. The part of the polymer layer 58 which is on the surface of the lower side of the wafer 1 is etched so as to clear the ball reception zones 62 of an integrated circuit 13 and the reception zones 63 of the balls 20 of B11044 - 11-GR1-0322EN01

10 mounting of the wafer on a printed circuit not shown. The zones 62 are prepared in advance, during the formation of the interconnection levels 5. The zones 62 are part of a set of conductive tracks and conductive niases 52, connected to the portion of the stack of conductive layers. 57 via via which is on the surface of the slice 1 on the side of its underside. On the side of the upper face of the wafer 1, the ball receiving zones 61 of an integrated circuit 8 are prepared during the formation of the interconnection levels 3. The zones 61 form part of a set of conductive tracks and conductive nias 51, connected to the portion of the stack of conductive layers 57 located at the bottom of the opening. Thus, via the sets of tracks and nias 51 and 52 and via via, balls 9 of the integrated circuit 8 on the side of the upper face of the wafer 1 are electrically connected to balls 9 of the integrated circuit 13 of the side of the lower face of the wafer 1. A method as described in connection with Figure 4 has several advantages over methods of the type described in relation to Figures 2A to 2D and 3A to 3D. As the traversing nias are formed after the formation of the interconnection levels on both sides of the silicon wafer, it is no longer necessary for the face of the wafer from which the openings are formed to be flat after the formation of the wafers. crossing nias. The through nias may consist of a conductive layer or a stack of conductive layers covering the walls and the bottom of the openings without filling it. The conductive layer or the stack of conductive layers of the through nias may be covered with a polymer layer, the polymer layer does not necessarily fill the openings. Thus, the duration and cost of formation of the through nias remains reasonable, even in the case of thick silicon wafers and large diameter openings. In any case, it is possible to form several interconnection levels of B11044 - 11-GR1-0322EN01

11 high density, on both sides of the silicon wafer, since they are formed before the crossing nias. This improves the compactness, and therefore the manufacturing cost and performance, of a circuit assembly as illustrated in FIG. 1. Those skilled in the art will know how to use the proposed method for making assemblies of integrated circuits such as schematically illustrated in Figure 1, with a number of interconnection levels on each side of the silicon wafer adapted to the desired connections between the various integrated circuit chips.

Claims (15)

REVENDICATIONS1. A method of forming a structure having interconnection levels (3, 5) on its front face and on its rear face and comprising a plurality of through-nodes (15), said method comprising the steps of: a) forming levels interconnection (3, 5) on both sides of a silicon wafer (1); b) forming, by etching, openings in the structure from one of its faces until reaching the boundary between the silicon wafer (1) and the interconnection levels of the other face of the structure; and c) covering the bottom and the walls of the openings with at least one layer of conductive material (57). 2. The method of claim 1, wherein the structure carries at least four levels of interconnection on its front face, and two to four levels of interconnection on its rear face. The method of claim 1 or 2 comprising, after step c), a step of depositing a polymer layer (58) over said at least one layer of conductive material (57) to fill the openings formed in step b). 4. A method according to any one of claims 1 to 3, comprising, between step b) and step c), a step of forming an insulating layer (56) on the walls of the openings. 5. Method according to any one of claims 1 to 4, wherein the silicon wafer (1) has a thickness of between 200 and 300 micrometers. 6. A process according to any one of claims 1 to 5, wherein in step b) the diameter of the apertures formed is between 100 and 150 micrometers. 7. A method according to any one of claims 1 to 6, wherein, in step c), the bottom and the walls of the apertures are covered with a stack of a first and a second one. a second layer of conductive material. The method of claim 7, wherein the first layer of conductive material is of a material selected from the group consisting of Ti, TiN, Ta and TaN. The method of claim 7 or 8, wherein the second layer of conductive material is of a material selected from the group consisting of Cu, W, Al and AlSiCu. The method of claim 3, wherein the polymer layer (58) is of a material selected from the group consisting of polyimide, benzocyclobutene (BCB) and epoxy. 11. The method of claim 3, wherein the polymer layer (58) is based on an alumina compound (Al-X). The method of claim 4, wherein the insulating layer (56) is of a material selected from the group consisting of SiO 2 and Si 3 N 4. The method of claim 4, wherein the insulating layer (56) is a polymer layer. 14. A device comprising a silicon wafer (1) carrying interconnection levels (3, 5) on its front face and on its rear face and comprising a plurality of traversing nias (15), said traversing nias stopping at the boundary between the silicon wafer (1) and the interconnection levels of one of the two faces, and crossing the interconnection levels of the other face. 15. Device according to claim 14, wherein the silicon wafer (1) carries at least four levels of interconnection on its front face, and two to four levels of interconnection on its rear face.