CN100428492C - Ultrahigh voltage metal oxide semiconductor transistor component - Google Patents
Ultrahigh voltage metal oxide semiconductor transistor component Download PDFInfo
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- CN100428492C CN100428492C CNB2005101097965A CN200510109796A CN100428492C CN 100428492 C CN100428492 C CN 100428492C CN B2005101097965 A CNB2005101097965 A CN B2005101097965A CN 200510109796 A CN200510109796 A CN 200510109796A CN 100428492 C CN100428492 C CN 100428492C
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Abstract
The element includes parts: substrate with first conduction type (CT); a doping area of source electrode with second CT setup in substrate; first doping area with first CT in substrate and adjacent to the doping area of source electrode closely; first ion trap with first CT of surrounding the doping area of source electrode and the first doping area; gate oxide layer formed on the doping area of source electrode and the first ion trap; being formed on a semiconductor area, a field oxide layer is linked up to the gate oxide layer; thickened dielectric layer of covering above the field oxide; being far away from the doping area of source electrode, the doping area of drain electrode with second CT is setup on side of the field oxide layer; second ion trap with second CT of surrounding the doping area of drain electrode; being setup on the gate oxide layer, the gate electrode is extended to the field oxide layer and the thickened dielectric layer.
Description
Technical field
The present invention relates to a kind of semiconductor superhigh pressure element, particularly relate to a kind of can with the superhigh pressure MOS transistor element of low voltage component compatibility, simultaneously can solve the superelevation vertical electric field effect that is caused the grid corner.
Background technology
As is known to the person skilled in the art, with superhigh pressure element and low voltage component, as high/low pressure metal-oxide-semiconductor (MOS) (MOS) transistor, the integrated circuit technique of integration and making is existing skill simultaneously.
See also Fig. 1, what it illustrated is the generalized section of existing superhigh pressure nmos pass transistor element.Existing superhigh pressure nmos pass transistor element 1 is produced at semiconductor-based the end 10, P type silicon base for example, and completely cut off by field oxide 44.In general, existing superhigh pressure nmos pass transistor element 1 includes one source pole 14, a grid 50 and a drain electrode 24, wherein source electrode 14 is a high concentration N type doped region, it is in close proximity to a high concentration P type doped region 16, and high concentration N type doped region (source electrode) 14 all is located in the P type trap 12 with high concentration P type doped region 16.Drain electrode 24 and source electrode 14 may be at a distance of to more than several microns, and wherein draining 24 is a high concentration N type doped region, be located in the N type trap 22, and N type trap 22 are located at again in the dark N type trap 30, so constitute triple gradient well structures.
As shown in Figure 1, on source electrode 14, be formed with a grid oxic horizon 46, and grid 50 is arranged on promptly on the grid oxic horizon 46, and extends to a field oxide 42 tops.In addition, on field oxide 42, be provided with a plurality of field plates of floating 52 in addition, be used for upsetting horizontal electric field.Field oxide 42 is with locality silicon oxidation (local oxidation of silicon, LOCOS) mode forms, it is between source electrode 14 and drain electrode 24, and be can be in the extra-high pressure scope, for example hundreds of volt, even go up the kilovolt work of finishing drilling, the thickness t of field oxide 42 needs 10 at least, the thickness that 000 dust (angstrom) is above can reduce the superelevation vertical electric field effect that the corner 70 of grid 50 is caused.
Yet, grow thick field oxide 42 like this and not only can in boiler tube, consume more time, cause productivity impairment, and the thicker field oxide 42 of growing up, also can lose chip area owing to the beak of field oxide (bird ' sbeak) effect causes the area of low voltage component excessively to increase.Therefore, how on technology, to cooperate low voltage component, when can reduce field oxide 42 thickness, take into account the superelevation vertical electric field effect that the corner 70 of reducing grid 50 is caused again, promptly become present problem demanding prompt solution.
Summary of the invention
Main purpose of the present invention promptly provide a kind of can with the superhigh pressure MOS transistor element of low voltage component compatibility, can solve simultaneously the superelevation vertical electric field effect that cause the corner of grid.
According to a preferred embodiment of the invention, the present invention discloses a kind of superhigh pressure MOS transistor element, comprises a substrate, and it has one first conduction type; One has the source doping region of one second conduction type, is located in this substrate; One has first doped region of this first conduction type, is located in this substrate, and is in close proximity to this source doping region; One has first ion trap of this first conduction type, and it surrounds this source doping region and this first doped region; One grid oxic horizon is formed on this source doping region and this first ion trap; One field oxide is connected mutually with this grid oxic horizon, and is formed on the semiconductor regions of this first ion trap, one side; One thickens dielectric layer, covers this field oxide top; One has the drain doping region of this second conduction type, away from this source doping region, is located at the opposite side of this field oxide with respect to this first ion trap; One has second ion trap of this second conduction type, and it surrounds this drain doping region; An and grid, be located on this grid oxic horizon, and extending to this field oxide and this thickens on the dielectric layer, this field oxide has one first thickness, and this first thickness is 5,000 dust to 6,000 dust, and this thickens dielectric layer and has one second thickness, and this second thickness is 10,000 dust to 15,000 dust.
According to another preferred embodiment of the invention, the present invention discloses a kind of superhigh pressure MOS transistor element, comprises a silicon epitaxial layers; One has first ion trap of one first conduction type, is located in this silicon epitaxial layers; One has the source doping region of one second conduction type, is located in this first ion trap; One has first doped region of this first conduction type, is located in this first ion trap, and is in close proximity to this source doping region; One grid oxic horizon is formed on this source doping region and this first ion trap; One has second ion trap of this second conduction type, is located in this silicon epitaxial layers; One has the drain doping region of this second conduction type, is located in this second ion trap; One field oxide is connected mutually with this grid oxic horizon, and is formed on this silicon epitaxial layers between this first ion trap and this drain doping region; One thickens dielectric layer, covers this field oxide top; An and grid, be located on this grid oxic horizon, and extending to this field oxide and this thickens on the dielectric layer, this field oxide has one first thickness, and this first thickness is 5,000 dust to 6,000 dust, and this thickens dielectric layer and has one second thickness, and this second thickness is 10,000 dust to 15,000 dust.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 illustrated is the generalized section of existing superhigh pressure nmos pass transistor element.
What Fig. 2 illustrated is the generalized section of superhigh pressure NMOS element of the present invention.
What Fig. 3 illustrated is the generalized section of the superhigh pressure NMOS element of another preferred embodiment of the present invention.
What Fig. 4 illustrated is the present invention's generalized section of the superhigh pressure NMOS element of another preferred embodiment again.
The simple symbol explanation
The 10 semiconductor-based ends of 1 superhigh pressure nmos pass transistor element
12 P type traps, 14 source electrodes
16 high concentration P type doped region 22N type traps
24 drain electrodes, 30 dark N type traps
32 N type silicon epitaxial layers
42 field oxides, 44 field oxides
46 grid oxic horizons, 50 grids
52 field plates
100 superhigh pressure nmos pass transistor elements
142 field oxides, 148 dielectric layers
149 etching stopping layers
200 superhigh pressure nmos pass transistor elements
300 superhigh pressure nmos pass transistor elements
Embodiment
See also Fig. 2, what it illustrated is the generalized section of superhigh pressure NMOS element of the present invention.The present invention can also be applied in superhigh pressure PMOS element technology, only needs to get final product electrically making suitable modification.
According to a preferred embodiment of the invention, superhigh pressure nmos pass transistor element 100 is produced at semiconductor-based the end 10, P type silicon base for example, and completely cut off by field oxide 44.Superhigh pressure nmos pass transistor element 100 includes one source pole 14, a grid 50 and a drain electrode 24 equally, wherein source electrode 14 is a high concentration N type doped region, it is in close proximity to a high concentration P type doped region 16, and high concentration N type doped region (source electrode) 14 all is located in the P type trap 12 with high concentration P type doped region 16.Drain electrode 24 and source electrode 14 may be at a distance of to more than several microns, and wherein draining 24 is a high concentration N type doped region, be located in the N type trap 22, and N type trap 22 are located at again in the dark N type trap 30, so constitute triple gradient well structures.Grid 50 can be metal or polysilicon gate.
According to a preferred embodiment of the invention, on source electrode 14, be formed with a grid oxic horizon 46, and grid 50 is arranged on promptly on the grid oxic horizon 46, and extends transverse to a field oxide 142 and a dielectric layer 148 tops.In addition, on dielectric layer 148, also be provided with a plurality of (floating) field plates (fieldplate) 52 of floating, be used for upsetting horizontal electric field.Field oxide 142 with the locality silicon oxidation (local oxidationof silicon, LOCOS) mode forms, its between source electrode 14 and the drain electrode 24 between, thickness is t
1, t wherein
1Be about 5,000 dusts to 6, the 000 Izod right side.The invention is characterized in addition that on field oxide 42 it is t that storehouse has thickness
2 Dielectric layer 148, t wherein
2Be about 10,000 dusts to 15, the 000 Izod right side.
According to a preferred embodiment of the invention, dielectric layer 148 utilize chemical vapour deposition (CVD) (chemical vapordeposition, CVD) the formed CVD silica layer of method, perhaps, can also first dopant deposition polysilicon layer, reoxidize this doped polysilicon layer subsequently.By such practice, can make the integral thickness of field oxide 142 and dielectric layer 148 increase to 18,000 dust to 20, the 000 Izod right side, but the high grid 50 of frame not only solve the problem of the superelevation vertical electric field that the corner of grid causes by this, and because field oxide 142 thickness that form in the thermal oxidation mode are limited in 5,000 dust to 6, the 000 Izod right side can be compatible with the making of low voltage component.
In addition, because dielectric layer 148 utilizes the formed CVD silica layer of chemical gaseous phase depositing process, so its density is unlike the field oxide 142 that forms in locality silicon oxidation mode below it.In other words, another characteristic of the present invention promptly additionally forms a more unsound relatively dielectric layer 148 on the field oxide 142 of densification (dense).
See also Fig. 3, what it illustrated is the generalized section of another preferred embodiment superhigh pressure of the present invention NMOS element 200.The dielectric layer 148 of the superhigh pressure NMOS element 200 that the difference between the superhigh pressure NMOS element 100 that is illustrated in the superhigh pressure NMOS element 200 that is illustrated among Fig. 3, itself and Fig. 2 only is among Fig. 3 to be illustrated includes an etching stopping layer 149, for example silicon nitride layer.In addition, dielectric layer 148 can also be that low-k (k＜4.0) material constitutes, for example porous silica or the like.
See also Fig. 4, what it illustrated is the present invention's generalized section of the superhigh pressure NMOS element 300 of another preferred embodiment again.The superhigh pressure NMOS element 300 that is illustrated among Fig. 4, the dark N type trap 30 of the superhigh pressure NMOS element 300 that the difference between the superhigh pressure NMOS element 100 that is illustrated among itself and Fig. 2 only is among Fig. 4 to be illustrated is with 32 replacements of N type silicon epitaxial layers, and P type trap 12 all is formed in N type epitaxial silicon (epitaxial silicon) layer 32 with N type trap 22.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. MOS transistor element comprises:
One substrate, it has one first conduction type;
One has the source doping region of one second conduction type, is located in this substrate;
One has first doped region of this first conduction type, is located in this substrate, and is in close proximity to this source doping region;
One has first ion trap of this first conduction type, and it surrounds this source doping region and this first doped region;
One grid oxic horizon is formed on this source doping region and this first ion trap;
One field oxide is connected mutually with this grid oxic horizon, and is formed on the semiconductor regions of this first ion trap, one side;
One thickens dielectric layer, covers this field oxide top;
One has the drain doping region of this second conduction type, away from this source doping region, is located at the opposite side of this field oxide with respect to this first ion trap;
One has second ion trap of this second conduction type, and it surrounds this drain doping region; And
One grid is located on this grid oxic horizon, and extends to this field oxide and this thickens on the dielectric layer,
This field oxide has one first thickness, and this first thickness is 5,000 dusts to 6,000 dust, and
This thickens dielectric layer and has one second thickness, and this second thickness is 10,000 dusts to 15,000 dust.
2. MOS transistor element as claimed in claim 1, wherein this MOS transistor element thickens on the dielectric layer at this, is positioned at a side of this grid, also comprises a plurality of field plates of floating.
3. MOS transistor element as claimed in claim 1, wherein this to thicken dielectric layer be a chemical vapor deposited silicon oxygen layer.
4. MOS transistor element as claimed in claim 1 comprises also in this substrate below this field oxide of this MOS transistor element that wherein one has the 3rd ion trap of this second conduction type, and it surrounds this second ion trap.
5. MOS transistor element as claimed in claim 1, wherein this thickens between dielectric layer and this field oxide and also comprises an etching stopping layer.
6. MOS transistor element as claimed in claim 5, wherein this etching stopping layer is a silicon nitride layer.
7. MOS transistor element comprises:
One silicon epitaxial layers;
One has first ion trap of one first conduction type, is located in this silicon epitaxial layers;
One has the source doping region of one second conduction type, is located in this first ion trap;
One has first doped region of this first conduction type, is located in this first ion trap, and is in close proximity to this source doping region;
One grid oxic horizon is formed on this source doping region and this first ion trap;
One has second ion trap of this second conduction type, is located in this silicon epitaxial layers;
One has the drain doping region of this second conduction type, is located in this second ion trap;
One field oxide is connected mutually with this grid oxic horizon, and is formed on this silicon epitaxial layers between this first ion trap and this drain doping region;
One thickens dielectric layer, covers this field oxide top; And
One grid is located on this grid oxic horizon, and extends to this field oxide and this thickens on the dielectric layer,
This field oxide has one first thickness, and this first thickness is 5,000 dusts to 6,000 dust, and
This thickens dielectric layer and has one second thickness, and this second thickness is 10,000 dusts to 15,000 dust.
8. MOS transistor element as claimed in claim 7, wherein this silicon epitaxial layers has this second conduction type.
9. MOS transistor element as claimed in claim 7, wherein this MOS transistor element thickens on the dielectric layer at this, is positioned at a side of this grid, also comprises a plurality of field plates of floating.
10. MOS transistor element as claimed in claim 7, wherein this to thicken dielectric layer be a chemical vapor deposited silicon oxygen layer.
11. MOS transistor element as claimed in claim 7, wherein this grid is constituted by polysilicon.
12. MOS transistor element as claimed in claim 7, wherein this grid is constituted by metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101097965A CN100428492C (en) | 2005-09-20 | 2005-09-20 | Ultrahigh voltage metal oxide semiconductor transistor component |
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| CNB2005101097965A CN100428492C (en) | 2005-09-20 | 2005-09-20 | Ultrahigh voltage metal oxide semiconductor transistor component |
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| CN1937248A CN1937248A (en) | 2007-03-28 |
| CN100428492C true CN100428492C (en) | 2008-10-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866868B (en) * | 2009-04-17 | 2011-10-05 | 中芯国际集成电路制造(上海)有限公司 | Monitoring method of semiconductor process |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037178B (en) * | 2017-06-12 | 2020-08-21 | 世界先进积体电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN110634834B (en) * | 2018-06-25 | 2021-10-08 | 世界先进积体电路股份有限公司 | Semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5591681A (en) * | 1994-06-03 | 1997-01-07 | Advanced Micro Devices, Inc. | Method for achieving a highly reliable oxide film |
| CN1514481A (en) * | 2002-12-31 | 2004-07-21 | 上海贝岭股份有限公司 | Technology of manufacturing high voltage semiconductor device |
| CN1591800A (en) * | 2003-09-01 | 2005-03-09 | 上海宏力半导体制造有限公司 | Method for mfg. improed structure high-voltage elements |
-
2005
- 2005-09-20 CN CNB2005101097965A patent/CN100428492C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5591681A (en) * | 1994-06-03 | 1997-01-07 | Advanced Micro Devices, Inc. | Method for achieving a highly reliable oxide film |
| CN1514481A (en) * | 2002-12-31 | 2004-07-21 | 上海贝岭股份有限公司 | Technology of manufacturing high voltage semiconductor device |
| CN1591800A (en) * | 2003-09-01 | 2005-03-09 | 上海宏力半导体制造有限公司 | Method for mfg. improed structure high-voltage elements |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866868B (en) * | 2009-04-17 | 2011-10-05 | 中芯国际集成电路制造(上海)有限公司 | Monitoring method of semiconductor process |
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