CN1509001A - Multi channel digital signal generator - Google Patents
Multi channel digital signal generator Download PDFInfo
- Publication number
- CN1509001A CN1509001A CNA021280320A CN02128032A CN1509001A CN 1509001 A CN1509001 A CN 1509001A CN A021280320 A CNA021280320 A CN A021280320A CN 02128032 A CN02128032 A CN 02128032A CN 1509001 A CN1509001 A CN 1509001A
- Authority
- CN
- China
- Prior art keywords
- module
- signal
- state
- digital signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Debugging And Monitoring (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The generator comprises module for analyzing signal to be generated, module for selecting system clock, module for determining status number, and module for generating excitation source. With external condition being met, under driving of time clock, finite state machine completes state transition in sequence as well as outputs digital signal waveform in designated number. When external excitation condition is met, finite state machine enters a state in every other clock cycle time. Under different states, finite state machine outputs different signal levels. The invention provides a method of generating digital signal with multiple channels and arbitrary duty ratio for personnel of programming hardware. The functional modules can be integrated into users' programmable hardware design simply and seamlessly.
Description
Affiliated technical field:
The present invention relates to the digital communication technology field, particularly a kind of generator that produces multichannel, any duty ratio digital signal.
Background technology:
At present, the square wave scheme of any duty ratio of existing chip microcontroller, be regularly to export I and O by scm software control IO pin, reach the purpose of output one road to the square wave of any duty ratio of multichannel, this technical scheme main application fields is as an independently signal generator use; The major defect of this technical scheme is: not at the Embedded Application design, and system integration difficulty, timing accuracy is not high, limited by the single-chip microcomputer instruction cycle, can't produce the high-frequency waveform, as 100MHz; Be subjected to the restriction of single-chip microcomputer number of pins simultaneously, can't produce the waveform of numerous number of active lanes.
Summary of the invention:
The purpose of this invention is to provide a kind of generator that produces multichannel, any duty ratio digital signal, this generator is characteristics of using programmable logic device at existing Design of Digital System in a large number, can be for the hardware programming personnel provide the method that produces multichannel, any duty ratio digital signal, this functional module can simply seamlessly be integrated in user's the programmable hardware design.
Concrete technical scheme of the present invention is as follows:
Operation principle of the present invention is: after external condition satisfied, under clock drove, finite state machine was exported the digital signal waveform that specifies number when finishing each state exchange successively.When the external drive condition satisfied, finite state machine just entered next state every time clock cycle, under different conditions, and the signal level that finite state machine output is different.Like this, after limited state machine is finished change-over period, just obtained one group of signal output waveform sequence.This signal output waveform sequence is not limited in the square-wave signal of any duty ratio, and is more extensive, can generate the chip read-write control signal, finishes functions such as serial data stream format conversion.The signal that produces both can be from master mode, can be again the response of pumping signal to external world, both can be periodic, also can be acyclic; Phase relation is determined between the signal that produces, no burr.
The present invention includes and analyze signaling module to be produced, the selective system clock module, determine the state number module, generate the driving source module, fill in the output signal module, draw the state exchange module, translate into the hardware identification code module, compiling and debugging module, it is characterized in that: finite state machine is at analysis signaling module to be produced, under selective system clock module and the determined driving parameter of definite state number module, finish each state exchange successively, again under the pumping signal control that generates the generation of driving source module, output specifies number the digital signal with designated length and relative position, and by fill in the output signal module as required the high-low level of corresponding time period of output signal give each state output signal assignment, be easy-to-read and through picture state exchange module again with state, excitation and output are summarized in together, translate into the hardware identification code module and then state transition graph is translated into hardware identification code, process compiling and debugging module are finished the conversion of serial data stream format.
Signal of the present invention is from master mode, or the response of pumping signal to external world.
Signal of the present invention is periodic, or acyclic.
Phase relation is determined between signal of the present invention, no burr.
When analysis of the present invention is waited to produce signaling module and produced signal and be periodic signal, return first state behind last state, continue the output of second period signal; Analysis is waited to produce signaling module and is produced when being not periodic signal, and last state returns " free time " state, waits for that excitation arrives next time.
Selective system clock module of the present invention is the core of finite state machine, drives the automatic operation of finite state machine, the frequency and the precision of its clock frequency decision output waveform.
Clock cycle of the present invention is the longest can not to surpass output signal frequency.
When selective system clock module of the present invention produces corresponding two output signals, when the clock cycle is minute.
The generation driving source module of the present invention automatically output periodic signal of back that powers on enters a state of finite state machine behind input signal, output signal level is through entering the next state of finite state machine behind the input signal once more; The periodic signal of input signal is not stuck in the Last status of finite state machine.
The pumping signal that selective system clock module of the present invention is imported is chosen wantonly, is the Rule of judgment whether state machine enters next state.
Institute's output signal length is the long-pending of required state number and clock cycle in definite state number module of the present invention, during the output periodic signal, finite state machine enters first state automatically after finishing last state, begin second period work, and have only the state number of one-period length.
The present invention is from the application of any duty ratio square wave of generation, remedied the system integration difficulty that has with chip microcontroller fully, timing accuracy is not high, limited by the single-chip microcomputer instruction cycle, the shortcomings such as waveform that can't produce the high-frequency waveform and can't produce numerous number of active lanes, the also available a kind of general method for designing of the present invention is finished most of hardware interface control logic, the design work of hardware interface control logic is transformed into following the prescribed order of through engineering approaches from artistic the representing of individual, hardware engineering is an apprentice of in the heavy Interface design frees, concentrate one's energy to realize core design.
Accompanying drawing and drawing explanation:
Fig. 1 theory diagram of the present invention
Fig. 2 logic diagram of the present invention
Fig. 3 the present invention analyzes and waits to produce signal box machine frame figure
Fig. 4 selective system clock frequency of the present invention is selected instance graph
Fig. 5 the present invention draws state transition graph and implements illustration
Fig. 6 periodic signal waves figure of the present invention
Fig. 7 driving source product process of the present invention figure
The chip of Fig. 8 embodiment of the invention 4 is read sequential chart
The oscillogram that Fig. 9 embodiment of the invention 4 generates
Embodiment:
Embodiment 1:
As attached Fig. 1 and 2.The present invention includes and analyze signaling module to be produced, the selective system clock module, determine the state number module, generate the driving source module, fill in the output signal module, draw the state exchange module, translate into the hardware identification code module, compiling and debugging module, it is characterized in that:: finite state machine is at analysis signaling module to be produced, under selective system clock module and the determined driving parameter of definite state number module, finish each state exchange successively, again under the pumping signal control that generates the generation of driving source module, output specifies number the digital signal with designated length and relative position, and by fill in the output signal module as required the high-low level of corresponding time period of output signal give each state output signal assignment, be easy-to-read and through picture state exchange module again with state, excitation and output are summarized in together, translate into the hardware identification code module and then state transition graph is translated into hardware identification code, process compiling and debugging module are finished the conversion of serial data stream format.
Signal of the present invention is from master mode, or the response of pumping signal to external world.
Signal of the present invention is periodic, or acyclic.
Phase relation is determined between signal of the present invention, no burr.
As Fig. 3.When analysis of the present invention is waited to produce signaling module and produced signal and be periodic signal, return first state behind last state, continue the output of second period signal; Analysis is waited to produce signaling module and is produced when being not periodic signal, and last state returns " free time " state, waits for that excitation arrives next time.
As Fig. 7.The generation driving source module of the present invention automatically output periodic signal of back that powers on enters a state of finite state machine behind input signal, output signal level is through entering the next state of finite state machine behind the input signal once more; The periodic signal of input signal is not stuck in the Last status of finite state machine.
Embodiment 2:
As Fig. 4.Selective system clock module of the present invention is the core of finite state machine, drives the automatic operation of finite state machine, the frequency and the precision of its clock frequency decision output waveform.
Clock cycle of the present invention is the longest can not to surpass output signal frequency.
When selective system clock module of the present invention produces corresponding two output signals, when the clock cycle is minute.
In accompanying drawing 4, produce two output signals, its clock cycle is 10ns, 20ns.
Embodiment 3:
Produce as shown in Figure 6 periodic signal W1 and W2 output, its signal resolution is 10ns, i.e. 100MHz, so should select the 100MHz clock for use, the minimum of W1 and W2 altogether the multiple cycle be 30ns, so selection mode order number is 3.Owing to be self-energizing periodic signal, so do not use pumping signal.In conjunction with the accompanying drawings 5, top has indicated an input signal CLK, two input signal W1 and W2, and S1, S2, S3 are three states of finite state machine, arrow has been represented conversion direction, has indicated under various states output state signal in the right square frame of Fig. 5.
Adopt VHDL or Verilog language to realize, readable and portable strong.
Embodiment 4:
The chip read signal.As Fig. 8, Fig. 9.The selection clock cycle is 30ns, and state number is 7, needs the pumping signal of external control, increase electrification reset state machine signal RST, read the address and be placed in the register, the data-storing that reads in is in register, and the rising edge by the RD signal latchs in the register.State machine is in the IDLE state at ordinary times, in case the dynamic excitation signal effectively after, promptly, get back to the IDLE state at last again according to the state exchange of t1 to t4, prepare next read operation.The waveform that this state machine produces can satisfy corresponding sequential requirement as shown in Figure 9.
The present invention is from the application of any duty ratio square wave of generation, remedied the system integration difficulty that has with chip microcontroller fully, timing accuracy is not high, limited by the single-chip microcomputer instruction cycle, the shortcomings such as waveform that can't produce the high-frequency waveform and can't produce numerous number of active lanes, the also available a kind of general method for designing of the present invention is finished most of hardware interface control logic, the design work of hardware interface control logic is transformed into following the prescribed order of through engineering approaches from artistic the representing of individual, hardware engineering is an apprentice of in the heavy Interface design frees, concentrate one's energy to realize core design.
Claims (9)
1, a kind of multi channel digital signal generator, comprise and analyze signaling module to be produced, the selective system clock module, determine the state number module, generate the driving source module, fill in the output signal module, draw the state exchange module, translate into the hardware identification code module, compiling and debugging module, it is characterized in that:: finite state machine is at analysis signaling module to be produced, under selective system clock module and the determined driving parameter of definite state number module, finish each state exchange successively, again under the pumping signal control that generates the generation of driving source module, output specifies number the digital signal with designated length and relative position, and by fill in the output signal module as required the high-low level of corresponding time period of output signal give each state output signal assignment, be easy-to-read and through picture state exchange module again with state, excitation and output are summarized in together, translate into the hardware identification code module and then state transition graph is translated into hardware identification code, process compiling and debugging module are finished the conversion of serial data stream format.
2, a kind of multi channel digital signal generator according to claim 1, it is characterized in that: described signal is from master mode, or the response of pumping signal to external world.
3, a kind of multi channel digital signal generator according to claim 1 is characterized in that: described signal is periodic, or acyclic.
4, a kind of multi channel digital signal generator according to claim 1 is characterized in that: when described analysis is waited to produce signaling module and produced signal and be periodic signal, return first state behind last state, continue the output of second period signal; Analysis is waited to produce signaling module and is produced when being not periodic signal, and last state returns " free time " state, waits for that excitation arrives next time.
5, a kind of multi channel digital signal generator according to claim 1, it is characterized in that: described selective system clock module is the core of finite state machine, drive the automatic operation of finite state machine, the frequency and the precision of its clock frequency decision output waveform.
6, a kind of according to claim 1 or 5 multi channel digital signal generator is characterized in that: the described clock cycle is the longest can not to surpass output signal frequency.
7, a kind of according to claim 1 or 5 multi channel digital signal generator is characterized in that: when described selective system clock module produces corresponding two output signals, when the clock cycle is minute.
8, a kind of multi channel digital signal generator according to claim 1, it is characterized in that: export periodic signal after described generation driving source module powers on automatically, behind input signal, enter a state of finite state machine, output signal level is through entering the next state of finite state machine behind the input signal once more; The periodic signal of input signal is not stuck in the Last status of finite state machine.
9, according to claim 1 or 8 described a kind of multi channel digital signal generators, it is characterized in that: the pumping signal that described selective system clock module is imported is chosen wantonly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021280320A CN1299463C (en) | 2002-12-16 | 2002-12-16 | Multi channel digital signal generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021280320A CN1299463C (en) | 2002-12-16 | 2002-12-16 | Multi channel digital signal generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1509001A true CN1509001A (en) | 2004-06-30 |
| CN1299463C CN1299463C (en) | 2007-02-07 |
Family
ID=34231201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021280320A Expired - Fee Related CN1299463C (en) | 2002-12-16 | 2002-12-16 | Multi channel digital signal generator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1299463C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079890B (en) * | 2007-07-04 | 2011-03-30 | 杭州华三通信技术有限公司 | A method and device for generating characteristic code and identifying status machine |
| CN105487862A (en) * | 2015-11-26 | 2016-04-13 | 中国船舶重工集团公司第七〇五研究所 | Multichannel waveform synchronous output method based on multifunctional acquisition card of PXI bus |
| CN108279591A (en) * | 2017-12-20 | 2018-07-13 | 北京控制工程研究所 | A kind of general output method of emulation platform digital quantity |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85200160U (en) * | 1985-04-01 | 1986-07-16 | 东北工学院 | Multifunction programmable signal generator |
| CN2154566Y (en) * | 1993-03-16 | 1994-01-26 | 西安交通大学 | Signal generator with programming arbitrary digit |
| CN1074551C (en) * | 1997-06-13 | 2001-11-07 | 邹清环 | Multichannel programmable logic signal generator |
-
2002
- 2002-12-16 CN CNB021280320A patent/CN1299463C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079890B (en) * | 2007-07-04 | 2011-03-30 | 杭州华三通信技术有限公司 | A method and device for generating characteristic code and identifying status machine |
| CN105487862A (en) * | 2015-11-26 | 2016-04-13 | 中国船舶重工集团公司第七〇五研究所 | Multichannel waveform synchronous output method based on multifunctional acquisition card of PXI bus |
| CN105487862B (en) * | 2015-11-26 | 2019-02-01 | 中国船舶重工集团公司第七〇五研究所 | Multi-channel waveform synchronism output method based on PXI bus multi-function data acquisition card |
| CN108279591A (en) * | 2017-12-20 | 2018-07-13 | 北京控制工程研究所 | A kind of general output method of emulation platform digital quantity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1299463C (en) | 2007-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1170242C (en) | Logic synthetic method of semiconductor integrated circuit | |
| CN103178815B (en) | Pulse wavelength modulation (PWM) generator based on field programmable gate array (FPGA) | |
| CN1819197A (en) | Semiconductor device tested using minimum pins and methods of testing the same | |
| CN1690724A (en) | Circuit and method for testing semiconductor device | |
| CN101051332A (en) | Verifying system and method for SOC chip system grade | |
| CN86106695A (en) | A kind of isomorphism type multicomputer system and cooperation method thereof with ability to cooperate | |
| CN1717643A (en) | Clock synchronization circuit | |
| CN101047372A (en) | Pulse width modulation circuit | |
| CN1422406A (en) | Digital circuit implementation by means of parallel sequencers | |
| Borriello | Formalized timing diagrams | |
| CN1299463C (en) | Multi channel digital signal generator | |
| US20120005638A1 (en) | Race Logic Synthesis for Large-Scale Integrated Circuit Designs | |
| CN101047317A (en) | Digital synchronous indication, control method for ship power station generator | |
| CN1588639A (en) | Reset method and reset system for integrated circuit | |
| CN1959422A (en) | Detection instrument of low frequency electromagnetic wave detector | |
| CN1315018C (en) | Clock pulse switchover structure and its clock pulse switchover method | |
| CN102542161A (en) | Magnetic resonance pulse sequence integrated development system | |
| CN2624292Y (en) | ASIC for multimachine sharing of counter and signal generator | |
| EP3173895A1 (en) | Clock tree implementation method, system-on-chip and computer storage medium | |
| Kucukcakar et al. | A methodology and design tools to support system-level VLSI design | |
| Dutt et al. | Exel: A language for interactive behavioral synthesis | |
| Gopalakrishnan et al. | Towards amalgamating the synchronous and asynchronous styles | |
| Passerone et al. | Evaluation of trade-offs in the design of embedded systems via co-simulation | |
| CN1691020A (en) | Method for fast generation of pseudo-random code as driving source for simulation | |
| CN1315258C (en) | Method of generating chaos timing sequential signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070207 Termination date: 20111216 |