CN1494293A - Random storage implemented TCP connecting timer and its implementing method - Google Patents
Random storage implemented TCP connecting timer and its implementing method Download PDFInfo
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- CN1494293A CN1494293A CNA021456984A CN02145698A CN1494293A CN 1494293 A CN1494293 A CN 1494293A CN A021456984 A CNA021456984 A CN A021456984A CN 02145698 A CN02145698 A CN 02145698A CN 1494293 A CN1494293 A CN 1494293A
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Abstract
In the invention, storage unit in dual ports RAM is mapped to TCP connection timer. Initialization module sets an initialization value to the timer needed to start, and others are cleared. In rising edge of clock signal, the degression operation module reads value in storage unit starting from start address of RAM. If the value is zero, then value of next storage unit is read continuously. If the value is not zero, after minus one, the value is written in original storage unit. If the value is not zero, but is equal to one, then a position signal for controlling an interrupt controller is output. Then, the value of next storage unit is fetched and read. In the same clock signal cycle, the above operation is completed for each storage unit in RAM so as to realize corresponding function of timer. The invention makes numbers of TCP connections supported by TOE hardware increase greatly.
Description
Technical field
The present invention relates to realization and management that TCP in TCP/IP (TCP) offload engine (TOE, i.e. TCP Offload Engine) of network technology connects timer.
Background technology
Increase day by day along with the network bandwidth, particularly in data storage network, the network interface of at present traditional server just develops towards the direction of gigabit Ethernet and 10Gbps, this is a powerful challenge for processor system, the TCP/IP speed technology has appearred in this case, be offload engine, TCP Offload Engine is called for short TOE.Just the function of ICP/IP protocol stack is handled from I/O processor or the ASIC (application-specific integrated circuit (ASIC)) that traditional processor moves on to intelligent network adapter, to alleviate the burden of HOST (main frame) processor.
There are two kinds of tendencies in each producer in the TOE realization at present, and a kind of software that is based on is realized, adds the processing that the I/O processor is finished the ICP/IP protocol stack on network interface unit; And the another kind of unloading that is based on hardware asics realization ICP/IP protocol stack.
In Transmission Control Protocol, each TCP connects will use 7 timers, and they are respectively that connection is set up timer, retransmission timer, delayed acknowledgement timer, adhered to timer, keep-alive timer, FIN_WAIT_2 timer and TIME_WAIT timer.About the function and the effect of these several timers, can be referring to associated description in the ICP/IP protocol.Wherein some timer is mutual exclusion to each other, comprise connecting setting up timer and keep-alive timer, and FIN_WAIT_2 timer and TIME_WAIT timer, so these two groups of timers can be multiplexing.
Because the required precision of these timers is not too high, these timers all are to adopt software mode to realize in traditional TCP realizes.And in TOE hardware because TCP connect to be dynamically and to set up concomitantly that and generally all will support the TCP of several K～tens K to connect, if adopt traditional hardware timer method then need to expend bigger resource, and extensibility is not strong.
As seen, in the hardware implementations of present TCP offload engine, the TCP timer adopts traditional hardware timer to realize, in case TCP unloading chip is finished, the maximum concurrent TCP linking number that it is supported is just immutable, and the resource that expends is bigger.
Summary of the invention
The technical problem to be solved in the present invention is, above-mentioned defective at prior art, provide a kind of TCP that realizes with random asccess memory to connect timer and its implementation, make hardware TOE support configurable maximum number of connections, save resource on the one hand, strengthen the extensibility and the manageability of timer on the other hand.
The technical solution adopted for the present invention to solve the technical problems is: provide a kind of and realize that with random asccess memory TCP connects the method for timer, it is characterized in that, adopt double-port RAM, realize timer function according to the following steps:
(1) be that required TCP connects timer with the memory cell relationship map that is connected the timer corresponding number in the described double-port RAM with required TCP;
(2) each memory cell in the described double-port RAM is carried out initialization, the pairing memory cell of TCP connection timer that needs start is put initial value, and with the remaining memory cell zero clearing;
(3) when each clock signal arrives, begin to read the value of corresponding stored unit from the initial address of described double-port RAM;
(4) if the value of the memory cell that is read is 0, then continue to read the value of next memory cell,
If the value of the memory cell that is read is 1, then export an asserts signal that is used to control interrupt control unit simultaneously, and then read the value of next memory cell,
If the value of the memory cell that is read is not 0 and is not 1, write former memory cell again after then it being subtracted 1, and then read the value of next memory cell;
(5) in a clock signal period, repeat described (4) step, until the operation of each memory cell in the described double-port RAM being finished in (4) step.
In same clock signal period, each memory cell in the described double-port RAM is finished above-mentioned (4) step operation, can realize corresponding function of timer.
The present invention also provides a kind of TCP that realizes with random asccess memory to connect timer, it is characterized in that, comprising:
A double-port RAM wherein comprises a plurality of memory cell, and each memory cell can be mapped as a TCP and connect timer;
One is connected with an end of described double-port RAM, the pairing memory cell of timer that needs in the described double-port RAM to start can be put initial value, and with the initialization module of remaining memory cell zero clearing;
A decrement operations module that is connected with the other end of described double-port RAM, described decrement operations module is from the initial address of the described double-port RAM value of each memory cell successively, if the value of the memory cell that is read is 0, then continue to read the value of next memory cell, if the value of the memory cell that is read is 1, then export an asserts signal that is used to control interrupt control unit simultaneously, and then read the value of next memory cell, if the value of the memory cell that is read is not 0 and is not 1, write former memory cell again after then it being subtracted 1, and then read the value of next memory cell.
Connect in timer and its implementation with the TCP that random asccess memory realizes in the present invention, if the cycle of each clock signal is 200ms, then Dui Ying maximum TCP linking number can reach 500000; As seen, the present invention increases the supported TCP linking number of hardware TOE greatly, has saved resource on the one hand, has also strengthened the extensibility and the manageability of timer on the other hand.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the theory diagram of timer of the present invention;
Fig. 2 is the workflow diagram of timer of the present invention.
Embodiment
The principle of timer of the present invention as shown in Figure 1, as can be seen from the figure, the present invention adopts a double-port RAM (DPRAM), wherein comprises a plurality of memory cell, memory cell can be mapped as the timer that TCP connects.The right of DPRAM is an initialization module, and the left side is a decrement operations module.Signal between DPRAM and this two modules comprises address signal, clock signal and RAM data-signal.
Wherein, initialization module is connected with a tcp state machine primary module, can according to tcp state machine primary module input put initial value or reset signal, the memory cell of DPRAM is put initial value or clear operation accordingly.
The decrement operations module can read the value of each memory cell among the DPRAM under the control of clock signal, and can rewrite the value of each memory cell.The asserts signal output of decrement operations module is connected with interrupt control unit, and the output of interrupt control unit is connected to described tcp state machine primary module again.
In TCP connected, the value of each timer was all different, and general being provided with is as shown in table 1:
Table 1 TCP connects timer parameter list is set
| Timer | Time is provided with | |
| ????1 | Connect and set up timer | 75 seconds |
| ????2 | Retransmission timer | 1～64 second |
| ????3 | The delayed acknowledgement timer | 200 milliseconds |
| ????4 | Adhere to timer | 5～60 seconds |
| ????5 | The keep-alive timer | 7200 seconds |
| ????6 | The FIN_WAIT_2 timer | 600 seconds (for the first time); 75 seconds (for the second time) |
| ????7 | The TIME_WAIT timer | 30 seconds |
Prerequisite of the present invention is that each memory cell among the DPRAM is mapped as a plurality of timers that TCP connects, and makes each timer correspond to 16 memory cell among the DPRAM, just 16 bits in the corresponding stored unit.The timer clock benchmark that the present invention adopts is 200ms, that is to say that the cycle of each clock signal is 200ms.Setting up timer with connection is example, and because of it is set to 75s, and every 200ms carries out once-through operation, and then Dui Ying data should equal 75*1000/200=375, are equivalent to 16 bits 0000000101110111, and the rest may be inferred for other timer.
As can be seen from Table 1, the delayed acknowledgement timer is 200ms, therefore should not adopt the solution of the present invention to realize.In remaining 6 timer; timer is set up in connection and the keep-alive timer can be multiplexing; FIN_WAIT_2 timer and TIME_WAIT timer can be multiplexing simultaneously; therefore each TCP connects timer and only needs four memory cell that the address is continuous among the corresponding DPRAM; for example: memory cell 1 is corresponding to be connected and sets up timer (or keep-alive timer), memory cell 2 corresponding retransmission timers, memory cell 3 correspondences and adhere to timer, memory cell 4 corresponding FIN_WAIT_2 timers (or TIME_WAIT timer), repeats according to this to analogize.
On the basis of the above, timer of the present invention can be elaborated below by works shown in Figure 2.
Step 101: by initialization module each memory cell among the DPRAM is carried out initialization, the pairing memory cell of timer that needs start is put initial value, the remaining memory cell zero clearing.Suppose to need to start to connect to set up timer, then its pairing memory cell 1 is put initial value, just binary number 0000000101110111 is write wherein.
Step 102: judged whether a rising edge clock signal input decrement operations module, if then enter step 103.
Step 103: begin to read the value of DPRAM memory cell from initial address, just from memory cell 1.
Step 104: whether the value of judging the memory cell that is read is 0, is to represent that then this timer does not start work, and do not need execution in step 105-107 this moment, leaps to step 108; Otherwise represent that this timer is in the startup operating state, need execution in step 105;
Step 105: judging this is not whether 0 value is 1, is execution in step 106 then again, otherwise execution in step 107;
Step 106: the value of the memory cell that read was not 0 and was not 1 yet this moment, write former memory cell again after will this value being subtracted 1 by the decrement operations module, promptly read-subtract the 1-write operation.Like this, whenever receive a clock signal, the data of this memory cell all can subtract 1.Directly enter step 108 after this step.
Step 107: the value of the memory cell that read this moment is 1, the data of expression memory cell are through after repeatedly successively decreasing, reduced to 0000000000000001 from initial value, finished a count cycle, this moment, the decrement operations module can be sent an asserts signal to interrupt control unit, corresponding positions set with interrupt control unit, then by interrupt control unit notice tcp state machine primary module, carry out respective handling, for example whether to once more this memory cell be put initial value, restart a count cycle.
Step 108: when the value of the memory cell that is read is 0, perhaps be not 0 but the intact step 105 of executed to 106 or 107 o'clock, this step judges whether to have read the value of all memory cell among this DPRAM, just to memory cell 1 to memory cell N all executed the action among the step 104-107, be then to get back to step 102, wait for that new rising edge clock signal arrives, the 1-write operation is read-subtracted to a beginning new round; Otherwise execution in step 109.
Step 109, this moment expression also have the not action among the execution in step 104-107 of a memory cell at least, need read the value of next memory cell, get back to step 104 then, repeat above-mentioned action, until to memory cell 1 to memory cell N all executed till the action among the step 104-107.
Introduced the workflow of timer of the present invention above, suppose that it is 100ns that DPRAM is once read-subtract the 1-write operation time, then in a clock cycle, be can be in cycle of 200ms to the action of the individual memory cell execution in step of 2000000 (200*1000000/100=2000000) 103-109, that is to say that the number of memory cells that can travel through is 2000000; As previously mentioned, take 4 memory cell because of each TCP connects timer, then Dui Ying TCP linking number is that 500000 (2000000/4=500000) are individual; Corresponding maximum manageable DPRAM is 2M*16bits, and this value can change according to the maximum number of connections that TOE supports.
As seen, the present invention increases the supported TCP linking number of hardware TOE greatly, has saved resource on the one hand, has also strengthened the extensibility and the manageability of timer on the other hand.
Claims (6)
1, a kind of method that connects timer with random asccess memory realization TCP is characterized in that the employing double-port RAM is realized timer function according to the following steps:
(1) be that required TCP connects timer with the memory cell relationship map that is connected the timer corresponding number in the described double-port RAM with required TCP;
(2) each memory cell in the described double-port RAM is carried out initialization, the pairing memory cell of TCP connection timer that needs start is put initial value, and with the remaining memory cell zero clearing;
(3) when each clock signal arrives, begin to read the value of corresponding stored unit from the initial address of described double-port RAM;
(4) if the value of the memory cell that is read is 0, then continue to read the value of next memory cell,
If the value of the memory cell that is read is 1, then export an asserts signal that is used to control interrupt control unit simultaneously, and then read the value of next memory cell,
If the value of the memory cell that is read is not 0 and is not 1, write former memory cell again after then it being subtracted 1, and then read the value of next memory cell;
(5) in a clock signal period, repeat described (4) step, until the operation of each memory cell in the described double-port RAM being finished in (4) step.
2, method according to claim 1, it is characterized in that, in described (1) step, four memory cell that the address in the described double-port RAM is continuous are mapped as the connection of a TCP connection successively and set up timer, retransmission timer, adhere to timer and FIN_WAIT_2 timer; Connecing wherein set up timer and can be multiplexed with the keep-alive timer, and the FIN_WAIT_2 timer can be multiplexed with the TIME_WAIT timer.
3, method according to claim 1 is characterized in that, the cycle of the clock signal in described (3) step is 200ms.
4, a kind of TCP that realizes with random asccess memory connects timer, it is characterized in that, comprising:
A double-port RAM wherein comprises a plurality of memory cell, and each memory cell can be mapped as a TCP and connect timer;
One is connected with an end of described double-port RAM, the pairing memory cell of timer that needs in the described double-port RAM to start can be put initial value, and with the initialization module of remaining memory cell zero clearing;
A decrement operations module that is connected with the other end of described double-port RAM, described decrement operations module is from the initial address of the described double-port RAM value of each memory cell successively, if the value of the memory cell that is read is 0, then continue to read the value of next memory cell, if the value of the memory cell that is read is 1, then export an asserts signal that is used to control interrupt control unit simultaneously, and then read the value of next memory cell, if the value of the memory cell that is read is not 0 and is not 1, write former memory cell again after then it being subtracted 1, and then read the value of next memory cell.
5, connect timer according to the right 4 described TCP that realize with random asccess memory, it is characterized in that, described initialization module is connected with a tcp state machine primary module, according to the input of described tcp state machine primary module put initial value or reset signal, the memory cell of described double-port RAM is put initial value or clear operation accordingly.
6, connect timer according to the right 5 described TCP that realize with random asccess memory, it is characterized in that the asserts signal output of described decrement operations module is connected with interrupt control unit, the output of described interrupt control unit is connected to described tcp state machine primary module.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021456984A CN1254065C (en) | 2002-10-29 | 2002-10-29 | Random storage implemented TCP connecting timer and its implementing method |
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| CNB021456984A CN1254065C (en) | 2002-10-29 | 2002-10-29 | Random storage implemented TCP connecting timer and its implementing method |
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| CN1494293A true CN1494293A (en) | 2004-05-05 |
| CN1254065C CN1254065C (en) | 2006-04-26 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101253745B (en) * | 2005-07-18 | 2011-06-22 | 博通以色列研发公司 | Method and system for transparent TCP offload |
| CN101515888B (en) * | 2009-03-06 | 2012-02-01 | 华为技术有限公司 | port mapping method and device |
| CN101741870B (en) * | 2008-11-07 | 2012-11-14 | 英业达股份有限公司 | Storage system of Internet small computer system interface |
-
2002
- 2002-10-29 CN CNB021456984A patent/CN1254065C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101253745B (en) * | 2005-07-18 | 2011-06-22 | 博通以色列研发公司 | Method and system for transparent TCP offload |
| CN101741870B (en) * | 2008-11-07 | 2012-11-14 | 英业达股份有限公司 | Storage system of Internet small computer system interface |
| CN101515888B (en) * | 2009-03-06 | 2012-02-01 | 华为技术有限公司 | port mapping method and device |
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| Publication number | Publication date |
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| CN1254065C (en) | 2006-04-26 |
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Effective date of registration: 20170928 Address after: Lin Chang Dong Keng Cun Wei Xin Wu Cun, Xinyu City, Jiangxi province 338000 Fenyi County Dongkeng No. 30 Patentee after: Wang Bilan Address before: 518057 Guangdong Shenzhen science and Technology Park HUAWEI road user service center building intellectual property department Patentee before: Huawei Technologies Co., Ltd. |
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