CN1210917C

CN1210917C - Treatment method of sequence number ordering in virtual cascade connection

Info

Publication number: CN1210917C
Application number: CNB021179670A
Authority: CN
Inventors: 廖志权
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2002-05-27
Filing date: 2002-05-27
Publication date: 2005-07-13
Anticipated expiration: 2022-05-27
Also published as: CN1462118A

Abstract

The present invention discloses a method for sorting sequence numbers in virtual cascade connection. The method has the steps that firstly, a host site figures out a channel sequence number from the frame structure of a slave synchronization numerical sequence (SDH); the key point lies in that the host site temporarily stores the sequence number in a random access memory (RAM) of a digital chip and sorts a plurality of sequence numbers in the virtual cascade connection by controlling the R/W order. The method has the advantages that the consumption of logical resources is reduced and a sequence number sorting process is simplified, and supports the multi-channel virtual cascade connection sorting.

Description

The processing method of sequence number ordering in the Virtual Concatenation

Technical field

The present invention relates to the Virtual Concatenation technology in the synchronous digital transmission network (SDH), be meant the processing method of sequence number ordering in a kind of Virtual Concatenation especially.

Background technology

Cascade is one of key property of SDH, and it can guaranteed capacity effectively transmits greater than the client signal of C-4 (149760kbit/s), and client signal is not introduced additional injury.Cascade is a kind of cohesive process, can combine a plurality of virtual containers (VC) by cascade, makes the bank capability of a plurality of VC can be used as a single container use that still keeps the bit sequence integrality.For example, be that the cascade of the virtual container of VC-4 is exactly with the combined capacity of X C-4 together for type, form a big container, satisfy requirement greater than the big capacity client signal transmission of C-4.Cascade can be divided into Adjacent Concatenation and Virtual Concatenation, and Adjacent Concatenation is in same N rank synchronous transfer modes (STM-N), utilizes adjacent C-4 cascade to become VC-4-Xc, becomes an overall structure and transmits.And Virtual Concatenation is to be distributed in VC-4 among the different STM-N by the method for cascade, to form a virtual macrostructure VC-4-Xv and transmit.Wherein, each VC-4 may be same route, also may be different routes.For Virtual Concatenation, because the path that each VC-4 transmission is passed through may be different, so between each VC-4, transmission time delay difference may occur, under extreme case, the possible occurrence sequence number VC-4 after partially arrives the place termination point earlier than the VC-4 of sequence number before partially, bring difficulty for the reduction of client signal, so need carry out on the time and the alignment on the space to VC-4.

In the implementation procedure of Virtual Concatenation, the main deadline is adjusted and the space is adjusted.Wherein, the space adjustment is in order normally to recover the business that Virtual Concatenation carries in the residential site, and sequence, passage relation must send the Source Site time are recovered.The key of space adjustment is exactly the ordering of sequence number, and existing virtual concatenation protocol is supported maximum 256 sequence numbers.

As shown in Figure 1, Fig. 1 is a principle schematic of handling the sequence number ordering in the Virtual Concatenation.Its processing procedure is such: in the Source Site, and 256 corresponding 256 sequence numbers of passage order, the business that each passage carries self transfers to the residential site after the SDH interconnection, and at this moment, no longer order is corresponding with sequence number for each passage.In the residential site, behind spacing shaping, the rank order in the time of sequence number can being sent by the Source Site.

At present, finish the sequence number ordering and adopt following two kinds of methods usually:

1, direct mutually relatively size: be exactly size relatively between per two sequence numbers, relatively good after, press comparative result again and sort.This scheme is fit to handle with software cycles, can handle the Virtual Concatenation situation of a small amount of passage, but complex disposal process, cycle-index is many, when with programmable logic array (FPGA) or application-specific integrated circuit (ASIC) (ASIC) logic realization, then need inner a large amount of logical resources, particularly a large amount of lookup logic table and comparator.

2, bubbling method ordering: the bubbling method claims standard exchange sort again, and the element that is about in the table rearranges tissue by certain rule (rise progressively or successively decrease).This scheme is by flexible Application and temporary corresponding result, reduced the sequence number number of comparisons in a large number, be particularly suitable for handling with software cycles, can handle the Virtual Concatenation situation of a small amount of passage, but it can not handle multichannel Virtual Concatenation, because when port number increases, resource cost becomes geometric progression to increase, and device cost can't bear.

Summary of the invention

In view of this, main purpose of the present invention is to provide the processing method of sequence number ordering in a kind of Virtual Concatenation, makes it can reduce expending of logical resource, simplifies the sequence number sequencer procedure, supports multichannel Virtual Concatenation ordering.

For achieving the above object, technical scheme of the present invention is achieved in that

The processing method of sequence number ordering in a kind of Virtual Concatenation, at first, the residential site parses the passage sequence number from Synchronous Digital Hierarchy (SDH) frame structure, key is: the residential site is temporary in this passage sequence number in the random asccess memory (RAM) of its digit chip inside, in proper order a plurality of passage sequence numbers in the Virtual Concatenation is sorted by the read-write of control RAM.Wherein, digit chip can adopt field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) (ASIC), and RAM can adopt block random asccess memory (Block RAM), distributed random memory (Distributed RAM) or pushup storage (FIFO).

This method specifically comprises:

A. the residential site will work as the sequence number of prepass and to effective indication that should sequence number according to writing the designated address space that port address writes random asccess memory (RAM);

B. when reading sequence number, press the ascending order of address ram, read ordered sequence number successively, carry out subsequent treatment according to effective indicating bit of sequence number correspondence.

Wherein, the port address of writing described in the step a equals when the prepass sequence number value.

This method further comprises: the random asccess memory (RAM) that in the digit chip of residential site a memory capacity to be set in advance be N * 9bit is stored the passage sequence number in the Virtual Concatenation, and wherein, N is the sequence number value of current Virtual Concatenation passage.Described N can be the maximum of passage sequence number in the current Virtual Concatenation.

In said method, preestablish each passage sequence number and form by the sequence number value of 8bit and the effective indicating bit of sequence number of 1bit.

This method also further comprises: when the passage sequence number changes, earlier RAM is emptied, carry out the sequence number ordering again and handle.

Because the present invention adopts the temporary multichannel Virtual Concatenation sequence number of the random asccess memory (RAM) of digit chip inside, read-write by control RAM comes multichannel Virtual Concatenation sequence number is sorted, so implementation method is simple, the logical resource that takies digit chip inside is few, can support multichannel Virtual Concatenation ordering to handle.

Description of drawings

Fig. 1 is a principle schematic of handling the sequence number ordering in the Virtual Concatenation.

The principle schematic of Fig. 2 for sorting with RAM storage and processing sequence number in the Virtual Concatenation of the present invention.

Embodiment

The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.

Fig. 2 has provided the principle that sorts by RAM storage and processing sequence number in the Virtual Concatenation of the present invention.In the agreement of Virtual Concatenation, SDH utilizes the overhead byte H4 in the frame structure to pass on time-delay and sequencing information, and the sequence number of respective channel just can be found out in the residential site by the H4 byte.The present invention is temporary in the sequence number that parses earlier in the appropriate address space of RAM in the digit chip of residential site just, calls over by address size then, to reach the purpose of sequence number ordering.

Referring to Fig. 2, the capacity of the used RAM of present embodiment is N * 9bit, and wherein, N is the maximum of Virtual Concatenation sequence number, and for example: N can be 255; 9bit refers to the memory capacity of each sequence number, comprises two parts: 8bit is a sequence number value, and 1bit is the effective indicating bit of sequence number.The signal that writes RAM comprises: the sequence number of sequence number effective index signal and 8bit, the signal of reading from RAM comprises: sequence number effective index signal and the 8bit sequence number through sorting.Read-write control signal comprises that writing port address signal and one for one reads the port address signal, respectively the position in the expression sequence number place RAM memory that writes and read.In addition, also have clock (CLOCK) signal, be used to control read-write sequence.So, as shown in Figure 2, concrete ordering processing procedure is finished like this:

1) after sequence number is found out in the residential site, the sequential that provides according to clock writes sequence number among the RAM of a N * 9bit, and this sequence number value accounts for 8 bit.When sequence number was write the address space of RAM, the address was promptly write port address and is equaled current sequence number value by sequence number decision itself, such as: the current sequence number value is 99, so, just the sequence number relevant data is write RAM[99], promptly in the 100th of RAM the address space.In writing sequence number, effective indication of this sequence number correspondence is also write corresponding address space among the RAM, this effectively indication take 1 bit.

When 2) from RAM, reading sequence number, read ordered sequence number successively by the ascending order in address, for example by from 0 to 255 order, according to effective indicating bit, can know which time slot is effective sequence number, the ordered sequence of reading earlier number is for little, and then finishes the sequence number ordering, will offer subsequent processes through the sequence number that sorts then.In fact, read order and also can stipulate, as long as follow certain rules according to user's needs.

This method needs N * 2 clock cycle to handle at most, for example: and 256 * 2=512 clock cycle, and sequence number once needs the time of 16 frames, is far longer than 512 clock cycle, this shows, handle surplus in the time very big.In Virtual Concatenation, the sequence number of each passage generally is indeclinable, if the passage sequence number changes, then will before carrying out sequence number ordering processing earlier with RAM clearly once repeat above process again.

In the above-described embodiment, the digit chip that adopts can be programmable logic array (FPGA) or application-specific integrated circuit (ASIC) (ASIC), and RAM can adopt block random asccess memory (Block RAM), distributed random memory (Distributed RAM) or pushup storage (FIFO).

In a word, the above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.

Claims

1, the processing method of sequence number ordering in a kind of Virtual Concatenation, at first, the residential site parses the passage sequence number from the Synchronous Digital Hierarchy frame structure, it is characterized in that: the residential site is temporary in this passage sequence number in the random asccess memory (RAM) of its digit chip inside, in proper order a plurality of passage sequence numbers in the Virtual Concatenation is sorted by the read-write of control RAM.

2, processing method according to claim 1 is characterized in that this method further comprises:

A. will work as the sequence number of prepass and to effective indication that should sequence number according to writing the designated address space that port address writes random asccess memory (RAM);

3, processing method according to claim 2 is characterized in that: the port address of writing described in the step a equals when the prepass sequence number value.

4, processing method according to claim 1, it is characterized in that this method further comprises: the random asccess memory (RAM) that in the digit chip of residential site a memory capacity to be set in advance be N * 9bit is stored the passage sequence number in the Virtual Concatenation, wherein, N is the sequence number value of current Virtual Concatenation passage.

5, processing method according to claim 4 is characterized in that: described N is the maximum of passage sequence number in the current Virtual Concatenation.

6, processing method according to claim 1 and 2 is characterized in that: preestablish each passage sequence number and be made up of the sequence number value of 8bit and the effective indicating bit of sequence number of 1bit.

7, processing method according to claim 1 is characterized in that this method further comprises: when the passage sequence number changes, earlier RAM is emptied, carry out the sequence number ordering again and handle.