WO2013029411A1

WO2013029411A1 - Hybrid granularity virtual concatenation delay compensation method and device

Info

Publication number: WO2013029411A1
Application number: PCT/CN2012/077372
Authority: WO
Inventors: 张艳辉
Original assignee: 中兴通讯股份有限公司
Priority date: 2011-09-02
Filing date: 2012-06-21
Publication date: 2013-03-07
Also published as: CN102983929A

Abstract

Disclosed are a hybrid granularity virtual concatenation delay compensation method and device, comprising: generating a write direction control pointer used for writing data of each VC into a first memory according to received data, data location indicators and VC time slot serial numbers; designating a VCG port number for each VC, and constructing a read direction control pointer used for reading VCs in each VCG from the first memory based on a VC member that arrives last in each VCG; according to an offset of the write direction control pointer and a write operation data bit width of the first memory, writing the data of the VC in a valid state into the first memory; and according to an offset of the read direction control pointer and a read operation data bit width of the first memory, reading the data of the VC in a valid state from the first memory. The present invention adopts an SDH time division multiplexing structure to complete the virtual concatenation data recovery of the hybrid granularity in a serial manner with small resources, which better solves the problem that the virtual concatenation data recovery takes up too many resources.

Description

Method and device for mixing granularity virtual cascade delay compensation

The present invention relates to a signal transmission processing method for SDH (Synchronous Digital Hierarchy), and more particularly to a method and apparatus for hybrid granularity cascading delay compensation. Background technique

As the mainstream equipment of the transmission network, SDH equipment has been widely used in the field of communication. The frame information structure of the SDH system has a rich overhead byte, which facilitates the transmission of information and network management. The unified interface parameters enable the devices of different vendors to work together to realize the communication between the regional and even global communication networks. In recent years, data services have developed rapidly, and people have strong demand for data services. However, the establishment of a complete data network has a large investment and a long period of time, and makes full use of existing SDH network resources to achieve high-speed, large-capacity, and long-distance data. Transfer is a more appropriate way.

SDH is a hierarchy of standardized digital signals that can be used for simultaneous information transmission, multiplexing, add-drop, and cross-connect. The frame structure of SDH is a block frame structure, which has rich control information for network management, and has flexible multiplexing and mapping structure, allowing different levels of signals to be processed and put into different VCs (Virtual Container, Virtual container).

VC-n (n=2, 3, 4, 11, 12) is an information mechanism used to support the SDH channel layer connection. It is an information terminal of the SDH channel, and is composed of information static load and channel arranged in the block frame structure. The cost is composed. VC-11, VC-12, VC-3 and VC-2 are called low-order virtual containers because of their low code rate, while VC-4 is called high-order virtual container because of its high code rate. VC-ll, VC-12, VC-3, and VC-4 of the SDH standard can be used to carry TDM (Time Division Multiplex) services with fixed bandwidths such as E1/T1, E3/T3, and E4.

Multiple VCs of the same type can be cascaded according to a virtual concatenation protocol to form a cascading virtual container VC-n-xV, where VC-n represents the type of virtual container in the virtual concatenation container, x represents the number of virtual containers, and the last V represents the virtual concatenation mode, for example, 8 VC-3s pass the virtual concatenation mode. Can form a virtual cascade virtual container VC-3-8V.

Cascading is the combination of multiple containers of the same type to deliver rate services between two SDH standard containers. Cascading includes Continuous Concatenation and Virtual Concatenation. The concept of cascading in SDH is to adapt to the suddenness of data services and the variable bandwidth.

The so-called real cascading is to transmit adjacent virtual containers in the same STM-N (Synchronous Transport Module level n) data frame as a whole structure along the same path. The service it transmits is a whole, and the various parts of the data do not generate delay, and the signal transmission quality is high. The application of the real cascading mode has certain limitations. It requires that the path transmitted by each virtual container must be the same, and the network and nodes that it passes through support the real cascading mode.

Virtual cascading is a logical cascading relationship that is independent of the container transport path that is cascaded. Virtual concatenation is a mechanism that logically bundles multiple containers of the same type to deliver traffic. Physically, these containers are delivered in the same way as they were originally. In other words, how SDH originally transmitted such a container is now also used, which ensures compatibility with existing SDH networks. In actual operation, logically bundled containers are issued simultaneously at the transmitting end, but different delays are generated due to different transmission paths. At the receiving end, these delays need to be compensated to enable the service to recover normally at the receiving end. Figure 1, Figure 2, Figure 3 and Figure 4 show the virtual cascade of VC-4, VC-3, VC-12 and VC-11 virtual containers. Virtual concatenation is widely used because it has no special requirements for SDH equipment on the transmission path.

Under the virtual level protocol, each VC-n acts as the smallest "particle" of the virtual concatenation, and its transmission can be performed independently. For example, in the transmission process of the virtual concatenated virtual container VC-3-8V formed by 8 VC3 virtual concatenations, the source or the sender simultaneously transmits 8 virtual containers in the virtual concatenated virtual container VC-3-8V through the path. VC-3 frames, these frames can be transmitted independently in the SDH network and have the same complex The frame number but the serial number is different. Since the delays of different paths in the SDH network are different, the VC-3 frames simultaneously transmitted at the transmitting end are not necessarily received at the receiving end at the same time, which becomes a delay.

The main technical issue that virtual concatenation needs to consider is latency. Since the path through which each virtual container of the virtual concatenation is transmitted may be different, a transmission time difference may occur between the virtual containers. In an extreme case, the virtual container with the serial number may be earlier than the serial number. The virtual container first reaches the destination node, which undoubtedly brings difficulties to the restoration of the signal. In order to correctly extract the original service signal, the receiving end must perform synchronous alignment processing on the received virtual concatenated signal. The current solution is to use the delay sufficient to compensate the memory to buffer the data and perform sequence rearrangement. The general method is to time The extended data is buffered in internal or external RAM (Random Access Memory). The size of the memory determines the ability of virtual cascade recovery. In the G707 protocol, virtual cascade recovery can theoretically compensate for a branch delay of 256ms. Since DDR SDRAM (Double Data Rate SDRAM) is inexpensive, large in capacity, and cost-effective, the current data buffer of virtual cascade recovery generally uses external DDR SDRAM.

In the prior art, after data is read from the DDR SDRAM, data recovery is performed in parallel, so there is a disadvantage of solving the problem that the hybrid virtual concatenation service delay compensation occupies too much resources. Summary of the invention

The object of the present invention is to provide a method and a device for the hybrid granularity cascading delay compensation, which can better solve the problem of excessive resources occupied by the hybrid virtual cascade service delay compensation.

In order to achieve the above object, the technical solution of the present invention is achieved as follows:

A method for hybrid granularity cascading delay compensation, the method comprising:

A) generating a write direction control pointer for writing each VC data of the first memory according to the received data, the data location indication, and the virtual container VC slot number, each write direction control pointer containing the VC slot number and the offset Transfer amount

B) assign a virtual container group VCG port number to each VC, and finally arrive at each VCG The VC member is a reference structure for reading the read direction control pointer of the VC in each VCG from the first memory, and each read direction control pointer contains the VC slot number and the offset;

C) controlling the offset of the pointer and the first memory write operation data bit width according to the write direction, and writing the data of the valid VC to the first memory;

D) controlling the offset of the pointer and the first memory read operation data bit width according to the read direction, and reading the data of the valid VC from the first memory.

The step C includes:

C1) determining a state of the write direction VC according to the offset of the write direction control pointer and the first memory write operation data bit width, if the data amount of the VC represented by the offset amount satisfies the first memory write operation data bit Wide, then the status is determined to be valid;

C2) Query the write direction VC state according to the VC slot number, so as to read the write direction control pointer of the VC whose write status is valid;

C3) Converting the read write direction control pointer to the first memory write address and writing the data to the first memory by the write address.

The step D includes:

D1) determining, according to the read direction, the offset of the pointer and the first memory read operation data bit width, determining the state of the read direction VC, if the data amount of the VC represented by the offset satisfies the first memory read operation data Bit width, then the status is determined to be valid;

D2) Query the read direction VC state according to the VC slot number, so as to read the read direction control pointer of the VC whose read status is valid;

D3) Converting the read read direction control pointer into a first memory read address and reading data from the first memory in accordance with the read address.

The method further includes the virtual concatenation recovery service data step E performed after the step D, comprising: storing the data read from the first memory in a second memory in a read control pointer; performing the VCG port number Adding addresses to obtain the current read location of the second memory Address to read data from the second memory.

The step E further includes:

And storing, by the VCG port number, a write address of the second memory into a third memory; comparing a write address read from the third memory with a current read address of the second memory;

Reading data from the second memory if a current read address of the second memory is less than a write address read from the third memory;

If the current read address of the second memory is greater than or equal to the write address read from the third memory, then reading data from the second memory is stopped.

A device for mixing granularity cascading delay compensation, the device comprising:

Double rate synchronous dynamic random access memory DDR SDRAM read/write control processor for generating write direction control pointers for writing VC data for each memory according to received data, data position indication and VC time slot number, each The write direction control pointer includes a VC slot number and an offset; and is further configured to specify a VCG port number for each VC, and is configured to read each VCG from the first memory with reference to a VC member that is finally reached by each VCG. The read direction control pointer of the VC, each read direction control pointer contains a VC slot number and an offset;

a DDR SDRAM controller, configured to: control an offset of the pointer and a first memory write operation data bit width according to the write direction, and write data of the state-effective VC into the first memory; and further, according to the read direction The offset of the pointer and the first memory read operation data bit width are controlled, and the data of the state-active VC is read from the first memory.

The DDR SDRAM read/write control processor further includes a DDR SDRAM write control pointer/state processor;

The DDR SDRAM write control pointer/status processor is configured to determine a state of the write direction VC according to the offset of the write direction control pointer and the first memory write operation data bit width, if the offset represents a VC The amount of data satisfies the first memory write operation data bit width, and the state is determined Effective

The DDR SDRAM write control pointer/status processor is further configured to query the write direction VC state according to the VC slot number, so as to read the write direction control pointer of the write direction VC whose state is valid; the DDR SDRAM write control pointer/state The processor is further configured to convert the read write direction control pointer to a first memory write address and write the data to the first memory in accordance with the write address.

The DDR SDRAM read/write control processor further includes a DDR SDRAM read control pointer/state processor;

The DDR SDRAM read control pointer/status processor is configured to determine a state of the read direction VC according to the read direction control pointer offset and the first memory read operation data bit width, if the offset represents a VC The amount of data satisfies the memory read operation data bit width, and the determined state is valid;

The DDR SDRAM read control pointer/status processor is further configured to query a read direction VC state according to a VC slot number to read a read direction control pointer of a read direction VC whose state is valid; the DDR SDRAM read control pointer/state The processor is further configured to convert the read read direction control pointer to a first memory read address and read data from the first memory by the read address.

The device further includes a data recovery processor, configured to store data read from the first memory in a second memory by using a read control pointer, and perform address accumulation by using the VCG port number to obtain the The current read address of the second memory to read data from the second memory.

The data recovery processor further includes:

a second memory for storing data read from the DDR SDRAM with the read control pointer as an address;

a third memory, configured to store a write address of the second memory;

An adder, configured to store, by the VCG port number, a write address of the second memory into a third memory; a comparator, configured to compare a write address read from the third memory with a current read address of the second memory, if a current read address of the second memory is smaller than a write address read from the third memory And reading data from the second memory; if the current read address of the second memory is greater than or equal to a write address read from the third memory, stopping reading data from the second memory .

Compared with the prior art, the present invention has the following advantages: The present invention utilizes the SDH time division multiplexing structure to use a serial manner, completes virtual granular data recovery with a mixed granularity with a small resource, and supports up to 64 virtual concatenation groups. Delay compensation. DRAWINGS

1 is a schematic diagram of a virtual concatenation of a VC-4 provided by the prior art;

2 is a schematic diagram of a virtual concatenation of VC-3 provided by the prior art;

3 is a schematic diagram of a virtual cascade of VC-12 provided by the prior art;

4 is a schematic diagram of a virtual concatenation of a VC-11 provided by the prior art;

FIG. 5 is a schematic diagram of a method for hybrid granularity cascading delay compensation according to an embodiment of the present invention; FIG.

6 is a flow chart of a method for hybrid granularity cascading delay compensation according to an embodiment of the present invention;

Figure 6a is a schematic diagram of allocating 8 VCs of 8 STM-1 into 3 virtual container groups (VCGs);

Figure 6b is a schematic diagram of the hybrid VC slot numbering;

6c is a schematic diagram of a VC3 state processing in a DDR SDRAM read/write control processor; FIG. 7 is a schematic structural diagram of an apparatus for mixing granularity virtual cascade recovery delay compensation according to an embodiment of the present invention;

8 is a schematic structural diagram of a data recovery processor according to an embodiment of the present invention; FIG. 8a is a read/write address display of a RAMI in a data recovery processor according to an embodiment of the present invention; detailed description

The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

FIG. 5 is a schematic diagram of a method for hybrid granularity cascading delay compensation according to an embodiment of the present invention. As shown in FIG. 5, the method includes the following steps:

Step S501: Generate, according to the received data, the data location indication, and the virtual container VC time slot number, a write direction control pointer for writing each VC data of the first memory, where each write direction control pointer includes a VC slot number and Offset;

Step S502: Specify a VCG port number for each VC, and configure a read direction control pointer for reading VCs in each VCG from the first memory with reference to the VC member finally arrived by each VCG, and each read direction control pointer includes VC slot number and offset;

Step S503, according to the offset of the write direction control pointer and the first memory write operation data bit width, write the data of the state-effective VC into the first memory;

Step S504, according to the read direction control pointer offset and the first memory read operation data bit width, read the data of the valid VC from the first memory.

FIG. 6 is a flow chart of a method for hybrid granularity cascading delay compensation according to an embodiment of the present invention.

Taking the SDH virtual concatenation capacity as 1.25 Gbit/s as an example, the virtual concatenation technology of eight STM-1 hybrid virtual containers is used to transmit data. The received data traffic is divided into three VCGs, which are set to VCG-M (M=0, 1, 2). There are 4 VC4 members in VCG-0, 3 VC3 members in VCG-1, and 2 VC12 members in VCG-2. As shown in Figure 6a. The VC member's slot number and virtual container type are stored in the VCG-M correspondence table. The slot number of the hybrid VC member is shown in Figure 6b. As shown in FIG. 6, the method includes the following steps:

Step S601, generating a DDR SDRAM write direction control pointer. The circuit clock is 8xl55.52/8=155.52MHz. According to the SDH time division multiplexing frame structure, the offset of the DDR SDRAM write direction control pointer is generated according to the received data, the data position indication SPE (Synchronous Payload Envelope) and the VC slot number. For VC4, the maximum offset is equal to {260 (column) x9 (row) xl6 (multiframe) xMFI2 (Multiframe Indicator) }; for VC3, the maximum offset is equal to {84 ( Column) x9 (row) xl6 (multiframe) xMFI2} ; For VC12, the maximum offset is equal to {34 (column) x4 (row) x32 (multiframe) xMFI2} ; for VC11, offset The maximum value is equal to {25 (column) x4 (row) x32 (multiframe) xMFI2}. For each VC, each time a byte of data is received, the offset is incremented by one. When the maximum value is reached, the offset is reset and recounted. The write direction control pointer format is {VC slot number, write direction control pointer offset}. The VC slot number in the write direction control pointer is extracted from the input data.

Step S602, generating a DDR SDRAM read direction control pointer.

The VC slot number RD_VCNUM of 8xSTM-l is constructed with a 155.52Mhz clock. The read direction control pointer offset and the read direction control pointer multiframe number are generated based on the latest arrival member of each VCG in the receiving direction. A VCG read direction control pointer offset keeps track of the write direction control pointer offset of the latest member received by the VCG. When the write direction control pointer is incremented, the read direction control pointer can be increased. The DDR SDRAM read direction control pointer format is {RD_VCNUM, read direction control pointer offset}. The VC slot number of the read direction control pointer is obtained by loop counting.

Step S603, performing a merge/decomposition process on the read/write direction control pointer.

The read/write direction control pointer is merged/decomposed according to the burst (BURST) operation of the DDR SDRAM block. Assume that the DDR SDRAM has BURST=8 and the data bit width is 16 bits, indicating that the DDR SDRAM read/write operation data bit width is 16x8=128 bits. Because SDH works in byte interleaving mode, when the write direction control pointer offset of a VC's DDR SDRAM counts up to 16, it means that the VC already has the data that meets the requirements of the DDR BURST block. 16xlbyte=16x8bit=128bit data. At this time, the state of the VC (STATE) is set to be valid, waiting for the DDR SDRAM to read the write direction control pointer. When the read pointer offset of a VC's DDR SDRAM counts up to 16, it means that the VC already has the requirement of satisfying the DDR BURST block. At this time, the state STATE of the VC is set to be valid, waiting for the DDR SDRAM to read the direction control. pointer.

Step S604, the DDR SDRAM controller constructs the VC slot number VCNUM according to the VC multiplexing structure of the mixed granularity.

For example, the DDR SDRAM controller generates the slot number 0~7 of VC4, the time slot number of each VC3 is 0~2, and the slot number of each VC12 is 0~20. The slot number is used to query the VC status in the read or write direction. Assuming that the array of DDR SDRAM (BANK) is 8, then the read/write frequency can be set to 8, that is, 8 consecutive read and 8 consecutive write interleaving operations. When the controller fetches a VC's read direction control pointer or write direction control pointer, the VC's STATE is invalid. Figure 6c depicts a schematic diagram of the state of the VC3 type read direction control pointer set to active and inactive.

Step S605, the DDR SDRAM converts the read/write direction control pointer into a read/write address according to the hybrid VC type.

The BANK and column addresses of DDR SDRAM are independent of the mixed VC type. For the row address, the VC4 type directly reads the read/write direction control address; when the VC3 type, the row address is equal to {VC3 slot number, read/write/control address}; when VC12 type, the row address is equal to {VC12 slot number, Read/write direction control address}; When VC11 type, the row address is equal to {VC11 slot number, read/write direction control address}.

Step S606, the virtual concatenation recovers the service data.

The virtual cascade recovery service data is mainly completed by the data recovery processor. The data recovery processor consists of RAMI, adder, RAM2 and comparator. The data recovery processor stores the data read from the DDR SDRAM in the RAMI with the read direction control pointer. The adder generates the read address of the RAMI, and the read address of the RAMI is accumulated by the VCG number, so that the read data is the recombined VCG data. RAM2 is used to store the write address of RAMI. The comparator is used to control the read progress of the RAMI. When the read address of the RAMI is smaller than the address read from the RAM 2, it is necessary to read data from the RAMI; when the read address of the RAMI is equal to the address read from the RAM 2, the read data is stopped.

Wherein, the VC slot in the write address of the RAMI is obtained by loop counting, and the byte count of each VC takes the read pointer offset in the read direction control pointer; the VC slot of the RAMI read address is the VC member of the VCG. After sorting, the VC slot of the read address and the VC slot of the write address are not in the same order. The VC byte count of the RAMI read address is accumulated by the VCG number, so the byte count of each member of each VCG is required to be the same, so that each member of each VCG can be read from the RAMI by the same byte count. The data is output, so the data read out is the result of the recovery.

FIG. 7 is a schematic structural diagram of a device for hybrid granularity cascading recovery delay compensation according to an embodiment of the present invention. As shown in FIG. 7, the device includes: DDR SDRAM, DDR SDRAM controller, DDR SDRAM read/write control processing. , data recovery processor.

DDR SDRAM, used to store received data.

a DDR SDRAM controller, configured to control the offset of the pointer and the first memory write operation data bit width according to the write direction, and write the data of the valid VC to the first memory, and further, according to the read direction The offset of the pointer and the first memory read operation data bit width are controlled, and the data of the state-active VC is read from the first memory.

a DDR SDRAM read/write control processor, configured to generate a write direction control pointer for each VC data written in the memory according to the received data, the data location indication, and the VC time slot number, and each write direction control pointer includes a VC The slot number and the offset are also used to specify a VCG port number for each VC, and are configured to read a read direction control pointer of the VC in each VCG from the first memory, based on the VC member that is finally reached by each VCG. Each read direction control pointer contains a VC slot number and an offset.

The DDR SDRAM read/write control processor further includes a DDR SDRAM write direction control pointer/state processor, a DDR SDRAM read direction control pointer/state processor, and a VC configuration storage. Device.

The DDR SDRAM write direction control pointer/status processor is configured to determine a state of the write direction VC according to the offset of the write direction control pointer and the first memory write operation data bit width, if the offset represents a VC The amount of data satisfies the first memory write operation data bit width, and then determines that the state is valid; the DDR SDRAM write direction control pointer/status processor is further configured to query the write direction VC state according to the VC slot number, so as to read the state The write direction control pointer of the write direction VC; the DDR SDRAM write direction control pointer/status processor is further configured to convert the read write direction control pointer into a first memory write address, and write the data to the memory according to the write address in.

The DDR SDRAM read direction control pointer/status processor is configured to determine a state of the read direction VC according to the read direction control pointer offset and the first memory read operation data bit width, if the offset represents The data amount of the VC satisfies the memory read operation data bit width, and then determines that the state is valid; the DDR SDRAM read direction control pointer/status processor is further configured to query the read direction VC state according to the VC slot number, so as to read the state of the VC state. a read direction control pointer of the read direction VC; the DDR SDRAM read direction control pointer/status processor is further configured to convert the read read direction control pointer into a first memory read address, and read the address from the first memory Read data in.

The VC configuration memory is used to store VC attributes such as VC type and VCG port number. a data recovery processor, configured to store data read from the first memory in a read direction control pointer into a second memory, perform address accumulation by using the VCG port number, and obtain a current read address of the second memory To read data from the second memory.

FIG. 8 is a schematic structural diagram of a data recovery processor according to an embodiment of the present invention. As shown in FIG. 8, the data recovery processor includes a second memory RAM1, an adder, a comparator, and a third memory RAM2. Wherein, the RAMI is used to store the data read from the DDR SDRAM with the read direction control pointer as an address; the RAM2 is used to store the write address of the RAMI; the adder, Storing a write address of the RAMI to the RAM 2 according to the VCG port number; a comparator for comparing a write address read from the RAM 2 with a current read address of the RAMI, if the current RAMI is current Reading data from the RAMI when the read address is smaller than the write address read from the RAM 2; stopping from the RAMI if the current read address of the RAMI is greater than or equal to the write address read from the RAM 2 Read data in.

Figure 8a is a diagram showing the read and write addresses of the RAMI in the data recovery processor according to the embodiment of the present invention. Suppose there are two VCGs, the member type is VC4, and the VCG numbers are 0 and 1. VCG0 has 3 members, VC slot number is 0, 2, 3, VCG1 has 5 members, which are 1, 4, 5, 6, 7. As shown in FIG. 8a, the slot number of the write address of the RAMI is 8 VC4 sequential counts, and the byte count of the write address is counted according to the order of each VC member; the VC slot of the RAMI read address is each VC member of the VCG. After sorting, the VC slot of the read address and the VC slot of the write address are not in the same order. The VC byte count of the RAMI read address is accumulated by the VCG number. The VC byte count of the RAMI read address follows the VC byte count of the RAMI write address.

In summary, the present invention solves the problem of excessive data occupation resources by using the SDH time division multiplexing structure using a serial mode with less imaginary cascading.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. INDUSTRIAL APPLICABILITY The present invention discloses a method and apparatus for hybrid granularity cascading delay compensation, and generates write direction control for each VC data written in the first memory according to received data, data position indication, and VC slot number a pointer; a VCG port number is assigned to each VC, and the read direction control pointer of the VC in each VCG is read from the first memory according to the VC member finally arrived at each VCG; the offset of the pointer is controlled according to the write direction and The first memory write operation data bit width, the state is valid The data of the VC is written into the memory; the offset of the pointer is controlled according to the read direction and the bit width of the first memory read operation data, and the data of the VC that is valid is read from the first memory. The invention utilizes the SDH time division multiplexing structure to use the serial mode and complete the virtual cascading data recovery with mixed granularity with smaller resources, thereby better solving the problem that the virtual cascade recovery data occupies too much resources.

Claims

B) assigning a virtual container group VCG port number to each VC, and configuring a read direction control pointer for reading VC in each VCG from the first memory based on the VC member finally arrived by each VCG, each read direction control The pointer contains the VC slot number and offset;

2. The method according to claim 1, wherein the step C comprises:

3. The method according to claim 1, wherein the step D comprises:

D2) Query the VC status of the read direction according to the VC slot number, so as to read the status of the VC Reading direction control pointer of the read direction VC;

The method according to any one of claims 1 to 3, further comprising the virtual concatenation recovery service data step E performed after the step D, comprising:

The data read from the first memory is stored in the second memory as a read control pointer; the address is accumulated by the VCG port number to obtain the current read address of the second memory, so as to be read from the second memory. Out of the data.

5. The method according to claim 4, wherein the step E further comprises: storing the write address of the second memory into the third memory according to the VCG port number; reading from the third memory The write address is compared with the current read address of the second memory;

6. A device for mixing granularity cascading delay compensation, the device comprising:

a DDR SDRAM controller, configured to control the offset of the pointer and the first memory write operation data bit width according to the write direction, and write the data of the valid VC to the first memory; And controlling the offset of the pointer and the first memory read operation data bit width according to the read direction, and reading the data of the VC that is valid from the first memory.

7. The apparatus according to claim 6, wherein the DDR SDRAM read/write control processor further comprises a DDR SDRAM write control pointer/state processor;

The DDR SDRAM write control pointer/status processor is configured to determine a state of the write direction VC according to the offset of the write direction control pointer and the first memory write operation data bit width, if the offset represents a VC If the amount of data satisfies the first memory write operation data bit width, it is determined that the state is valid;

8. The apparatus according to claim 6, wherein the DDR SDRAM read/write control processor further comprises a DDR SDRAM read control pointer/state processor;

The apparatus according to any one of claims 6 to 8, wherein the apparatus further comprises a data recovery processor for storing data read from the first memory as a read control pointer to In the second memory, the address is accumulated by the VCG port number to obtain a current read address of the second memory, so as to read data from the second memory.

10. The apparatus according to claim 9, wherein the data recovery processor further comprises: a second memory, configured to store data read from the DDR SDRAM with the read control pointer as an address;

a third memory, configured to store a write address of the second memory;

An adder, configured to store the write address of the second memory into the third memory according to the VCG port number;

a comparator, configured to compare a write address read from the third memory with a current read address of the second memory, if a current read address of the second memory is smaller than a write address read from the third memory And reading data from the second memory; if the current read address of the second memory is greater than or equal to a write address read from the third memory, stopping reading data from the second memory .