CN1889066A - Automatic switching device for complexing pin working mode - Google Patents
Automatic switching device for complexing pin working mode Download PDFInfo
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- CN1889066A CN1889066A CNA2006100896927A CN200610089692A CN1889066A CN 1889066 A CN1889066 A CN 1889066A CN A2006100896927 A CNA2006100896927 A CN A2006100896927A CN 200610089692 A CN200610089692 A CN 200610089692A CN 1889066 A CN1889066 A CN 1889066A
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Abstract
The invention provides an automatic transfer device of the multiplexing pin work mode which includes the work mode register and the pin control circuit. The enable signal, the data signal, the clock signal and the reset signal are all inputted to the work mode register. When the reset signal is invalid and the enable signal is available, in the time of the clock jumping edge, the mode data is written in and saved; then it is outputted to the pin control circuit. The device also includes the mode switching control unit, the selector and the logical unit. The mode switching control signal outputted by the mode switching control unit is set to be available when the reset signal is invalid; the bus mode data and the mode 2 data are all inputted into the selector, the output is mode data of the work mode register, when the mode switching control signal is available, the mode 2 data is outputted; the bus enable and the mode switching control signal are all inputted into the logical unit. The two signals are computed by the 'or' to get the enable signal of the work mode register.
Description
Technical field
The present invention proposes a kind of automatic switching control equipment of complexing pin working mode.
Background technology
In chip design, because the chip pin limited in number often needs complexing pin.In general, the mode of operation of pin (function) is decided by register.Program can be controlled the mode of operation of this pin by writing relevant register.In existing circuit structure, the mode of operation of the pin that is re-used can't change in during this period of time before the back that powers on writes relevant register to program, can only be in default mode of operation all the time.This has just limited the dirigibility of pin multiplexing.
Fig. 1 has shown the control circuit structure of existing complexing pin working mode.Fig. 2 has shown the mode switch sequential chart of available circuit structure.As can be seen from the figure, in existing this structure, the mode of operation of the pin that is re-used is set to default mode in the effect of back owing to reset signal that power on.Before program write the corresponding work mode register, after reset signal was invalid, the rising edge of first clock when enable signal is effective write data, and the mode of operation of this pin can't change, and can only be in default mode of operation all the time.This has just limited the dirigibility of pin multiplexing.If be used in the program loading procedure of a pin behind electrification reset, the default mode of operation of this pin in the electrification reset process also just must be set to consistent with pattern in the program loading procedure.That is to say that this pin can not be used to other function in the electrification reset process.
Summary of the invention
The technical problem to be solved in the present invention is to improve the available circuit structure, and the mode of operation of the feasible pin that is re-used automatically switches to another required pattern before the program run behind electrification reset, increases the dirigibility of pin multiplexing.
The present invention proposes a kind of automatic switching control equipment of complexing pin working mode, comprise mode of operation register and pin control circuit, enable, mode data, clock and reset signal are input in this mode of operation register, after reset signal is invalid, when enable signal is effective, this mode of operation register is under the driving of clock hopping edge, described mode data is write and preserves, simultaneously it is outputed to the pin control circuit, it is characterized in that: this device also comprises a mode switch control module, one selector switch and a logical block
Described mode switch control module is exported a mode switch control signal to selector switch one input end and logical block one input end, after reset signal is invalid, this mode switch control signal is changed to effectively and lasts till that at least the drive pattern data write the clock hopping edge of mode of operation register, before bus enabled effectively, it is invalid that the mode switch control signal is changed to;
One of described selector switch is input as the mode bus data, another is input as pattern 2 data that will automatically switch to behind the electrification reset, its output is the mode data of input service mode register, when the mode switch control signal of its control end is effective, and the output of preference pattern 2 data;
One of described logical block is input as bus and enables, and another is input as the mode switch control signal, described two input signals are carried out inclusive-OR operation after, obtain importing the enable signal of described mode of operation register.
Further, said method can also have following characteristics: described mode switch control module is a delayer, this delayer receives described reset signal, become when invalid in this reset signal, it is deferred to output again behind the clock hopping edge that the drive pattern data write the mode of operation register to the major general.
Further, said method can also have following characteristics: described delayer is a d type flip flop, the data input pin D of d type flip flop connects logical one, clock is identical with the clock and the reset signal of mode of operation register with reset signal, and the reverse data output of d type flip flop is as the mode switch control signal.
Further, said method can also have following characteristics: described delayer is a d type flip flop, the termination 0 that resets, and D termination reset signal, the Q end data output of d type flip flop is as the mode switch control signal.
Further, said method can also have following characteristics: described mode switch control module comprises counter and comparer, described counter is cleared when resetting, reset invalid back begins counting to counter, when being increased to maximal value, this counter stops counting and keeps maximal value, and the count value of counter is imported into comparer and compares with the initialize data that is input in the comparer equally, when the output of counter equated with initialize data, the mode switch control signal was output as effectively.
Further, said method can also have following characteristics: described initialize data should be less than invalid back of reset signal and the effectively preceding clock number of bus enable signal, and described counter is since 0 counting.
In sum, the present invention has improved existing complexing pin working mode control circuit, and the mode of operation of the feasible pin that is re-used need not programmed control behind electrification reset just can be automatically switched to required pattern in the time of setting.The advantage of doing like this is can be operated in different patterns in the program loading procedure of pin after the neutralization of electrification reset process that is re-used, and has increased the dirigibility of pin multiplexing.
Description of drawings
Fig. 1 is existing pin working mode control circuit structural drawing.
Fig. 2 is the mode switch sequential chart of available circuit structure among Fig. 1.
Fig. 3 is the structural drawing of the automatic switching control equipment in the first embodiment of the present invention.
Fig. 4 is the sequential transition diagram of automatic switching control equipment among Fig. 3 of the present invention.
Fig. 5 is the structural drawing of the automatic switching control equipment in the second embodiment of the present invention.
Fig. 6 is the sequential transition diagram of automatic switching control equipment among Fig. 5 of the present invention.
Fig. 7 is the structural drawing of the automatic switching control equipment in the third embodiment of the present invention.
Fig. 8 is the sequential transition diagram (initialize data=0) of automatic switching control equipment among Fig. 7 of the present invention.
Fig. 9 is the sequential transition diagram (initialize data=2) of automatic switching control equipment among Fig. 7 of the present invention.
Embodiment
First embodiment
Fig. 3 is a structural drawing of realizing the automatic switching control equipment of a kind of complexing pin working mode of the present invention.Compare with existing circuit structure, increased a d type flip flop, selector switch and one or.The data input pin D of d type flip flop connects logical one, and clock is identical with the clock and the reset signal of mode of operation register with reset signal.The enable signal of mode of operation register enables to carry out inclusive-OR operation with the reverse data of d type flip flop output Q by bus and obtains later on.The reverse data output of d type flip flop also is used for controlling the data input that selector switch produces the mode of operation register simultaneously.One of them input of selector switch is still the mode bus data, represents with pattern 1 herein, and another is input as the mode data that will automatically switch to behind the electrification reset, represents with pattern 2 herein.
The mode of operation of pin of being re-used in the back that powering on because the effect of reset signal still is set to default mode.After reset signal is invalid, before also not arriving next rising edge clock, the reverse data output of d type flip flop still is 1, this output enables to carry out to obtain enabling output behind the exclusive disjunction with bus, so, enabling of mode of operation register is 1, again because the output of the reverse data of described d type flip flop is used for controlling the data input that selector switch produces the mode of operation register.This moment, selector switch was output as pattern 2, so the data of mode of operation register are input as pattern 2.So, the 1st rising edge clock after reset signal is invalid, the content of mode of operation register is rewritten as pattern 2, and the program that so just realized after this pin working mode is by electrification reset writes the automatic switchover before the relevant register.
Simultaneously, because the data input pin of d type flip flop connects 1, the reverse data output of d type flip flop also becomes 0 at same rising edge.Accordingly, the enabling of mode of operation register enabled with the reverse data of d type flip flop after inclusive-OR operation is carried out in output by bus, the gained result enables control by bus, and the mode bus data link to each other with selector switch, the selector switch of this moment is output as pattern 1, the mode bus data are consistent with selector switch output, so, the data input is controlled by the mode bus data, this is consistent with existing design, when the bus enable signal is effective, pattern 1 data is write the mode of operation register, thereby pin working mode is switched to pattern 1 again.
Fig. 4 is the sequential transition diagram of the automatic switchover structure of the complexing pin working mode of Fig. 3 of the present invention's proposition.The 1st～2 reset clock signal that illustrates in the drawings is effective, and the mode of operation of pin is a default mode, and the 3rd rising edge clock switches to pattern 2, switches to pattern 1 once more at the 11st rising edge clock.
Second embodiment
In fact to be delayed to the signal that next rising edge clock produces identical with reset signal for enable signal as seen from Figure 4, so the present invention also can realize with the circuit as Fig. 5.Compare with the circuit structure of Fig. 4, the Q end of d type flip flop is used to control selector switch and enable signal, reset termination 0 (not resetting), D termination reset signal.The function of this d type flip flop is equivalent to reset signal is deferred to next rising edge clock, and unique change is the waveform that the waveform of Q has become Q.Other connect with Fig. 3 in identical.
The mode of operation of pin of being re-used in the back that powering on because the effect of reset signal still is set to default mode.After reset signal is invalid, before also not arriving next rising edge clock, the reverse data output of d type flip flop still is 1, this output enables to carry out to obtain enabling output behind the exclusive disjunction with bus, so enabling of mode of operation register is 1, again because the output of the data of described d type flip flop is used for controlling the data input that selector switch produces the mode of operation register, this moment, selector switch was output as pattern 2, so the data of mode of operation register are input as pattern 2.So, the 1st rising edge clock after reset signal is invalid, the content of mode of operation register is rewritten as pattern 2, and the program that so just realized after this pin working mode is by electrification reset writes the automatic switchover before the relevant register.
Simultaneously, since reset termination 0, D termination reset signal, the data input pin of d type flip flop connects 0, and is corresponding, enables to enable control by bus, the data input is controlled by the mode bus data, when the bus enable signal is effective, pin working mode is switched to pattern 1 again.
Corresponding sequential converted-wave figure as shown in the figure.Mode of operation is a default mode at the 1st～2 clock, switches to pattern 2 at the 3rd rising edge clock, switches to pattern 1 once more at the 11st rising edge clock.
As can be seen, in fact the d type flip flop of first and second embodiment is equivalent to a delayer, this delayer receives described reset signal, becomes when invalid in this reset signal, and it is deferred to output again behind the clock hopping edge that the drive pattern data write the mode of operation register to the major general.But the present invention also can adopt other can realize the various delayers of this function.
The 3rd embodiment
Compare with the circuit structure among Fig. 5 with Fig. 3, the function of the d type flip flop among Fig. 7 is realized by counter and comparer.Counter in the circuit is cleared when resetting, and resets to begin counting after invalid.When being increased to maximal value, this counter stops counting and keeps maximal value (not cycle count).The numerical value of counter is output to comparer and initialize data compares.When the output of counter equated with initialize data, the signal of comparer equated output 1, and all the other situations all export 0.Other connect with Fig. 3 in identical.
When the signal of comparer is output as 1, described output and bus enable to carry out to obtain enabling output after the inclusive-OR operation, so, enabling of mode of operation register is 1, again because feasible selector switch output mode 2 data that link to each other of described output, and the output of the data of selector switch is as the data input of mode of operation register, so described data are output as pattern 2 data.
In the circuit implementation structure of Fig. 7, the automatic switchover time of Be Controlled pin working mode can be controlled by initialize data.It shown in Fig. 8 is 0 o'clock sequential transition diagram for initialize data, because counter output all is 0 at the 1st～2 clock, so the signal of comparer equates to be output as 1, so, the mode of operation register to enable at the 1st～2 and the 10th clock be 1, described data are output as pattern 2 data.So, the 1st rising edge clock after reset signal is invalid, the content of mode of operation register is rewritten as pattern 2.This function with the circuit structure of Fig. 3 and Fig. 5 is identical.Simultaneously, at this rising edge clock, counter output becomes 1, makes the output of comparer become 0, this moment register enable enable control by bus, data are imported by the mode bus Data Control, switch to pattern 1 once more at the 11st rising edge clock.
It shown in Fig. 9 is 2 o'clock sequential transition diagram for initialize data, counter output equates to be output as 1 at the signal of the 4th clock comparator, so, the mode of operation register to enable at the 4th and the 10th clock be 1, described data are output as pattern 2 data at the 4th clock.So, the 3rd rising edge clock after reset signal is invalid, the content of mode of operation register is rewritten as pattern 2.
When the signal of comparer is output as 0, enable output and enable control by bus, the data input is controlled by the mode bus data.
In above design, we have supposed that restriction release time (Recovery) and checkout time that the process of the design of the chip clock and the control module that resets and placement-and-routing has guaranteed that this circuit can satisfy between reset signal and the clock signal limit (Removal), that is to say that reset signal can not change and produce unpredictable circuit state near rising edge clock.
In actual applications, can select corresponding circuit structure as required.Delay a period of time after reset signal is invalid is switched the mode of operation of Be Controlled pin more if desired, then should select the circuit structure among Fig. 7.Otherwise can select the circuit structure of Fig. 3 or Fig. 5 to realize the required hardware spending of this circuit to reduce.
The present invention can also do various conversion on the basis of the foregoing description.
For example, can under the driving of rising edge clock, write the mode of operation of mode of operation register, also can under the driving of negative edge, write.
Claims (6)
1, a kind of automatic switching control equipment of complexing pin working mode, comprise mode of operation register and pin control circuit, enable, mode data, clock and reset signal are input in this mode of operation register, after reset signal is invalid, when enable signal is effective, this mode of operation register is under the driving of clock hopping edge, described mode data is write and preserves, simultaneously it is outputed to the pin control circuit, it is characterized in that: this device also comprises a mode switch control module, one selector switch and a logical block
Described mode switch control module is exported a mode switch control signal to selector switch control end and logical block one input end, after reset signal is invalid, this mode switch control signal is changed to effectively and lasts till that at least the drive pattern data write the clock hopping edge of mode of operation register, before bus enabled effectively, it is invalid that the mode switch control signal is changed to;
One of described selector switch is input as the mode bus data, another is input as the interim switch mode data that will automatically switch to behind the electrification reset, its output is the mode data of input service mode register, when the mode switch control signal of its control end is effective, select interim switch mode data output;
One of described logical block is input as bus and enables, and another is input as the mode switch control signal, described two input signals are carried out inclusive-OR operation after, obtain importing the enable signal of described mode of operation register.
2, automatic switching control equipment as claimed in claim 1 is characterized in that:
Described mode switch control module is a delayer, and this delayer receives described reset signal, becomes when invalid in this reset signal, and it is deferred to output again behind the clock hopping edge that the drive pattern data write the mode of operation register to the major general.
3, automatic switching control equipment as claimed in claim 2 is characterized in that:
Described delayer is a d type flip flop, and the data input pin D of d type flip flop connects logical one, and clock is identical with the clock and the reset signal of mode of operation register with reset signal, and the reverse data output of d type flip flop is as the mode switch control signal.
4, automatic switching control equipment as claimed in claim 2 is characterized in that:
Described delayer is a d type flip flop, the termination 0 that resets, and D termination reset signal, the Q end data output of d type flip flop is as the mode switch control signal.
5, automatic switching control equipment as claimed in claim 2 is characterized in that:
Described mode switch control module comprises counter and comparer, described counter is cleared when resetting, reset invalid back begins counting to counter, when being increased to maximal value, this counter stops counting and keeps maximal value, the count value of counter is imported into comparer and compares with the initialize data that is input in the comparer equally, and when the output of counter equated with initialize data, the mode switch control signal was output as effectively.
6, automatic switching control equipment as claimed in claim 5 is characterized in that:
Described initialize data should be less than invalid back of reset signal and the effectively preceding clock number of bus enable signal, and described counter is since 0 counting.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100896927A CN100397381C (en) | 2006-07-12 | 2006-07-12 | Automatic switching device for complexing pin working mode |
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| CNB2006100896927A CN100397381C (en) | 2006-07-12 | 2006-07-12 | Automatic switching device for complexing pin working mode |
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| CN1889066A true CN1889066A (en) | 2007-01-03 |
| CN100397381C CN100397381C (en) | 2008-06-25 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101299601B (en) * | 2007-04-30 | 2012-01-25 | 天利半导体（深圳）有限公司 | Clock switching circuit |
| CN102478787A (en) * | 2010-11-24 | 2012-05-30 | 炬才微电子（深圳）有限公司 | Function control circuit and multimedia equipment |
| CN105068950A (en) * | 2015-07-24 | 2015-11-18 | 深圳市微纳集成电路与系统应用研究院 | Pin multiplexing system and method |
| CN109062840A (en) * | 2018-07-25 | 2018-12-21 | 合肥联宝信息技术有限公司 | A kind of method and device of multiplex interface pin |
| CN110008075A (en) * | 2018-01-05 | 2019-07-12 | 深圳市中兴微电子技术有限公司 | A kind of chip adjustment method and device |
| CN114861572A (en) * | 2022-07-05 | 2022-08-05 | 上海泰矽微电子有限公司 | Control system and method for multifunctional enabling pin |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102567776B (en) * | 2011-12-27 | 2015-07-22 | 广州中大微电子有限公司 | Double-interface intelligent card capable of quickly implementing mode selection and implementing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127844A (en) * | 1997-02-20 | 2000-10-03 | Altera Corporation | PCI-compatible programmable logic devices |
| CN1196266C (en) * | 1999-09-15 | 2005-04-06 | 汤姆森许可公司 | Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement |
| CN1331069C (en) * | 2002-11-25 | 2007-08-08 | 杭州士兰微电子股份有限公司 | Method of pins multiplexing based on PCI bus |
-
2006
- 2006-07-12 CN CNB2006100896927A patent/CN100397381C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101299601B (en) * | 2007-04-30 | 2012-01-25 | 天利半导体（深圳）有限公司 | Clock switching circuit |
| CN102478787A (en) * | 2010-11-24 | 2012-05-30 | 炬才微电子（深圳）有限公司 | Function control circuit and multimedia equipment |
| CN102478787B (en) * | 2010-11-24 | 2013-10-23 | 炬才微电子（深圳）有限公司 | Function control circuit and multimedia equipment |
| CN105068950A (en) * | 2015-07-24 | 2015-11-18 | 深圳市微纳集成电路与系统应用研究院 | Pin multiplexing system and method |
| CN110008075A (en) * | 2018-01-05 | 2019-07-12 | 深圳市中兴微电子技术有限公司 | A kind of chip adjustment method and device |
| CN109062840A (en) * | 2018-07-25 | 2018-12-21 | 合肥联宝信息技术有限公司 | A kind of method and device of multiplex interface pin |
| CN114861572A (en) * | 2022-07-05 | 2022-08-05 | 上海泰矽微电子有限公司 | Control system and method for multifunctional enabling pin |
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