CN1752925A - Flow line circuit capable of bypass register and using said register - Google Patents
Flow line circuit capable of bypass register and using said register Download PDFInfo
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- CN1752925A CN1752925A CN 200410066642 CN200410066642A CN1752925A CN 1752925 A CN1752925 A CN 1752925A CN 200410066642 CN200410066642 CN 200410066642 CN 200410066642 A CN200410066642 A CN 200410066642A CN 1752925 A CN1752925 A CN 1752925A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
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Abstract
The present invention provides a by-passable register and pipeline circuit using said register. This circuit uses the ''by-passable'' register as pipeline register. When the pipeline circuit is worked in lower working frequency, these pipeline registers in the circuit can be by-passed, and are not in working state, so that they do not consume any power and can greatly reduce power consumption of whole circuit, and when the pipeline circuit is worked in maximum working frequency, these registers can be gated and are in working state.
Description
Technical field
The present invention relates to the The pipeline design of integrated circuit.
Background technology
In past 20 years, digital integrated circuit, particularly the frequency of operation of cmos digital integrated circuit improves constantly, and has reached the level of Gigahertz today.A main design means that improves frequency of operation is to use flow line circuit (pipeline circuit).Use the multi-stage pipeline circuit can significantly improve the frequency of operation of circuit, also need to insert a large amount of register (register) or latch (latch) but then, increased the power consumption of circuit greatly.And reduce the energy consumption of the energy consumption, particularly portable product (as mobile phone, digital camera, digital camera) of various electronic products, for improving these competitiveness of product, it is very important reducing human consumption to natural resources.Therefore, low-power consumption also is an important indicator in the integrated circuit (IC) design.
As shown in Figure 1, the prior art of at present disclosed flow line circuit design all be the combination logic function module that will realize (as add, subtract, multiplication and division, with or, the combination of arithmetic such as non-or logical operation) resolve into a plurality of relative simply combinatorial logic unit A, B, C, between these combinatorial logic unit A, B, C, insert pipeline register 102,104 and 106 then respectively, form multi-stage pipeline arrangement, the maximum circuit delay that makes every level production line is all less than period of time T.Because the maximum operation frequency of flow line circuit is the inverse of the maximum circuit delay in every level production line circuit delay, like this, the maximum operation frequency of this flow line circuit is fmax=1/T.If T=10 nanosecond (10
-8Second), fmax=100MHz (100 megahertzes=10 so
8Hertz).Clearly,, just must reduce period of time T, and T is more little, just must resolve into more part to combination logic function in order to improve frequency of operation fmax, just more multistage streamline, and insert the more pipeline register.The pipeline register additional in order to improve frequency of operation all needs to consume more power.
When the CMOS power consumption of integrated circuit overwhelming majority occurs in node in the circuit level upset (from low to high or from high to low) is arranged.Because the upset of level all takes place in each of clock in the clock node (comprising register clock internal node) of register along (rising edge or negative edge), other nodes then have only time of 5% to 50% that the upset of level takes place, so the pipeline register in the CMOS integrated circuit has occupied 50% to 80% of total power consumption.
Under a lot of situations, integrated circuit needs the multi-job frequency.As digital video camera when taking high-definition image, several times even tens times of the frequency of operation of the frequency of operation of its internal integrated circuit when taking the single-definition image.The integrated circuit that the multi-job frequency is arranged must be designed to also can work under maximum operation frequency when design, therefore need be subdivided into the abundant multi-stage pipeline that can satisfy under the maximum operation frequency to combination logic function.In fact such integrated circuit does not need so multistage streamline when being operated in lower frequency of operation, these unnecessary pipeline registers make integrated circuit increase a lot of unnecessary power consumptions.
Summary of the invention
The object of the present invention is to provide a kind of register capable of bypass and the flow line circuit of this register of use, this register can control cutting out and opening of its duty by control end and clock signal, i.e. bypass whether, thereby the flow line circuit that make to use described register capable of bypass unnecessary register capable of bypass of bypass selectively under non-maximum operation frequency, thereby reduce the power consumption of entire circuit.
Therefore, in one aspect of the invention, a kind of register capable of bypass is provided, comprise register, described register has input end, output terminal and clock end, described register capable of bypass also comprises: selector switch, two input ends that it has control end, output terminal and links to each other with output terminal with the input end of described register respectively; Wherein, when the control signal of the control end of described selector switch is first level, and described register is not when working, and described selector switch selective reception is from the input end of described register input end signal, with its output signal as its output terminal; And when the control signal of the control end of described selector switch be second level, and during the work of described register, described selector switch selective reception is from another input end of described register output end signal, as the output signal of its output terminal.
And in another aspect of this invention, a kind of flow line circuit is provided, the multi-stage pipeline that comprises series connection, at least one level production line in the described multi-stage pipeline comprises a combinatorial logic unit and coupled register capable of bypass, described register capable of bypass comprises register, described register has input end, output terminal and clock end, described register capable of bypass also comprises: selector switch, two input ends that it has control end, output terminal and links to each other with output terminal with the input end of described register respectively; Wherein, when the by-pass governing signal of described register controlled end capable of bypass is first level, and when the register in the described register capable of bypass was not worked, described selector switch selected directly to receive the input end from described register input end signal, as the output signal of its output terminal; When the by-pass governing signal of described register controlled end capable of bypass is second level, and during the register operate as normal in the described register capable of bypass, described selector switch selective reception is from the input end of described register output end signal, as the output signal of its output terminal.
By by-pass governing signal F and clock signal, flow line circuit with multi-job frequency can be when non-maximum operation frequency, indicate the register in the unnecessary register capable of bypass to close, directly give the next stage combinatorial logic unit with the output of this grade combinatorial logic unit, thereby realize that power consumption reduces.
Description of drawings
Traditional multi-stage pipeline circuit structure block diagram that Fig. 1 is in the prior art to be adopted.
Fig. 2 is according to register architecture block diagram capable of bypass of the present invention.
Fig. 3 is the flow line circuit block diagram that has two level production lines according to of the present invention.
Fig. 4 is the flow line circuit block diagram that has three class pipeline according to of the present invention.
Fig. 5 is the flow line circuit block diagram that has the level Four streamline according to of the present invention.
Embodiment
As shown in Figure 2, register capable of bypass 200 of the present invention is made up of selector switch 202 and register 201.Described register 201 is exactly employed register in the common flow line circuit in embodiments of the present invention, d type flip flop for example, and it has input end D, output terminal Q1 and clock end Clock.But must be pointed out that register capable of bypass of the present invention is not limited to use above-mentioned d type flip flop as register, the trigger of other types or register, for example: employed register all is applicable to the present invention in register that R-S flip-flop, asynchronous set reset flip-flop, band detection synchronously imported etc. or the prior art.Therefore, the applicant only describes as example with d type flip flop, and the trigger of other types and the embodiment of register also are applicable to the present invention fully, in this no longer repeat specification.Described d type flip flop 201 comes gating by the clock signal of clock end Clock, and its principle of work is well known to those skilled in the art, and no longer repeats at this.And selector switch 202 has two input end IN1 and IN2, output terminal Q2 and a control end F.Described input end IN1 links to each other with the input end D of d type flip flop 201, and another input end IN2 links to each other with the output terminal Q1 of d type flip flop 201.When the work of described selector switch, can be according to the control signal of control end F, select a signal among two input end IN1 and the IN2 as the output signal of output terminal Q2.Described selector switch can be realized by the element that can realize above-mentioned functions in any prior art, for example, can use two path multiplexers (2-to-1Multiplexer), various on-off element (as transistor) etc.Be example with two path multiplexers below, specify the course of work of this register capable of bypass:
When control signal F=0, two path multiplexers 202 are selected from the output as multiplexer 202 output terminal Q2 of the signal of d type flip flop 201 input end D, and just input signal D has walked around d type flip flop 201 and directly is sent to output terminal Q2.At this moment, guarantee simultaneously that by external circuit clock signal C lock keeps low level always, just can make d type flip flop 201 be in the off position of bypass (not gating), thereby reduce power consumption.
When control signal F=1, two path multiplexers 202 are selected from the output as multiplexer output terminal Q2 of the signal of d type flip flop 201 output terminal Q1, at this moment, external circuit keeps clock signal C lock to be in normal working frequency, described register 200 capable of bypass just as the common pipeline register of d type flip flop type equally work.
Therefore, according under the multi-job frequency to the demand of d type flip flop 201, the duty of each d type flip flop 201 of clock signal C lock may command, close unwanted d type flip flop 201, to save power consumption, and select appropriate signal by the selector switch 202 that control signal F is controlled, just can avoid the problem that input signal can't directly be exported when closing d type flip flop 201.Like this, when register capable of bypass is just worked as pipeline register during by gating like that, and just do not work during bypass (not gating), input signal directly can be exported simultaneously.
Need explanation; the level definition of described control signal F just example explanation is not limited thereto; those skilled in the art can carry out the opposite levels definition with it according to embodiments of the invention; select Q1 when being F=0; and during F=1; select input end D, these change all in invention which is intended to be protected.In the pipeline organization below, above-mentioned explanation is also followed in the definition of control signal F, only is example.
Multi-stage pipeline circuit with this register is described below in conjunction with above-mentioned register capable of bypass.
In general, for m (m be integer and more than or equal to 2) level series connection flow line circuit, in every m level production line register, it is capable of bypass that m-1 level production line register is generally arranged.When this m-1 level production line register all is in bypass (not gating), the combinatorial logic unit of corresponding m part all directly links to each other, no longer separated by register capable of bypass, therefore, the maximum circuit delay of the combinatorial logic unit of this m part is mT, just frequency of operation becomes f=1/ (mT)=(1/m) fmax, the just m of maximum operation frequency fmax/one.Under this lower frequency of operation, all m-1 level production line registers are consumed power no longer all, greatly reduces the power consumption of circuit.
Shown in Fig. 3 is the flow line circuit that has two level production lines according to of the present invention.
As shown in Figure 3, described two-stage flow line circuit has two level production lines.First order streamline comprises combinatorial logic unit A 301 and 302, the liang of level production lines of register capable of bypass comprise combinatorial logic unit B 303 and common pipeline register 304.And for first order streamline, control d type flip flop clock signal C lock with "/bypass " (by convention, "/" expression low level in the control signal name "/bypass " is represented bypass, but also can define level signal as required, the present invention represents bypass with low level) signal F by with door 307 mutually " with " link to each other with the d type flip flop of register 302 capable of bypass more afterwards.Like this, for first order streamline, its duty is as described below:
When by-pass governing signal F=0, register 302 capable of bypass is in bypass (not gating) state, the clock signal C lock that is sent to register 302 capable of bypass is blocked with door 307, therefore, d type flip flop in the register 302 capable of bypass is not worked, the input D that selector switch is selected register 302 capable of bypass is directly as the output Q of register (the concrete duty of register capable of bypass when the F=0, can with reference to the explanation of the relevant register capable of bypass of Fig. 2).In fact, at this moment, whole flow line circuit has only pipeline register 304 in work.Like this, when not needing maximum operation frequency, just reduce the number of unnecessary pipeline register relatively, made the power consumption of whole flow line circuit to descend.Under this situation of this embodiment, the maximum circuit delay of flow line circuit is 2T, and its frequency of operation is (1/2) fmax, half of maximum operation frequency just, and power consumption approximately can reduce by 40% at most.
When by-pass governing signal F=1, register 302 capable of bypass is in strobe state, clock signal C lock can be given d type flip flop in the register 302 capable of bypass with door 307, and during control signal F=1, selector switch is selected the output signal of the output of d type flip flop as register.Therefore, register 302 capable of bypass is equally worked with general pipeline register, and just at the rising edge of clock, input D directly is sent to output Q, and free in other institutes, output Q continues to have.At this moment, the two-stage flow line circuit is in maximum operation frequency, and register capable of bypass is also in running order, does not reduce power consumption.
The truth table of the register capable of bypass 302 among Fig. 3 is:
Input and output
F Clock D Q[n+1]
0 x 0 0
0 x 1 1
1 rising edge 00
1 rising edge 11
1 other x Q[n]
Fig. 4 is the flow line circuit that has three class pipeline according to of the present invention.
There is two-stage to have register capable of bypass in this three class pipeline circuit.First order streamline comprises combinatorial logic unit A 401 and register capable of bypass 402, the level production line comprises combinatorial logic unit B 403 and register capable of bypass 404, and third level streamline comprises combinatorial logic unit C 405 and common pipeline register 406.And for the first order and second level streamline, control d type flip flop clock signal C lock with "/bypass " signal F by with door 407 mutually " with " link to each other with their d type flip flop respectively more afterwards.Like this, for the first order and second level streamline, its duty is as described below:
When by-pass governing signal F=0, register 402 capable of bypass and 404 is in bypass (not gating) state, the clock signal C lock that is sent to these two registers capable of bypass is blocked with door 407, therefore, d type flip flop in the register 402 capable of bypass and 404 is not worked, therefore, the input D of register 402 capable of bypass has directly been delivered to the output Q of register 404 capable of bypass (the concrete duty of register capable of bypass when F=0, can with reference to the explanation of the relevant register capable of bypass of Fig. 2).In fact, at this moment, whole flow line circuit has only pipeline register 406 in work.Like this, when not needing maximum operation frequency, just reduce the number of unnecessary pipeline register relatively, made the power consumption of whole flow line circuit to descend.Under this situation of this embodiment, the maximum circuit delay of this flow line circuit is 3T, and its frequency of operation is (1/3) fmax, just 1/3rd of maximum operation frequency, and power consumption approximately can reduce by 55% at most.
When by-pass governing signal F=1, register 402 and 404 capable of bypass is in strobe state, and clock signal C lock can be given d type flip flop in these registers capable of bypass with door 407.Therefore, register 402 capable of bypass is worked with general pipeline register is the same with 404, and just at the rising edge of clock, input D directly is sent to output Q, and free in other institutes, output Q continues to have.At this moment, the three class pipeline circuit is in maximum operation frequency, and register capable of bypass is also in running order, does not reduce power consumption.
Fig. 5 is the flow line circuit that has the level Four streamline according to of the present invention.
In the level Four flow line circuit of present embodiment, there are 3 level production lines to have register capable of bypass.First order streamline comprises combinatorial logic unit A 501 and register capable of bypass 502, the level production line comprises combinatorial logic unit B 503 and register capable of bypass 504, third level streamline comprises combinatorial logic unit C 505 and register capable of bypass 506, and fourth stage streamline comprises combinatorial logic unit D 507 and common pipeline register 508.For the first order, third level streamline, the clock signal C lock that controls its d type flip flop with the signal F of/bypass 1 by with door 509 mutually " with " link to each other with their d type flip flop respectively more afterwards.And for second level streamline, the clock signal C lock that controls its d type flip flop with the signal F of/bypass 2 by with door 510 mutually " with " link to each other with d type flip flop more afterwards.By introduce a plurality of bypass signal and with door, can be so that this level Four flow line circuit works in 3 kinds of different frequency of operation, its duty is as described below:
1) when the by-pass governing signal: during/bypass 1=/bypass 2=1, clock signal C lock is through having given all registers capable of bypass with door 509 and 510.Register capable of bypass 502,504,506 is equally worked with general pipeline register, registers all in the circuit is all in running order, and just at the rising edge of clock, input D directly is sent to output Q, and free in other institutes, output Q remains unchanged.This moment, the maximum circuit delay (delay from the one-level work register to the next stage work register) of every level production line was T, and this flow line circuit is maximum operation frequency fmax=1/T.Under this duty and frequency, all registers are consumed power all.
2) when the by-pass governing signal :/bypass 1=0 during/bypass 2=1, is blocked through the clock signal C lock with door 509, and passes through the d type flip flop that is fed to register 504 capable of bypass with the clock signal C lock of door 510.Therefore, register 502 capable of bypass and 506 is in idle bypass (not gating) state, and register 504 capable of bypass and pipeline register 508 are in running order, this moment, the maximum circuit delay (delay from the in running order register of one-level to the in running order register of next stage) of every level production line was 2T, and the frequency of operation of circuit is f
1=1/ (2T)=(1/2) fmax.Under this duty and frequency, the register consumed power of half is only arranged, compare with the traditional multi-stage pipeline circuit under being operated in same frequency, can reduce power consumption and be up to 40%.
3) when the by-pass governing signal: during/bypass 1=/bypass 2=0, through all being blocked with the clock signal C lock of door 509 with through clock signal C lock with door 510, all registers 502,504 capable of bypass and 506 all are in idle bypass (not gating) state, have only pipeline register 508 work in the entire circuit.Therefore, 1/4 register is in running order, and other 3/4 then is in the off position of bypass (not gating).This moment, the maximum circuit delay (delay from the in running order register of one-level to the in running order register of next stage) of every level production line was 4T, and the frequency of operation of circuit is f
2=1/ (4T)=(1/4) fmax.Under this duty and frequency, 1/4 register consumed power is only arranged, compare with the traditional multi-stage pipeline circuit under being operated in same frequency, can reduce power consumption and be up to 60%.
As for working as the by-pass governing signal :/bypass 1=1; During/bypass 2=0, because register 504 capable of bypass not gating is not worked, and register 502 capable of bypass and 506 gating work, therefore, the maximum circuit delay of circuit (delay from the in running order register capable of bypass 502 of the first order to the in running order register capable of bypass 506 of the third level) is 2T, and the frequency of operation of circuit is f
1=1/ (2T)=(1/2) fmax.Under this duty and frequency, the state that has identical frequency of operation during with above-mentioned situation 2 bypass 1=0 bypass 2=1 is compared, and has more a register capable of bypass in work, and therefore, its power consumption reduces not obvious, does not generally adopt this duty.
In sum, come according to actual operating frequency some unnecessary register of bypass (not gating) selectively by in flow line circuit, introducing register capable of bypass, just can significantly reduce the power consumption of entire circuit, it is significant that this prolongs its service time for various mancarried devices.As for the number of bypass signal, the applicant it may be noted that this can have the how many kinds of frequency of operation according to the flow line circuit in the real work and determine, is not limited to the foregoing description.And among Fig. 3-5 and gating element, just there is corresponding relation between by-pass governing signal and the clock signal in order to make, be that the clock signal is when offering register, bypass signal is selected this register, and register does not have clock signal not during gating, bypass signal just makes input signal walk around this register, there is above-mentioned relation as long as can make between bypass signal and the clock signal, it also is fully passable using other elements with above-mentioned functions, such as, can block or pass through clock signal with so-called path transistor (Pass Transistor).And the definition of the truth table of described register capable of bypass also is an illustrative, but not is confined to this, such as, the rising edge upset in the table also can be the negative edge upset.
In addition, though the present invention has only described the embodiment of two-stage to the level Four flow line circuit, should be understood that the present invention is not limited thereto.By top description and for example, those skilled in the art have the ability fully to apply the present invention to go in the more multistage flow line circuit and do not need to pay creative work.These changes all belong to invention which is intended to be protected.
Claims (9)
1. a register capable of bypass (200) comprises register (201), and described register (201) has input end (D), and output terminal (Q1) and clock end (Clock) is characterized in that, described register capable of bypass (200) also comprises:
Selector switch (202), two input ends (IN1, IN2) that have control end (F), output terminal (Q2) and link to each other with output terminal (Q1) with the input end (D) of described register (201) respectively;
Wherein, when the control signal F of the control end of described selector switch is first level, and described register (201) is not when working, and described selector switch is used to select input end (IN1), receives from the signal of described register (201) input end (D) output signal as its output terminal (Q2);
And the control signal F that works as the control end of described selector switch is second level, and during described register (201) work, described selector switch is used to select input end (IN2), receives from the signal of described register (201) output terminal (Q1) output signal as its output terminal (Q2).
2. register capable of bypass as claimed in claim 1 is characterized in that, described register (201) is a d type flip flop, synchronously R-S flip-flop, asynchronous set reset flip-flop, band detect a kind of in the register of input.
3. register capable of bypass as claimed in claim 1 is characterized in that, described selector switch is two path multiplexers or on-off element.
4. register capable of bypass as claimed in claim 1 is characterized in that, the duty of described register (201) is controlled by clock end Clock.
5. flow line circuit, the multi-stage pipeline that comprises series connection, it is characterized in that, at least one level production line in the described multi-stage pipeline comprises a combinatorial logic unit and coupled register capable of bypass (200), described register capable of bypass (200) comprises register (201), described register (201) has input end (D), output terminal (Q1) and clock end (Clock); And selector switch (202), two input ends (IN1, IN2) that have control end (F), output terminal (Q2) and link to each other with output terminal (Q1) with the input end (D) of described register (201) respectively;
Wherein, when the by-pass governing signal of described register capable of bypass (200) control end is first level, and the register (201) in the described register capable of bypass (200) is not when working, described selector switch is used to select input end (IN1), directly receives from the signal of described register (201) input end (D) output signal as its output terminal (Q2);
When the by-pass governing signal of described register capable of bypass (200) control end is second level, and during register (201) operate as normal in the described register capable of bypass (200), described selector switch is used to select input end (IN2), receives from the signal of described register (201) output terminal (Q1) output signal as its output terminal (Q2).
6. flow line circuit as claimed in claim 5 is characterized in that, described flow line circuit also comprises and door, described by-pass governing signal (F) and clock signal is carried out and operation, to block or to pass through clock signal.
7. flow line circuit as claimed in claim 5 is characterized in that described flow line circuit also comprises path transistor, described by-pass governing signal (F) and clock signal is operated, with blocking-up or pass through clock signal.
8. flow line circuit as claimed in claim 5 is characterized in that, when described multi-stage pipeline circuit was the m level, m-1 level production line wherein all can comprise described register capable of bypass (200), and m is an integer and more than or equal to 2.
9. as claim 6 or 7 described flow line circuits, it is characterized in that described by-pass governing signal and can adjust according to the number of the multi-job frequency of described multi-stage pipeline circuit with the number of door or path transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100666428A CN100377077C (en) | 2004-09-24 | 2004-09-24 | Flow line circuit capable of bypass register and using said register |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100666428A CN100377077C (en) | 2004-09-24 | 2004-09-24 | Flow line circuit capable of bypass register and using said register |
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| CN1752925A true CN1752925A (en) | 2006-03-29 |
| CN100377077C CN100377077C (en) | 2008-03-26 |
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| CNB2004100666428A Expired - Fee Related CN100377077C (en) | 2004-09-24 | 2004-09-24 | Flow line circuit capable of bypass register and using said register |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996064B (en) * | 2009-08-19 | 2012-04-18 | 中国科学院微电子研究所 | Double-edge-trigger pipeline accumulator structure of GaAs heterojunction bipolar transistor (HBT) |
| CN105739948A (en) * | 2014-12-12 | 2016-07-06 | 超威半导体(上海)有限公司 | Self-adaptive adjustable assembly line and method for adaptively adjusting assembly line |
| CN111045957A (en) * | 2019-12-26 | 2020-04-21 | 江南大学 | ICache implementation method pseudo-same frequency with processor assembly line |
| CN113381736A (en) * | 2021-06-25 | 2021-09-10 | 上海威固信息技术股份有限公司 | Pipeline circuit with high throughput rate |
| WO2022241785A1 (en) * | 2021-05-21 | 2022-11-24 | 华为技术有限公司 | Integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH05199080A (en) * | 1992-01-17 | 1993-08-06 | Sony Corp | Complementary logic circuit |
| US6226772B1 (en) * | 1998-11-06 | 2001-05-01 | Lih-Jyh Weng | Pipelined combined system for producing error correction code symbols and error syndromes for large ECC redundancy |
| JP3508625B2 (en) * | 1999-05-28 | 2004-03-22 | 日本電気株式会社 | Low power digital logic circuit |
| JP2001118387A (en) * | 1999-10-15 | 2001-04-27 | Mitsubishi Electric Corp | Synchronizing type semiconductor memory |
| US6586966B1 (en) * | 2001-09-13 | 2003-07-01 | Altera Corporation | Data latch with low-power bypass mode |
| US6696854B2 (en) * | 2001-09-17 | 2004-02-24 | Broadcom Corporation | Methods and circuitry for implementing first-in first-out structure |
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2004
- 2004-09-24 CN CNB2004100666428A patent/CN100377077C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996064B (en) * | 2009-08-19 | 2012-04-18 | 中国科学院微电子研究所 | Double-edge-trigger pipeline accumulator structure of GaAs heterojunction bipolar transistor (HBT) |
| CN105739948A (en) * | 2014-12-12 | 2016-07-06 | 超威半导体(上海)有限公司 | Self-adaptive adjustable assembly line and method for adaptively adjusting assembly line |
| CN111045957A (en) * | 2019-12-26 | 2020-04-21 | 江南大学 | ICache implementation method pseudo-same frequency with processor assembly line |
| CN111045957B (en) * | 2019-12-26 | 2023-10-27 | 江南大学 | ICache realizing method of pseudo same frequency as processor pipeline |
| WO2022241785A1 (en) * | 2021-05-21 | 2022-11-24 | 华为技术有限公司 | Integrated circuit |
| CN113381736A (en) * | 2021-06-25 | 2021-09-10 | 上海威固信息技术股份有限公司 | Pipeline circuit with high throughput rate |
| CN113381736B (en) * | 2021-06-25 | 2023-11-21 | 上海威固信息技术股份有限公司 | Pipelined circuit with high throughput rate |
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|---|---|
| CN100377077C (en) | 2008-03-26 |
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